[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / maverick.c

/* Copyright (C) 2000, 2003 Free Software Foundation
   Contributed by Alexandre Oliva <aoliva@cygnus.com>

   This file is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

/* Generator of tests for Maverick.

   See the following file for usage and documentation.  */
#include "../all/test-gen.c"

/* These are the ARM registers.  Some of them have canonical names
   other than r##, so we'll use both in the asm input, but only the
   canonical names in the expected disassembler output.  */
char *arm_regs[] =
  {
    /* Canonical names.  */
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
    /* Alternate names, i.e., those that can be used in the assembler,
     * but that will never be emitted by the disassembler.  */
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
  };

/* The various types of registers: ARM's registers, Maverick's
   f/d/fx/dx registers, Maverick's accumulators and Maverick's
   status register.  */
#define armreg(shift) \
  reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))
#define mvreg(prefix, shift) \
  reg_p ("mv" prefix, shift, mk_get_bits (4u))
#define acreg(shift) \
  reg_p ("mvax", shift, mk_get_bits (2u))
#define dspsc \
  literal ("dspsc"), tick_random

/* This outputs the condition flag that may follow each ARM insn.
   Since the condition 15 is invalid, we use it to check that the
   assembler recognizes the absence of a condition as `al'.  However,
   the disassembler won't ever output `al', so, if we emit it in the
   assembler, expect the condition to be omitted in the disassembler
   output.  */

int
arm_cond (func_arg * arg, insn_data * data)
#define arm_cond { arm_cond }
{
  static const char conds[16][3] =
    {
      "eq", "ne", "cs", "cc",
      "mi", "pl", "vs", "vc",
      "hi", "ls", "ge", "lt",
      "gt", "le", "al", ""
    };
  unsigned val = get_bits (4u);

  data->as_in = data->dis_out = strdup (conds[val]);
  if (val == 14)
    data->dis_out = strdup ("");
  data->bits = (val == 15 ? 14 : val) << 28;
  return 0;
}

/* The sign of an offset is actually used to determined whether the
   absolute value of the offset should be added or subtracted, so we
   must adjust negative values so that they do not overflow: -1024 is
   not valid, but -0 is distinct from +0.  */
int
off8s (func_arg * arg, insn_data * data)
#define off8s { off8s }
{
  int val;
  char value[9];

  /* Zero values are problematical.
     The assembler performs translations on the addressing modes
     for these values, meaning that we cannot just recreate the
     disassembler string in the LDST macro without knowing what
     value had been generated in off8s.  */
  do
    {
      val  = get_bits (9s);
    }
  while (val == -1 || val == 0);
  
  val <<= 2;
  if (val < 0)
    {
      val = -4 - val;
      sprintf (value, ", #-%i", val);
      data->dis_out = strdup (value);
      sprintf (value, ", #-%i", val);
      data->as_in = strdup (value);
      data->bits = val >> 2;
    }
  else
    {
      sprintf (value, ", #%i", val);
      data->as_in = data->dis_out = strdup (value);
      data->bits = (val >> 2) | (1 << 23);
    }
  
  return 0;
}

/* This function generates a 7-bit signed constant, emitted as
   follows: the 4 least-significant bits are stored in the 4
   least-significant bits of the word; the 3 most-significant bits are
   stored in bits 7:5, i.e., bit 4 is skipped.  */
int
imm7 (func_arg *arg, insn_data *data)
#define imm7 { imm7 }
{
  int val = get_bits (7s);
  char value[6];

  data->bits = (val & 0x0f) | (2 * (val & 0x70));
  sprintf (value, "#%i", val);
  data->as_in = data->dis_out = strdup (value);
  return 0;
}

/* Convenience wrapper to define_insn, that prefixes every insn with
   `cf' (so, if you specify command-line arguments, remember that `cf'
   must *not* be part of the string), and post-fixes a condition code.
   insname and insnvar specify the main insn name and a variant;
   they're just concatenated, and insnvar is often empty.  word is the
   bit pattern that defines the insn, properly shifted, and funcs is a
   sequence of funcs that define the operands and the syntax of the
   insn.  */
#define mv_insn(insname, insnvar, word, funcs...) \
  define_insn (insname ## insnvar, \
	      literal ("cf"), \
	      insn_bits (insname, word), \
	      arm_cond, \
	      tab, \
	      ## funcs)

/* Define a single LDC/STC variant.  op is the main insn opcode; ld
   stands for load (it should be 0 on stores), dword selects 64-bit
   operations, pre should be enabled for pre-increment, and wb, for
   write-back.  sep1, sep2 and sep3 are syntactical elements ([]!)
   that the assembler will use to enable pre and wb.  It would
   probably have been cleaner to couple the syntactical elements with
   the pre/wb bits directly, but it would have required the definition
   of more functions.  */
#define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \
  mv_insn (insname, insnvar, \
	   (12 << 24) | (op << 8) | (ld << 20) | (pre << 24) | (dword << 22) | (wb << 21), \
	    mvreg (regname, 12), comma, \
	    lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \
	    tick_random)

/* Define all variants of an LDR or STR instruction, namely,
   pre-indexed without write-back, pre-indexed with write-back and
   post-indexed.  */
#define LDSTall(insname, op, ld, dword, regname) \
  LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \
  LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \
  LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing)

/* Produce the insn identifiers of all LDST variants of a given insn.
   To be used in the initialization of an insn group array.  */
#define insns_LDSTall(insname) \
  insn (insname ## _p), insn (insname ## _pw), insn (insname)

/* Define a CDP variant that uses two registers, at offsets 12 and 16.
   The two opcodes and the co-processor number identify the CDP
   insn.  */
#define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \
  mv_insn (insname##var, , \
	   (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
	   mvreg (reg1name, 12), comma, mvreg (reg2name, 16))

/* Define a 32-bit integer CDP instruction with two operands.  */
#define CDP2fx(insname, opcode1, opcode2) \
  CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")

/* Define a 64-bit integer CDP instruction with two operands.  */
#define CDP2dx(insname, opcode1, opcode2) \
  CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")

/* Define a float CDP instruction with two operands.  */
#define CDP2f(insname, opcode1, opcode2) \
  CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")

/* Define a double CDP instruction with two operands.  */
#define CDP2d(insname, opcode1, opcode2) \
  CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")

/* Define a CDP instruction with two register operands and one 7-bit
   signed immediate generated with imm7.  */
#define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \
  mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8), \
	   mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
	   tick_random)

/* Produce the insn identifiers of CDP floating-point or integer insn
   pairs (i.e., it appends the suffixes for 32-bit and 64-bit
   insns.  */
#define CDPfp_insns(insname) \
  insn (insname ## s), insn (insname ## d)
#define CDPx_insns(insname) \
  insn (insname ## 32), insn (insname ## 64)

/* Define a CDP instruction with 3 operands, at offsets 12, 16, 0.  */
#define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \
  mv_insn (insname##var, , \
	   (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
	   mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \
	   mvreg (reg3name, 0), tick_random)

/* Define a 32-bit integer CDP instruction with three operands.  */
#define CDP3fx(insname, opcode1, opcode2) \
  CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")

/* Define a 64-bit integer CDP instruction with three operands.  */
#define CDP3dx(insname, opcode1, opcode2) \
  CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")

/* Define a float CDP instruction with three operands.  */
#define CDP3f(insname, opcode1, opcode2) \
  CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")

/* Define a double CDP instruction with three operands.  */
#define CDP3d(insname, opcode1, opcode2) \
  CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")

/* Define a CDP instruction with four operands, at offsets 5, 12, 16
 * and 0.  Used only for ACC instructions.  */
#define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \
  mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | (6 << 8), \
	   acreg (5), comma, reg2spec, comma, \
	   mvreg (reg3name, 16), comma, mvreg (reg4name, 0))

/* Define a CDP4 instruction with one accumulator operands.  */
#define CDP41A(insname, opcode1) \
  CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")

/* Define a CDP4 instruction with two accumulator operands.  */
#define CDP42A(insname, opcode1) \
  CDP4 (insname, opcode1, acreg (12), "fx", "fx")

/* Define a MCR or MRC instruction with two register operands.  */
#define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \
  mv_insn (insname, , \
	   ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
	    ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
	   reg1spec, comma, reg2spec)

/* Define a move from a DSP register to an ARM register.  */
#define MVDSPARM(insname, cpnum, opcode2, regDSPname) \
  MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \
	 mvreg (regDSPname, 16), armreg (12))

/* Define a move from an ARM register to a DSP register.  */
#define MVARMDSP(insname, cpnum, opcode2, regDSPname) \
  MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
	 armreg (12), mvreg (regDSPname, 16))

/* Move between coprocessor registers. A two operand CDP insn.   */
#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \
  mv_insn (insname, , \
	   ((14 << 24) | ((opcode1) << 20) | \
	    (4 << 8) | ((opcode2) << 5)), \
	   reg1spec, comma, reg2spec)

/* Define a move from a DSP register to a DSP accumulator.  */
#define MVDSPACC(insname, opcode2, regDSPname) \
  MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))

/* Define a move from a DSP accumulator to a DSP register.  */
#define MVACCDSP(insname, opcode2, regDSPname) \
  MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))

/* Define move insns between a float DSP register and an ARM
   register.  */
#define MVf(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 4, opcode2, "f"); \
  MVARMDSP (nameDA, 4, opcode2, "f")

/* Define move insns between a double DSP register and an ARM
   register.  */
#define MVd(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 4, opcode2, "d"); \
  MVARMDSP (nameDA, 4, opcode2, "d")

/* Define move insns between a 32-bit integer DSP register and an ARM
   register.  */
#define MVfx(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 5, opcode2, "fx"); \
  MVARMDSP (nameDA, 5, opcode2, "fx")

/* Define move insns between a 64-bit integer DSP register and an ARM
   register.  */
#define MVdx(nameAD, nameDA, opcode2) \
  MVDSPARM (nameAD, 5, opcode2, "dx"); \
  MVARMDSP (nameDA, 5, opcode2, "dx")

/* Define move insns between a 32-bit DSP register and a DSP
   accumulator.  */
#define MVfxa(nameFA, nameAF, opcode2) \
  MVDSPACC (nameFA, opcode2, "fx"); \
  MVACCDSP (nameAF, opcode2, "fx")

/* Define move insns between a 64-bit DSP register and a DSP
   accumulator.  */
#define MVdxa(nameDA, nameAD, opcode2) \
  MVDSPACC (nameDA, opcode2, "dx"); \
  MVACCDSP (nameAD, opcode2, "dx")

/* Produce the insn identifiers for a pair of mv insns.  */
#define insns_MV(name1, name2) \
  insn (mv ## name1), insn (mv ## name2)

/* Define a MCR or MRC instruction with three register operands.  */
#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \
  mv_insn (insname, , \
	   ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
	    ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
	   reg1spec, comma, reg2spec, comma, reg3spec, \
	   tick_random)

/* Define all load_store insns.  */
LDSTall (ldrs, 4, 1, 0, "f");
LDSTall (ldrd, 4, 1, 1, "d");
LDSTall (ldr32, 5, 1, 0, "fx");
LDSTall (ldr64, 5, 1, 1, "dx");
LDSTall (strs, 4, 0, 0, "f");
LDSTall (strd, 4, 0, 1, "d");
LDSTall (str32, 5, 0, 0, "fx");
LDSTall (str64, 5, 0, 1, "dx");

/* Create the load_store insn group.  */
func *load_store_insns[] =
  {
    insns_LDSTall (ldrs),  insns_LDSTall (ldrd),
    insns_LDSTall (ldr32), insns_LDSTall (ldr64),
    insns_LDSTall (strs),  insns_LDSTall (strd),
    insns_LDSTall (str32), insns_LDSTall (str64),
    0
  };

/* Define all move insns.  */
MVf (sr, rs, 2);
MVd (dlr, rdl, 0);
MVd (dhr, rdh, 1);
MVdx (64lr, r64l, 0);
MVdx (64hr, r64h, 1);
MVfxa (al32, 32al, 2);
MVfxa (am32, 32am, 3);
MVfxa (ah32, 32ah, 4);
MVfxa (a32, 32a, 5);
MVdxa (a64, 64a, 6);
MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12));
MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc);
CDP2 (cpys, , 4, 0, 0, "f", "f");
CDP2 (cpyd, , 4, 0, 1, "d", "d");

/* Create the move insns group.  */
func * move_insns[] =
  {
    insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
    insns_MV (64lr, r64l), insns_MV (64hr, r64h),
    insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
    insns_MV (a32, 32a), insns_MV (a64, 64a),
    insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
    0
  };

/* Define all conversion insns.  */
CDP2 (cvtsd, , 4, 0, 3, "d", "f");
CDP2 (cvtds, , 4, 0, 2, "f", "d");
CDP2 (cvt32s, , 4, 0, 4, "f", "fx");
CDP2 (cvt32d, , 4, 0, 5, "d", "fx");
CDP2 (cvt64s, , 4, 0, 6, "f", "dx");
CDP2 (cvt64d, , 4, 0, 7, "d", "dx");
CDP2 (cvts32, , 5, 1, 4, "fx", "f");
CDP2 (cvtd32, , 5, 1, 5, "fx", "d");
CDP2 (truncs32, , 5, 1, 6, "fx", "f");
CDP2 (truncd32, , 5, 1, 7, "fx", "d");

/* Create the conv insns group.  */
func * conv_insns[] =
  {
    insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
    insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
    insn (truncs32), insn (truncd32),
    0
  };

/* Define all shift insns.  */
MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg (12));
MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg (12));
CDP2_imm7 (sh32, 5, 0, "fx", "fx");
CDP2_imm7 (sh64, 5, 2, "dx", "dx");

/* Create the shift insns group.  */
func *shift_insns[] =
  {
    insn (rshl32), insn (rshl64),
    insn (sh32), insn (sh64),
    0
  };

/* Define all comparison insns.  */
MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0));
MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0));
MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0));
MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0));

/* Create the comp insns group.  */
func *comp_insns[] =
  {
    insn (cmps), insn (cmpd),
    insn (cmp32), insn (cmp64),
    0
  };

/* Define all floating-point arithmetic insns.  */
CDP2f (abs, 3, 0);
CDP2d (abs, 3, 1);
CDP2f (neg, 3, 2);
CDP2d (neg, 3, 3);
CDP3f (add, 3, 4);
CDP3d (add, 3, 5);
CDP3f (sub, 3, 6);
CDP3d (sub, 3, 7);
CDP3f (mul, 1, 0);
CDP3d (mul, 1, 1);

/* Create the fp-arith insns group.  */
func *fp_arith_insns[] =
  {
    CDPfp_insns (abs), CDPfp_insns (neg),
    CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul),
    0
  };

/* Define all integer arithmetic insns.  */
CDP2fx (abs, 3, 0);
CDP2dx (abs, 3, 1);
CDP2fx (neg, 3, 2);
CDP2dx (neg, 3, 3);
CDP3fx (add, 3, 4);
CDP3dx (add, 3, 5);
CDP3fx (sub, 3, 6);
CDP3dx (sub, 3, 7);
CDP3fx (mul, 1, 0);
CDP3dx (mul, 1, 1);
CDP3fx (mac, 1, 2);
CDP3fx (msc, 1, 3);

/* Create the int-arith insns group.  */
func * int_arith_insns[] =
  {
    CDPx_insns (abs), CDPx_insns (neg),
    CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
    insn (mac32), insn (msc32),
    0
  };

/* Define all accumulator arithmetic insns.  */
CDP41A (madd32, 0);
CDP41A (msub32, 1);
CDP42A (madda32, 2);
CDP42A (msuba32, 3);

/* Create the acc-arith insns group.  */
func * acc_arith_insns[] =
  {
    insn (madd32), insn (msub32),
    insn (madda32), insn (msuba32),
    0
  };

/* Create the set of all groups.  */
group_t groups[] =
  {
    { "load_store", load_store_insns },
    { "move", move_insns },
    { "conv", conv_insns },
    { "shift", shift_insns },
    { "comp", comp_insns },
    { "fp_arith", fp_arith_insns },
    { "int_arith", int_arith_insns },
    { "acc_arith", acc_arith_insns },
    { 0 }
  };

int
main (int argc, char *argv[])
{
  FILE *as_in = stdout, *dis_out = stderr;

  /* Check whether we're filtering insns.  */
  if (argc > 1)
    skip_list = argv + 1;

  /* Output assembler header.  */
  fputs ("\t.text\n"
	 "\t.align\n",
	 as_in);
  /* Output comments for the testsuite-driver and the initial
     disassembler output.  */
  fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
	 "#name: Maverick\n"
	 "#as: -mcpu=ep9312\n"
	 "\n"
	 "# Test the instructions of the Cirrus Maverick floating point co-processor\n"
	 "\n"
	 ".*: +file format.*arm.*\n"
	 "\n"
	 "Disassembly of section .text:\n",
	 dis_out);

  /* Now emit all (selected) insns.  */
  output_groups (groups, as_in, dis_out);

  exit (0);
}
Commit	Line	Data
cce4814f NC	1	/* Copyright (C) 2000, 2003 Free Software Foundation
	2	Contributed by Alexandre Oliva <aoliva@cygnus.com>
	3
	4	This file is free software; you can redistribute it and/or modify it
	5	under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful, but
	10	WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
4b4da160	16	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
9ac3a342 AH	17
9ac3a342 AH	18	/* Generator of tests for Maverick.
cce4814f NC	19
cce4814f NC	20	See the following file for usage and documentation. */
9ac3a342 AH	21	#include "../all/test-gen.c"
	22
	23	/* These are the ARM registers. Some of them have canonical names
cce4814f NC	24	other than r##, so we'll use both in the asm input, but only the
	25	canonical names in the expected disassembler output. */
	26	char *arm_regs[] =
	27	{
	28	/* Canonical names. */
	29	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	30	"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
	31	/* Alternate names, i.e., those that can be used in the assembler,
	32	* but that will never be emitted by the disassembler. */
	33	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	34	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
	35	};
9ac3a342 AH	36
9ac3a342 AH	37	/* The various types of registers: ARM's registers, Maverick's
cce4814f NC	38	f/d/fx/dx registers, Maverick's accumulators and Maverick's
cce4814f NC	39	status register. */
9ac3a342 AH	40	#define armreg(shift) \
	41	reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))
	42	#define mvreg(prefix, shift) \
	43	reg_p ("mv" prefix, shift, mk_get_bits (4u))
	44	#define acreg(shift) \
	45	reg_p ("mvax", shift, mk_get_bits (2u))
	46	#define dspsc \
	47	literal ("dspsc"), tick_random
	48
	49	/* This outputs the condition flag that may follow each ARM insn.
cce4814f NC	50	Since the condition 15 is invalid, we use it to check that the
	51	assembler recognizes the absence of a condition as `al'. However,
	52	the disassembler won't ever output `al', so, if we emit it in the
	53	assembler, expect the condition to be omitted in the disassembler
	54	output. */
	55
9ac3a342	56	int
cce4814f	57	arm_cond (func_arg * arg, insn_data * data)
9ac3a342 AH	58	#define arm_cond { arm_cond }
9ac3a342 AH	59	{
cce4814f NC	60	static const char conds[16][3] =
	61	{
	62	"eq", "ne", "cs", "cc",
	63	"mi", "pl", "vs", "vc",
	64	"hi", "ls", "ge", "lt",
	65	"gt", "le", "al", ""
	66	};
9ac3a342 AH	67	unsigned val = get_bits (4u);
	68
	69	data->as_in = data->dis_out = strdup (conds[val]);
	70	if (val == 14)
	71	data->dis_out = strdup ("");
	72	data->bits = (val == 15 ? 14 : val) << 28;
	73	return 0;
	74	}
	75
	76	/* The sign of an offset is actually used to determined whether the
cce4814f	77	absolute value of the offset should be added or subtracted, so we
06516a5e	78	must adjust negative values so that they do not overflow: -1024 is
cce4814f	79	not valid, but -0 is distinct from +0. */
9ac3a342	80	int
cce4814f	81	off8s (func_arg * arg, insn_data * data)
9ac3a342 AH	82	#define off8s { off8s }
9ac3a342 AH	83	{
cce4814f	84	int val;
06516a5e	85	char value[9];
cce4814f	86
06516a5e	87	/* Zero values are problematical.
cce4814f NC	88	The assembler performs translations on the addressing modes
	89	for these values, meaning that we cannot just recreate the
	90	disassembler string in the LDST macro without knowing what
	91	value had been generated in off8s. */
	92	do
	93	{
	94	val = get_bits (9s);
	95	}
06516a5e	96	while (val == -1 \|\| val == 0);
cce4814f	97
06516a5e	98	val <<= 2;
9ac3a342 AH	99	if (val < 0)
9ac3a342 AH	100	{
06516a5e	101	val = -4 - val;
eb4286fc	102	sprintf (value, ", #-%i", val);
cce4814f NC	103	data->dis_out = strdup (value);
	104	sprintf (value, ", #-%i", val);
	105	data->as_in = strdup (value);
06516a5e	106	data->bits = val >> 2;
9ac3a342 AH	107	}
9ac3a342 AH	108	else
cce4814f	109	{
cce4814f NC	110	sprintf (value, ", #%i", val);
cce4814f NC	111	data->as_in = data->dis_out = strdup (value);
06516a5e	112	data->bits = (val >> 2) \| (1 << 23);
cce4814f NC	113	}
cce4814f NC	114
9ac3a342 AH	115	return 0;
	116	}
	117
	118	/* This function generates a 7-bit signed constant, emitted as
cce4814f NC	119	follows: the 4 least-significant bits are stored in the 4
	120	least-significant bits of the word; the 3 most-significant bits are
	121	stored in bits 7:5, i.e., bit 4 is skipped. */
9ac3a342 AH	122	int
	123	imm7 (func_arg arg, insn_data data)
	124	#define imm7 { imm7 }
	125	{
	126	int val = get_bits (7s);
	127	char value[6];
	128
	129	data->bits = (val & 0x0f) \| (2 * (val & 0x70));
	130	sprintf (value, "#%i", val);
	131	data->as_in = data->dis_out = strdup (value);
	132	return 0;
	133	}
	134
	135	/* Convenience wrapper to define_insn, that prefixes every insn with
cce4814f NC	136	`cf' (so, if you specify command-line arguments, remember that `cf'
	137	must not be part of the string), and post-fixes a condition code.
	138	insname and insnvar specify the main insn name and a variant;
	139	they're just concatenated, and insnvar is often empty. word is the
	140	bit pattern that defines the insn, properly shifted, and funcs is a
	141	sequence of funcs that define the operands and the syntax of the
	142	insn. */
9ac3a342	143	#define mv_insn(insname, insnvar, word, funcs...) \
cce4814f	144	define_insn (insname ## insnvar, \
9ac3a342 AH	145	literal ("cf"), \
	146	insn_bits (insname, word), \
	147	arm_cond, \
	148	tab, \
	149	## funcs)
	150
	151	/* Define a single LDC/STC variant. op is the main insn opcode; ld
cce4814f NC	152	stands for load (it should be 0 on stores), dword selects 64-bit
	153	operations, pre should be enabled for pre-increment, and wb, for
	154	write-back. sep1, sep2 and sep3 are syntactical elements ([]!)
	155	that the assembler will use to enable pre and wb. It would
	156	probably have been cleaner to couple the syntactical elements with
	157	the pre/wb bits directly, but it would have required the definition
	158	of more functions. */
9ac3a342 AH	159	#define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \
9ac3a342 AH	160	mv_insn (insname, insnvar, \
cce4814f	161	(12 << 24) \| (op << 8) \| (ld << 20) \| (pre << 24) \| (dword << 22) \| (wb << 21), \
9ac3a342	162	mvreg (regname, 12), comma, \
cce4814f	163	lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \
9ac3a342 AH	164	tick_random)
	165
	166	/* Define all variants of an LDR or STR instruction, namely,
cce4814f NC	167	pre-indexed without write-back, pre-indexed with write-back and
cce4814f NC	168	post-indexed. */
9ac3a342 AH	169	#define LDSTall(insname, op, ld, dword, regname) \
9ac3a342 AH	170	LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \
cce4814f NC	171	LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \
cce4814f NC	172	LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing)
9ac3a342 AH	173
9ac3a342 AH	174	/* Produce the insn identifiers of all LDST variants of a given insn.
cce4814f	175	To be used in the initialization of an insn group array. */
9ac3a342 AH	176	#define insns_LDSTall(insname) \
	177	insn (insname ## _p), insn (insname ## _pw), insn (insname)
	178
	179	/* Define a CDP variant that uses two registers, at offsets 12 and 16.
cce4814f NC	180	The two opcodes and the co-processor number identify the CDP
cce4814f NC	181	insn. */
9ac3a342 AH	182	#define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \
9ac3a342 AH	183	mv_insn (insname##var, , \
cce4814f	184	(14 << 24) \| ((opcode1) << 20) \| ((cpnum) << 8) \| ((opcode2) << 5), \
9ac3a342 AH	185	mvreg (reg1name, 12), comma, mvreg (reg2name, 16))
	186
	187	/* Define a 32-bit integer CDP instruction with two operands. */
	188	#define CDP2fx(insname, opcode1, opcode2) \
	189	CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")
	190
	191	/* Define a 64-bit integer CDP instruction with two operands. */
	192	#define CDP2dx(insname, opcode1, opcode2) \
	193	CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")
	194
	195	/* Define a float CDP instruction with two operands. */
	196	#define CDP2f(insname, opcode1, opcode2) \
	197	CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")
	198
	199	/* Define a double CDP instruction with two operands. */
	200	#define CDP2d(insname, opcode1, opcode2) \
	201	CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")
	202
	203	/* Define a CDP instruction with two register operands and one 7-bit
cce4814f	204	signed immediate generated with imm7. */
9ac3a342	205	#define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \
cce4814f	206	mv_insn (insname, , (14 << 24) \| ((opcode1) << 20) \| ((cpnum) << 8), \
9ac3a342 AH	207	mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
	208	tick_random)
	209
	210	/* Produce the insn identifiers of CDP floating-point or integer insn
cce4814f NC	211	pairs (i.e., it appends the suffixes for 32-bit and 64-bit
cce4814f NC	212	insns. */
9ac3a342 AH	213	#define CDPfp_insns(insname) \
	214	insn (insname ## s), insn (insname ## d)
	215	#define CDPx_insns(insname) \
	216	insn (insname ## 32), insn (insname ## 64)
	217
	218	/* Define a CDP instruction with 3 operands, at offsets 12, 16, 0. */
	219	#define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \
	220	mv_insn (insname##var, , \
cce4814f	221	(14 << 24) \| ((opcode1) << 20) \| ((cpnum) << 8) \| ((opcode2) << 5), \
9ac3a342 AH	222	mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \
	223	mvreg (reg3name, 0), tick_random)
	224
	225	/* Define a 32-bit integer CDP instruction with three operands. */
	226	#define CDP3fx(insname, opcode1, opcode2) \
	227	CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")
	228
	229	/* Define a 64-bit integer CDP instruction with three operands. */
	230	#define CDP3dx(insname, opcode1, opcode2) \
	231	CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")
	232
	233	/* Define a float CDP instruction with three operands. */
	234	#define CDP3f(insname, opcode1, opcode2) \
	235	CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")
	236
	237	/* Define a double CDP instruction with three operands. */
	238	#define CDP3d(insname, opcode1, opcode2) \
	239	CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")
	240
	241	/* Define a CDP instruction with four operands, at offsets 5, 12, 16
	242	* and 0. Used only for ACC instructions. */
	243	#define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \
cce4814f	244	mv_insn (insname, , (14 << 24) \| ((opcode1) << 20) \| (6 << 8), \
9ac3a342 AH	245	acreg (5), comma, reg2spec, comma, \
	246	mvreg (reg3name, 16), comma, mvreg (reg4name, 0))
	247
	248	/* Define a CDP4 instruction with one accumulator operands. */
	249	#define CDP41A(insname, opcode1) \
	250	CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")
	251
	252	/* Define a CDP4 instruction with two accumulator operands. */
	253	#define CDP42A(insname, opcode1) \
	254	CDP4 (insname, opcode1, acreg (12), "fx", "fx")
	255
	256	/* Define a MCR or MRC instruction with two register operands. */
	257	#define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \
	258	mv_insn (insname, , \
cce4814f NC	259	((14 << 24) \| ((opcode1) << 21) \| ((dir) << 20)\| \
cce4814f NC	260	((cpnum) << 8) \| ((opcode2) << 5) \| (1 << 4)), \
9ac3a342 AH	261	reg1spec, comma, reg2spec)
	262
	263	/* Define a move from a DSP register to an ARM register. */
	264	#define MVDSPARM(insname, cpnum, opcode2, regDSPname) \
	265	MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \
cce4814f	266	mvreg (regDSPname, 16), armreg (12))
9ac3a342 AH	267
	268	/* Define a move from an ARM register to a DSP register. */
	269	#define MVARMDSP(insname, cpnum, opcode2, regDSPname) \
	270	MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
	271	armreg (12), mvreg (regDSPname, 16))
	272
06516a5e PB	273	/* Move between coprocessor registers. A two operand CDP insn. */
	274	#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \
	275	mv_insn (insname, , \
	276	((14 << 24) \| ((opcode1) << 20) \| \
	277	(4 << 8) \| ((opcode2) << 5)), \
	278	reg1spec, comma, reg2spec)
	279
9ac3a342 AH	280	/* Define a move from a DSP register to a DSP accumulator. */
9ac3a342 AH	281	#define MVDSPACC(insname, opcode2, regDSPname) \
06516a5e	282	MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))
9ac3a342 AH	283
	284	/* Define a move from a DSP accumulator to a DSP register. */
	285	#define MVACCDSP(insname, opcode2, regDSPname) \
06516a5e	286	MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))
9ac3a342 AH	287
9ac3a342 AH	288	/* Define move insns between a float DSP register and an ARM
cce4814f	289	register. */
9ac3a342 AH	290	#define MVf(nameAD, nameDA, opcode2) \
	291	MVDSPARM (nameAD, 4, opcode2, "f"); \
	292	MVARMDSP (nameDA, 4, opcode2, "f")
	293
	294	/* Define move insns between a double DSP register and an ARM
cce4814f	295	register. */
9ac3a342 AH	296	#define MVd(nameAD, nameDA, opcode2) \
	297	MVDSPARM (nameAD, 4, opcode2, "d"); \
	298	MVARMDSP (nameDA, 4, opcode2, "d")
	299
	300	/* Define move insns between a 32-bit integer DSP register and an ARM
cce4814f	301	register. */
9ac3a342 AH	302	#define MVfx(nameAD, nameDA, opcode2) \
	303	MVDSPARM (nameAD, 5, opcode2, "fx"); \
	304	MVARMDSP (nameDA, 5, opcode2, "fx")
	305
	306	/* Define move insns between a 64-bit integer DSP register and an ARM
cce4814f	307	register. */
9ac3a342 AH	308	#define MVdx(nameAD, nameDA, opcode2) \
	309	MVDSPARM (nameAD, 5, opcode2, "dx"); \
	310	MVARMDSP (nameDA, 5, opcode2, "dx")
	311
	312	/* Define move insns between a 32-bit DSP register and a DSP
cce4814f	313	accumulator. */
9ac3a342 AH	314	#define MVfxa(nameFA, nameAF, opcode2) \
	315	MVDSPACC (nameFA, opcode2, "fx"); \
	316	MVACCDSP (nameAF, opcode2, "fx")
	317
	318	/* Define move insns between a 64-bit DSP register and a DSP
cce4814f	319	accumulator. */
9ac3a342 AH	320	#define MVdxa(nameDA, nameAD, opcode2) \
	321	MVDSPACC (nameDA, opcode2, "dx"); \
	322	MVACCDSP (nameAD, opcode2, "dx")
	323
	324	/* Produce the insn identifiers for a pair of mv insns. */
	325	#define insns_MV(name1, name2) \
	326	insn (mv ## name1), insn (mv ## name2)
	327
	328	/* Define a MCR or MRC instruction with three register operands. */
	329	#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \
	330	mv_insn (insname, , \
cce4814f NC	331	((14 << 24) \| ((opcode1) << 21) \| ((dir) << 20)\| \
cce4814f NC	332	((cpnum) << 8) \| ((opcode2) << 5) \| (1 << 4)), \
9ac3a342 AH	333	reg1spec, comma, reg2spec, comma, reg3spec, \
	334	tick_random)
	335
	336	/* Define all load_store insns. */
	337	LDSTall (ldrs, 4, 1, 0, "f");
	338	LDSTall (ldrd, 4, 1, 1, "d");
	339	LDSTall (ldr32, 5, 1, 0, "fx");
	340	LDSTall (ldr64, 5, 1, 1, "dx");
	341	LDSTall (strs, 4, 0, 0, "f");
	342	LDSTall (strd, 4, 0, 1, "d");
	343	LDSTall (str32, 5, 0, 0, "fx");
	344	LDSTall (str64, 5, 0, 1, "dx");
	345
	346	/* Create the load_store insn group. */
cce4814f NC	347	func *load_store_insns[] =
	348	{
	349	insns_LDSTall (ldrs), insns_LDSTall (ldrd),
	350	insns_LDSTall (ldr32), insns_LDSTall (ldr64),
	351	insns_LDSTall (strs), insns_LDSTall (strd),
	352	insns_LDSTall (str32), insns_LDSTall (str64),
	353	0
	354	};
9ac3a342 AH	355
	356	/* Define all move insns. */
	357	MVf (sr, rs, 2);
	358	MVd (dlr, rdl, 0);
	359	MVd (dhr, rdh, 1);
	360	MVdx (64lr, r64l, 0);
	361	MVdx (64hr, r64h, 1);
06516a5e PB	362	MVfxa (al32, 32al, 2);
	363	MVfxa (am32, 32am, 3);
	364	MVfxa (ah32, 32ah, 4);
	365	MVfxa (a32, 32a, 5);
	366	MVdxa (a64, 64a, 6);
	367	MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12));
	368	MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc);
9ac3a342 AH	369	CDP2 (cpys, , 4, 0, 0, "f", "f");
	370	CDP2 (cpyd, , 4, 0, 1, "d", "d");
	371
	372	/* Create the move insns group. */
cce4814f NC	373	func * move_insns[] =
	374	{
	375	insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
	376	insns_MV (64lr, r64l), insns_MV (64hr, r64h),
	377	insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
	378	insns_MV (a32, 32a), insns_MV (a64, 64a),
	379	insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
	380	0
	381	};
9ac3a342 AH	382
	383	/* Define all conversion insns. */
	384	CDP2 (cvtsd, , 4, 0, 3, "d", "f");
	385	CDP2 (cvtds, , 4, 0, 2, "f", "d");
	386	CDP2 (cvt32s, , 4, 0, 4, "f", "fx");
	387	CDP2 (cvt32d, , 4, 0, 5, "d", "fx");
	388	CDP2 (cvt64s, , 4, 0, 6, "f", "dx");
	389	CDP2 (cvt64d, , 4, 0, 7, "d", "dx");
	390	CDP2 (cvts32, , 5, 1, 4, "fx", "f");
	391	CDP2 (cvtd32, , 5, 1, 5, "fx", "d");
	392	CDP2 (truncs32, , 5, 1, 6, "fx", "f");
	393	CDP2 (truncd32, , 5, 1, 7, "fx", "d");
	394
	395	/* Create the conv insns group. */
cce4814f NC	396	func * conv_insns[] =
	397	{
	398	insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
	399	insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
	400	insn (truncs32), insn (truncd32),
	401	0
	402	};
9ac3a342 AH	403
9ac3a342 AH	404	/* Define all shift insns. */
cce4814f NC	405	MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg (12));
cce4814f NC	406	MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg (12));
9ac3a342 AH	407	CDP2_imm7 (sh32, 5, 0, "fx", "fx");
	408	CDP2_imm7 (sh64, 5, 2, "dx", "dx");
	409
	410	/* Create the shift insns group. */
cce4814f NC	411	func *shift_insns[] =
	412	{
	413	insn (rshl32), insn (rshl64),
	414	insn (sh32), insn (sh64),
	415	0
	416	};
9ac3a342 AH	417
	418	/* Define all comparison insns. */
	419	MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0));
	420	MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0));
	421	MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0));
	422	MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0));
	423
	424	/* Create the comp insns group. */
cce4814f NC	425	func *comp_insns[] =
	426	{
	427	insn (cmps), insn (cmpd),
	428	insn (cmp32), insn (cmp64),
	429	0
	430	};
9ac3a342 AH	431
	432	/* Define all floating-point arithmetic insns. */
	433	CDP2f (abs, 3, 0);
	434	CDP2d (abs, 3, 1);
	435	CDP2f (neg, 3, 2);
	436	CDP2d (neg, 3, 3);
	437	CDP3f (add, 3, 4);
	438	CDP3d (add, 3, 5);
	439	CDP3f (sub, 3, 6);
	440	CDP3d (sub, 3, 7);
	441	CDP3f (mul, 1, 0);
	442	CDP3d (mul, 1, 1);
	443
	444	/* Create the fp-arith insns group. */
cce4814f NC	445	func *fp_arith_insns[] =
	446	{
	447	CDPfp_insns (abs), CDPfp_insns (neg),
	448	CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul),
	449	0
	450	};
9ac3a342 AH	451
	452	/* Define all integer arithmetic insns. */
	453	CDP2fx (abs, 3, 0);
	454	CDP2dx (abs, 3, 1);
	455	CDP2fx (neg, 3, 2);
	456	CDP2dx (neg, 3, 3);
	457	CDP3fx (add, 3, 4);
	458	CDP3dx (add, 3, 5);
	459	CDP3fx (sub, 3, 6);
	460	CDP3dx (sub, 3, 7);
	461	CDP3fx (mul, 1, 0);
	462	CDP3dx (mul, 1, 1);
	463	CDP3fx (mac, 1, 2);
	464	CDP3fx (msc, 1, 3);
	465
	466	/* Create the int-arith insns group. */
cce4814f NC	467	func * int_arith_insns[] =
	468	{
	469	CDPx_insns (abs), CDPx_insns (neg),
	470	CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
	471	insn (mac32), insn (msc32),
	472	0
	473	};
9ac3a342 AH	474
	475	/* Define all accumulator arithmetic insns. */
	476	CDP41A (madd32, 0);
	477	CDP41A (msub32, 1);
	478	CDP42A (madda32, 2);
	479	CDP42A (msuba32, 3);
	480
	481	/* Create the acc-arith insns group. */
cce4814f NC	482	func * acc_arith_insns[] =
	483	{
	484	insn (madd32), insn (msub32),
	485	insn (madda32), insn (msuba32),
	486	0
	487	};
9ac3a342 AH	488
9ac3a342 AH	489	/* Create the set of all groups. */
cce4814f NC	490	group_t groups[] =
	491	{
	492	{ "load_store", load_store_insns },
	493	{ "move", move_insns },
	494	{ "conv", conv_insns },
	495	{ "shift", shift_insns },
	496	{ "comp", comp_insns },
	497	{ "fp_arith", fp_arith_insns },
	498	{ "int_arith", int_arith_insns },
	499	{ "acc_arith", acc_arith_insns },
	500	{ 0 }
	501	};
9ac3a342 AH	502
9ac3a342 AH	503	int
cce4814f	504	main (int argc, char *argv[])
9ac3a342 AH	505	{
	506	FILE as_in = stdout, dis_out = stderr;
	507
	508	/* Check whether we're filtering insns. */
	509	if (argc > 1)
	510	skip_list = argv + 1;
	511
	512	/* Output assembler header. */
	513	fputs ("\t.text\n"
	514	"\t.align\n",
	515	as_in);
	516	/* Output comments for the testsuite-driver and the initial
cce4814f	517	disassembler output. */
9ac3a342 AH	518	fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
9ac3a342 AH	519	"#name: Maverick\n"
cce4814f	520	"#as: -mcpu=ep9312\n"
9ac3a342	521	"\n"
cce4814f	522	"# Test the instructions of the Cirrus Maverick floating point co-processor\n"
9ac3a342 AH	523	"\n"
	524	".: +file format.arm.*\n"
	525	"\n"
	526	"Disassembly of section .text:\n",
	527	dis_out);
	528
	529	/* Now emit all (selected) insns. */
	530	output_groups (groups, as_in, dis_out);
	531
	532	exit (0);
	533	}