projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a8465a06 AV |
1 | [^:]*: Assembler messages: |
| 2 | [^:]*:10: Error: bad type in SIMD instruction -- `vmla.f16 q0,q1,r2' | |
| 3 | [^:]*:11: Error: bad type in SIMD instruction -- `vmla.s64 q0,q1,r2' | |
| 4 | [^:]*:12: Error: selected FPU does not support instruction -- `vmla.s32 q0,q1,q2' | |
| 5 | [^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand | |
| 6 | [^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand | |
| 7 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 8 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 9 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 10 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 11 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 12 | [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block | |
| 13 | [^:]*:17: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' | |
| 14 | [^:]*:18: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' | |
| 15 | [^:]*:20: Error: syntax error -- `vmlaeq.u16 q0,q1,r2' | |
| 16 | [^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmlat.u16 q0,q1,r2' | |
| 17 | [^:]*:23: Error: instruction missing MVE vector predication code -- `vmla.u16 q0,q1,r2' |