Commit | Line | Data |
---|---|---|
a302e574 AV |
1 | [^:]*: Assembler messages: |
2 | [^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block | |
3 | [^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block | |
4 | [^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block | |
5 | [^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block | |
6 | [^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block | |
7 | [^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block | |
8 | [^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block | |
9 | [^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block | |
10 | [^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block | |
11 | [^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block | |
12 | [^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block | |
13 | [^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block | |
14 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
15 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
16 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
17 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
18 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
19 | [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block | |
20 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
21 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
22 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
23 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
24 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
25 | [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block | |
26 | [^:]*:14: Error: bad type in SIMD instruction -- `vmladav.s64 r0,q1,q2' | |
27 | [^:]*:15: Error: bad type in SIMD instruction -- `vmladav.f32 r0,q1,q2' | |
28 | [^:]*:16: Error: bad type in SIMD instruction -- `vmladava.s64 r0,q1,q2' | |
29 | [^:]*:17: Error: bad type in SIMD instruction -- `vmladava.f32 r0,q1,q2' | |
30 | [^:]*:18: Error: bad type in SIMD instruction -- `vmladavx.s64 r0,q1,q2' | |
31 | [^:]*:19: Error: bad type in SIMD instruction -- `vmladavx.f32 r0,q1,q2' | |
32 | [^:]*:20: Error: bad type in SIMD instruction -- `vmladavax.s64 r0,q1,q2' | |
33 | [^:]*:21: Error: bad type in SIMD instruction -- `vmladavax.f32 r0,q1,q2' | |
34 | [^:]*:22: Error: bad type in SIMD instruction -- `vmladavx.u32 r0,q1,q2' | |
35 | [^:]*:23: Error: bad type in SIMD instruction -- `vmladavax.u16 r0,q1,q2' | |
36 | [^:]*:25: Error: syntax error -- `vmladaveq.s32 r0,q1,q2' | |
37 | [^:]*:26: Error: syntax error -- `vmladaveq.s32 r0,q1,q2' | |
38 | [^:]*:28: Error: syntax error -- `vmladaveq.s32 r0,q1,q2' | |
39 | [^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavt.s32 r0,q1,q2' | |
40 | [^:]*:31: Error: instruction missing MVE vector predication code -- `vmladav.s32 r0,q1,q2' | |
41 | [^:]*:33: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2' | |
42 | [^:]*:34: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2' | |
43 | [^:]*:36: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2' | |
44 | [^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavat.s32 r0,q1,q2' | |
45 | [^:]*:39: Error: instruction missing MVE vector predication code -- `vmladava.s32 r0,q1,q2' | |
46 | [^:]*:41: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2' | |
47 | [^:]*:42: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2' | |
48 | [^:]*:44: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2' | |
49 | [^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavxt.s32 r0,q1,q2' | |
50 | [^:]*:47: Error: instruction missing MVE vector predication code -- `vmladavx.s32 r0,q1,q2' | |
51 | [^:]*:49: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2' | |
52 | [^:]*:50: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2' | |
53 | [^:]*:52: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2' | |
54 | [^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavaxt.s32 r0,q1,q2' | |
55 | [^:]*:55: Error: instruction missing MVE vector predication code -- `vmladavax.s32 r0,q1,q2' |