[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / mve-vmlaldav-bad.l

[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Error: bad type in SIMD instruction -- `vmlaldav.s64 r0,r1,q1,q2'
[^:]*:16: Error: bad type in SIMD instruction -- `vmlaldav.f32 r0,r1,q1,q2'
[^:]*:17: Error: bad type in SIMD instruction -- `vmlaldav.s8 r0,r1,q1,q2'
[^:]*:18: Error: ARM register expected -- `vmlaldav.s16 r0,q1,q2'
[^:]*:19: Error: bad type in SIMD instruction -- `vmlaldava.s64 r0,r1,q1,q2'
[^:]*:20: Error: bad type in SIMD instruction -- `vmlaldava.f32 r0,r1,q1,q2'
[^:]*:21: Error: bad type in SIMD instruction -- `vmlaldava.s8 r0,r1,q1,q2'
[^:]*:22: Error: ARM register expected -- `vmlaldava.s16 r0,q1,q2'
[^:]*:23: Error: bad type in SIMD instruction -- `vmlaldavx.s64 r0,r1,q1,q2'
[^:]*:24: Error: bad type in SIMD instruction -- `vmlaldavx.f32 r0,r1,q1,q2'
[^:]*:25: Error: bad type in SIMD instruction -- `vmlaldavx.s8 r0,r1,q1,q2'
[^:]*:26: Error: ARM register expected -- `vmlaldavx.s16 r0,q1,q2'
[^:]*:27: Error: bad type in SIMD instruction -- `vmlaldavax.s64 r0,r1,q1,q2'
[^:]*:28: Error: bad type in SIMD instruction -- `vmlaldavax.f32 r0,r1,q1,q2'
[^:]*:29: Error: bad type in SIMD instruction -- `vmlaldavax.s8 r0,r1,q1,q2'
[^:]*:30: Error: ARM register expected -- `vmlaldavax.s16 r0,q1,q2'
[^:]*:32: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
[^:]*:33: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
[^:]*:34: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavt.s16 r0,r1,q1,q2'
[^:]*:37: Error: instruction missing MVE vector predication code -- `vmlaldav.s16 r0,r1,q1,q2'
[^:]*:39: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
[^:]*:40: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
[^:]*:41: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
[^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavat.s16 r0,r1,q1,q2'
[^:]*:44: Error: instruction missing MVE vector predication code -- `vmlaldava.s16 r0,r1,q1,q2'
[^:]*:46: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
[^:]*:47: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
[^:]*:48: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
[^:]*:49: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavxt.s16 r0,r1,q1,q2'
[^:]*:51: Error: instruction missing MVE vector predication code -- `vmlaldavx.s16 r0,r1,q1,q2'
[^:]*:53: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
[^:]*:54: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
[^:]*:55: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
[^:]*:56: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavaxt.s16 r0,r1,q1,q2'
[^:]*:58: Error: instruction missing MVE vector predication code -- `vmlaldavax.s16 r0,r1,q1,q2'
Commit	Line	Data
93925576 AV	1	[^:]*: Assembler messages:
	2	[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
	3	[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
	4	[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
	5	[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
	6	[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
	7	[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
	8	[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
	9	[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
	10	[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
	11	[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
	12	[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
	13	[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
	14	[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
	15	[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
	16	[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
	17	[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
	18	[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
	19	[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
	20	[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
	21	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	22	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	23	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	24	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	25	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	26	[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
	27	[^:]*:15: Error: bad type in SIMD instruction -- `vmlaldav.s64 r0,r1,q1,q2'
	28	[^:]*:16: Error: bad type in SIMD instruction -- `vmlaldav.f32 r0,r1,q1,q2'
	29	[^:]*:17: Error: bad type in SIMD instruction -- `vmlaldav.s8 r0,r1,q1,q2'
	30	[^:]*:18: Error: ARM register expected -- `vmlaldav.s16 r0,q1,q2'
	31	[^:]*:19: Error: bad type in SIMD instruction -- `vmlaldava.s64 r0,r1,q1,q2'
	32	[^:]*:20: Error: bad type in SIMD instruction -- `vmlaldava.f32 r0,r1,q1,q2'
	33	[^:]*:21: Error: bad type in SIMD instruction -- `vmlaldava.s8 r0,r1,q1,q2'
	34	[^:]*:22: Error: ARM register expected -- `vmlaldava.s16 r0,q1,q2'
	35	[^:]*:23: Error: bad type in SIMD instruction -- `vmlaldavx.s64 r0,r1,q1,q2'
	36	[^:]*:24: Error: bad type in SIMD instruction -- `vmlaldavx.f32 r0,r1,q1,q2'
	37	[^:]*:25: Error: bad type in SIMD instruction -- `vmlaldavx.s8 r0,r1,q1,q2'
	38	[^:]*:26: Error: ARM register expected -- `vmlaldavx.s16 r0,q1,q2'
	39	[^:]*:27: Error: bad type in SIMD instruction -- `vmlaldavax.s64 r0,r1,q1,q2'
	40	[^:]*:28: Error: bad type in SIMD instruction -- `vmlaldavax.f32 r0,r1,q1,q2'
	41	[^:]*:29: Error: bad type in SIMD instruction -- `vmlaldavax.s8 r0,r1,q1,q2'
	42	[^:]*:30: Error: ARM register expected -- `vmlaldavax.s16 r0,q1,q2'
	43	[^:]*:32: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
	44	[^:]*:33: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
	45	[^:]*:34: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
	46	[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavt.s16 r0,r1,q1,q2'
	47	[^:]*:37: Error: instruction missing MVE vector predication code -- `vmlaldav.s16 r0,r1,q1,q2'
	48	[^:]*:39: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
	49	[^:]*:40: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
	50	[^:]*:41: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
	51	[^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavat.s16 r0,r1,q1,q2'
	52	[^:]*:44: Error: instruction missing MVE vector predication code -- `vmlaldava.s16 r0,r1,q1,q2'
	53	[^:]*:46: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
	54	[^:]*:47: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
	55	[^:]*:48: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
	56	[^:]*:49: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavxt.s16 r0,r1,q1,q2'
	57	[^:]*:51: Error: instruction missing MVE vector predication code -- `vmlaldavx.s16 r0,r1,q1,q2'
	58	[^:]*:53: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
	59	[^:]*:54: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
	60	[^:]*:55: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
	61	[^:]*:56: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavaxt.s16 r0,r1,q1,q2'
	62	[^:]*:58: Error: instruction missing MVE vector predication code -- `vmlaldavax.s16 r0,r1,q1,q2'