Commit | Line | Data |
---|---|---|
a8465a06 AV |
1 | [^:]*: Assembler messages: |
2 | [^:]*:10: Error: bad type in SIMD instruction -- `vqadd.s64 q0,q1,q2' | |
3 | [^:]*:11: Error: bad type in SIMD instruction -- `vqsub.u64 q0,q1,q2' | |
4 | [^:]*:12: Error: bad type in SIMD instruction -- `vqadd.s64 q0,q1,r2' | |
5 | [^:]*:13: Error: bad type in SIMD instruction -- `vqsub.s64 q0,q1,r2' | |
6 | [^:]*:14: Error: bad type in SIMD instruction -- `vqadd.f32 q0,q1,q2' | |
7 | [^:]*:15: Error: bad type in SIMD instruction -- `vqsub.f32 q0,q1,q2' | |
8 | [^:]*:16: Error: bad type in SIMD instruction -- `vqadd.f32 q0,q1,r2' | |
9 | [^:]*:17: Error: bad type in SIMD instruction -- `vqsub.f32 q0,q1,r2' | |
10 | [^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand | |
11 | [^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand | |
12 | [^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand | |
13 | [^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand | |
14 | [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block | |
15 | [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block | |
16 | [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block | |
17 | [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block | |
18 | [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block | |
19 | [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block | |
20 | [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block | |
21 | [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block | |
22 | [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block | |
23 | [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block | |
24 | [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block | |
25 | [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block | |
26 | [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block | |
27 | [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block | |
28 | [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block | |
29 | [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block | |
30 | [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block | |
31 | [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block | |
32 | [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block | |
33 | [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block | |
34 | [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block | |
35 | [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block | |
36 | [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block | |
37 | [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block | |
38 | [^:]*:27: Error: syntax error -- `vqaddeq.s32 q0,q1,q2' | |
39 | [^:]*:28: Error: syntax error -- `vqaddeq.s32 q0,q1,q2' | |
40 | [^:]*:30: Error: syntax error -- `vqaddeq.s32 q0,q1,q2' | |
41 | [^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vqaddt.s32 q0,q1,q2' | |
42 | [^:]*:33: Error: instruction missing MVE vector predication code -- `vqadd.s32 q0,q1,q2' | |
43 | [^:]*:35: Error: syntax error -- `vqsubeq.s32 q0,q1,q2' | |
44 | [^:]*:36: Error: syntax error -- `vqsubeq.s32 q0,q1,q2' | |
45 | [^:]*:38: Error: syntax error -- `vqsubeq.s32 q0,q1,q2' | |
46 | [^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vqsubt.s32 q0,q1,q2' | |
47 | [^:]*:41: Error: instruction missing MVE vector predication code -- `vqsub.s32 q0,q1,q2' | |
48 | [^:]*:43: Error: syntax error -- `vqaddeq.s32 q0,q1,r2' | |
49 | [^:]*:44: Error: syntax error -- `vqaddeq.s32 q0,q1,r2' | |
50 | [^:]*:46: Error: syntax error -- `vqaddeq.s32 q0,q1,r2' | |
51 | [^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vqaddt.s32 q0,q1,r2' | |
52 | [^:]*:49: Error: instruction missing MVE vector predication code -- `vqadd.s32 q0,q1,r2' | |
53 | [^:]*:51: Error: syntax error -- `vqsubeq.s32 q0,q1,r2' | |
54 | [^:]*:52: Error: syntax error -- `vqsubeq.s32 q0,q1,r2' | |
55 | [^:]*:54: Error: syntax error -- `vqsubeq.s32 q0,q1,r2' | |
56 | [^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vqsubt.s32 q0,q1,r2' | |
57 | [^:]*:57: Error: instruction missing MVE vector predication code -- `vqsub.s32 q0,q1,r2' |