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[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M Baseline
[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / sp-pc-validations-bad-t.s
CommitLineData
5be8be5d 1.syntax unified
5c8ed6a4 2@ Enable Thumb mode
5be8be5d 3.thumb
5be8be5d
DG		 4.macro it_test opcode operands:vararg
5itt eq
6\opcode\()eq r15, \operands
7moveq r0, r0
8.endm
9
10.macro it_testw opcode operands:vararg
11itt eq
12\opcode\()eq.w r15, \operands
13moveq r0, r0
14.endm
15
16.macro LOAD operands:vararg
17it_test ldr, \operands
18.endm
19
20.macro LOADw operands:vararg
21it_testw ldr, \operands
22.endm
23
24@ Loads ===============================================================
25
26@ LDR (register)
27LOAD [r0]
28LOAD [r0,#0]
29LOAD [sp]
30LOAD [sp,#0]
31LOADw [r0]
32LOADw [r0,#0]
33LOAD [r0,#-4]
34LOAD [r0],#4
35LOAD [r0,#0]!
36
37@ LDR (literal)
38LOAD label
39LOADw label
40LOADw [pc, #-0]
41
42@ LDR (register)
43LOAD [r0, r1]
44LOADw [r0, r1]
45LOADw [r0, r1, LSL #2]
46
47@ LDRB (immediate, Thumb)
48ldrb pc, [r0,#4] @ low reg
49@ldrb r0, [pc,#4] @ ALLOWED!
50ldrb.w sp, [r0,#4] @ Unpredictable
51ldrb.w pc, [r0,#4] @ => PLD
52ldrb pc, [r0, #-4] @ => PLD
53@ LDRB<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRBT
54ldrb pc, [r0],#4 @ BadReg
55ldrb sp, [r0],#4 @ ditto
56ldrb pc,[r0,#4]! @ ditto
57ldrb sp,[r0,#4]! @ ditto
58
59@ LDRB (literal)
60ldrb pc,label @ => PLD
61ldrb pc,[PC,#-0] @ => PLD (special case)
62ldrb sp,label @ Unpredictable
63ldrb sp,[PC,#-0] @ ditto
64
65@ LDRB (register)
66ldrb pc,[r0,r1] @ low reg
67ldrb r0,[pc,r1] @ ditto
68ldrb r0,[r1,pc] @ ditto
69ldrb.w pc,[r0,r1,LSL #1] @ => PLD
70ldrb.w sp,[r0,r1] @ Unpredictable
71ldrb.w r2,[r0,pc,LSL #2] @ BadReg
72ldrb.w r2,[r0,sp,LSL #2] @ ditto
73
74@ LDRBT
75ldrbt pc, [r0, #4] @ BadReg
76ldrbt sp, [r0, #4] @ ditto
77
78@ LDRD (immediate)
79ldrd pc, r0, [r1] @ BadReg
80ldrd sp, r0, [r1] @ ditto
bd340a04
MGD		 81ldrd r12, [r1] @ ditto
82ldrd r14, [r1] @ ditto
5be8be5d
DG		 83ldrd r0, pc, [r1] @ ditto
84ldrd r0, sp, [r1] @ ditto
85ldrd pc, r0, [r1], #4 @ ditto
86ldrd sp, r0, [r1], #4 @ ditto
87ldrd r0, pc, [r1], #4 @ ditto
88ldrd r0, sp, [r1], #4 @ ditto
bd340a04
MGD		 89ldrd r12, [r1], #4 @ ditto
90ldrd r14, [r1], #4 @ ditto
5be8be5d
DG		 91ldrd pc, r0, [r1, #4]! @ ditto
92ldrd sp, r0, [r1, #4]! @ ditto
93ldrd r0, pc, [r1, #4]! @ ditto
94ldrd r0, sp, [r1, #4]! @ ditto
bd340a04
MGD		 95ldrd r12, [r1, #4]! @ ditto
96ldrd r14, [r1, #4]! @ ditto
5be8be5d
DG		 97
98@ LDRD (literal)
99ldrd pc, r0, label @ BadReg
100ldrd sp, r0, label @ ditto
101ldrd r0, pc, label @ ditto
102ldrd r0, sp, label @ ditto
103ldrd pc, r0, [pc, #-0] @ ditto
104ldrd sp, r0, [pc, #-0] @ ditto
105ldrd r0, pc, [pc, #-0] @ ditto
106ldrd r0, sp, [pc, #-0] @ ditto
107
108@ LDRD (register): ARM only
109
110@ LDREX/B/D/H
111ldrex pc, [r0] @ BadReg
112ldrex sp, [r0] @ ditto
113ldrex r0, [pc] @ Unpredictable
114ldrexb pc, [r0] @ BadReg
115ldrexb sp, [r0] @ ditto
116ldrexb r0, [pc] @ Unpredictable
117ldrexd pc, r0, [r1] @ BadReg
118ldrexd sp, r0, [r1] @ ditto
119ldrexd r0, pc, [r1] @ ditto
120ldrexd r0, sp, [r1] @ ditto
121ldrexd r0, r1, [pc] @ Unpredictable
122ldrexh pc, [r0] @ BadReg
123ldrexh sp, [r0] @ ditto
124ldrexh r0, [pc] @ Unpredictable
125
126@ LDRH (immediate)
127ldrh pc, [r0] @ low reg
128ldrh pc, [r0, #4] @ ditto
129@ldrh r0, [pc] @ ALLOWED!
130@ldrh r0, [pc, #4] @ ditto
131ldrh.w pc, [r0] @ => Unallocated memory hints
132ldrh.w pc, [r0, #4] @ ditto
133ldrh.w sp, [r0] @ Unpredictable
134ldrh.w sp, [r0, #4] @ ditto
135ldrh pc, [r0, #-3] @ => Unallocated memory hint
136@ LDRH<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRHT
137ldrh pc,[r0],#4 @ BadReg
138ldrh sp,[r0],#4 @ ditto
139ldrh pc,[r0,#4]! @ ditto
140ldrh sp,[r0,#4]! @ ditto
141
142@ LDRH (literal)
143ldrh pc, label @ Unallocated memory hint
144ldrh pc, [pc, #-0] @ ditto
145ldrh sp, label @ Unpredictable
146ldrh sp, [pc, #-0] @ ditto
147
148@ LDRH (register)
149ldrh pc, [r0, r1] @ low reg
150ldrh r0, [pc, r1] @ ditto
151ldrh r0, [r1, pc] @ ditto
152ldrh.w pc,[r0,r1,LSL #1] @ => Unallocated memory hints
153ldrh.w sp,[r0,r1,LSL #1] @ Unpredictable
154ldrh.w r2,[r0,pc,LSL #1] @ ditto
155ldrh.w r2,[r0,sp,LSL #1] @ ditto
156
157@ LDRHT
158ldrht pc, [r0, #4] @ BadReg
159ldrht sp, [r0, #4] @ ditto
160
161@ LDRSB (immediate)
162ldrsb pc, [r0, #4] @ => PLI
163@ldrsb r0, [pc, #4] => LDRSB (literal)
164ldrsb sp, [r0, #4] @ Unpredictable
165ldrsb pc, [r0, #-4] @ => PLI
166ldrsb sp,[r0,#-4] @ BadReg
167ldrsb pc,[r0],#4 @ ditto
168ldrsb sp,[r0],#4 @ ditto
169ldrsb pc,[r0,#4]! @ ditto
170ldrsb sp,[r0,#4]! @ ditto
171
172@ LDRSB (literal)
173ldrsb pc, label @ => PLI
174ldrsb pc, [pc, #-0] @ => PLI
175ldrsb sp, label @ Unpredictable
176ldrsb sp, [pc, #-0] @ ditto
177
178@ LDRSB (register)
179ldrsb pc, [r0, r1] @ low reg
180ldrsb r0, [pc, r1] @ ditto
181ldrsb r0, [r1, pc] @ ditto
182ldrsb.w pc, [r0, r1, LSL #2] @ => PLI
183@ldrsb.w r0, [pc, r0, LSL #2] => LDRSB (literal)
184ldrsb.w sp, [r0, r1, LSL #2] @ Unpredictable
185ldrsb.w r2, [r0, pc, LSL #2] @ ditto
186ldrsb.w r2, [r0, sp, LSL #2] @ ditto
187
188@ LDRSBT
189@ldrsbt r0, [pc, #4] => LDRSB (literal)
190ldrsbt pc, [r0, #4] @ BadReg
191ldrsbt sp, [r0, #4] @ ditto
192
193@ LDRSH (immediate)
194@ldrsh r0,[pc,#4] => LDRSH (literal)
195ldrsh pc,[r0,#4] @ => Unallocated memory hints
196ldrsh sp,[r0,#4] @ Unpredictable
197ldrsh pc, [r0, #-4] @ => Unallocated memory hints
198ldrsh pc,[r0],#4 @ BadReg
199ldrsh pc,[r0,#4]! @ ditto
200ldrsh sp,[r0,#-4] @ ditto
201ldrsh sp,[r0],#4 @ ditto
202ldrsh sp,[r0,#4]! @ ditto
203
204@ LDRSH (literal)
205ldrsh pc, label @ => Unallocated memory hints
206ldrsh sp, label @ Unpredictable
207ldrsh sp, [pc,#-0] @ ditto
208
209@ LDRSH (register)
210ldrsh pc,[r0,r1] @ low reg
211ldrsh r0,[pc,r1] @ ditto
212ldrsh r0,[r1,pc] @ ditto
213@ldrsh.w r0,[pc,r1,LSL #3] => LDRSH (literal)
214ldrsh.w pc,[r0,r1,LSL #3] @ => Unallocated memory hints
215ldrsh.w sp,[r0,r1,LSL #3] @ Unpredictable
216ldrsh.w r0,[r1,sp,LSL #3] @ BadReg
217ldrsh.w r0,[r1,pc,LSL #3] @ ditto
218
219@ LDRSHT
220@ldrsht r0,[pc,#4] => LDRSH (literal)
221ldrsht pc,[r0,#4] @ BadReg
222ldrsht sp,[r0,#4] @ ditto
223
224@ LDRT
225@ldrt r0,[pc,#4] => LDR (literal)
226ldrt pc,[r0,#4] @ BadReg
227ldrt sp,[r0,#4] @ ditto
228
229@ Stores ==============================================================
230
231@ STR (immediate, Thumb)
232str pc, [r0, #4] @ Unpredictable
233str.w r0, [pc, #4] @ Undefined
234str r0, [pc, #-4] @ ditto
235str r0, [pc], #4 @ ditto
236str r0, [pc, #4]! @ ditto
237
238@ STR (register)
239str.w r0,[pc,r1] @ Undefined
240str.w r0,[pc,r1,LSL #2] @ ditto
241@str.w pc,[r0,r1{,LSL #<imm2>}] @ Unpredictable
242@str.w r1,[r0,sp{,LSL #<imm2>}] @ ditto
243@str.w r1,[r0,pc{,LSL #<imm2>}] @ ditto
244
245@ STRB (immediate, Thumb)
246strb.w r0,[pc,#4] @ Undefined
247strb.w pc,[r0,#4] @ Unpredictable
248strb.w sp,[r0,#4] @ ditto
249strb r0,[pc,#-4] @ Undefined
250strb r0,[pc],#4 @ ditto
251strb r0,[pc,#4]! @ ditto
252strb pc,[r0,#-4] @ Unpredictable
253strb pc,[r0],#4 @ ditto
254strb pc,[r0,#4]! @ ditto
255strb sp,[r0,#-4] @ ditto
256strb sp,[r0],#4 @ ditto
257strb sp,[r0,#4]! @ ditto
258
259@ STRB (register)
260strb.w r0,[pc,r1] @ Undefined
261strb.w r0,[pc,r1,LSL #2] @ ditto
262strb.w pc,[r0,r1] @ Unpredictable
263strb.w pc,[r0,r1,LSL #2] @ ditto
264strb.w sp,[r0,r1] @ ditto
265strb.w sp,[r0,r1,LSL #2] @ ditto
266strb.w r0,[r1,pc] @ ditto
267strb.w r0,[r1,pc,LSL #2] @ ditto
268strb.w r0,[r1,sp] @ ditto
269strb.w r0,[r1,sp,LSL #2] @ ditto
270
271@ STRBT
272strbt r0,[pc,#4] @ Undefined
273strbt pc,[r0,#4] @ Unpredictable
274strbt sp,[r0,#4] @ ditto
275
276@ STRD (immediate)
277strd r0,r1,[pc,#4] @ Unpredictable
278strd r0,r1,[pc],#4 @ ditto
279strd r0,r1,[pc,#4]! @ ditto
280strd pc,r0,[r1,#4] @ ditto
281strd pc,r0,[r1],#4 @ ditto
282strd pc,r0,[r1,#4]! @ ditto
283strd sp,r0,[r1,#4] @ ditto
284strd sp,r0,[r1],#4 @ ditto
285strd sp,r0,[r1,#4]! @ ditto
286strd r0,pc,[r1,#4] @ ditto
287strd r0,pc,[r1],#4 @ ditto
288strd r0,pc,[r1,#4]! @ ditto
289strd r0,sp,[r1,#4] @ ditto
290strd r0,sp,[r1],#4 @ ditto
291strd r0,sp,[r1,#4]! @ ditto
292
293@ STRD (register)
294@No thumb.
295
296@ STREX
297strex pc,r0,[r1] @ Unpredictable
298strex pc,r0,[r1,#4] @ ditto
299strex sp,r0,[r1] @ ditto
300strex sp,r0,[r1,#4] @ ditto
301strex r0,pc,[r1] @ ditto
302strex r0,pc,[r1,#4] @ ditto
303strex r0,sp,[r1] @ ditto
304strex r0,sp,[r1,#4] @ ditto
305strex r0,r1,[pc] @ ditto
306strex r0,r1,[pc,#4] @ ditto
307
308@ STREXB
309strexb pc,r0,[r1] @ Unpredictable
310strexb sp,r0,[r1] @ ditto
311strexb r0,pc,[r1] @ ditto
312strexb r0,sp,[r1] @ ditto
313strexb r0,r1,[pc] @ ditto
314
315@ STREXD
316strexd pc,r0,r1,[r2] @ Unpredictable
317strexd sp,r0,r1,[r2] @ ditto
318strexd r0,pc,r1,[r2] @ ditto
319strexd r0,sp,r1,[r2] @ ditto
320strexd r0,r1,pc,[r2] @ ditto
321strexd r0,r1,sp,[r2] @ ditto
322strexd r0,r1,r2,[pc] @ ditto
323
324@ STREXH
325strexh pc,r0,[r1] @ Unpredictable
326strexh sp,r0,[r1] @ ditto
327strexh r0,pc,[r1] @ ditto
328strexh r0,sp,[r1] @ ditto
329strexh r0,r1,[pc] @ ditto
330
331@ STRH (immediate, Thumb)
332strh.w r0,[pc] @ Undefined
333strh.w r0,[pc,#4] @ ditto
334strh r0,[pc,#-4] @ ditto
335strh r0,[pc],#4 @ ditto
336strh r0,[pc,#4]! @ ditto
337
338@ STRH (register)
339strh.w r0,[pc,r1] @ Undefined
340strh.w r0,[pc,r1,LSL #2] @ ditto
341strh.w pc,[r0,#4] @ Unpredictable
342strh.w pc,[r0] @ ditto
343strh.w sp,[r0,#4] @ ditto
344strh.w sp,[r0] @ ditto
345strh pc,[r0,#-4] @ ditto
346strh pc,[r0],#4 @ ditto
347strh pc,[r0,#4]! @ ditto
348strh sp,[r0,#-4] @ ditto
349strh sp,[r0],#4 @ ditto
350strh sp,[r0,#4]! @ ditto
351strh.w pc,[r0,r1] @ ditto
352strh.w sp,[r0,r1] @ ditto
353strh.w r0,[r1,pc] @ ditto
354strh.w r0,[r1,sp] @ ditto
355strh.w pc,[r0,r1,LSL #2] @ ditto
356strh.w sp,[r0,r1,LSL #2] @ ditto
357strh.w r0,[r1,pc,LSL #2] @ ditto
358strh.w r0,[r1,sp,LSL #2] @ ditto
359
360@ STRHT
361strht r0,[pc,#4] @ Undefined
362strht pc,[r0,#4] @ Unpredictable
363strht sp,[pc,#4] @ ditto
364
365@ STRT
366strt r0,[pc,#4] @ Undefined
367strt pc,[r0,#4] @ Unpredictable
368strt sp,[r0,#4] @ ditto
369
370@ ============================================================================
371
372.label:
373ldr r0, [r1]
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