Commit | Line | Data |
---|---|---|
32f76c67 GJL |
1 | .text |
2 | ||
3 | ;;; Use SREG | |
4 | ||
5 | __start1: | |
6 | set | |
7 | ||
8 | __vec1_start: | |
9 | __gcc_isr 1 | |
10 | foo = __gcc_isr.n_pushed | |
11 | cpi r16,1 | |
12 | __gcc_isr 2 | |
13 | __gcc_isr 0,r0 | |
14 | clt | |
15 | __vec1_end: | |
16 | __data1: | |
17 | ldi r16, foo - 2 | |
18 | .word (__vec1_end - __vec1_start) / 2 | |
19 | ||
20 | ;;; Nothing used. | |
21 | ||
22 | __start2: | |
23 | set | |
24 | ||
25 | __vec2_start: | |
26 | __gcc_isr 1 | |
27 | foo = __gcc_isr.n_pushed | |
28 | ldi r30, 1 | |
29 | lds r31, 0 | |
30 | sts 0, r31 | |
31 | movw r2, r4 | |
32 | swap r17 | |
33 | __gcc_isr 2 | |
34 | reti | |
35 | __gcc_isr 2 | |
36 | cpse r7, r8 | |
37 | sei | |
38 | cli | |
39 | in r10, 0x3f | |
40 | out 0x3f, r10 | |
41 | reti | |
42 | __gcc_isr 0,r0 | |
43 | clt | |
44 | __vec2_end: | |
45 | __data2: | |
46 | ldi r16, foo - 0 | |
47 | .word (__vec2_end - __vec2_start) / 2 | |
48 | ||
49 | ;;; Use SREG, ZERO and R24 | |
50 | ||
51 | __start3: | |
52 | set | |
53 | ||
54 | __vec3_start: | |
55 | __gcc_isr 1 | |
56 | foo = __gcc_isr.n_pushed | |
57 | __gcc_isr 2 | |
58 | reti | |
59 | __gcc_isr 2 | |
60 | reti | |
61 | inc r1 | |
62 | __gcc_isr 0,r24 | |
63 | clt | |
64 | __vec3_end: | |
65 | __data3: | |
66 | ldi r16, foo - 3 | |
67 | .word (__vec3_end - __vec3_start) / 2 | |
68 | ||
69 | ;;; Use SREG, ZERO, TMP and R24 | |
70 | ||
71 | __start4: | |
72 | set | |
73 | ||
74 | __vec4_start: | |
75 | __gcc_isr 1 | |
76 | foo = __gcc_isr.n_pushed | |
77 | __gcc_isr 2 | |
78 | reti | |
79 | __gcc_isr 2 | |
80 | reti | |
81 | mul 16, 17 | |
82 | __gcc_isr 0,r24 | |
83 | clt | |
84 | __vec4_end: | |
85 | __data4: | |
86 | ldi r16, foo - 4 | |
87 | .word (__vec4_end - __vec4_start) / 2 | |
88 | ||
89 | ;;; Use TMP | |
90 | ||
91 | __start5: | |
92 | set | |
93 | ||
94 | __vec5_start: | |
95 | __gcc_isr 1 | |
96 | lpm | |
97 | foo = __gcc_isr.n_pushed | |
98 | __gcc_isr 2 | |
99 | reti | |
100 | __gcc_isr 2 | |
101 | reti | |
102 | __gcc_isr 0,r0 | |
103 | clt | |
104 | __vec5_end: | |
105 | __data5: | |
106 | ldi r16, foo - 1 | |
107 | .word (__vec5_end - __vec5_start) / 2 | |
108 | ||
109 | ;;; Use SREG, R26 | |
110 | ||
111 | __start6: | |
112 | set | |
113 | ||
114 | __vec6_start: | |
115 | __gcc_isr 1 | |
116 | foo = __gcc_isr.n_pushed | |
117 | __gcc_isr 2 | |
118 | reti | |
119 | __gcc_isr 2 | |
120 | reti | |
121 | clc | |
122 | __gcc_isr 0,r26 | |
123 | clt | |
124 | __vec6_end: | |
125 | __data6: | |
126 | ldi r16, foo - 2 | |
127 | .word (__vec6_end - __vec6_start) / 2 |