projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a01eda85 MF |
1 | #objdump: -dr |
| 2 | #name: pseudo | |
| 3 | .*: +file format .* | |
| 4 | Disassembly of section .text: | |
| 5 | ||
| 6 | 00000000 <debug>: | |
| 7 | 0: 00 f8 DBG R0; | |
| 8 | 2: 01 f8 DBG R1; | |
| 9 | 4: 02 f8 DBG R2; | |
| 10 | 6: 03 f8 DBG R3; | |
| 11 | 8: 04 f8 DBG R4; | |
| 12 | a: 05 f8 DBG R5; | |
| 13 | c: 06 f8 DBG R6; | |
| 14 | e: 07 f8 DBG R7; | |
| 15 | 10: 08 f8 DBG P0; | |
| 16 | 12: 09 f8 DBG P1; | |
| 17 | 14: 0a f8 DBG P2; | |
| 18 | 16: 0b f8 DBG P3; | |
| 19 | 18: 0c f8 DBG P4; | |
| 20 | 1a: 0d f8 DBG P5; | |
| 21 | 1c: 0e f8 DBG SP; | |
| 22 | 1e: 0f f8 DBG FP; | |
| 23 | 20: 10 f8 DBG I0; | |
| 24 | 22: 11 f8 DBG I1; | |
| 25 | 24: 12 f8 DBG I2; | |
| 26 | 26: 13 f8 DBG I3; | |
| 27 | 28: 14 f8 DBG M0; | |
| 28 | 2a: 15 f8 DBG M1; | |
| 29 | 2c: 16 f8 DBG M2; | |
| 30 | 2e: 17 f8 DBG M3; | |
| 31 | 30: 18 f8 DBG B0; | |
| 32 | 32: 19 f8 DBG B1; | |
| 33 | 34: 1a f8 DBG B2; | |
| 34 | 36: 1b f8 DBG B3; | |
| 35 | 38: 1c f8 DBG L0; | |
| 36 | 3a: 1d f8 DBG L1; | |
| 37 | 3c: 1e f8 DBG L2; | |
| 38 | 3e: 1f f8 DBG L3; | |
| 39 | 40: 20 f8 DBG A0.X; | |
| 40 | 42: 21 f8 DBG A0.W; | |
| 41 | 44: 22 f8 DBG A1.X; | |
| 42 | 46: 23 f8 DBG A1.W; | |
| 43 | 48: 26 f8 DBG ASTAT; | |
| 44 | 4a: 27 f8 DBG RETS; | |
| 45 | 4c: 30 f8 DBG LC0; | |
| 46 | 4e: 31 f8 DBG LT0; | |
| 47 | 50: 32 f8 DBG LB0; | |
| 48 | 52: 33 f8 DBG LC1; | |
| 49 | 54: 34 f8 DBG LT1; | |
| 50 | 56: 35 f8 DBG LB1; | |
| 51 | 58: 36 f8 DBG CYCLES; | |
| 52 | 5a: 37 f8 DBG CYCLES2; | |
| 53 | 5c: 38 f8 DBG USP; | |
| 54 | 5e: 39 f8 DBG SEQSTAT; | |
| 55 | 60: 3a f8 DBG SYSCFG; | |
| 56 | 62: 3b f8 DBG RETI; | |
| 57 | 64: 3c f8 DBG RETX; | |
| 58 | 66: 3d f8 DBG RETN; | |
| 59 | 68: 3e f8 DBG RETE; | |
| 60 | 6a: 3f f8 DBG EMUDAT; | |
| 61 | ||
| 62 | 0000006c <debug_assert>: | |
| 63 | 6c: 00 f0 00 00 DBGA \(R0.L, 0x0\); | |
| 64 | 70: 40 f0 10 00 DBGA \(R0.H, 0x10\); | |
| 65 | 74: 00 f0 00 02 DBGA \(R0.L, 0x200\); | |
| 66 | 78: 40 f0 00 30 DBGA \(R0.H, 0x3000\); | |
| 67 | 7c: 01 f0 01 00 DBGA \(R1.L, 0x1\); | |
| 68 | 80: 41 f0 01 10 DBGA \(R1.H, 0x1001\); | |
| 69 | 84: 01 f0 08 80 DBGA \(R1.L, 0x8008\); | |
| 70 | 88: 41 f0 00 c0 DBGA \(R1.H, 0xc000\); | |
| 71 | 8c: 02 f0 00 04 DBGA \(R2.L, 0x400\); | |
| 72 | 90: 42 f0 00 08 DBGA \(R2.H, 0x800\); | |
| 73 | 94: 02 f0 00 10 DBGA \(R2.L, 0x1000\); | |
| 74 | 98: 42 f0 00 20 DBGA \(R2.H, 0x2000\); | |
| 75 | 9c: 03 f0 ff ff DBGA \(R3.L, 0xffff\); | |
| 76 | a0: 43 f0 ff 7f DBGA \(R3.H, 0x7fff\); | |
| 77 | a4: 03 f0 ff 3f DBGA \(R3.L, 0x3fff\); | |
| 78 | a8: 43 f0 ff 1f DBGA \(R3.H, 0x1fff\); | |
| 79 | ac: 0b f0 ff ff DBGA \(P3.L, 0xffff\); | |
| 80 | b0: 4b f0 9c ff DBGA \(P3.H, 0xff9c\); | |
| 81 | b4: 0b f0 18 fc DBGA \(P3.L, 0xfc18\); | |
| 82 | b8: 4b f0 01 e0 DBGA \(P3.H, 0xe001\); |