[deliverable/binutils-gdb.git] / gas / testsuite / gas / epiphany / regression.s

;; -*-asm-*-

	TABLE=0x8000
	RZ=r63

	.macro FAIL
	mov	r0,#1
	trap	3
	.endm

	.macro PASS
	mov	r0,#0
	trap	3
	.endm


	.macro VERIFY ra,rb,ref,label
	sub	\ra,\rb,\ref
	beq	\label
	FAIL
	.endm


/*****************************************/
/*INITIALIZING REGISTERS                 */
/*****************************************/
/*Check that sum is correct*/
START:	MOV R0, #TABLE   ; //Setting R0 to TABLE
	LSL R0,R0,#2	 ; //Create 00020000

	;; Load r1.63 with 1..63
	.irpc num,63
	mov r\num,#\num
	.endr


	;; Sum the registers
	.irpc num,62
	add r63,r63,r\num
	.endr

	mov r62,#2016	 ;//Correct sum of 1..63 = 63*32 + 63
	VERIFY	r63,r63,R62,BRANCH1;//CHECK SUM


/*****************************************/
/*BRANCHING                              */
/*****************************************/
//Check that all condition codes work
BRANCH1:	BEQ  BRANCH2     ; //taken
	FAIL	         ;
	FAIL		 ;
	FAIL		 ;
	FAIL             ;
BRANCH2:	BNE  FAIL_BRANCH ; //not taken
BRANCH3:	BGT  FAIL_BRANCH ; //not taken
BRANCH4:	BGTE BRANCH5     ; //taken
	FAIL		;
BRANCH5:	BLTE BRANCH6	; //taken
	FAIL		;
BRANCH6:	BLT  FAIL_BRANCH ; //not taken
BRANCH8:	B    LONGJUMP    ; //taken
	FAIL		 ;
RETURN:	bl  FUNCTION	 ; //jump to subroutine
	MOV R63,JARLAB   ;//REGISTER JUMP
	JR  R63		 ;
	FAIL		 ;
JARLAB:	MOV R63,FUNCTION ; //REGISTER CALL
	JALR R63		 ; //16 bit
        B    NEXT	 ; //jump over fail
	FAIL		;

FAIL_BRANCH:	FAIL	; //fail branch

/*****************************************/
/*LOAD-STORE DISPLACEMENT                */
/*****************************************/
//Check max displacement value(0xf)
//Check that offset is correct
//all load/stores are aligned
//this gives greater range(2 more bits)
//offset is shifted by 2x bits

NEXT:	STRB R4,[R0,#0x0] ;//Store Byte
	LDRB R63,[R0,#0x0] ;//Load Byte
	VERIFY	R63,R63,R4,STOREB  ;

STOREB:	STRB R5,[R0,#0xf] ;//Store Byte
	LDRB R63,[R0,#0xf] ;//Load Byte
	VERIFY	R63,R63,R5,STORES  ;

STORES:	STRH R4,[R0,#0x0] ;//Store Short
	LDRH R63,[R0,#0x0] ;//Load Short
	VERIFY	R63,R63,R4,STORES2  ;

STORES2:	STRH R5,[R0,#0xe] ;//Store Short
	LDRH R63,[R0,#0xe] ;//Load Short
	VERIFY	R63,R63,R5,STORE  ;

STORE:	STR  R4,[R0,#0x0] ;//Store Word
	LDR  R63,[R0,#0x0] ;//Load Word
	VERIFY	R63,R63,R4,STORE2  ;

STORE2:	STR  R5,[R0,#0xc] ;//Store Word
	LDR  R63,[R0,#0xc] ;//Load Word
	VERIFY	R63,R63,R5,STOREBI ;


/*****************************************/
/*LOAD-STORE INDEX                       */
/*****************************************/

STOREBI:	STRB R4,[R0,R4]	 ;//Store Word
	LDRB R63,[R0,R4]	 ;//Load Word
	VERIFY	R63,R63,R4,STORESI	;

STORESI:	STRH R5,[R0,R4]	 ;//Store Word
	LDRH R63,[R0,R4]	 ;//Load Word
	VERIFY	R63,R63,R5,STOREI	 ;

STOREI:	STR  R6,[R0,R4]	 ;//Store Word
	LDR  R63,[R0,R4]	 ;//Load Word
	VERIFY	R63,R63,R6,PMB	 ;

/*****************************************/
/*LOAD-STORE POSTMODIFY                  */
/*****************************************/

PMB:	STRB R4,[R0],R4	 ;//Store Word
	SUB  R0,R0,#0x4	 ;//restoring R0
	LDRB R63,[R0],R4	 ;//Load Word
	SUB  R0,R0,#0x4	 ;//restoring R0
	VERIFY	R63,R63,R4,PMS	 ;

PMS:	STRH R5,[R0],R4	 ;//Store Word
	SUB  R0,R0,#0x4	 ;//restoring R0
	LDRH R63,[R0],R4	 ;//Load Word
	VERIFY	R63,R63,R5,PM	 ;

PM:	SUB  R0,R0,#0x4	 ;//restoring R0
	STR  R6,[R0],R4	 ;//Store Word
	SUB  R0,R0,#0x4	 ;//restoring R0
	LDR  R63,[R0],R4	 ;//Load Word
	SUB  R0,R0,#0x4	 ;//restoring R0
	VERIFY	R63,R63,R6,MOVLAB	 ;


/*****************************************/
/*IMMEDIATE LOAD                         */
/*****************************************/
MOVLAB:	MOV R63,#0xFF;
	MOV R1,#0xFF;
	VERIFY	R63,R63,R1,ADDLAB	;

/*****************************************/
/*2 REG ADD/SUB PROCESSING               */
/*****************************************/
ADDLAB:	ADD R63,R2,#3;	//2+3=5
	VERIFY	R63,R63,#5,SUBLAB	;
SUBLAB:	SUB R63,R2,#1;	//2+1=1
	VERIFY	R63,R63,#1,LSRLAB	;

/*****************************************/
/*SHIFTS                                 */
/*****************************************/
//Note ASR does not work

	//Immediates
LSRLAB:	LSR R63,R6,#0x2   ; //6>>2=1
	VERIFY	R63,R63,#1,LSLLAB	 ;
LSLLAB:	LSL R63,R3,#0x2   ; //3<<2=12
	VERIFY	R63,R63,#12,LSRILAB	;
	//Registers
LSRILAB:	LSR R63,R6,R2     ; //6>>2=1
	VERIFY	R63,R63,#1,LSLILAB	 ;
LSLILAB:	LSL R63,R3,R2     ; //3<<2=12
	VERIFY	R63,R63,#12,ORRLAB	;


/*****************************************/
/*LOGICAL                                */
/*****************************************/
ORRLAB:	ORR R5,R3,R4     ; //0x3 | 0x4 -->0x7
	VERIFY	R63,R5,#7,ANDLAB	 ;
ANDLAB:	AND R5,R3,R4     ; //0x3 & 0x4 -->0
	VERIFY	R63,R5,#0,EORLAB	 ;
EORLAB:	EOR R5,R3,R2     ; //0x3 ^ 0x2 -->1
	VERIFY	R63,R5,#1,ADD3LAB	 ;


/****************************************/
/*3-REGISTER ADD/SUB                     */
/*****************************************/
ADD3LAB:	ADD R63,R2,R3    ; //3+2=5
	VERIFY	R63,R63,#5,SUB3LAB	 ;
SUB3LAB:	SUB R63,R6,R4    ; //6-4=2
	VERIFY	R63,R63,#2,MOVRLAB	 ;

/*****************************************/
/*MOVE REGISTER                          */
/*****************************************/
MOVRLAB:	MOV R63,R2	;
	VERIFY	R63,R63,#2,NOPLAB	 ;

/*****************************************/
/*MOVE TO/FROM SPECIAL REGISTER          */
/*****************************************/
MOVTFLAB:	MOVTS status,R0	;
	MOVFS R63,status	;
	VERIFY	R63,R63,R0,MOVTFLAB	;


/*****************************************/
/*NOP                                    */
/*****************************************/
NOPLAB:	NOP		;
	NOP		;
	NOP		;
	NOP		;

/*****************************************/
/*PASS INDICATOR                         */
/*****************************************/
PASSED:	PASS;
	IDLE;
/*****************************************/
/*FAIL INDICATOR                         */
/*****************************************/
FAILED:	FAIL;
	IDLE;

/*****************************************/
/*LONG JUMP INDICATOR                    */
/*****************************************/
LONGJUMP:	B RETURN; //jump back to next
/*****************************************/
/*SUBROUTINE                             */
/*****************************************/
FUNCTION:	RTS;      //return from subroutine
Commit	Line	Data
cfb8c092 NC	1	;; --asm--
	2
	3	TABLE=0x8000
	4	RZ=r63
	5
	6	.macro FAIL
	7	mov r0,#1
	8	trap 3
	9	.endm
	10
	11	.macro PASS
	12	mov r0,#0
	13	trap 3
	14	.endm
	15
	16
	17	.macro VERIFY ra,rb,ref,label
	18	sub \ra,\rb,\ref
	19	beq \label
	20	FAIL
	21	.endm
	22
	23
	24	/*****************************************/
	25	/INITIALIZING REGISTERS /
	26	/*****************************************/
	27	/Check that sum is correct/
	28	START: MOV R0, #TABLE ; //Setting R0 to TABLE
	29	LSL R0,R0,#2 ; //Create 00020000
	30
	31	;; Load r1.63 with 1..63
	32	.irpc num,63
	33	mov r\num,#\num
	34	.endr
	35
	36
	37	;; Sum the registers
	38	.irpc num,62
	39	add r63,r63,r\num
	40	.endr
	41
	42	mov r62,#2016 ;//Correct sum of 1..63 = 63*32 + 63
	43	VERIFY r63,r63,R62,BRANCH1;//CHECK SUM
	44
	45
	46	/*****************************************/
	47	/BRANCHING /
	48	/*****************************************/
	49	//Check that all condition codes work
	50	BRANCH1: BEQ BRANCH2 ; //taken
	51	FAIL ;
	52	FAIL ;
	53	FAIL ;
	54	FAIL ;
	55	BRANCH2: BNE FAIL_BRANCH ; //not taken
	56	BRANCH3: BGT FAIL_BRANCH ; //not taken
	57	BRANCH4: BGTE BRANCH5 ; //taken
	58	FAIL ;
	59	BRANCH5: BLTE BRANCH6 ; //taken
	60	FAIL ;
	61	BRANCH6: BLT FAIL_BRANCH ; //not taken
	62	BRANCH8: B LONGJUMP ; //taken
	63	FAIL ;
	64	RETURN: bl FUNCTION ; //jump to subroutine
65	MOV R63,JARLAB ;//REGISTER JUMP
66	JR R63 ;
67	FAIL ;
68	JARLAB: MOV R63,FUNCTION ; //REGISTER CALL
69	JALR R63 ; //16 bit
70	B NEXT ; //jump over fail
71	FAIL ;
72
73	FAIL_BRANCH: FAIL ; //fail branch
74
75	/*****************************************/
76	/LOAD-STORE DISPLACEMENT /
77	/*****************************************/
78	//Check max displacement value(0xf)
79	//Check that offset is correct
80	//all load/stores are aligned
81	//this gives greater range(2 more bits)
82	//offset is shifted by 2x bits
83
84	NEXT: STRB R4,[R0,#0x0] ;//Store Byte
85	LDRB R63,[R0,#0x0] ;//Load Byte
86	VERIFY R63,R63,R4,STOREB ;
87
88	STOREB: STRB R5,[R0,#0xf] ;//Store Byte
89	LDRB R63,[R0,#0xf] ;//Load Byte
90	VERIFY R63,R63,R5,STORES ;
91
92	STORES: STRH R4,[R0,#0x0] ;//Store Short
93	LDRH R63,[R0,#0x0] ;//Load Short
94	VERIFY R63,R63,R4,STORES2 ;
95
96	STORES2: STRH R5,[R0,#0xe] ;//Store Short
97	LDRH R63,[R0,#0xe] ;//Load Short
98	VERIFY R63,R63,R5,STORE ;
99
100	STORE: STR R4,[R0,#0x0] ;//Store Word
101	LDR R63,[R0,#0x0] ;//Load Word
102	VERIFY R63,R63,R4,STORE2 ;
103
104	STORE2: STR R5,[R0,#0xc] ;//Store Word
105	LDR R63,[R0,#0xc] ;//Load Word
106	VERIFY R63,R63,R5,STOREBI ;
107
108
109	/*****************************************/
110	/LOAD-STORE INDEX /
111	/*****************************************/
112
113	STOREBI: STRB R4,[R0,R4] ;//Store Word
114	LDRB R63,[R0,R4] ;//Load Word
115	VERIFY R63,R63,R4,STORESI ;
116
117	STORESI: STRH R5,[R0,R4] ;//Store Word
118	LDRH R63,[R0,R4] ;//Load Word
119	VERIFY R63,R63,R5,STOREI ;
120
121	STOREI: STR R6,[R0,R4] ;//Store Word
122	LDR R63,[R0,R4] ;//Load Word
123	VERIFY R63,R63,R6,PMB ;
124
125	/*****************************************/
126	/LOAD-STORE POSTMODIFY /
127	/*****************************************/
128
129	PMB: STRB R4,[R0],R4 ;//Store Word
130	SUB R0,R0,#0x4 ;//restoring R0
131	LDRB R63,[R0],R4 ;//Load Word
132	SUB R0,R0,#0x4 ;//restoring R0
133	VERIFY R63,R63,R4,PMS ;
134
135	PMS: STRH R5,[R0],R4 ;//Store Word
136	SUB R0,R0,#0x4 ;//restoring R0
137	LDRH R63,[R0],R4 ;//Load Word
138	VERIFY R63,R63,R5,PM ;
139
140	PM: SUB R0,R0,#0x4 ;//restoring R0
141	STR R6,[R0],R4 ;//Store Word
142	SUB R0,R0,#0x4 ;//restoring R0
143	LDR R63,[R0],R4 ;//Load Word
144	SUB R0,R0,#0x4 ;//restoring R0
145	VERIFY R63,R63,R6,MOVLAB ;
146
147
148
149	/*****************************************/
150	/IMMEDIATE LOAD /
151	/*****************************************/
152	MOVLAB: MOV R63,#0xFF;
153	MOV R1,#0xFF;
154	VERIFY R63,R63,R1,ADDLAB ;
155
156	/*****************************************/
157	/2 REG ADD/SUB PROCESSING /
158	/*****************************************/
159	ADDLAB: ADD R63,R2,#3; //2+3=5
160	VERIFY R63,R63,#5,SUBLAB ;
161	SUBLAB: SUB R63,R2,#1; //2+1=1
162	VERIFY R63,R63,#1,LSRLAB ;
163
164	/*****************************************/
165	/SHIFTS /
166	/*****************************************/
167	//Note ASR does not work
168
169	//Immediates
170	LSRLAB: LSR R63,R6,#0x2 ; //6>>2=1
171	VERIFY R63,R63,#1,LSLLAB ;
172	LSLLAB: LSL R63,R3,#0x2 ; //3<<2=12
173	VERIFY R63,R63,#12,LSRILAB ;
174	//Registers
175	LSRILAB: LSR R63,R6,R2 ; //6>>2=1
176	VERIFY R63,R63,#1,LSLILAB ;
177	LSLILAB: LSL R63,R3,R2 ; //3<<2=12
178	VERIFY R63,R63,#12,ORRLAB ;
179
180
181	/*****************************************/
182	/LOGICAL /
183	/*****************************************/
184	ORRLAB: ORR R5,R3,R4 ; //0x3 \| 0x4 -->0x7
185	VERIFY R63,R5,#7,ANDLAB ;
186	ANDLAB: AND R5,R3,R4 ; //0x3 & 0x4 -->0
187	VERIFY R63,R5,#0,EORLAB ;
188	EORLAB: EOR R5,R3,R2 ; //0x3 ^ 0x2 -->1
189	VERIFY R63,R5,#1,ADD3LAB ;
190
191
192	/****************************************/
193	/3-REGISTER ADD/SUB /
194	/*****************************************/
195	ADD3LAB: ADD R63,R2,R3 ; //3+2=5
196	VERIFY R63,R63,#5,SUB3LAB ;
197	SUB3LAB: SUB R63,R6,R4 ; //6-4=2
198	VERIFY R63,R63,#2,MOVRLAB ;
199
200	/*****************************************/
201	/MOVE REGISTER /
202	/*****************************************/
203	MOVRLAB: MOV R63,R2 ;
204	VERIFY R63,R63,#2,NOPLAB ;
205
206	/*****************************************/
207	/MOVE TO/FROM SPECIAL REGISTER /
208	/*****************************************/
209	MOVTFLAB: MOVTS status,R0 ;
210	MOVFS R63,status ;
211	VERIFY R63,R63,R0,MOVTFLAB ;
212
213
214	/*****************************************/
215	/NOP /
216	/*****************************************/
217	NOPLAB: NOP ;
218	NOP ;
219	NOP ;
220	NOP ;
221
222	/*****************************************/
223	/PASS INDICATOR /
224	/*****************************************/
225	PASSED: PASS;
226	IDLE;
227	/*****************************************/
228	/FAIL INDICATOR /
229	/*****************************************/
230	FAILED: FAIL;
231	IDLE;
232
233	/*****************************************/
234	/LONG JUMP INDICATOR /
235	/*****************************************/
236	LONGJUMP: B RETURN; //jump back to next
237	/*****************************************/
238	/SUBROUTINE /
239	/*****************************************/
240	FUNCTION: RTS; //return from subroutine