Commit | Line | Data |
---|---|---|
436709ee | 1 | .LEVEL 2.0 |
68196d70 | 2 | .code |
436709ee JL |
3 | .align 4 |
4 | ; Basic add/sh?add instruction tests. | |
5 | ; | |
6 | ; We could/should test some of the corner cases for register and | |
7 | ; immediate fields. We should also check the assorted field | |
8 | ; selectors to make sure they're handled correctly. | |
9 | add,* %r4,%r5,%r6 | |
10 | add,*= %r4,%r5,%r6 | |
11 | add,*< %r4,%r5,%r6 | |
12 | add,*<= %r4,%r5,%r6 | |
13 | add,*nuv %r4,%r5,%r6 | |
14 | add,*znv %r4,%r5,%r6 | |
15 | add,*sv %r4,%r5,%r6 | |
16 | add,*od %r4,%r5,%r6 | |
17 | add,*tr %r4,%r5,%r6 | |
18 | add,*<> %r4,%r5,%r6 | |
19 | add,*>= %r4,%r5,%r6 | |
20 | add,*> %r4,%r5,%r6 | |
21 | add,*uv %r4,%r5,%r6 | |
22 | add,*vnz %r4,%r5,%r6 | |
23 | add,*nsv %r4,%r5,%r6 | |
24 | add,*ev %r4,%r5,%r6 | |
25 | ||
26 | add,l,* %r4,%r5,%r6 | |
27 | add,l,*= %r4,%r5,%r6 | |
28 | add,l,*< %r4,%r5,%r6 | |
29 | add,l,*<= %r4,%r5,%r6 | |
30 | add,l,*nuv %r4,%r5,%r6 | |
31 | add,l,*znv %r4,%r5,%r6 | |
32 | add,l,*sv %r4,%r5,%r6 | |
33 | add,l,*od %r4,%r5,%r6 | |
34 | add,l,*tr %r4,%r5,%r6 | |
35 | add,l,*<> %r4,%r5,%r6 | |
36 | add,l,*>= %r4,%r5,%r6 | |
37 | add,l,*> %r4,%r5,%r6 | |
38 | add,l,*uv %r4,%r5,%r6 | |
39 | add,l,*vnz %r4,%r5,%r6 | |
40 | add,l,*nsv %r4,%r5,%r6 | |
41 | add,l,*ev %r4,%r5,%r6 | |
42 | ||
43 | add,tsv,* %r4,%r5,%r6 | |
44 | add,tsv,*= %r4,%r5,%r6 | |
45 | add,tsv,*< %r4,%r5,%r6 | |
46 | add,tsv,*<= %r4,%r5,%r6 | |
47 | add,tsv,*nuv %r4,%r5,%r6 | |
48 | add,tsv,*znv %r4,%r5,%r6 | |
49 | add,tsv,*sv %r4,%r5,%r6 | |
50 | add,tsv,*od %r4,%r5,%r6 | |
51 | add,tsv,*tr %r4,%r5,%r6 | |
52 | add,tsv,*<> %r4,%r5,%r6 | |
53 | add,tsv,*>= %r4,%r5,%r6 | |
54 | add,tsv,*> %r4,%r5,%r6 | |
55 | add,tsv,*uv %r4,%r5,%r6 | |
56 | add,tsv,*vnz %r4,%r5,%r6 | |
57 | add,tsv,*nsv %r4,%r5,%r6 | |
58 | add,tsv,*ev %r4,%r5,%r6 | |
59 | ||
60 | add,dc,* %r4,%r5,%r6 | |
61 | add,dc,*= %r4,%r5,%r6 | |
62 | add,dc,*< %r4,%r5,%r6 | |
63 | add,dc,*<= %r4,%r5,%r6 | |
64 | add,dc,*nuv %r4,%r5,%r6 | |
65 | add,dc,*znv %r4,%r5,%r6 | |
66 | add,dc,*sv %r4,%r5,%r6 | |
67 | add,dc,*od %r4,%r5,%r6 | |
68 | add,dc,*tr %r4,%r5,%r6 | |
69 | add,dc,*<> %r4,%r5,%r6 | |
70 | add,dc,*>= %r4,%r5,%r6 | |
71 | add,dc,*> %r4,%r5,%r6 | |
72 | add,dc,*uv %r4,%r5,%r6 | |
73 | add,dc,*vnz %r4,%r5,%r6 | |
74 | add,dc,*nsv %r4,%r5,%r6 | |
75 | add,dc,*ev %r4,%r5,%r6 | |
76 | ||
77 | add,dc,tsv,* %r4,%r5,%r6 | |
78 | add,dc,tsv,*= %r4,%r5,%r6 | |
79 | add,dc,tsv,*< %r4,%r5,%r6 | |
80 | add,dc,tsv,*<= %r4,%r5,%r6 | |
81 | add,dc,tsv,*nuv %r4,%r5,%r6 | |
82 | add,dc,tsv,*znv %r4,%r5,%r6 | |
83 | add,dc,tsv,*sv %r4,%r5,%r6 | |
84 | add,dc,tsv,*od %r4,%r5,%r6 | |
85 | add,tsv,dc,*tr %r4,%r5,%r6 | |
86 | add,tsv,dc,*<> %r4,%r5,%r6 | |
87 | add,tsv,dc,*>= %r4,%r5,%r6 | |
88 | add,tsv,dc,*> %r4,%r5,%r6 | |
89 | add,tsv,dc,*uv %r4,%r5,%r6 | |
90 | add,tsv,dc,*vnz %r4,%r5,%r6 | |
91 | add,tsv,dc,*nsv %r4,%r5,%r6 | |
92 | add,tsv,dc,*ev %r4,%r5,%r6 | |
bb7835b8 NC |
93 | |
94 | ;; PR gas/11395: Check for the correct assembly | |
a64718d3 | 95 | ;; of unconditional 32-bit and 64-bit add instructions. |
bb7835b8 | 96 | add %r1,%r1,%r1 |
a64718d3 | 97 | add,dc %r1,%r1,%r1 |