[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / avx512er-rcigrd-intel.d

#as: -mevexrcig=rd
#objdump: -dw -Mintel
#name: i386 AVX512ER rcig insns (Intel disassembly)
#source: avx512er-rcig.s

.*: +file format .*


Disassembly of section \.text:

00000000 <_start>:
[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 38 c8 f5[ 	]*vexp2ps zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 38 c8 f5[ 	]*vexp2pd zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 38 ca f5[ 	]*vrcp28ps zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 38 ca f5[ 	]*vrcp28pd zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 55 3f cb f4[ 	]*vrcp28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 d5 3f cb f4[ 	]*vrcp28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 38 cc f5[ 	]*vrsqrt28ps zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 38 cc f5[ 	]*vrsqrt28pd zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 55 3f cd f4[ 	]*vrsqrt28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 d5 3f cd f4[ 	]*vrsqrt28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 38 c8 f5[ 	]*vexp2ps zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 38 c8 f5[ 	]*vexp2pd zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 38 ca f5[ 	]*vrcp28ps zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 38 ca f5[ 	]*vrcp28pd zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 55 3f cb f4[ 	]*vrcp28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 d5 3f cb f4[ 	]*vrcp28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 38 cc f5[ 	]*vrsqrt28ps zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 38 cc f5[ 	]*vrsqrt28pd zmm6,zmm5,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 55 3f cd f4[ 	]*vrsqrt28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
[ 	]*[a-f0-9]+:[ 	]*62 f2 d5 3f cd f4[ 	]*vrsqrt28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
#pass
Commit	Line	Data
d3d3c6db IT	1	#as: -mevexrcig=rd
	2	#objdump: -dw -Mintel
	3	#name: i386 AVX512ER rcig insns (Intel disassembly)
	4	#source: avx512er-rcig.s
	5
	6	.: +file format .
	7
	8
	9	Disassembly of section \.text:
	10
	11	00000000 <_start>:
	12	[ ][a-f0-9]+:[ ]62 f2 7d 38 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
	13	[ ][a-f0-9]+:[ ]62 f2 fd 38 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
	14	[ ][a-f0-9]+:[ ]62 f2 7d 38 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
	15	[ ][a-f0-9]+:[ ]62 f2 fd 38 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\}
	16	[ ][a-f0-9]+:[ ]62 f2 55 3f cb f4[ ]*vrcp28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
	17	[ ][a-f0-9]+:[ ]62 f2 d5 3f cb f4[ ]*vrcp28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
	18	[ ][a-f0-9]+:[ ]62 f2 7d 38 cc f5[ ]*vrsqrt28ps zmm6,zmm5,\{sae\}
	19	[ ][a-f0-9]+:[ ]62 f2 fd 38 cc f5[ ]*vrsqrt28pd zmm6,zmm5,\{sae\}
	20	[ ][a-f0-9]+:[ ]62 f2 55 3f cd f4[ ]*vrsqrt28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
	21	[ ][a-f0-9]+:[ ]62 f2 d5 3f cd f4[ ]*vrsqrt28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
	22	[ ][a-f0-9]+:[ ]62 f2 7d 38 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
	23	[ ][a-f0-9]+:[ ]62 f2 fd 38 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
	24	[ ][a-f0-9]+:[ ]62 f2 7d 38 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
	25	[ ][a-f0-9]+:[ ]62 f2 fd 38 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\}
	26	[ ][a-f0-9]+:[ ]62 f2 55 3f cb f4[ ]*vrcp28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
	27	[ ][a-f0-9]+:[ ]62 f2 d5 3f cb f4[ ]*vrcp28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
	28	[ ][a-f0-9]+:[ ]62 f2 7d 38 cc f5[ ]*vrsqrt28ps zmm6,zmm5,\{sae\}
	29	[ ][a-f0-9]+:[ ]62 f2 fd 38 cc f5[ ]*vrsqrt28pd zmm6,zmm5,\{sae\}
	30	[ ][a-f0-9]+:[ ]62 f2 55 3f cd f4[ ]*vrsqrt28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
	31	[ ][a-f0-9]+:[ ]62 f2 d5 3f cd f4[ ]*vrsqrt28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
	32	#pass