x86: add missing pseudo ops for VPCLMULQDQ ISA extension
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / avx512f_vpclmulqdq-intel.d
CommitLineData
ff1982d5
IT
1#as:
2#objdump: -dw -Mintel
3#name: i386 AVX512F/VPCLMULQDQ insns (Intel disassembly)
4#source: avx512f_vpclmulqdq.s
5
6.*: +file format .*
7
8
9Disassembly of section \.text:
10
1100000000 <_start>:
12[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 c9 ab[ ]*vpclmulqdq zmm1,zmm3,zmm1,0xab
13[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
14[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 4a 7f 7b[ ]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
cd546e7b
JB
15[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 d9 11[ ]*vpclmulhqhqdq zmm3,zmm2,zmm1
16[ ]*[a-f0-9]+:[ ]*62 f3 65 48 44 e2 01[ ]*vpclmulhqlqdq zmm4,zmm3,zmm2
17[ ]*[a-f0-9]+:[ ]*62 f3 5d 48 44 eb 10[ ]*vpclmullqhqdq zmm5,zmm4,zmm3
18[ ]*[a-f0-9]+:[ ]*62 f3 55 48 44 f4 00[ ]*vpclmullqlqdq zmm6,zmm5,zmm4
ff1982d5
IT
19[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 d2 ab[ ]*vpclmulqdq zmm2,zmm2,zmm2,0xab
20[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
21[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 44 52 7f 7b[ ]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
22#pass
This page took 0.104411 seconds and 4 git commands to generate.