[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / avx512vl_vpclmulqdq.s

# Check 32bit AVX512VL,VPCLMULQDQ instructions

	.allow_index_reg
	.text
_start:
	vpclmulqdq	$0xab, %xmm2, %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, -123456(%esp,%esi,8), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, 2032(%edx), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ Disp8
	vpclmulqdq	$0xab, %ymm1, %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ Disp8

	{evex} vpclmulqdq	$0xab, %xmm2, %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, -123456(%esp,%esi,8), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, 2032(%edx), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ Disp8
	{evex} vpclmulqdq	$0xab, %ymm1, %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ Disp8

	.intel_syntax noprefix
	vpclmulqdq	xmm3, xmm5, xmm3, 0xab	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	xmm3, xmm5, XMMWORD PTR [edx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
	vpclmulqdq	ymm2, ymm2, ymm2, 0xab	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	ymm2, ymm2, YMMWORD PTR [edx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8

	{evex} vpclmulqdq	xmm3, xmm5, xmm3, 0xab	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	xmm3, xmm5, XMMWORD PTR [edx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
	{evex} vpclmulqdq	ymm2, ymm2, ymm2, 0xab	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	ymm2, ymm2, YMMWORD PTR [edx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
Commit	Line	Data
ff1982d5 IT	1	# Check 32bit AVX512VL,VPCLMULQDQ instructions
	2
	3	.allow_index_reg
	4	.text
	5	_start:
	6	vpclmulqdq $0xab, %xmm2, %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
	7	vpclmulqdq $123, -123456(%esp,%esi,8), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
	8	vpclmulqdq $123, 2032(%edx), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ Disp8
	9	vpclmulqdq $0xab, %ymm1, %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
	10	vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
	11	vpclmulqdq $123, 4064(%edx), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ Disp8
	12
	13	{evex} vpclmulqdq $0xab, %xmm2, %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
	14	{evex} vpclmulqdq $123, -123456(%esp,%esi,8), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ
	15	{evex} vpclmulqdq $123, 2032(%edx), %xmm2, %xmm3 # AVX512VL,VPCLMULQDQ Disp8
	16	{evex} vpclmulqdq $0xab, %ymm1, %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
	17	{evex} vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ
	18	{evex} vpclmulqdq $123, 4064(%edx), %ymm5, %ymm4 # AVX512VL,VPCLMULQDQ Disp8
	19
	20	.intel_syntax noprefix
	21	vpclmulqdq xmm3, xmm5, xmm3, 0xab # AVX512VL,VPCLMULQDQ
	22	vpclmulqdq xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
	23	vpclmulqdq xmm3, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
	24	vpclmulqdq ymm2, ymm2, ymm2, 0xab # AVX512VL,VPCLMULQDQ
	25	vpclmulqdq ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
	26	vpclmulqdq ymm2, ymm2, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
	27
	28	{evex} vpclmulqdq xmm3, xmm5, xmm3, 0xab # AVX512VL,VPCLMULQDQ
	29	{evex} vpclmulqdq xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
	30	{evex} vpclmulqdq xmm3, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
	31	{evex} vpclmulqdq ymm2, ymm2, ymm2, 0xab # AVX512VL,VPCLMULQDQ
	32	{evex} vpclmulqdq ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
	33	{evex} vpclmulqdq ymm2, ymm2, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8