i386: Also check R12-R15 registers when optimizing testq to testb
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / avx512vnni.d
CommitLineData
8cfcb765
IT
1#as:
2#objdump: -dw
3#name: i386 AVX512VNNI insns
4#source: avx512vnni.s
5
6.*: +file format .*
7
8
9Disassembly of section \.text:
10
1100000000 <_start>:
12[ ]*[a-f0-9]+:[ ]*62 f2 75 48 52 e3[ ]*vpdpwssd %zmm3,%zmm1,%zmm4
13[ ]*[a-f0-9]+:[ ]*62 f2 75 49 52 e3[ ]*vpdpwssd %zmm3,%zmm1,%zmm4\{%k1\}
14[ ]*[a-f0-9]+:[ ]*62 f2 75 c9 52 e3[ ]*vpdpwssd %zmm3,%zmm1,%zmm4\{%k1\}\{z\}
15[ ]*[a-f0-9]+:[ ]*62 f2 75 48 52 a4 f4 c0 1d fe ff[ ]*vpdpwssd -0x1e240\(%esp,%esi,8\),%zmm1,%zmm4
16[ ]*[a-f0-9]+:[ ]*62 f2 75 48 52 62 7f[ ]*vpdpwssd 0x1fc0\(%edx\),%zmm1,%zmm4
17[ ]*[a-f0-9]+:[ ]*62 f2 75 58 52 62 7f[ ]*vpdpwssd 0x1fc\(%edx\)\{1to16\},%zmm1,%zmm4
18[ ]*[a-f0-9]+:[ ]*62 f2 55 48 53 d4[ ]*vpdpwssds %zmm4,%zmm5,%zmm2
19[ ]*[a-f0-9]+:[ ]*62 f2 55 4e 53 d4[ ]*vpdpwssds %zmm4,%zmm5,%zmm2\{%k6\}
20[ ]*[a-f0-9]+:[ ]*62 f2 55 ce 53 d4[ ]*vpdpwssds %zmm4,%zmm5,%zmm2\{%k6\}\{z\}
21[ ]*[a-f0-9]+:[ ]*62 f2 55 48 53 94 f4 c0 1d fe ff[ ]*vpdpwssds -0x1e240\(%esp,%esi,8\),%zmm5,%zmm2
22[ ]*[a-f0-9]+:[ ]*62 f2 55 48 53 52 7f[ ]*vpdpwssds 0x1fc0\(%edx\),%zmm5,%zmm2
23[ ]*[a-f0-9]+:[ ]*62 f2 55 58 53 52 7f[ ]*vpdpwssds 0x1fc\(%edx\)\{1to16\},%zmm5,%zmm2
24[ ]*[a-f0-9]+:[ ]*62 f2 6d 48 50 eb[ ]*vpdpbusd %zmm3,%zmm2,%zmm5
25[ ]*[a-f0-9]+:[ ]*62 f2 6d 49 50 eb[ ]*vpdpbusd %zmm3,%zmm2,%zmm5\{%k1\}
26[ ]*[a-f0-9]+:[ ]*62 f2 6d c9 50 eb[ ]*vpdpbusd %zmm3,%zmm2,%zmm5\{%k1\}\{z\}
27[ ]*[a-f0-9]+:[ ]*62 f2 6d 48 50 ac f4 c0 1d fe ff[ ]*vpdpbusd -0x1e240\(%esp,%esi,8\),%zmm2,%zmm5
28[ ]*[a-f0-9]+:[ ]*62 f2 6d 48 50 6a 7f[ ]*vpdpbusd 0x1fc0\(%edx\),%zmm2,%zmm5
29[ ]*[a-f0-9]+:[ ]*62 f2 6d 58 50 6a 7f[ ]*vpdpbusd 0x1fc\(%edx\)\{1to16\},%zmm2,%zmm5
30[ ]*[a-f0-9]+:[ ]*62 f2 65 48 51 e9[ ]*vpdpbusds %zmm1,%zmm3,%zmm5
31[ ]*[a-f0-9]+:[ ]*62 f2 65 4a 51 e9[ ]*vpdpbusds %zmm1,%zmm3,%zmm5\{%k2\}
32[ ]*[a-f0-9]+:[ ]*62 f2 65 ca 51 e9[ ]*vpdpbusds %zmm1,%zmm3,%zmm5\{%k2\}\{z\}
33[ ]*[a-f0-9]+:[ ]*62 f2 65 48 51 ac f4 c0 1d fe ff[ ]*vpdpbusds -0x1e240\(%esp,%esi,8\),%zmm3,%zmm5
34[ ]*[a-f0-9]+:[ ]*62 f2 65 48 51 6a 7f[ ]*vpdpbusds 0x1fc0\(%edx\),%zmm3,%zmm5
35[ ]*[a-f0-9]+:[ ]*62 f2 65 58 51 6a 7f[ ]*vpdpbusds 0x1fc\(%edx\)\{1to16\},%zmm3,%zmm5
36[ ]*[a-f0-9]+:[ ]*62 f2 5d 48 52 d9[ ]*vpdpwssd %zmm1,%zmm4,%zmm3
37[ ]*[a-f0-9]+:[ ]*62 f2 5d 4b 52 d9[ ]*vpdpwssd %zmm1,%zmm4,%zmm3\{%k3\}
38[ ]*[a-f0-9]+:[ ]*62 f2 5d cb 52 d9[ ]*vpdpwssd %zmm1,%zmm4,%zmm3\{%k3\}\{z\}
39[ ]*[a-f0-9]+:[ ]*62 f2 5d 48 52 9c f4 c0 1d fe ff[ ]*vpdpwssd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm3
40[ ]*[a-f0-9]+:[ ]*62 f2 5d 48 52 5a 7f[ ]*vpdpwssd 0x1fc0\(%edx\),%zmm4,%zmm3
41[ ]*[a-f0-9]+:[ ]*62 f2 5d 58 52 5a 7f[ ]*vpdpwssd 0x1fc\(%edx\)\{1to16\},%zmm4,%zmm3
42[ ]*[a-f0-9]+:[ ]*62 f2 75 48 53 da[ ]*vpdpwssds %zmm2,%zmm1,%zmm3
43[ ]*[a-f0-9]+:[ ]*62 f2 75 4f 53 da[ ]*vpdpwssds %zmm2,%zmm1,%zmm3\{%k7\}
44[ ]*[a-f0-9]+:[ ]*62 f2 75 cf 53 da[ ]*vpdpwssds %zmm2,%zmm1,%zmm3\{%k7\}\{z\}
45[ ]*[a-f0-9]+:[ ]*62 f2 75 48 53 9c f4 c0 1d fe ff[ ]*vpdpwssds -0x1e240\(%esp,%esi,8\),%zmm1,%zmm3
46[ ]*[a-f0-9]+:[ ]*62 f2 75 48 53 5a 7f[ ]*vpdpwssds 0x1fc0\(%edx\),%zmm1,%zmm3
47[ ]*[a-f0-9]+:[ ]*62 f2 75 58 53 5a 7f[ ]*vpdpwssds 0x1fc\(%edx\)\{1to16\},%zmm1,%zmm3
48[ ]*[a-f0-9]+:[ ]*62 f2 5d 48 50 d9[ ]*vpdpbusd %zmm1,%zmm4,%zmm3
49[ ]*[a-f0-9]+:[ ]*62 f2 5d 4e 50 d9[ ]*vpdpbusd %zmm1,%zmm4,%zmm3\{%k6\}
50[ ]*[a-f0-9]+:[ ]*62 f2 5d ce 50 d9[ ]*vpdpbusd %zmm1,%zmm4,%zmm3\{%k6\}\{z\}
51[ ]*[a-f0-9]+:[ ]*62 f2 5d 48 50 9c f4 c0 1d fe ff[ ]*vpdpbusd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm3
52[ ]*[a-f0-9]+:[ ]*62 f2 5d 48 50 5a 7f[ ]*vpdpbusd 0x1fc0\(%edx\),%zmm4,%zmm3
53[ ]*[a-f0-9]+:[ ]*62 f2 5d 58 50 5a 7f[ ]*vpdpbusd 0x1fc\(%edx\)\{1to16\},%zmm4,%zmm3
54[ ]*[a-f0-9]+:[ ]*62 f2 75 48 51 c9[ ]*vpdpbusds %zmm1,%zmm1,%zmm1
55[ ]*[a-f0-9]+:[ ]*62 f2 75 49 51 c9[ ]*vpdpbusds %zmm1,%zmm1,%zmm1\{%k1\}
56[ ]*[a-f0-9]+:[ ]*62 f2 75 c9 51 c9[ ]*vpdpbusds %zmm1,%zmm1,%zmm1\{%k1\}\{z\}
57[ ]*[a-f0-9]+:[ ]*62 f2 75 48 51 8c f4 c0 1d fe ff[ ]*vpdpbusds -0x1e240\(%esp,%esi,8\),%zmm1,%zmm1
58[ ]*[a-f0-9]+:[ ]*62 f2 75 48 51 4a 7f[ ]*vpdpbusds 0x1fc0\(%edx\),%zmm1,%zmm1
59[ ]*[a-f0-9]+:[ ]*62 f2 75 58 51 4a 7f[ ]*vpdpbusds 0x1fc\(%edx\)\{1to16\},%zmm1,%zmm1
60#pass
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