projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 47acf0bd IT |
1 | #objdump: -dw -Mintel |
| 2 | #name: x86_64 AVX512/4VNNIW insns (Intel disassembly) | |
| 3 | #source: x86-64-avx512_4vnniw.s | |
| 4 | ||
| 5 | .*: +file format .* | |
| 6 | ||
| 7 | ||
| 8 | Disassembly of section \.text: | |
| 9 | ||
| 10 | 0+ <_start>: | |
| 11 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\] | |
| 12 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\] | |
| 13 | [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\] | |
| 14 | [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\] | |
| 15 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\] | |
| 16 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\] | |
| 17 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\] | |
| 18 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\] | |
| 19 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\] | |
| 20 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\] | |
| 21 | [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\] | |
| 22 | [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\] | |
| 23 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\] | |
| 24 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\] | |
| 25 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\] | |
| 26 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\] | |
| 27 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\] | |
| 28 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rcx\] | |
| 29 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\] | |
| 30 | [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\] | |
| 31 | [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\] | |
| 32 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\] | |
| 33 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\] | |
| 34 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\] | |
| 35 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\] | |
| 36 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\] | |
| 37 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rcx\] | |
| 38 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds zmm1\{k7\},zmm8,XMMWORD PTR \[rcx\] | |
| 39 | [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds zmm1\{k7\}\{z\},zmm8,XMMWORD PTR \[rcx\] | |
| 40 | [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rax\+r14\*8-0x1e240\] | |
| 41 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0xfe0\] | |
| 42 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx\+0x1000\] | |
| 43 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1000\] | |
| 44 | [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds zmm1,zmm8,XMMWORD PTR \[rdx-0x1020\] | |
| 45 | #pass |