Commit | Line | Data |
---|---|---|
99282af6 IT |
1 | # Check 64bit AVX512{CD,VL} instructions |
2 | ||
3 | .allow_index_reg | |
4 | .text | |
5 | _start: | |
6 | vpconflictd %xmm29, %xmm30 # AVX512{CD,VL} | |
7 | vpconflictd %xmm29, %xmm30{%k7} # AVX512{CD,VL} | |
8 | vpconflictd %xmm29, %xmm30{%k7}{z} # AVX512{CD,VL} | |
9 | vpconflictd (%rcx), %xmm30 # AVX512{CD,VL} | |
10 | vpconflictd 0x123(%rax,%r14,8), %xmm30 # AVX512{CD,VL} | |
11 | vpconflictd (%rcx){1to4}, %xmm30 # AVX512{CD,VL} | |
12 | vpconflictd 2032(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
13 | vpconflictd 2048(%rdx), %xmm30 # AVX512{CD,VL} | |
14 | vpconflictd -2048(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
15 | vpconflictd -2064(%rdx), %xmm30 # AVX512{CD,VL} | |
16 | vpconflictd 508(%rdx){1to4}, %xmm30 # AVX512{CD,VL} Disp8 | |
17 | vpconflictd 512(%rdx){1to4}, %xmm30 # AVX512{CD,VL} | |
18 | vpconflictd -512(%rdx){1to4}, %xmm30 # AVX512{CD,VL} Disp8 | |
19 | vpconflictd -516(%rdx){1to4}, %xmm30 # AVX512{CD,VL} | |
20 | vpconflictd %ymm29, %ymm30 # AVX512{CD,VL} | |
21 | vpconflictd %ymm29, %ymm30{%k7} # AVX512{CD,VL} | |
22 | vpconflictd %ymm29, %ymm30{%k7}{z} # AVX512{CD,VL} | |
23 | vpconflictd (%rcx), %ymm30 # AVX512{CD,VL} | |
24 | vpconflictd 0x123(%rax,%r14,8), %ymm30 # AVX512{CD,VL} | |
25 | vpconflictd (%rcx){1to8}, %ymm30 # AVX512{CD,VL} | |
26 | vpconflictd 4064(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
27 | vpconflictd 4096(%rdx), %ymm30 # AVX512{CD,VL} | |
28 | vpconflictd -4096(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
29 | vpconflictd -4128(%rdx), %ymm30 # AVX512{CD,VL} | |
30 | vpconflictd 508(%rdx){1to8}, %ymm30 # AVX512{CD,VL} Disp8 | |
31 | vpconflictd 512(%rdx){1to8}, %ymm30 # AVX512{CD,VL} | |
32 | vpconflictd -512(%rdx){1to8}, %ymm30 # AVX512{CD,VL} Disp8 | |
33 | vpconflictd -516(%rdx){1to8}, %ymm30 # AVX512{CD,VL} | |
34 | vpconflictq %xmm29, %xmm30 # AVX512{CD,VL} | |
35 | vpconflictq %xmm29, %xmm30{%k7} # AVX512{CD,VL} | |
36 | vpconflictq %xmm29, %xmm30{%k7}{z} # AVX512{CD,VL} | |
37 | vpconflictq (%rcx), %xmm30 # AVX512{CD,VL} | |
38 | vpconflictq 0x123(%rax,%r14,8), %xmm30 # AVX512{CD,VL} | |
39 | vpconflictq (%rcx){1to2}, %xmm30 # AVX512{CD,VL} | |
40 | vpconflictq 2032(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
41 | vpconflictq 2048(%rdx), %xmm30 # AVX512{CD,VL} | |
42 | vpconflictq -2048(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
43 | vpconflictq -2064(%rdx), %xmm30 # AVX512{CD,VL} | |
44 | vpconflictq 1016(%rdx){1to2}, %xmm30 # AVX512{CD,VL} Disp8 | |
45 | vpconflictq 1024(%rdx){1to2}, %xmm30 # AVX512{CD,VL} | |
46 | vpconflictq -1024(%rdx){1to2}, %xmm30 # AVX512{CD,VL} Disp8 | |
47 | vpconflictq -1032(%rdx){1to2}, %xmm30 # AVX512{CD,VL} | |
48 | vpconflictq %ymm29, %ymm30 # AVX512{CD,VL} | |
49 | vpconflictq %ymm29, %ymm30{%k7} # AVX512{CD,VL} | |
50 | vpconflictq %ymm29, %ymm30{%k7}{z} # AVX512{CD,VL} | |
51 | vpconflictq (%rcx), %ymm30 # AVX512{CD,VL} | |
52 | vpconflictq 0x123(%rax,%r14,8), %ymm30 # AVX512{CD,VL} | |
53 | vpconflictq (%rcx){1to4}, %ymm30 # AVX512{CD,VL} | |
54 | vpconflictq 4064(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
55 | vpconflictq 4096(%rdx), %ymm30 # AVX512{CD,VL} | |
56 | vpconflictq -4096(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
57 | vpconflictq -4128(%rdx), %ymm30 # AVX512{CD,VL} | |
58 | vpconflictq 1016(%rdx){1to4}, %ymm30 # AVX512{CD,VL} Disp8 | |
59 | vpconflictq 1024(%rdx){1to4}, %ymm30 # AVX512{CD,VL} | |
60 | vpconflictq -1024(%rdx){1to4}, %ymm30 # AVX512{CD,VL} Disp8 | |
61 | vpconflictq -1032(%rdx){1to4}, %ymm30 # AVX512{CD,VL} | |
62 | vplzcntd %xmm29, %xmm30 # AVX512{CD,VL} | |
63 | vplzcntd %xmm29, %xmm30{%k7} # AVX512{CD,VL} | |
64 | vplzcntd %xmm29, %xmm30{%k7}{z} # AVX512{CD,VL} | |
65 | vplzcntd (%rcx), %xmm30 # AVX512{CD,VL} | |
66 | vplzcntd 0x123(%rax,%r14,8), %xmm30 # AVX512{CD,VL} | |
67 | vplzcntd (%rcx){1to4}, %xmm30 # AVX512{CD,VL} | |
68 | vplzcntd 2032(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
69 | vplzcntd 2048(%rdx), %xmm30 # AVX512{CD,VL} | |
70 | vplzcntd -2048(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
71 | vplzcntd -2064(%rdx), %xmm30 # AVX512{CD,VL} | |
72 | vplzcntd 508(%rdx){1to4}, %xmm30 # AVX512{CD,VL} Disp8 | |
73 | vplzcntd 512(%rdx){1to4}, %xmm30 # AVX512{CD,VL} | |
74 | vplzcntd -512(%rdx){1to4}, %xmm30 # AVX512{CD,VL} Disp8 | |
75 | vplzcntd -516(%rdx){1to4}, %xmm30 # AVX512{CD,VL} | |
76 | vplzcntd %ymm29, %ymm30 # AVX512{CD,VL} | |
77 | vplzcntd %ymm29, %ymm30{%k7} # AVX512{CD,VL} | |
78 | vplzcntd %ymm29, %ymm30{%k7}{z} # AVX512{CD,VL} | |
79 | vplzcntd (%rcx), %ymm30 # AVX512{CD,VL} | |
80 | vplzcntd 0x123(%rax,%r14,8), %ymm30 # AVX512{CD,VL} | |
81 | vplzcntd (%rcx){1to8}, %ymm30 # AVX512{CD,VL} | |
82 | vplzcntd 4064(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
83 | vplzcntd 4096(%rdx), %ymm30 # AVX512{CD,VL} | |
84 | vplzcntd -4096(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
85 | vplzcntd -4128(%rdx), %ymm30 # AVX512{CD,VL} | |
86 | vplzcntd 508(%rdx){1to8}, %ymm30 # AVX512{CD,VL} Disp8 | |
87 | vplzcntd 512(%rdx){1to8}, %ymm30 # AVX512{CD,VL} | |
88 | vplzcntd -512(%rdx){1to8}, %ymm30 # AVX512{CD,VL} Disp8 | |
89 | vplzcntd -516(%rdx){1to8}, %ymm30 # AVX512{CD,VL} | |
90 | vplzcntq %xmm29, %xmm30 # AVX512{CD,VL} | |
91 | vplzcntq %xmm29, %xmm30{%k7} # AVX512{CD,VL} | |
92 | vplzcntq %xmm29, %xmm30{%k7}{z} # AVX512{CD,VL} | |
93 | vplzcntq (%rcx), %xmm30 # AVX512{CD,VL} | |
94 | vplzcntq 0x123(%rax,%r14,8), %xmm30 # AVX512{CD,VL} | |
95 | vplzcntq (%rcx){1to2}, %xmm30 # AVX512{CD,VL} | |
96 | vplzcntq 2032(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
97 | vplzcntq 2048(%rdx), %xmm30 # AVX512{CD,VL} | |
98 | vplzcntq -2048(%rdx), %xmm30 # AVX512{CD,VL} Disp8 | |
99 | vplzcntq -2064(%rdx), %xmm30 # AVX512{CD,VL} | |
100 | vplzcntq 1016(%rdx){1to2}, %xmm30 # AVX512{CD,VL} Disp8 | |
101 | vplzcntq 1024(%rdx){1to2}, %xmm30 # AVX512{CD,VL} | |
102 | vplzcntq -1024(%rdx){1to2}, %xmm30 # AVX512{CD,VL} Disp8 | |
103 | vplzcntq -1032(%rdx){1to2}, %xmm30 # AVX512{CD,VL} | |
104 | vplzcntq %ymm29, %ymm30 # AVX512{CD,VL} | |
105 | vplzcntq %ymm29, %ymm30{%k7} # AVX512{CD,VL} | |
106 | vplzcntq %ymm29, %ymm30{%k7}{z} # AVX512{CD,VL} | |
107 | vplzcntq (%rcx), %ymm30 # AVX512{CD,VL} | |
108 | vplzcntq 0x123(%rax,%r14,8), %ymm30 # AVX512{CD,VL} | |
109 | vplzcntq (%rcx){1to4}, %ymm30 # AVX512{CD,VL} | |
110 | vplzcntq 4064(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
111 | vplzcntq 4096(%rdx), %ymm30 # AVX512{CD,VL} | |
112 | vplzcntq -4096(%rdx), %ymm30 # AVX512{CD,VL} Disp8 | |
113 | vplzcntq -4128(%rdx), %ymm30 # AVX512{CD,VL} | |
114 | vplzcntq 1016(%rdx){1to4}, %ymm30 # AVX512{CD,VL} Disp8 | |
115 | vplzcntq 1024(%rdx){1to4}, %ymm30 # AVX512{CD,VL} | |
116 | vplzcntq -1024(%rdx){1to4}, %ymm30 # AVX512{CD,VL} Disp8 | |
117 | vplzcntq -1032(%rdx){1to4}, %ymm30 # AVX512{CD,VL} | |
118 | vpbroadcastmw2d %k6, %xmm30 # AVX512{CD,VL} | |
119 | vpbroadcastmw2d %k6, %ymm30 # AVX512{CD,VL} | |
120 | vpbroadcastmb2q %k6, %xmm30 # AVX512{CD,VL} | |
121 | vpbroadcastmb2q %k6, %ymm30 # AVX512{CD,VL} | |
122 | ||
123 | .intel_syntax noprefix | |
124 | vpconflictd xmm30, xmm29 # AVX512{CD,VL} | |
125 | vpconflictd xmm30{k7}, xmm29 # AVX512{CD,VL} | |
126 | vpconflictd xmm30{k7}{z}, xmm29 # AVX512{CD,VL} | |
127 | vpconflictd xmm30, XMMWORD PTR [rcx] # AVX512{CD,VL} | |
128 | vpconflictd xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
129 | vpconflictd xmm30, [rcx]{1to4} # AVX512{CD,VL} | |
130 | vpconflictd xmm30, XMMWORD PTR [rdx+2032] # AVX512{CD,VL} Disp8 | |
131 | vpconflictd xmm30, XMMWORD PTR [rdx+2048] # AVX512{CD,VL} | |
132 | vpconflictd xmm30, XMMWORD PTR [rdx-2048] # AVX512{CD,VL} Disp8 | |
133 | vpconflictd xmm30, XMMWORD PTR [rdx-2064] # AVX512{CD,VL} | |
134 | vpconflictd xmm30, [rdx+508]{1to4} # AVX512{CD,VL} Disp8 | |
135 | vpconflictd xmm30, [rdx+512]{1to4} # AVX512{CD,VL} | |
136 | vpconflictd xmm30, [rdx-512]{1to4} # AVX512{CD,VL} Disp8 | |
137 | vpconflictd xmm30, [rdx-516]{1to4} # AVX512{CD,VL} | |
138 | vpconflictd ymm30, ymm29 # AVX512{CD,VL} | |
139 | vpconflictd ymm30{k7}, ymm29 # AVX512{CD,VL} | |
140 | vpconflictd ymm30{k7}{z}, ymm29 # AVX512{CD,VL} | |
141 | vpconflictd ymm30, YMMWORD PTR [rcx] # AVX512{CD,VL} | |
142 | vpconflictd ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
143 | vpconflictd ymm30, [rcx]{1to8} # AVX512{CD,VL} | |
144 | vpconflictd ymm30, YMMWORD PTR [rdx+4064] # AVX512{CD,VL} Disp8 | |
145 | vpconflictd ymm30, YMMWORD PTR [rdx+4096] # AVX512{CD,VL} | |
146 | vpconflictd ymm30, YMMWORD PTR [rdx-4096] # AVX512{CD,VL} Disp8 | |
147 | vpconflictd ymm30, YMMWORD PTR [rdx-4128] # AVX512{CD,VL} | |
148 | vpconflictd ymm30, [rdx+508]{1to8} # AVX512{CD,VL} Disp8 | |
149 | vpconflictd ymm30, [rdx+512]{1to8} # AVX512{CD,VL} | |
150 | vpconflictd ymm30, [rdx-512]{1to8} # AVX512{CD,VL} Disp8 | |
151 | vpconflictd ymm30, [rdx-516]{1to8} # AVX512{CD,VL} | |
152 | vpconflictq xmm30, xmm29 # AVX512{CD,VL} | |
153 | vpconflictq xmm30{k7}, xmm29 # AVX512{CD,VL} | |
154 | vpconflictq xmm30{k7}{z}, xmm29 # AVX512{CD,VL} | |
155 | vpconflictq xmm30, XMMWORD PTR [rcx] # AVX512{CD,VL} | |
156 | vpconflictq xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
157 | vpconflictq xmm30, [rcx]{1to2} # AVX512{CD,VL} | |
158 | vpconflictq xmm30, XMMWORD PTR [rdx+2032] # AVX512{CD,VL} Disp8 | |
159 | vpconflictq xmm30, XMMWORD PTR [rdx+2048] # AVX512{CD,VL} | |
160 | vpconflictq xmm30, XMMWORD PTR [rdx-2048] # AVX512{CD,VL} Disp8 | |
161 | vpconflictq xmm30, XMMWORD PTR [rdx-2064] # AVX512{CD,VL} | |
162 | vpconflictq xmm30, [rdx+1016]{1to2} # AVX512{CD,VL} Disp8 | |
163 | vpconflictq xmm30, [rdx+1024]{1to2} # AVX512{CD,VL} | |
164 | vpconflictq xmm30, [rdx-1024]{1to2} # AVX512{CD,VL} Disp8 | |
165 | vpconflictq xmm30, [rdx-1032]{1to2} # AVX512{CD,VL} | |
166 | vpconflictq ymm30, ymm29 # AVX512{CD,VL} | |
167 | vpconflictq ymm30{k7}, ymm29 # AVX512{CD,VL} | |
168 | vpconflictq ymm30{k7}{z}, ymm29 # AVX512{CD,VL} | |
169 | vpconflictq ymm30, YMMWORD PTR [rcx] # AVX512{CD,VL} | |
170 | vpconflictq ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
171 | vpconflictq ymm30, [rcx]{1to4} # AVX512{CD,VL} | |
172 | vpconflictq ymm30, YMMWORD PTR [rdx+4064] # AVX512{CD,VL} Disp8 | |
173 | vpconflictq ymm30, YMMWORD PTR [rdx+4096] # AVX512{CD,VL} | |
174 | vpconflictq ymm30, YMMWORD PTR [rdx-4096] # AVX512{CD,VL} Disp8 | |
175 | vpconflictq ymm30, YMMWORD PTR [rdx-4128] # AVX512{CD,VL} | |
176 | vpconflictq ymm30, [rdx+1016]{1to4} # AVX512{CD,VL} Disp8 | |
177 | vpconflictq ymm30, [rdx+1024]{1to4} # AVX512{CD,VL} | |
178 | vpconflictq ymm30, [rdx-1024]{1to4} # AVX512{CD,VL} Disp8 | |
179 | vpconflictq ymm30, [rdx-1032]{1to4} # AVX512{CD,VL} | |
180 | vplzcntd xmm30, xmm29 # AVX512{CD,VL} | |
181 | vplzcntd xmm30{k7}, xmm29 # AVX512{CD,VL} | |
182 | vplzcntd xmm30{k7}{z}, xmm29 # AVX512{CD,VL} | |
183 | vplzcntd xmm30, XMMWORD PTR [rcx] # AVX512{CD,VL} | |
184 | vplzcntd xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
185 | vplzcntd xmm30, [rcx]{1to4} # AVX512{CD,VL} | |
186 | vplzcntd xmm30, XMMWORD PTR [rdx+2032] # AVX512{CD,VL} Disp8 | |
187 | vplzcntd xmm30, XMMWORD PTR [rdx+2048] # AVX512{CD,VL} | |
188 | vplzcntd xmm30, XMMWORD PTR [rdx-2048] # AVX512{CD,VL} Disp8 | |
189 | vplzcntd xmm30, XMMWORD PTR [rdx-2064] # AVX512{CD,VL} | |
190 | vplzcntd xmm30, [rdx+508]{1to4} # AVX512{CD,VL} Disp8 | |
191 | vplzcntd xmm30, [rdx+512]{1to4} # AVX512{CD,VL} | |
192 | vplzcntd xmm30, [rdx-512]{1to4} # AVX512{CD,VL} Disp8 | |
193 | vplzcntd xmm30, [rdx-516]{1to4} # AVX512{CD,VL} | |
194 | vplzcntd ymm30, ymm29 # AVX512{CD,VL} | |
195 | vplzcntd ymm30{k7}, ymm29 # AVX512{CD,VL} | |
196 | vplzcntd ymm30{k7}{z}, ymm29 # AVX512{CD,VL} | |
197 | vplzcntd ymm30, YMMWORD PTR [rcx] # AVX512{CD,VL} | |
198 | vplzcntd ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
199 | vplzcntd ymm30, [rcx]{1to8} # AVX512{CD,VL} | |
200 | vplzcntd ymm30, YMMWORD PTR [rdx+4064] # AVX512{CD,VL} Disp8 | |
201 | vplzcntd ymm30, YMMWORD PTR [rdx+4096] # AVX512{CD,VL} | |
202 | vplzcntd ymm30, YMMWORD PTR [rdx-4096] # AVX512{CD,VL} Disp8 | |
203 | vplzcntd ymm30, YMMWORD PTR [rdx-4128] # AVX512{CD,VL} | |
204 | vplzcntd ymm30, [rdx+508]{1to8} # AVX512{CD,VL} Disp8 | |
205 | vplzcntd ymm30, [rdx+512]{1to8} # AVX512{CD,VL} | |
206 | vplzcntd ymm30, [rdx-512]{1to8} # AVX512{CD,VL} Disp8 | |
207 | vplzcntd ymm30, [rdx-516]{1to8} # AVX512{CD,VL} | |
208 | vplzcntq xmm30, xmm29 # AVX512{CD,VL} | |
209 | vplzcntq xmm30{k7}, xmm29 # AVX512{CD,VL} | |
210 | vplzcntq xmm30{k7}{z}, xmm29 # AVX512{CD,VL} | |
211 | vplzcntq xmm30, XMMWORD PTR [rcx] # AVX512{CD,VL} | |
212 | vplzcntq xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
213 | vplzcntq xmm30, [rcx]{1to2} # AVX512{CD,VL} | |
214 | vplzcntq xmm30, XMMWORD PTR [rdx+2032] # AVX512{CD,VL} Disp8 | |
215 | vplzcntq xmm30, XMMWORD PTR [rdx+2048] # AVX512{CD,VL} | |
216 | vplzcntq xmm30, XMMWORD PTR [rdx-2048] # AVX512{CD,VL} Disp8 | |
217 | vplzcntq xmm30, XMMWORD PTR [rdx-2064] # AVX512{CD,VL} | |
218 | vplzcntq xmm30, [rdx+1016]{1to2} # AVX512{CD,VL} Disp8 | |
219 | vplzcntq xmm30, [rdx+1024]{1to2} # AVX512{CD,VL} | |
220 | vplzcntq xmm30, [rdx-1024]{1to2} # AVX512{CD,VL} Disp8 | |
221 | vplzcntq xmm30, [rdx-1032]{1to2} # AVX512{CD,VL} | |
222 | vplzcntq ymm30, ymm29 # AVX512{CD,VL} | |
223 | vplzcntq ymm30{k7}, ymm29 # AVX512{CD,VL} | |
224 | vplzcntq ymm30{k7}{z}, ymm29 # AVX512{CD,VL} | |
225 | vplzcntq ymm30, YMMWORD PTR [rcx] # AVX512{CD,VL} | |
226 | vplzcntq ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{CD,VL} | |
227 | vplzcntq ymm30, [rcx]{1to4} # AVX512{CD,VL} | |
228 | vplzcntq ymm30, YMMWORD PTR [rdx+4064] # AVX512{CD,VL} Disp8 | |
229 | vplzcntq ymm30, YMMWORD PTR [rdx+4096] # AVX512{CD,VL} | |
230 | vplzcntq ymm30, YMMWORD PTR [rdx-4096] # AVX512{CD,VL} Disp8 | |
231 | vplzcntq ymm30, YMMWORD PTR [rdx-4128] # AVX512{CD,VL} | |
232 | vplzcntq ymm30, [rdx+1016]{1to4} # AVX512{CD,VL} Disp8 | |
233 | vplzcntq ymm30, [rdx+1024]{1to4} # AVX512{CD,VL} | |
234 | vplzcntq ymm30, [rdx-1024]{1to4} # AVX512{CD,VL} Disp8 | |
235 | vplzcntq ymm30, [rdx-1032]{1to4} # AVX512{CD,VL} | |
236 | vpbroadcastmw2d xmm30, k6 # AVX512{CD,VL} | |
237 | vpbroadcastmw2d ymm30, k6 # AVX512{CD,VL} | |
238 | vpbroadcastmb2q xmm30, k6 # AVX512{CD,VL} | |
239 | vpbroadcastmb2q ymm30, k6 # AVX512{CD,VL} |