Commit | Line | Data |
---|---|---|
d3d3c6db IT |
1 | #as: -mevexrcig=rd |
2 | #objdump: -dw -Mintel | |
3 | #name: x86_64 AVX512ER rcig insns (Intel disassembly) | |
4 | #source: x86-64-avx512er-rcig.s | |
5 | ||
6 | .*: +file format .* | |
7 | ||
8 | ||
9 | Disassembly of section \.text: | |
10 | ||
11 | 0+ <_start>: | |
12 | [ ]*[a-f0-9]+:[ ]*62 02 7d 38 c8 f5[ ]*vexp2ps zmm30,zmm29,\{sae\} | |
13 | [ ]*[a-f0-9]+:[ ]*62 02 fd 38 c8 f5[ ]*vexp2pd zmm30,zmm29,\{sae\} | |
14 | [ ]*[a-f0-9]+:[ ]*62 02 7d 38 ca f5[ ]*vrcp28ps zmm30,zmm29,\{sae\} | |
15 | [ ]*[a-f0-9]+:[ ]*62 02 fd 38 ca f5[ ]*vrcp28pd zmm30,zmm29,\{sae\} | |
16 | [ ]*[a-f0-9]+:[ ]*62 02 15 30 cb f4[ ]*vrcp28ss xmm30,xmm29,xmm28,\{sae\} | |
17 | [ ]*[a-f0-9]+:[ ]*62 02 95 30 cb f4[ ]*vrcp28sd xmm30,xmm29,xmm28,\{sae\} | |
18 | [ ]*[a-f0-9]+:[ ]*62 02 7d 38 cc f5[ ]*vrsqrt28ps zmm30,zmm29,\{sae\} | |
19 | [ ]*[a-f0-9]+:[ ]*62 02 fd 38 cc f5[ ]*vrsqrt28pd zmm30,zmm29,\{sae\} | |
20 | [ ]*[a-f0-9]+:[ ]*62 02 15 30 cd f4[ ]*vrsqrt28ss xmm30,xmm29,xmm28,\{sae\} | |
21 | [ ]*[a-f0-9]+:[ ]*62 02 95 30 cd f4[ ]*vrsqrt28sd xmm30,xmm29,xmm28,\{sae\} | |
22 | [ ]*[a-f0-9]+:[ ]*62 02 7d 38 c8 f5[ ]*vexp2ps zmm30,zmm29,\{sae\} | |
23 | [ ]*[a-f0-9]+:[ ]*62 02 fd 38 c8 f5[ ]*vexp2pd zmm30,zmm29,\{sae\} | |
24 | [ ]*[a-f0-9]+:[ ]*62 02 7d 38 ca f5[ ]*vrcp28ps zmm30,zmm29,\{sae\} | |
25 | [ ]*[a-f0-9]+:[ ]*62 02 fd 38 ca f5[ ]*vrcp28pd zmm30,zmm29,\{sae\} | |
26 | [ ]*[a-f0-9]+:[ ]*62 02 15 30 cb f4[ ]*vrcp28ss xmm30,xmm29,xmm28,\{sae\} | |
27 | [ ]*[a-f0-9]+:[ ]*62 02 95 30 cb f4[ ]*vrcp28sd xmm30,xmm29,xmm28,\{sae\} | |
28 | [ ]*[a-f0-9]+:[ ]*62 02 7d 38 cc f5[ ]*vrsqrt28ps zmm30,zmm29,\{sae\} | |
29 | [ ]*[a-f0-9]+:[ ]*62 02 fd 38 cc f5[ ]*vrsqrt28pd zmm30,zmm29,\{sae\} | |
30 | [ ]*[a-f0-9]+:[ ]*62 02 15 30 cd f4[ ]*vrsqrt28ss xmm30,xmm29,xmm28,\{sae\} | |
31 | [ ]*[a-f0-9]+:[ ]*62 02 95 30 cd f4[ ]*vrsqrt28sd xmm30,xmm29,xmm28,\{sae\} | |
32 | #pass |