projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 2cc1b5aa IT |
1 | # Check 64bit AVX512{IFMA,VL} instructions |
| 2 | ||
| 3 | .allow_index_reg | |
| 4 | .text | |
| 5 | _start: | |
| 6 | vpmadd52luq %xmm28, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 7 | vpmadd52luq %xmm28, %xmm29, %xmm30{%k7} # AVX512{IFMA,VL} | |
| 8 | vpmadd52luq %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{IFMA,VL} | |
| 9 | vpmadd52luq (%rcx), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 10 | vpmadd52luq 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 11 | vpmadd52luq (%rcx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 12 | vpmadd52luq 2032(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 13 | vpmadd52luq 2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 14 | vpmadd52luq -2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 15 | vpmadd52luq -2064(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 16 | vpmadd52luq 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 17 | vpmadd52luq 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 18 | vpmadd52luq -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 19 | vpmadd52luq -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 20 | vpmadd52luq %ymm28, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 21 | vpmadd52luq %ymm28, %ymm29, %ymm30{%k7} # AVX512{IFMA,VL} | |
| 22 | vpmadd52luq %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{IFMA,VL} | |
| 23 | vpmadd52luq (%rcx), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 24 | vpmadd52luq 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 25 | vpmadd52luq (%rcx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 26 | vpmadd52luq 4064(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 27 | vpmadd52luq 4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 28 | vpmadd52luq -4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 29 | vpmadd52luq -4128(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 30 | vpmadd52luq 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 31 | vpmadd52luq 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 32 | vpmadd52luq -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 33 | vpmadd52luq -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 34 | vpmadd52huq %xmm28, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 35 | vpmadd52huq %xmm28, %xmm29, %xmm30{%k7} # AVX512{IFMA,VL} | |
| 36 | vpmadd52huq %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{IFMA,VL} | |
| 37 | vpmadd52huq (%rcx), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 38 | vpmadd52huq 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 39 | vpmadd52huq (%rcx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 40 | vpmadd52huq 2032(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 41 | vpmadd52huq 2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 42 | vpmadd52huq -2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 43 | vpmadd52huq -2064(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 44 | vpmadd52huq 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 45 | vpmadd52huq 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 46 | vpmadd52huq -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8 | |
| 47 | vpmadd52huq -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} | |
| 48 | vpmadd52huq %ymm28, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 49 | vpmadd52huq %ymm28, %ymm29, %ymm30{%k7} # AVX512{IFMA,VL} | |
| 50 | vpmadd52huq %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{IFMA,VL} | |
| 51 | vpmadd52huq (%rcx), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 52 | vpmadd52huq 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 53 | vpmadd52huq (%rcx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 54 | vpmadd52huq 4064(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 55 | vpmadd52huq 4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 56 | vpmadd52huq -4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 57 | vpmadd52huq -4128(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 58 | vpmadd52huq 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 59 | vpmadd52huq 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 60 | vpmadd52huq -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8 | |
| 61 | vpmadd52huq -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} | |
| 62 | ||
| 63 | .intel_syntax noprefix | |
| 64 | vpmadd52luq xmm30, xmm29, xmm28 # AVX512{IFMA,VL} | |
| 65 | vpmadd52luq xmm30{k7}, xmm29, xmm28 # AVX512{IFMA,VL} | |
| 66 | vpmadd52luq xmm30{k7}{z}, xmm29, xmm28 # AVX512{IFMA,VL} | |
| 67 | vpmadd52luq xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{IFMA,VL} | |
| 68 | vpmadd52luq xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL} | |
| 69 | vpmadd52luq xmm30, xmm29, [rcx]{1to2} # AVX512{IFMA,VL} | |
| 70 | vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{IFMA,VL} Disp8 | |
| 71 | vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{IFMA,VL} | |
| 72 | vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{IFMA,VL} Disp8 | |
| 73 | vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{IFMA,VL} | |
| 74 | vpmadd52luq xmm30, xmm29, [rdx+1016]{1to2} # AVX512{IFMA,VL} Disp8 | |
| 75 | vpmadd52luq xmm30, xmm29, [rdx+1024]{1to2} # AVX512{IFMA,VL} | |
| 76 | vpmadd52luq xmm30, xmm29, [rdx-1024]{1to2} # AVX512{IFMA,VL} Disp8 | |
| 77 | vpmadd52luq xmm30, xmm29, [rdx-1032]{1to2} # AVX512{IFMA,VL} | |
| 78 | vpmadd52luq ymm30, ymm29, ymm28 # AVX512{IFMA,VL} | |
| 79 | vpmadd52luq ymm30{k7}, ymm29, ymm28 # AVX512{IFMA,VL} | |
| 80 | vpmadd52luq ymm30{k7}{z}, ymm29, ymm28 # AVX512{IFMA,VL} | |
| 81 | vpmadd52luq ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{IFMA,VL} | |
| 82 | vpmadd52luq ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL} | |
| 83 | vpmadd52luq ymm30, ymm29, [rcx]{1to4} # AVX512{IFMA,VL} | |
| 84 | vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{IFMA,VL} Disp8 | |
| 85 | vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{IFMA,VL} | |
| 86 | vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{IFMA,VL} Disp8 | |
| 87 | vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{IFMA,VL} | |
| 88 | vpmadd52luq ymm30, ymm29, [rdx+1016]{1to4} # AVX512{IFMA,VL} Disp8 | |
| 89 | vpmadd52luq ymm30, ymm29, [rdx+1024]{1to4} # AVX512{IFMA,VL} | |
| 90 | vpmadd52luq ymm30, ymm29, [rdx-1024]{1to4} # AVX512{IFMA,VL} Disp8 | |
| 91 | vpmadd52luq ymm30, ymm29, [rdx-1032]{1to4} # AVX512{IFMA,VL} | |
| 92 | vpmadd52huq xmm30, xmm29, xmm28 # AVX512{IFMA,VL} | |
| 93 | vpmadd52huq xmm30{k7}, xmm29, xmm28 # AVX512{IFMA,VL} | |
| 94 | vpmadd52huq xmm30{k7}{z}, xmm29, xmm28 # AVX512{IFMA,VL} | |
| 95 | vpmadd52huq xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{IFMA,VL} | |
| 96 | vpmadd52huq xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL} | |
| 97 | vpmadd52huq xmm30, xmm29, [rcx]{1to2} # AVX512{IFMA,VL} | |
| 98 | vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{IFMA,VL} Disp8 | |
| 99 | vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{IFMA,VL} | |
| 100 | vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{IFMA,VL} Disp8 | |
| 101 | vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{IFMA,VL} | |
| 102 | vpmadd52huq xmm30, xmm29, [rdx+1016]{1to2} # AVX512{IFMA,VL} Disp8 | |
| 103 | vpmadd52huq xmm30, xmm29, [rdx+1024]{1to2} # AVX512{IFMA,VL} | |
| 104 | vpmadd52huq xmm30, xmm29, [rdx-1024]{1to2} # AVX512{IFMA,VL} Disp8 | |
| 105 | vpmadd52huq xmm30, xmm29, [rdx-1032]{1to2} # AVX512{IFMA,VL} | |
| 106 | vpmadd52huq ymm30, ymm29, ymm28 # AVX512{IFMA,VL} | |
| 107 | vpmadd52huq ymm30{k7}, ymm29, ymm28 # AVX512{IFMA,VL} | |
| 108 | vpmadd52huq ymm30{k7}{z}, ymm29, ymm28 # AVX512{IFMA,VL} | |
| 109 | vpmadd52huq ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{IFMA,VL} | |
| 110 | vpmadd52huq ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL} | |
| 111 | vpmadd52huq ymm30, ymm29, [rcx]{1to4} # AVX512{IFMA,VL} | |
| 112 | vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{IFMA,VL} Disp8 | |
| 113 | vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{IFMA,VL} | |
| 114 | vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{IFMA,VL} Disp8 | |
| 115 | vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{IFMA,VL} | |
| 116 | vpmadd52huq ymm30, ymm29, [rdx+1016]{1to4} # AVX512{IFMA,VL} Disp8 | |
| 117 | vpmadd52huq ymm30, ymm29, [rdx+1024]{1to4} # AVX512{IFMA,VL} | |
| 118 | vpmadd52huq ymm30, ymm29, [rdx-1024]{1to4} # AVX512{IFMA,VL} Disp8 | |
| 119 | vpmadd52huq ymm30, ymm29, [rdx-1032]{1to4} # AVX512{IFMA,VL} |