x86: add missing pseudo ops for VPCLMULQDQ ISA extension
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-avx512vl_vpclmulqdq-intel.d
CommitLineData
ff1982d5
IT
1#as:
2#objdump: -dw -Mintel
3#name: x86_64 AVX512VL/VPCLMULQDQ insns (Intel disassembly)
4#source: x86-64-avx512vl_vpclmulqdq.s
5
6.*: +file format .*
7
8
9Disassembly of section \.text:
10
110+ <_start>:
12[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 ca ab[ ]*vpclmulqdq xmm25,xmm29,xmm18,0xab
13[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
14[ ]*[a-f0-9]+:[ ]*62 63 15 00 44 4a 7f 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
15[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ea ab[ ]*vpclmulqdq ymm29,ymm18,ymm18,0xab
16[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
17[ ]*[a-f0-9]+:[ ]*62 63 6d 20 44 6a 7f 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
18[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 ca ab[ ]*vpclmulqdq xmm25,xmm29,xmm18,0xab
19[ ]*[a-f0-9]+:[ ]*62 23 15 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
20[ ]*[a-f0-9]+:[ ]*62 63 15 00 44 4a 7f 7b[ ]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
21[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ea ab[ ]*vpclmulqdq ymm29,ymm18,ymm18,0xab
22[ ]*[a-f0-9]+:[ ]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
23[ ]*[a-f0-9]+:[ ]*62 63 6d 20 44 6a 7f 7b[ ]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
cd546e7b
JB
24[ ]*[a-f0-9]+:[ ]*62 a3 55 00 44 f4 11[ ]*vpclmulhqhqdq xmm22,xmm21,xmm20
25[ ]*[a-f0-9]+:[ ]*62 a3 4d 00 44 fd 01[ ]*vpclmulhqlqdq xmm23,xmm22,xmm21
26[ ]*[a-f0-9]+:[ ]*62 23 45 00 44 c6 10[ ]*vpclmullqhqdq xmm24,xmm23,xmm22
27[ ]*[a-f0-9]+:[ ]*62 23 3d 00 44 cf 00[ ]*vpclmullqlqdq xmm25,xmm24,xmm23
28[ ]*[a-f0-9]+:[ ]*62 a3 55 20 44 f4 11[ ]*vpclmulhqhqdq ymm22,ymm21,ymm20
29[ ]*[a-f0-9]+:[ ]*62 a3 4d 20 44 fd 01[ ]*vpclmulhqlqdq ymm23,ymm22,ymm21
30[ ]*[a-f0-9]+:[ ]*62 23 45 20 44 c6 10[ ]*vpclmullqhqdq ymm24,ymm23,ymm22
31[ ]*[a-f0-9]+:[ ]*62 23 3d 20 44 cf 00[ ]*vpclmullqlqdq ymm25,ymm24,ymm23
ff1982d5
IT
32[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 dc ab[ ]*vpclmulqdq xmm19,xmm26,xmm20,0xab
33[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
34[ ]*[a-f0-9]+:[ ]*62 e3 2d 00 44 5a 7f 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rdx\+0x7f0\],0x7b
35[ ]*[a-f0-9]+:[ ]*62 83 15 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm29,ymm27,0xab
36[ ]*[a-f0-9]+:[ ]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
37[ ]*[a-f0-9]+:[ ]*62 e3 15 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
38[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 dc ab[ ]*vpclmulqdq xmm19,xmm26,xmm20,0xab
39[ ]*[a-f0-9]+:[ ]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
40[ ]*[a-f0-9]+:[ ]*62 e3 2d 00 44 5a 7f 7b[ ]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rdx\+0x7f0\],0x7b
41[ ]*[a-f0-9]+:[ ]*62 83 15 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm29,ymm27,0xab
42[ ]*[a-f0-9]+:[ ]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
43[ ]*[a-f0-9]+:[ ]*62 e3 15 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
44#pass
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