[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-avx512vl_vpclmulqdq-wig.s

# Check 64bit AVX512VL,VPCLMULQDQ WIG instructions

	.allow_index_reg
	.text
_start:
	vpclmulqdq	$0xab, %xmm23, %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, 0x123(%rax,%r14,8), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, 2032(%rdx), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ Disp8
	vpclmulqdq	$0xab, %ymm19, %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, 0x123(%rax,%r14,8), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	$123, 4064(%rdx), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ Disp8

	{evex} vpclmulqdq	$0xab, %xmm23, %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, 0x123(%rax,%r14,8), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, 2032(%rdx), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ Disp8
	{evex} vpclmulqdq	$0xab, %ymm19, %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, 0x123(%rax,%r14,8), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	$123, 4064(%rdx), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ Disp8

	.intel_syntax noprefix
	vpclmulqdq	xmm18, xmm22, xmm17, 0xab	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rdx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
	vpclmulqdq	ymm26, ymm25, ymm23, 0xab	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
	vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rdx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8

	{evex} vpclmulqdq	xmm18, xmm22, xmm17, 0xab	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rdx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
	{evex} vpclmulqdq	ymm26, ymm25, ymm23, 0xab	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
	{evex} vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rdx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
Commit	Line	Data
ff1982d5 IT	1	# Check 64bit AVX512VL,VPCLMULQDQ WIG instructions
	2
	3	.allow_index_reg
	4	.text
	5	_start:
	6	vpclmulqdq $0xab, %xmm23, %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
	7	vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
	8	vpclmulqdq $123, 2032(%rdx), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ Disp8
	9	vpclmulqdq $0xab, %ymm19, %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
	10	vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
	11	vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ Disp8
	12
	13	{evex} vpclmulqdq $0xab, %xmm23, %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
	14	{evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
	15	{evex} vpclmulqdq $123, 2032(%rdx), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ Disp8
	16	{evex} vpclmulqdq $0xab, %ymm19, %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
	17	{evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
	18	{evex} vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ Disp8
	19
	20	.intel_syntax noprefix
	21	vpclmulqdq xmm18, xmm22, xmm17, 0xab # AVX512VL,VPCLMULQDQ
	22	vpclmulqdq xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
	23	vpclmulqdq xmm18, xmm22, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
	24	vpclmulqdq ymm26, ymm25, ymm23, 0xab # AVX512VL,VPCLMULQDQ
	25	vpclmulqdq ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
	26	vpclmulqdq ymm26, ymm25, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
	27
	28	{evex} vpclmulqdq xmm18, xmm22, xmm17, 0xab # AVX512VL,VPCLMULQDQ
	29	{evex} vpclmulqdq xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
	30	{evex} vpclmulqdq xmm18, xmm22, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
	31	{evex} vpclmulqdq ymm26, ymm25, ymm23, 0xab # AVX512VL,VPCLMULQDQ
	32	{evex} vpclmulqdq ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
	33	{evex} vpclmulqdq ymm26, ymm25, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8