a09f656b |
1 | #source: x86-64-lfence-ret.s |
2 | #as: -mlfence-before-ret=shl |
3 | #warning_output: x86-64-lfence-ret.e |
4 | #objdump: -dw -Mintel64 |
5 | #name: x86-64 -mlfence-before-ret=yes |
6 | |
7 | .*: +file format .* |
8 | |
9 | |
10 | Disassembly of section .text: |
11 | |
12 | 0+ <_start>: |
13 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
14 | +[a-f0-9]+: 0f ae e8 lfence |
15 | +[a-f0-9]+: 66 c3 data16 retq |
16 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
17 | +[a-f0-9]+: 0f ae e8 lfence |
18 | +[a-f0-9]+: 66 c2 14 00 data16 retq \$0x14 |
19 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
20 | +[a-f0-9]+: 0f ae e8 lfence |
21 | +[a-f0-9]+: c3 retq |
22 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
23 | +[a-f0-9]+: 0f ae e8 lfence |
24 | +[a-f0-9]+: c2 1e 00 retq \$0x1e |
25 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
26 | +[a-f0-9]+: 0f ae e8 lfence |
27 | +[a-f0-9]+: 66 48 c3 data16 rex.W retq |
28 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
29 | +[a-f0-9]+: 0f ae e8 lfence |
30 | +[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28 |
31 | +[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\) |
32 | +[a-f0-9]+: 0f ae e8 lfence |
33 | +[a-f0-9]+: 66 cb lretw |
34 | +[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\) |
35 | +[a-f0-9]+: 0f ae e8 lfence |
36 | +[a-f0-9]+: 66 ca 28 00 lretw \$0x28 |
37 | +[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\) |
38 | +[a-f0-9]+: 0f ae e8 lfence |
39 | +[a-f0-9]+: cb lret |
40 | +[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\) |
41 | +[a-f0-9]+: 0f ae e8 lfence |
42 | +[a-f0-9]+: ca 28 00 lret \$0x28 |
43 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
44 | +[a-f0-9]+: 0f ae e8 lfence |
45 | +[a-f0-9]+: 48 cb lretq |
46 | +[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\) |
47 | +[a-f0-9]+: 0f ae e8 lfence |
48 | +[a-f0-9]+: 48 ca 28 00 lretq \$0x28 |
49 | #pass |