[deliverable/binutils-gdb.git] / gas / testsuite / gas / m68hc11 / insns-dwarf2.d

#objdump: -S
#as: -m68hc11 -gdwarf2
#name: Dwarf2 test on insns.s
#source: insns.s

# Test handling of basic instructions.

.*: +file format elf32\-m68hc11

Disassembly of section .text:

00000000 <_start>:
	.globl _start
	.sect .text

_start:
	lds #stack\+1024
   0:	8e 04 00    	lds	#400 <stack_end>
	ldx #1
   3:	ce 00 01    	ldx	#1 <_start\+0x1>

0+06 <Loop>:
Loop:	
	jsr test
   6:	bd 00 00    	jsr	0 <_start>
	dex
   9:	09          	dex
	bne Loop
   a:	26 fa       	bne	6 <Loop>

0000000c <Stop>:
   c:	cd 03       	.byte	0xcd, 0x03
Stop:
	
	.byte 0xcd
	.byte 3	
	bra _start
   e:	20 f0       	bra	0 <_start>

00000010 <test>:

test:
	ldd #2
  10:	cc 00 02    	ldd	#2 <_start\+0x2>
	jsr test2
  13:	bd 00 00    	jsr	0 <_start>
	rts
  16:	39          	rts

00000017 <test2>:

B_low = 12
A_low = 44
D_low = 50
value = 23
		
	.globl test2
test2:
	ldx value,y
  17:	cd ee 17    	ldx	23,y
	std value,x
  1a:	ed 17       	std	23,x
	ldd ,x
  1c:	ec 00       	ldd	0,x
	sty ,y
  1e:	18 ef 00    	sty	0,y
	stx ,y
  21:	cd ef 00    	stx	0,y
	brclr 6,x,#4,test2
  24:	1f 06 04 ef 	brclr	6,x #\$04 17 <test2>
	brclr 12,x #8 test2
  28:	1f 0c 08 eb 	brclr	12,x #\$08 17 <test2>
	ldd \*ZD1
  2c:	dc 00       	ldd	\*0 <_start>
	ldx \*ZD1\+2
  2e:	de 02       	ldx	\*2 <_start\+0x2>
	clr \*ZD2
  30:	7f 00 00    	clr	0 <_start>
	clr \*ZD2\+1
  33:	7f 00 01    	clr	1 <_start\+0x1>
	bne .-4
  36:	26 fc       	bne	34 <test2\+0x1d>
	beq .\+2
  38:	27 02       	beq	3c <test2\+0x25>
	bclr \*ZD1\+1, #32
  3a:	15 01 20    	bclr	\*1 <_start\+0x1> #\$20
	brclr \*ZD2\+2, #40, test2
  3d:	13 02 28 d6 	brclr	\*2 <_start\+0x2> #\$28 17 <test2>
	ldy #24\+_start-44
  41:	18 ce ff ec 	ldy	#ffec <stack_end\+0xfbec>
	ldd B_low,y
  45:	18 ec 0c    	ldd	12,y
	addd A_low,y
  48:	18 e3 2c    	addd	44,y
	addd D_low,y
  4b:	18 e3 32    	addd	50,y
	subd A_low
  4e:	b3 00 2c    	subd	2c <test2\+0x15>
	subd #A_low
  51:	83 00 2c    	subd	#2c <test2\+0x15>
	jmp Stop
  54:	7e 00 00    	jmp	0 <_start>

00000057 <L1>:
L1:	
	anda #%lo\(test2\)
  57:	84 17       	anda	#23
	andb #%hi\(test2\)
  59:	c4 00       	andb	#0
	ldab #%page\(test2\)	; Check that the relocs are against symbol
  5b:	c6 00       	ldab	#0
	ldy  #%addr\(test2\)	; otherwise linker relaxation fails
  5d:	18 ce 00 00 	ldy	#0 <_start>
	rts
  61:	39          	rts
Commit	Line	Data
68a581b8 SC	1	#objdump: -S
	2	#as: -m68hc11 -gdwarf2
	3	#name: Dwarf2 test on insns.s
	4	#source: insns.s
	5
	6	# Test handling of basic instructions.
	7
	8	.*: +file format elf32\-m68hc11
	9
	10	Disassembly of section .text:
	11
cd2b2939	12	00000000 <_start>:
68a581b8 SC	13	.globl _start
	14	.sect .text
	15
	16	_start:
	17	lds #stack\+1024
49fa082d	18	0: 8e 04 00 lds #400 <stack_end>
68a581b8 SC	19	ldx #1
	20	3: ce 00 01 ldx #1 <_start\+0x1>
	21
cd2b2939	22	0+06 <Loop>:
68a581b8 SC	23	Loop:
68a581b8 SC	24	jsr test
cd2b2939	25	6: bd 00 00 jsr 0 <_start>
68a581b8 SC	26	dex
	27	9: 09 dex
	28	bne Loop
	29	a: 26 fa bne 6 <Loop>
	30
	31	0000000c <Stop>:
	32	c: cd 03 .byte 0xcd, 0x03
	33	Stop:
	34
	35	.byte 0xcd
	36	.byte 3
	37	bra _start
	38	e: 20 f0 bra 0 <_start>
	39
	40	00000010 <test>:
	41
	42	test:
	43	ldd #2
	44	10: cc 00 02 ldd #2 <_start\+0x2>
	45	jsr test2
cd2b2939	46	13: bd 00 00 jsr 0 <_start>
68a581b8 SC	47	rts
	48	16: 39 rts
	49
	50	00000017 <test2>:
	51
	52	B_low = 12
	53	A_low = 44
	54	D_low = 50
	55	value = 23
	56
	57	.globl test2
	58	test2:
	59	ldx value,y
	60	17: cd ee 17 ldx 23,y
	61	std value,x
	62	1a: ed 17 std 23,x
	63	ldd ,x
	64	1c: ec 00 ldd 0,x
	65	sty ,y
	66	1e: 18 ef 00 sty 0,y
	67	stx ,y
	68	21: cd ef 00 stx 0,y
	69	brclr 6,x,#4,test2
	70	24: 1f 06 04 ef brclr 6,x #\$04 17 <test2>
	71	brclr 12,x #8 test2
	72	28: 1f 0c 08 eb brclr 12,x #\$08 17 <test2>
	73	ldd \*ZD1
	74	2c: dc 00 ldd \*0 <_start>
	75	ldx \*ZD1\+2
	76	2e: de 02 ldx \*2 <_start\+0x2>
	77	clr \*ZD2
	78	30: 7f 00 00 clr 0 <_start>
	79	clr \*ZD2\+1
	80	33: 7f 00 01 clr 1 <_start\+0x1>
	81	bne .-4
	82	36: 26 fc bne 34 <test2\+0x1d>
	83	beq .\+2
	84	38: 27 02 beq 3c <test2\+0x25>
	85	bclr \*ZD1\+1, #32
	86	3a: 15 01 20 bclr \*1 <_start\+0x1> #\$20
	87	brclr \*ZD2\+2, #40, test2
	88	3d: 13 02 28 d6 brclr \*2 <_start\+0x2> #\$28 17 <test2>
	89	ldy #24\+_start-44
49fa082d	90	41: 18 ce ff ec ldy #ffec <stack_end\+0xfbec>
68a581b8 SC	91	ldd B_low,y
	92	45: 18 ec 0c ldd 12,y
	93	addd A_low,y
	94	48: 18 e3 2c addd 44,y
	95	addd D_low,y
	96	4b: 18 e3 32 addd 50,y
	97	subd A_low
	98	4e: b3 00 2c subd 2c <test2\+0x15>
	99	subd #A_low
	100	51: 83 00 2c subd #2c <test2\+0x15>
	101	jmp Stop
cd2b2939	102	54: 7e 00 00 jmp 0 <_start>
68a581b8	103
cd2b2939	104	00000057 <L1>:
68a581b8 SC	105	L1:
	106	anda #%lo\(test2\)
	107	57: 84 17 anda #23
	108	andb #%hi\(test2\)
	109	59: c4 00 andb #0
ab53523a SC	110	ldab #%page\(test2\) ; Check that the relocs are against symbol
	111	5b: c6 00 ldab #0
	112	ldy #%addr\(test2\) ; otherwise linker relaxation fails
	113	5d: 18 ce 00 00 ldy #0 <_start>
68a581b8	114	rts
ab53523a	115	61: 39 rts