symver11.s: Add ".balign 8"
[deliverable/binutils-gdb.git] / gas / testsuite / gas / mips / mipsr6@mips32-dspr2.d
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1#objdump: -dr --prefix-addresses --show-raw-insn
2#name: MIPS DSP ASE Rev2 for MIPS32
3#as: -mdspr2 -32
4#source: mips32-dspr2.s
5
6# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly
7
8.*: +file format .*mips.*
9
10Disassembly of section .text:
110+0000 <[^>]*> 7c010052 absq_s\.qb zero,at
120+0004 <[^>]*> 7c430a10 addu\.ph at,v0,v1
130+0008 <[^>]*> 7c641310 addu_s\.ph v0,v1,a0
140+000c <[^>]*> 7c851818 adduh\.qb v1,a0,a1
150+0010 <[^>]*> 7ca62098 adduh_r\.qb a0,a1,a2
160+0014 <[^>]*> 7cc50031 append a1,a2,0x0
170+0018 <[^>]*> 7cc5f831 append a1,a2,0x1f
180+001c <[^>]*> 00000000 nop
190+0020 <[^>]*> 7ce60c31 balign a2,a3,0x1
200+0024 <[^>]*> 7cc73391 packrl\.ph a2,a2,a3
210+0028 <[^>]*> 7ce61c31 balign a2,a3,0x3
220+002c <[^>]*> 7ce83611 cmpgdu\.eq\.qb a2,a3,t0
230+0030 <[^>]*> 7d093e51 cmpgdu\.lt\.qb a3,t0,t1
240+0034 <[^>]*> 7d2a4691 cmpgdu\.le\.qb t0,t1,t2
250+0038 <[^>]*> 7d2a0030 dpa\.w\.ph \$ac0,t1,t2
260+003c <[^>]*> 7d4b0870 dps\.w\.ph \$ac1,t2,t3
270+0040 <[^>]*> 716c1000 madd \$ac2,t3,t4
280+0044 <[^>]*> 718d1801 maddu \$ac3,t4,t5
290+0048 <[^>]*> 71ae0004 msub \$ac0,t5,t6
300+004c <[^>]*> 71cf0805 msubu \$ac1,t6,t7
310+0050 <[^>]*> 7e117b18 mul\.ph t7,s0,s1
320+0054 <[^>]*> 7e328398 mul_s\.ph s0,s1,s2
330+0058 <[^>]*> 7e538dd8 mulq_rs\.w s1,s2,s3
340+005c <[^>]*> 7e749790 mulq_s\.ph s2,s3,s4
350+0060 <[^>]*> 7e959d98 mulq_s\.w s3,s4,s5
360+0064 <[^>]*> 7e9510b0 mulsa\.w\.ph \$ac2,s4,s5
370+0068 <[^>]*> 02b61818 mult \$ac3,s5,s6
380+006c <[^>]*> 02d70019 multu \$ac0,s6,s7
390+0070 <[^>]*> 7f19bb51 precr\.qb\.ph s7,t8,t9
400+0074 <[^>]*> 7f380791 precr_sra\.ph\.w t8,t9,0x0
410+0078 <[^>]*> 7f38ff91 precr_sra\.ph\.w t8,t9,0x1f
420+007c <[^>]*> 7f5907d1 precr_sra_r\.ph\.w t9,k0,0x0
430+0080 <[^>]*> 7f59ffd1 precr_sra_r\.ph\.w t9,k0,0x1f
440+0084 <[^>]*> 7f7a0071 prepend k0,k1,0x0
450+0088 <[^>]*> 7f7af871 prepend k0,k1,0x1f
460+008c <[^>]*> 7c1cd913 shra\.qb k1,gp,0x0
470+0090 <[^>]*> 7cfcd913 shra\.qb k1,gp,0x7
480+0094 <[^>]*> 7c1de153 shra_r\.qb gp,sp,0x0
490+0098 <[^>]*> 7cfde153 shra_r\.qb gp,sp,0x7
500+009c <[^>]*> 7ffee993 shrav\.qb sp,s8,ra
510+00a0 <[^>]*> 7c1ff1d3 shrav_r\.qb s8,ra,zero
520+00a4 <[^>]*> 7c00fe53 shrl\.ph ra,zero,0x0
530+00a8 <[^>]*> 7de0fe53 shrl\.ph ra,zero,0xf
540+00ac <[^>]*> 7c4106d3 shrlv\.ph zero,at,v0
550+00b0 <[^>]*> 7c430a50 subu\.ph at,v0,v1
560+00b4 <[^>]*> 7c641350 subu_s\.ph v0,v1,a0
570+00b8 <[^>]*> 7c851858 subuh\.qb v1,a0,a1
580+00bc <[^>]*> 7ca620d8 subuh_r\.qb a0,a1,a2
590+00c0 <[^>]*> 7cc72a18 addqh\.ph a1,a2,a3
600+00c4 <[^>]*> 7ce83298 addqh_r\.ph a2,a3,t0
610+00c8 <[^>]*> 7d093c18 addqh\.w a3,t0,t1
620+00cc <[^>]*> 7d2a4498 addqh_r\.w t0,t1,t2
630+00d0 <[^>]*> 7d4b4a58 subqh\.ph t1,t2,t3
640+00d4 <[^>]*> 7d6c52d8 subqh_r\.ph t2,t3,t4
650+00d8 <[^>]*> 7d8d5c58 subqh\.w t3,t4,t5
660+00dc <[^>]*> 7dae64d8 subqh_r\.w t4,t5,t6
670+00e0 <[^>]*> 7dae0a30 dpax\.w\.ph \$ac1,t5,t6
680+00e4 <[^>]*> 7dcf1270 dpsx\.w\.ph \$ac2,t6,t7
690+00e8 <[^>]*> 7df01e30 dpaqx_s\.w\.ph \$ac3,t7,s0
700+00ec <[^>]*> 7e1106b0 dpaqx_sa\.w\.ph \$ac0,s0,s1
710+00f0 <[^>]*> 7e320e70 dpsqx_s\.w\.ph \$ac1,s1,s2
720+00f4 <[^>]*> 7e5316f0 dpsqx_sa\.w\.ph \$ac2,s2,s3
73 \.\.\.
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