projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 7361da2c AB |
1 | #objdump: -dr --prefix-addresses --show-raw-insn |
| 2 | #name: MIPS MIPSR6 64 instructions | |
| 3 | #as: -64 | |
| 4 | #source: r6-64.s | |
| 5 | ||
| 6 | # Check MIPSR6 64 instructions | |
| 7 | ||
| 8 | .*: +file format .*mips.* | |
| 9 | ||
| 10 | Disassembly of section .text: | |
| 11 | 0+0000 <[^>]*> 0064109c dmul v0,v1,a0 | |
| 12 | 0+0004 <[^>]*> 006410dc dmuh v0,v1,a0 | |
| 13 | 0+0008 <[^>]*> 0064109e ddiv v0,v1,a0 | |
| 14 | 0+000c <[^>]*> 0064109d dmulu v0,v1,a0 | |
| 15 | 0+0010 <[^>]*> 006410dd dmuhu v0,v1,a0 | |
| 16 | 0+0014 <[^>]*> 006410de dmod v0,v1,a0 | |
| 17 | 0+0018 <[^>]*> 0064109f ddivu v0,v1,a0 | |
| 18 | 0+001c <[^>]*> 006410df dmodu v0,v1,a0 | |
| 19 | 0+0020 <[^>]*> 00641015 dlsa v0,v1,a0,0x1 | |
| 20 | 0+0024 <[^>]*> 006410d5 dlsa v0,v1,a0,0x4 | |
| 21 | 0+0028 <[^>]*> 00601052 dclz v0,v1 | |
| 22 | 0+002c <[^>]*> 00601053 dclo v0,v1 | |
| 23 | 0+0030 <[^>]*> 7c628037 lld v0,-256\(v1\) | |
| 24 | 0+0034 <[^>]*> 7c627fb7 lld v0,255\(v1\) | |
| 25 | 0+0038 <[^>]*> 7c628027 scd v0,-256\(v1\) | |
| 26 | 0+003c <[^>]*> 7c627fa7 scd v0,255\(v1\) | |
| 27 | 0+0040 <[^>]*> 7c432224 dalign a0,v0,v1,0 | |
| 28 | 0+0044 <[^>]*> 7c432264 dalign a0,v0,v1,1 | |
| 29 | 0+0048 <[^>]*> 7c4322a4 dalign a0,v0,v1,2 | |
| 30 | 0+004c <[^>]*> 7c4322e4 dalign a0,v0,v1,3 | |
| 31 | 0+0050 <[^>]*> 7c432324 dalign a0,v0,v1,4 | |
| 32 | 0+0054 <[^>]*> 7c432364 dalign a0,v0,v1,5 | |
| 33 | 0+0058 <[^>]*> 7c4323a4 dalign a0,v0,v1,6 | |
| 34 | 0+005c <[^>]*> 7c4323e4 dalign a0,v0,v1,7 | |
| 35 | 0+0060 <[^>]*> 7c022024 dbitswap a0,v0 | |
| 36 | 0+0064 <[^>]*> 7443ffff daui v1,v0,0xffff | |
| 37 | 0+0068 <[^>]*> 0466ffff dahi v1,v1,0xffff | |
| 38 | 0+006c <[^>]*> 047effff dati v1,v1,0xffff | |
| 39 | 0+0070 <[^>]*> ec900000 lwupc a0,0+0000070 <[^>]*> | |
| 40 | [ ]*70: R_MIPS_PC19_S2 \.L1.1 | |
| 41 | [ ]*70: R_MIPS_NONE \*ABS\* | |
| 42 | [ ]*70: R_MIPS_NONE \*ABS\* | |
| 43 | 0+0074 <[^>]*> ec900000 lwupc a0,0+0000074 <[^>]*> | |
| 44 | [ ]*74: R_MIPS_PC19_S2 L0.-0x100000 | |
| 45 | [ ]*74: R_MIPS_NONE \*ABS\*-0x100000 | |
| 46 | [ ]*74: R_MIPS_NONE \*ABS\*-0x100000 | |
| 47 | 0+0078 <[^>]*> ec900000 lwupc a0,0+0000078 <[^>]*> | |
| 48 | [ ]*78: R_MIPS_PC19_S2 L0.\+0xffffc | |
| 49 | [ ]*78: R_MIPS_NONE \*ABS\*\+0xffffc | |
| 50 | [ ]*78: R_MIPS_NONE \*ABS\*\+0xffffc | |
| 51 | 0+007c <[^>]*> ec940000 lwupc a0,f+ff0007c <[^>]*> | |
| 52 | 0+0080 <[^>]*> ec93ffff lwupc a0,0+010007c <[^>]*> | |
| 53 | 0+0084 <[^>]*> 00000000 nop | |
| 54 | 0+0088 <[^>]*> ec980000 ldpc a0,0+0000088 <[^>]*> | |
| 55 | [ ]*88: R_MIPS_PC18_S3 \.L1.1 | |
| 56 | [ ]*88: R_MIPS_NONE \*ABS\* | |
| 57 | [ ]*88: R_MIPS_NONE \*ABS\* | |
| 58 | 0+008c <[^>]*> 00000000 nop | |
| 59 | 0+0090 <[^>]*> ec980000 ldpc a0,0+0000090 <[^>]*> | |
| 60 | [ ]*90: R_MIPS_PC18_S3 L0.-0x100000 | |
| 61 | [ ]*90: R_MIPS_NONE \*ABS\*-0x100000 | |
| 62 | [ ]*90: R_MIPS_NONE \*ABS\*-0x100000 | |
| 63 | 0+0094 <[^>]*> 00000000 nop | |
| 64 | 0+0098 <[^>]*> ec980000 ldpc a0,0+0000098 <[^>]*> | |
| 65 | [ ]*98: R_MIPS_PC18_S3 L0.\+0xffff8 | |
| 66 | [ ]*98: R_MIPS_NONE \*ABS\*\+0xffff8 | |
| 67 | [ ]*98: R_MIPS_NONE \*ABS\*\+0xffff8 | |
| 68 | 0+009c <[^>]*> 00000000 nop | |
| 69 | 0+00a0 <[^>]*> ec9a0000 ldpc a0,f+ff000a0 <[^>]*> | |
| 70 | 0+00a4 <[^>]*> 00000000 nop | |
| 71 | 0+00a8 <[^>]*> ec99ffff ldpc a0,0+01000a0 <[^>]*> | |
| 72 | 0+00ac <[^>]*> 00000000 nop | |
| 73 | \.\.\. |