projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| fef14a42 TS |
1 | .text |
| 2 | ||
| 3 | .set noreorder | |
| 4 | .set noat | |
| 5 | ||
| 6 | .set arch=4010 | |
| 7 | ||
| 8 | flushi | |
| 9 | flushd | |
| 10 | flushid | |
| 11 | madd $4,$5 | |
| 12 | maddu $5,$6 | |
| 13 | ffc $6,$7 | |
| 14 | ffs $7,$8 | |
| 15 | msub $8,$9 | |
| 16 | msubu $9,$10 | |
| 17 | selsl $10,$11,$12 | |
| 18 | selsr $11,$12,$13 | |
| 19 | waiti | |
| 20 | wb 16($14) | |
| 21 | addciu $14,$15,16 | |
| 22 | ||
| 23 | .set arch=4100 | |
| 24 | ||
| 25 | hibernate | |
| 26 | standby | |
| 27 | suspend | |
| 28 | ||
| 29 | .set arch=4650 | |
| 30 | ||
| 31 | mad $4,$5 | |
| 32 | madu $5,$6 | |
| 33 | mul $6,$7,$8 | |
| 34 | ||
| 35 | # test mips4 instructions. | |
| 36 | ||
| 37 | .set arch=mips4 | |
| 38 | ||
| 39 | text_label: | |
| 40 | bc1f text_label | |
| 41 | bc1f $fcc1,text_label | |
| 42 | bc1fl $fcc1,text_label | |
| 43 | bc1t $fcc1,text_label | |
| 44 | bc1tl $fcc2,text_label | |
| 45 | c.f.d $f4,$f6 | |
| 46 | c.f.d $fcc1,$f4,$f6 | |
| 47 | ldxc1 $f2,$4($5) | |
| 48 | lwxc1 $f2,$4($5) | |
| 49 | madd.d $f0,$f2,$f4,$f6 | |
| 50 | madd.s $f0,$f2,$f4,$f6 | |
| 51 | movf $4,$5,$fcc4 | |
| 52 | movf.d $f4,$f6,$fcc0 | |
| 53 | movf.s $f4,$f6,$fcc0 | |
| 54 | movn $4,$6,$6 | |
| 55 | movn.d $f4,$f6,$6 | |
| 56 | movn.s $f4,$f6,$6 | |
| 57 | movt $4,$5,$fcc4 | |
| 58 | movt.d $f4,$f6,$fcc0 | |
| 59 | movt.s $f4,$f6,$fcc0 | |
| 60 | movz $4,$6,$6 | |
| 61 | movz.d $f4,$f6,$6 | |
| 62 | movz.s $f4,$f6,$6 | |
| 63 | msub.d $f0,$f2,$f4,$f6 | |
| 64 | msub.s $f0,$f2,$f4,$f6 | |
| 65 | nmadd.d $f0,$f2,$f4,$f6 | |
| 66 | nmadd.s $f0,$f2,$f4,$f6 | |
| 67 | nmsub.d $f0,$f2,$f4,$f6 | |
| 68 | nmsub.s $f0,$f2,$f4,$f6 | |
| 69 | ||
| 70 | # We don't test pref because currently the disassembler will | |
| 71 | # disassemble it as lwc3. lwc3 is correct for mips1 to mips3, | |
| 72 | # while pref is correct for mips4. Unfortunately, the | |
| 73 | # disassembler does not know which architecture it is | |
| 74 | # disassembling for. | |
| 75 | # pref 4,0($4) | |
| 76 | ||
| 77 | prefx 4,$4($5) | |
| 78 | recip.d $f4,$f6 | |
| 79 | recip.s $f4,$f6 | |
| 80 | rsqrt.d $f4,$f6 | |
| 81 | rsqrt.s $f4,$f6 | |
| 82 | sdxc1 $f4,$4($5) | |
| 83 | swxc1 $f4,$4($5) | |
| 84 | ||
| 85 | # test mips5 instructions. | |
| 86 | ||
| 87 | .set arch=mips5 | |
| 88 | ||
| 89 | abs.ps $f0, $f2 | |
| 90 | add.ps $f2, $f4, $f6 | |
| 91 | alnv.ps $f6, $f8, $f10, $3 | |
| 92 | c.eq.ps $f8, $f10 | |
| 93 | c.eq.ps $fcc2, $f10, $f12 | |
| 94 | c.f.ps $f8, $f10 | |
| 95 | c.f.ps $fcc2, $f10, $f12 | |
| 96 | c.le.ps $f8, $f10 | |
| 97 | c.le.ps $fcc2, $f10, $f12 | |
| 98 | c.lt.ps $f8, $f10 | |
| 99 | c.lt.ps $fcc2, $f10, $f12 | |
| 100 | c.nge.ps $f8, $f10 | |
| 101 | c.nge.ps $fcc2, $f10, $f12 | |
| 102 | c.ngl.ps $f8, $f10 | |
| 103 | c.ngl.ps $fcc2, $f10, $f12 | |
| 104 | c.ngle.ps $f8, $f10 | |
| 105 | c.ngle.ps $fcc2, $f10, $f12 | |
| 106 | c.ngt.ps $f8, $f10 | |
| 107 | c.ngt.ps $fcc2, $f10, $f12 | |
| 108 | c.ole.ps $f8, $f10 | |
| 109 | c.ole.ps $fcc2, $f10, $f12 | |
| 110 | c.olt.ps $f8, $f10 | |
| 111 | c.olt.ps $fcc2, $f10, $f12 | |
| 112 | c.seq.ps $f8, $f10 | |
| 113 | c.seq.ps $fcc2, $f10, $f12 | |
| 114 | c.sf.ps $f8, $f10 | |
| 115 | c.sf.ps $fcc2, $f10, $f12 | |
| 116 | c.ueq.ps $f8, $f10 | |
| 117 | c.ueq.ps $fcc2, $f10, $f12 | |
| 118 | c.ule.ps $f8, $f10 | |
| 119 | c.ule.ps $fcc2, $f10, $f12 | |
| 120 | c.ult.ps $f8, $f10 | |
| 121 | c.ult.ps $fcc2, $f10, $f12 | |
| 122 | c.un.ps $f8, $f10 | |
| 123 | c.un.ps $fcc2, $f10, $f12 | |
| 124 | cvt.ps.s $f12, $f14, $f16 | |
| 125 | cvt.s.pl $f16, $f18 | |
| 126 | cvt.s.pu $f18, $f20 | |
| 127 | luxc1 $f20, $4($5) | |
| 128 | madd.ps $f20, $f22, $f24, $f26 | |
| 129 | mov.ps $f24, $f26 | |
| 130 | movf.ps $f26, $f28, $fcc2 | |
| 131 | movn.ps $f26, $f28, $3 | |
| 132 | movt.ps $f28, $f30, $fcc4 | |
| 133 | movz.ps $f28, $f30, $5 | |
| 134 | msub.ps $f30, $f0, $f2, $f4 | |
| 135 | mul.ps $f2, $f4, $f6 | |
| 136 | neg.ps $f6, $f8 | |
| 137 | nmadd.ps $f6, $f8, $f10, $f12 | |
| 138 | nmsub.ps $f6, $f8, $f10, $f12 | |
| 139 | pll.ps $f10, $f12, $f14 | |
| 140 | plu.ps $f14, $f16, $f18 | |
| 141 | pul.ps $f16, $f18, $f20 | |
| 142 | puu.ps $f20, $f22, $f24 | |
| 143 | sub.ps $f22, $f24, $f26 | |
| 144 | suxc1 $f26, $6($7) | |
| 145 | ||
| 146 | c.eq.ps $fcc3, $f10, $f12 # warns | |
| 147 | movf.ps $f26, $f28, $fcc3 # warns | |
| 148 | ||
| 149 | # test assembly of mips32 instructions | |
| 150 | ||
| 151 | .set arch=mips32 | |
| 152 | ||
| 153 | # unprivileged CPU instructions | |
| 154 | ||
| 155 | clo $1, $2 | |
| 156 | clz $3, $4 | |
| 157 | madd $5, $6 | |
| 158 | maddu $7, $8 | |
| 159 | msub $9, $10 | |
| 160 | msubu $11, $12 | |
| 161 | mul $13, $14, $15 | |
| 162 | pref 4, ($16) | |
| 163 | pref 4, 32767($17) | |
| 164 | pref 4, -32768($18) | |
| 165 | ssnop | |
| 166 | ||
| 167 | # unprivileged coprocessor instructions. | |
| 168 | # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. | |
| 169 | ||
| 170 | bc2f text_label | |
| 171 | nop | |
| 172 | bc2fl text_label | |
| 173 | nop | |
| 174 | bc2t text_label | |
| 175 | nop | |
| 176 | bc2tl text_label | |
| 177 | nop | |
| 178 | # XXX other BCzCond encodings not currently expressable | |
| 179 | cfc2 $1, $2 | |
| 180 | cop2 0x1234567 # disassembles as c2 ... | |
| 181 | ctc2 $2, $3 | |
| 182 | mfc2 $3, $4 | |
| 183 | mfc2 $4, $5, 0 # disassembles without sel | |
| 184 | mfc2 $5, $6, 7 | |
| 185 | mtc2 $6, $7 | |
| 186 | mtc2 $7, $8, 0 # disassembles without sel | |
| 187 | mtc2 $8, $9, 7 | |
| 188 | ||
| 189 | # privileged instructions | |
| 190 | ||
| 191 | cache 5, ($1) | |
| 192 | cache 5, 32767($2) | |
| 193 | cache 5, -32768($3) | |
| 194 | eret | |
| 195 | tlbp | |
| 196 | tlbr | |
| 197 | tlbwi | |
| 198 | tlbwr | |
| 199 | wait | |
| 200 | wait 0 # disassembles without code | |
| 201 | wait 0x56789 | |
| 202 | ||
| 203 | # Instructions in previous ISAs or CPUs which are now slightly | |
| 204 | # different. | |
| 205 | break | |
| 206 | break 0 # disassembles without code | |
| 207 | break 0x12345 | |
| 208 | sdbbp | |
| 209 | sdbbp 0 # disassembles without code | |
| 210 | sdbbp 0x56789 | |
| 211 | ||
| 212 | # test assembly of mips32r2 instructions | |
| 213 | ||
| 214 | .set arch=mips32r2 | |
| 215 | ||
| 216 | # unprivileged CPU instructions | |
| 217 | ||
| 218 | ehb | |
| 219 | ||
| 220 | ext $4, $5, 6, 8 | |
| 221 | ||
| 222 | ins $4, $5, 6, 8 | |
| 223 | ||
| 224 | jalr.hb $8 | |
| 225 | jalr.hb $20, $9 | |
| 226 | ||
| 227 | jr.hb $8 | |
| 228 | ||
| 229 | # Note, further testing of rdhwr is done in hwr-names-mips32r2.d | |
| 230 | rdhwr $10, $0 | |
| 231 | rdhwr $11, $1 | |
| 232 | rdhwr $12, $2 | |
| 233 | rdhwr $13, $3 | |
| 234 | rdhwr $14, $4 | |
| 235 | rdhwr $15, $5 | |
| 236 | ||
| 237 | # This file checks that in fact HW rotate will | |
| 238 | # be used for this arch, and checks assembly | |
| 239 | # of the official MIPS mnemonics. (Note that disassembly | |
| 240 | # uses the traditional "ror" and "rorv" mnemonics.) | |
| 241 | # Additional rotate tests are done by rol-hw.d. | |
| 242 | rotl $25, $10, 4 | |
| 243 | rotr $25, $10, 4 | |
| 244 | rotl $25, $10, $4 | |
| 245 | rotr $25, $10, $4 | |
| 246 | rotrv $25, $10, $4 | |
| 247 | ||
| 248 | seb $7 | |
| 249 | seb $8, $10 | |
| 250 | ||
| 251 | seh $7 | |
| 252 | seh $8, $10 | |
| 253 | ||
| 254 | synci 0x5555($10) | |
| 255 | ||
| 256 | wsbh $7 | |
| 257 | wsbh $8, $10 | |
| 258 | ||
| 259 | # cp0 instructions | |
| 260 | ||
| 261 | di | |
| 262 | di $0 | |
| 263 | di $10 | |
| 264 | ||
| 265 | ei | |
| 266 | ei $0 | |
| 267 | ei $10 | |
| 268 | ||
| 269 | rdpgpr $10, $25 | |
| 270 | ||
| 271 | wrpgpr $10, $25 | |
| 272 | ||
| 273 | # FPU (cp1) instructions | |
| 274 | # | |
| 275 | # Even registers are supported w/ 32-bit FPU, odd | |
| 276 | # registers supported only for 64-bit FPU. | |
| 277 | # Only the 32-bit FPU instructions are tested here. | |
| 278 | ||
| 279 | mfhc1 $17, $f0 | |
| 280 | mthc1 $17, $f0 | |
| 281 | ||
| 282 | # cp2 instructions | |
| 283 | ||
| 284 | mfhc2 $17, 0x5555 | |
| 285 | mthc2 $17, 0x5555 | |
| 286 | ||
| 287 | .set arch=mips64 | |
| 288 | ||
| 289 | # test assembly of mips64 instructions | |
| 290 | ||
| 291 | # unprivileged CPU instructions | |
| 292 | ||
| 293 | dclo $1, $2 | |
| 294 | dclz $3, $4 | |
| 295 | ||
| 296 | # unprivileged coprocessor instructions. | |
| 297 | # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. | |
| 298 | ||
| 299 | dmfc2 $3, $4 | |
| 300 | dmfc2 $4, $5, 0 # disassembles without sel | |
| 301 | dmfc2 $5, $6, 7 | |
| 302 | dmtc2 $6, $7 | |
| 303 | dmtc2 $7, $8, 0 # disassembles without sel | |
| 304 | dmtc2 $8, $9, 7 | |
| 305 | ||
| 306 | .set arch=vr4111 | |
| 307 | ||
| 308 | dmadd16 $4,$5 | |
| 309 | madd16 $5,$6 | |
| 310 | ||
| 311 | .set arch=vr4120 | |
| 312 | ||
| 313 | # Include mflos to check for nop insertion. | |
| 314 | mflo $4 | |
| 315 | dmacc $4,$5,$6 | |
| 316 | dmacchi $4,$5,$6 | |
| 317 | dmacchis $4,$5,$6 | |
| 318 | dmacchiu $4,$5,$6 | |
| 319 | dmacchius $4,$5,$6 | |
| 320 | dmaccs $4,$5,$6 | |
| 321 | dmaccu $4,$5,$6 | |
| 322 | dmaccus $4,$5,$6 | |
| 323 | mflo $4 | |
| 324 | macc $4,$5,$6 | |
| 325 | macchi $4,$5,$6 | |
| 326 | macchis $4,$5,$6 | |
| 327 | macchiu $4,$5,$6 | |
| 328 | macchius $4,$5,$6 | |
| 329 | maccs $4,$5,$6 | |
| 330 | maccu $4,$5,$6 | |
| 331 | maccus $4,$5,$6 | |
| 332 | ||
| 333 | .set arch=vr5400 | |
| 334 | ||
| 335 | /* Integer instructions. */ | |
| 336 | ||
| 337 | mulu $4,$5,$6 | |
| 338 | mulhi $4,$5,$6 | |
| 339 | mulhiu $4,$5,$6 | |
| 340 | muls $4,$5,$6 | |
| 341 | mulsu $4,$5,$6 | |
| 342 | mulshi $4,$5,$6 | |
| 343 | mulshiu $4,$5,$6 | |
| 344 | macc $4,$5,$6 | |
| 345 | maccu $4,$5,$6 | |
| 346 | macchi $4,$5,$6 | |
| 347 | macchiu $4,$5,$6 | |
| 348 | msac $4,$5,$6 | |
| 349 | msacu $4,$5,$6 | |
| 350 | msachi $4,$5,$6 | |
| 351 | msachiu $4,$5,$6 | |
| 352 | ||
| 353 | ror $4,$5,25 | |
| 354 | rorv $4,$5,$6 | |
| 355 | dror $4,$5,25 | |
| 356 | dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */ | |
| 357 | dror32 $4,$5,25 | |
| 358 | drorv $4,$5,$6 | |
| 359 | ||
| 360 | /* Debug instructions. */ | |
| 361 | ||
| 362 | dbreak | |
| 363 | dret | |
| 364 | mfdr $3,$3 | |
| 365 | mtdr $3,$3 | |
| 366 | ||
| 367 | /* Coprocessor 0 instructions, minus standard ISA 3 ones. | |
| 368 | That leaves just the performance monitoring registers. */ | |
| 369 | ||
| 370 | mfpc $4,1 | |
| 371 | mfps $4,1 | |
| 372 | mtpc $4,1 | |
| 373 | mtps $4,1 | |
| 374 | ||
| 375 | /* Multimedia instructions. */ | |
| 376 | ||
| 377 | .macro nsel2 op | |
| 378 | /* Test each form of each vector opcode. */ | |
| 379 | \op $f0,$f2 | |
| 380 | \op $f4,$f6[2] | |
| 381 | \op $f6,15 | |
| 382 | .if 0 /* Which is right?? */ | |
| 383 | /* Test negative numbers in immediate-value slot. */ | |
| 384 | \op $f4,-3 | |
| 385 | .else | |
| 386 | /* Test that it's recognized as an unsigned field. */ | |
| 387 | \op $f4,31 | |
| 388 | .endif | |
| 389 | .endm | |
| 390 | ||
| 391 | .macro nsel3 op | |
| 392 | /* Test each form of each vector opcode. */ | |
| 393 | \op $f0,$f2,$f4 | |
| 394 | \op $f2,$f4,$f6[2] | |
| 395 | \op $f6,$f4,15 | |
| 396 | .if 0 /* Which is right?? */ | |
| 397 | /* Test negative numbers in immediate-value slot. */ | |
| 398 | \op $f4,$f6,-3 | |
| 399 | .else | |
| 400 | /* Test that it's recognized as an unsigned field. */ | |
| 401 | \op $f4,$f6,31 | |
| 402 | .endif | |
| 403 | .endm | |
| 404 | ||
| 405 | nsel3 add.ob | |
| 406 | nsel3 and.ob | |
| 407 | nsel2 c.eq.ob | |
| 408 | nsel2 c.le.ob | |
| 409 | nsel2 c.lt.ob | |
| 410 | nsel3 max.ob | |
| 411 | nsel3 min.ob | |
| 412 | nsel3 mul.ob | |
| 413 | nsel2 mula.ob | |
| 414 | nsel2 mull.ob | |
| 415 | nsel2 muls.ob | |
| 416 | nsel2 mulsl.ob | |
| 417 | nsel3 nor.ob | |
| 418 | nsel3 or.ob | |
| 419 | nsel3 pickf.ob | |
| 420 | nsel3 pickt.ob | |
| 421 | nsel3 sub.ob | |
| 422 | nsel3 xor.ob | |
| 423 | ||
| 424 | /* ALNI, SHFL: Vector only. */ | |
| 425 | alni.ob $f0,$f2,$f4,5 | |
| 426 | shfl.mixh.ob $f0,$f2,$f4 | |
| 427 | shfl.mixl.ob $f0,$f2,$f4 | |
| 428 | shfl.pach.ob $f0,$f2,$f4 | |
| 429 | shfl.pacl.ob $f0,$f2,$f4 | |
| 430 | ||
| 431 | /* SLL,SRL: Scalar or immediate. */ | |
| 432 | sll.ob $f2,$f4,$f6[3] | |
| 433 | sll.ob $f4,$f6,14 | |
| 434 | srl.ob $f2,$f4,$f6[3] | |
| 435 | srl.ob $f4,$f6,14 | |
| 436 | ||
| 437 | /* RZU: Immediate, must be 0, 8, or 16. */ | |
| 438 | rzu.ob $f2,13 | |
| 439 | ||
| 440 | /* No selector. */ | |
| 441 | rach.ob $f2 | |
| 442 | racl.ob $f2 | |
| 443 | racm.ob $f2 | |
| 444 | wach.ob $f2 | |
| 445 | wacl.ob $f2,$f4 | |
| 446 | ||
| 447 | ror $4,$5,$6 | |
| 448 | rol $4,$5,15 | |
| 449 | dror $4,$5,$6 | |
| 450 | drol $4,$5,31 | |
| 451 | drol $4,$5,62 | |
| 452 | ||
| 453 | .set arch=vr5500 | |
| 454 | ||
| 455 | /* Prefetch instructions. */ | |
| 456 | # We don't test pref because currently the disassembler will | |
| 457 | # disassemble it as lwc3. lwc3 is correct for mips1 to mips3, | |
| 458 | # while pref is correct for mips4. Unfortunately, the | |
| 459 | # disassembler does not know which architecture it is | |
| 460 | # disassembling for. | |
| 461 | # pref 4,0($4) | |
| 462 | ||
| 463 | prefx 4,$4($5) | |
| 464 | ||
| 465 | /* Miscellaneous instructions. */ | |
| 466 | ||
| 467 | wait | |
| 468 | wait 0 # disassembles without code | |
| 469 | wait 0x56789 | |
| 470 | ||
| 471 | ssnop | |
| 472 | ||
| 473 | clo $3,$4 | |
| 474 | dclo $3,$4 | |
| 475 | clz $3,$4 | |
| 476 | dclz $3,$4 | |
| 477 | ||
| 478 | luxc1 $f0,$4($2) | |
| 479 | suxc1 $f2,$4($2) | |
| 480 | ||
| 481 | tlbp | |
| 482 | tlbr | |
| 483 | ||
| 484 | .set arch=default | |
| 485 | ||
| 486 | # make objdump print ... | |
| 487 | .space 8 |