Commit | Line | Data |
---|---|---|
532c738a RS |
1 | #objdump: -dz --prefix-addresses -m mips:4120 |
2 | #as: -32 -march=vr4120 -mfix-vr4120 | |
3 | #name: MIPS vr4120 workarounds | |
4 | ||
5 | .*: +file format .*mips.* | |
6 | ||
7 | Disassembly of section .text: | |
8 | .* <[^>]*> macc a0,a1,a2 | |
9 | .* <[^>]*> nop | |
10 | .* <[^>]*> div zero,a3,t0 | |
11 | .* <[^>]*> or a0,a0,a1 | |
12 | .* <[^>]*> dmacc a0,a1,a2 | |
13 | .* <[^>]*> nop | |
14 | .* <[^>]*> div zero,a3,t0 | |
15 | .* <[^>]*> or a0,a0,a1 | |
16 | .* <[^>]*> macc a0,a1,a2 | |
17 | .* <[^>]*> nop | |
18 | .* <[^>]*> divu zero,a3,t0 | |
19 | .* <[^>]*> or a0,a0,a1 | |
20 | .* <[^>]*> dmacc a0,a1,a2 | |
21 | .* <[^>]*> nop | |
22 | .* <[^>]*> divu zero,a3,t0 | |
23 | .* <[^>]*> or a0,a0,a1 | |
24 | .* <[^>]*> macc a0,a1,a2 | |
25 | .* <[^>]*> nop | |
26 | .* <[^>]*> ddiv zero,a3,t0 | |
27 | .* <[^>]*> or a0,a0,a1 | |
28 | .* <[^>]*> dmacc a0,a1,a2 | |
29 | .* <[^>]*> nop | |
30 | .* <[^>]*> ddiv zero,a3,t0 | |
31 | .* <[^>]*> or a0,a0,a1 | |
32 | .* <[^>]*> macc a0,a1,a2 | |
33 | .* <[^>]*> nop | |
34 | .* <[^>]*> ddivu zero,a3,t0 | |
35 | .* <[^>]*> or a0,a0,a1 | |
36 | .* <[^>]*> dmacc a0,a1,a2 | |
37 | .* <[^>]*> nop | |
38 | .* <[^>]*> ddivu zero,a3,t0 | |
39 | .* <[^>]*> or a0,a0,a1 | |
40 | .* <[^>]*> dmult a0,a1 | |
41 | .* <[^>]*> nop | |
42 | .* <[^>]*> dmult a2,a3 | |
43 | .* <[^>]*> or a0,a0,a1 | |
44 | .* <[^>]*> dmultu a0,a1 | |
45 | .* <[^>]*> nop | |
46 | .* <[^>]*> dmultu a2,a3 | |
47 | .* <[^>]*> or a0,a0,a1 | |
48 | .* <[^>]*> dmacc a0,a1,a2 | |
49 | .* <[^>]*> nop | |
50 | .* <[^>]*> dmacc a2,a3,t0 | |
51 | .* <[^>]*> or a0,a0,a1 | |
52 | .* <[^>]*> dmult a0,a1 | |
53 | .* <[^>]*> nop | |
54 | .* <[^>]*> dmacc a2,a3,t0 | |
55 | .* <[^>]*> or a0,a0,a1 | |
56 | .* <[^>]*> macc a0,a1,a2 | |
57 | .* <[^>]*> nop | |
58 | .* <[^>]*> mtlo a3 | |
59 | .* <[^>]*> dmacc a0,a1,a2 | |
60 | .* <[^>]*> nop | |
61 | .* <[^>]*> mtlo a3 | |
62 | .* <[^>]*> macc a0,a1,a2 | |
63 | .* <[^>]*> nop | |
64 | .* <[^>]*> mthi a3 | |
65 | .* <[^>]*> dmacc a0,a1,a2 | |
66 | .* <[^>]*> nop | |
67 | .* <[^>]*> mthi a3 | |
68 | # | |
69 | # vr4181a_md1: | |
70 | # | |
71 | .* <[^>]*> macc a0,a1,a2 | |
72 | .* <[^>]*> nop | |
73 | .* <[^>]*> mult a0,a1 | |
74 | .* <[^>]*> or a0,a0,a1 | |
75 | # | |
76 | .* <[^>]*> macc a0,a1,a2 | |
77 | .* <[^>]*> nop | |
78 | .* <[^>]*> multu a0,a1 | |
79 | .* <[^>]*> or a0,a0,a1 | |
80 | # | |
81 | .* <[^>]*> macc a0,a1,a2 | |
82 | .* <[^>]*> nop | |
83 | .* <[^>]*> dmult a0,a1 | |
84 | .* <[^>]*> or a0,a0,a1 | |
85 | # | |
86 | .* <[^>]*> macc a0,a1,a2 | |
87 | .* <[^>]*> nop | |
88 | .* <[^>]*> dmultu a0,a1 | |
89 | .* <[^>]*> or a0,a0,a1 | |
90 | # | |
91 | .* <[^>]*> dmacc a0,a1,a2 | |
92 | .* <[^>]*> nop | |
93 | .* <[^>]*> mult a0,a1 | |
94 | .* <[^>]*> or a0,a0,a1 | |
95 | # | |
96 | .* <[^>]*> dmacc a0,a1,a2 | |
97 | .* <[^>]*> nop | |
98 | .* <[^>]*> multu a0,a1 | |
99 | .* <[^>]*> or a0,a0,a1 | |
100 | # | |
101 | .* <[^>]*> dmacc a0,a1,a2 | |
102 | .* <[^>]*> nop | |
103 | .* <[^>]*> dmult a0,a1 | |
104 | .* <[^>]*> or a0,a0,a1 | |
105 | # | |
106 | .* <[^>]*> dmacc a0,a1,a2 | |
107 | .* <[^>]*> nop | |
108 | .* <[^>]*> dmultu a0,a1 | |
109 | .* <[^>]*> or a0,a0,a1 | |
110 | # | |
111 | # vr4181a_md4: | |
112 | # | |
113 | .* <[^>]*> dmult a0,a1 | |
114 | .* <[^>]*> nop | |
115 | .* <[^>]*> macc a0,a1,a2 | |
116 | .* <[^>]*> or a0,a0,a1 | |
117 | # | |
118 | .* <[^>]*> dmultu a0,a1 | |
119 | .* <[^>]*> nop | |
120 | .* <[^>]*> macc a0,a1,a2 | |
121 | .* <[^>]*> or a0,a0,a1 | |
122 | # | |
123 | .* <[^>]*> div zero,a0,a1 | |
124 | .* <[^>]*> nop | |
125 | .* <[^>]*> macc a0,a1,a2 | |
126 | .* <[^>]*> or a0,a0,a1 | |
127 | # | |
128 | .* <[^>]*> divu zero,a0,a1 | |
129 | .* <[^>]*> nop | |
130 | .* <[^>]*> macc a0,a1,a2 | |
131 | .* <[^>]*> or a0,a0,a1 | |
132 | # | |
133 | .* <[^>]*> ddiv zero,a0,a1 | |
134 | .* <[^>]*> nop | |
135 | .* <[^>]*> macc a0,a1,a2 | |
136 | .* <[^>]*> or a0,a0,a1 | |
137 | # | |
138 | .* <[^>]*> ddivu zero,a0,a1 | |
139 | .* <[^>]*> nop | |
140 | .* <[^>]*> macc a0,a1,a2 | |
141 | .* <[^>]*> or a0,a0,a1 | |
142 | # | |
143 | .* <[^>]*> dmult a0,a1 | |
144 | .* <[^>]*> nop | |
145 | .* <[^>]*> dmacc a0,a1,a2 | |
146 | .* <[^>]*> or a0,a0,a1 | |
147 | # | |
148 | .* <[^>]*> dmultu a0,a1 | |
149 | .* <[^>]*> nop | |
150 | .* <[^>]*> dmacc a0,a1,a2 | |
151 | .* <[^>]*> or a0,a0,a1 | |
152 | # | |
153 | .* <[^>]*> div zero,a0,a1 | |
154 | .* <[^>]*> nop | |
155 | .* <[^>]*> dmacc a0,a1,a2 | |
156 | .* <[^>]*> or a0,a0,a1 | |
157 | # | |
158 | .* <[^>]*> divu zero,a0,a1 | |
159 | .* <[^>]*> nop | |
160 | .* <[^>]*> dmacc a0,a1,a2 | |
161 | .* <[^>]*> or a0,a0,a1 | |
162 | # | |
163 | .* <[^>]*> ddiv zero,a0,a1 | |
164 | .* <[^>]*> nop | |
165 | .* <[^>]*> dmacc a0,a1,a2 | |
166 | .* <[^>]*> or a0,a0,a1 | |
167 | # | |
168 | .* <[^>]*> ddivu zero,a0,a1 | |
169 | .* <[^>]*> nop | |
170 | .* <[^>]*> dmacc a0,a1,a2 | |
171 | .* <[^>]*> or a0,a0,a1 | |
172 | #... |