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9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
42a4f53d | 3 | Copyright (C) 2011-2019 Free Software Foundation, Inc. |
9d19df75 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
d55e5aa6 | 23 | #include "inferior.h" |
4de283e4 TT |
24 | #include "gdbcore.h" |
25 | #include "regcache.h" | |
d55e5aa6 | 26 | #include "linux-nat.h" |
4de283e4 TT |
27 | #include "target-descriptions.h" |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "aarch64-tdep.h" | |
31 | #include "aarch64-linux-tdep.h" | |
32 | #include "aarch32-linux-nat.h" | |
350fab54 | 33 | #include "arch/arm.h" |
d55e5aa6 | 34 | #include "nat/aarch64-linux.h" |
4de283e4 | 35 | #include "nat/aarch64-linux-hw-point.h" |
ba2d2bb2 | 36 | #include "nat/aarch64-sve-linux-ptrace.h" |
4de283e4 TT |
37 | |
38 | #include "elf/external.h" | |
39 | #include "elf/common.h" | |
40 | ||
5826e159 | 41 | #include "nat/gdb_ptrace.h" |
4de283e4 TT |
42 | #include <sys/utsname.h> |
43 | #include <asm/ptrace.h> | |
44 | ||
45 | #include "gregset.h" | |
46 | #include "linux-tdep.h" | |
9d19df75 | 47 | |
9d19df75 MS |
48 | /* Defines ps_err_e, struct ps_prochandle. */ |
49 | #include "gdb_proc_service.h" | |
4da037ef | 50 | #include "arch-utils.h" |
9d19df75 MS |
51 | |
52 | #ifndef TRAP_HWBKPT | |
53 | #define TRAP_HWBKPT 0x0004 | |
54 | #endif | |
55 | ||
f6ac5f3d PA |
56 | class aarch64_linux_nat_target final : public linux_nat_target |
57 | { | |
58 | public: | |
59 | /* Add our register access methods. */ | |
60 | void fetch_registers (struct regcache *, int) override; | |
61 | void store_registers (struct regcache *, int) override; | |
62 | ||
63 | const struct target_desc *read_description () override; | |
64 | ||
65 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
66 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
67 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
68 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
69 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
70 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
71 | struct expression *) override; | |
72 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
73 | struct expression *) override; | |
57810aa7 PA |
74 | bool stopped_by_watchpoint () override; |
75 | bool stopped_data_address (CORE_ADDR *) override; | |
76 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; | |
f6ac5f3d PA |
77 | |
78 | int can_do_single_step () override; | |
79 | ||
80 | /* Override the GNU/Linux inferior startup hook. */ | |
81 | void post_startup_inferior (ptid_t) override; | |
135340af | 82 | |
8363f9d5 RB |
83 | /* Override the GNU/Linux post attach hook. */ |
84 | void post_attach (int pid) override; | |
85 | ||
135340af PA |
86 | /* These three defer to common nat/ code. */ |
87 | void low_new_thread (struct lwp_info *lp) override | |
88 | { aarch64_linux_new_thread (lp); } | |
89 | void low_delete_thread (struct arch_lwp_info *lp) override | |
90 | { aarch64_linux_delete_thread (lp); } | |
91 | void low_prepare_to_resume (struct lwp_info *lp) override | |
92 | { aarch64_linux_prepare_to_resume (lp); } | |
93 | ||
94 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
95 | void low_forget_process (pid_t pid) override; | |
96 | ||
97 | /* Add our siginfo layout converter. */ | |
98 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
99 | override; | |
4da037ef AH |
100 | |
101 | struct gdbarch *thread_architecture (ptid_t) override; | |
f6ac5f3d PA |
102 | }; |
103 | ||
104 | static aarch64_linux_nat_target the_aarch64_linux_nat_target; | |
105 | ||
d6c44983 YZ |
106 | /* Per-process data. We don't bind this to a per-inferior registry |
107 | because of targets like x86 GNU/Linux that need to keep track of | |
108 | processes that aren't bound to any inferior (e.g., fork children, | |
109 | checkpoints). */ | |
9d19df75 | 110 | |
d6c44983 | 111 | struct aarch64_process_info |
9d19df75 | 112 | { |
d6c44983 YZ |
113 | /* Linked list. */ |
114 | struct aarch64_process_info *next; | |
9d19df75 | 115 | |
d6c44983 YZ |
116 | /* The process identifier. */ |
117 | pid_t pid; | |
9d19df75 | 118 | |
d6c44983 YZ |
119 | /* Copy of aarch64 hardware debug registers. */ |
120 | struct aarch64_debug_reg_state state; | |
121 | }; | |
122 | ||
123 | static struct aarch64_process_info *aarch64_process_list = NULL; | |
124 | ||
125 | /* Find process data for process PID. */ | |
126 | ||
127 | static struct aarch64_process_info * | |
128 | aarch64_find_process_pid (pid_t pid) | |
129 | { | |
130 | struct aarch64_process_info *proc; | |
131 | ||
132 | for (proc = aarch64_process_list; proc; proc = proc->next) | |
133 | if (proc->pid == pid) | |
134 | return proc; | |
135 | ||
136 | return NULL; | |
9d19df75 MS |
137 | } |
138 | ||
d6c44983 YZ |
139 | /* Add process data for process PID. Returns newly allocated info |
140 | object. */ | |
9d19df75 | 141 | |
d6c44983 YZ |
142 | static struct aarch64_process_info * |
143 | aarch64_add_process (pid_t pid) | |
9d19df75 | 144 | { |
d6c44983 | 145 | struct aarch64_process_info *proc; |
9d19df75 | 146 | |
8d749320 | 147 | proc = XCNEW (struct aarch64_process_info); |
d6c44983 | 148 | proc->pid = pid; |
9d19df75 | 149 | |
d6c44983 YZ |
150 | proc->next = aarch64_process_list; |
151 | aarch64_process_list = proc; | |
152 | ||
153 | return proc; | |
154 | } | |
155 | ||
156 | /* Get data specific info for process PID, creating it if necessary. | |
157 | Never returns NULL. */ | |
158 | ||
159 | static struct aarch64_process_info * | |
160 | aarch64_process_info_get (pid_t pid) | |
9d19df75 | 161 | { |
d6c44983 YZ |
162 | struct aarch64_process_info *proc; |
163 | ||
164 | proc = aarch64_find_process_pid (pid); | |
165 | if (proc == NULL) | |
166 | proc = aarch64_add_process (pid); | |
9d19df75 | 167 | |
d6c44983 | 168 | return proc; |
9d19df75 MS |
169 | } |
170 | ||
d6c44983 YZ |
171 | /* Called whenever GDB is no longer debugging process PID. It deletes |
172 | data structures that keep track of debug register state. */ | |
9d19df75 | 173 | |
135340af PA |
174 | void |
175 | aarch64_linux_nat_target::low_forget_process (pid_t pid) | |
9d19df75 | 176 | { |
d6c44983 | 177 | struct aarch64_process_info *proc, **proc_link; |
9d19df75 | 178 | |
d6c44983 YZ |
179 | proc = aarch64_process_list; |
180 | proc_link = &aarch64_process_list; | |
181 | ||
182 | while (proc != NULL) | |
9d19df75 | 183 | { |
d6c44983 YZ |
184 | if (proc->pid == pid) |
185 | { | |
186 | *proc_link = proc->next; | |
9d19df75 | 187 | |
d6c44983 YZ |
188 | xfree (proc); |
189 | return; | |
190 | } | |
191 | ||
192 | proc_link = &proc->next; | |
193 | proc = *proc_link; | |
194 | } | |
9d19df75 MS |
195 | } |
196 | ||
d6c44983 | 197 | /* Get debug registers state for process PID. */ |
9d19df75 | 198 | |
db3cb7cb | 199 | struct aarch64_debug_reg_state * |
d6c44983 | 200 | aarch64_get_debug_reg_state (pid_t pid) |
9d19df75 | 201 | { |
d6c44983 | 202 | return &aarch64_process_info_get (pid)->state; |
9d19df75 MS |
203 | } |
204 | ||
9d19df75 MS |
205 | /* Fill GDB's register array with the general-purpose register values |
206 | from the current thread. */ | |
207 | ||
208 | static void | |
209 | fetch_gregs_from_thread (struct regcache *regcache) | |
210 | { | |
607685ec | 211 | int ret, tid; |
ac7936df | 212 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 MS |
213 | elf_gregset_t regs; |
214 | struct iovec iovec; | |
215 | ||
607685ec YQ |
216 | /* Make sure REGS can hold all registers contents on both aarch64 |
217 | and arm. */ | |
218 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
219 | ||
e38504b3 | 220 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
221 | |
222 | iovec.iov_base = ®s; | |
607685ec YQ |
223 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
224 | iovec.iov_len = 18 * 4; | |
225 | else | |
226 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
227 | |
228 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
229 | if (ret < 0) | |
230 | perror_with_name (_("Unable to fetch general registers.")); | |
231 | ||
607685ec YQ |
232 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
233 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1); | |
234 | else | |
235 | { | |
236 | int regno; | |
237 | ||
238 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
73e1c03f | 239 | regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 240 | } |
9d19df75 MS |
241 | } |
242 | ||
243 | /* Store to the current thread the valid general-purpose register | |
244 | values in the GDB's register array. */ | |
245 | ||
246 | static void | |
247 | store_gregs_to_thread (const struct regcache *regcache) | |
248 | { | |
607685ec | 249 | int ret, tid; |
9d19df75 MS |
250 | elf_gregset_t regs; |
251 | struct iovec iovec; | |
ac7936df | 252 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 253 | |
607685ec YQ |
254 | /* Make sure REGS can hold all registers contents on both aarch64 |
255 | and arm. */ | |
256 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
e38504b3 | 257 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
258 | |
259 | iovec.iov_base = ®s; | |
607685ec YQ |
260 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
261 | iovec.iov_len = 18 * 4; | |
262 | else | |
263 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
264 | |
265 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
266 | if (ret < 0) | |
267 | perror_with_name (_("Unable to fetch general registers.")); | |
268 | ||
607685ec YQ |
269 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
270 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1); | |
271 | else | |
272 | { | |
273 | int regno; | |
274 | ||
275 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
0ec9f114 | 276 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 | 277 | regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 278 | } |
9d19df75 MS |
279 | |
280 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
281 | if (ret < 0) | |
282 | perror_with_name (_("Unable to store general registers.")); | |
283 | } | |
284 | ||
285 | /* Fill GDB's register array with the fp/simd register values | |
286 | from the current thread. */ | |
287 | ||
288 | static void | |
289 | fetch_fpregs_from_thread (struct regcache *regcache) | |
290 | { | |
607685ec | 291 | int ret, tid; |
9d19df75 MS |
292 | elf_fpregset_t regs; |
293 | struct iovec iovec; | |
ac7936df | 294 | struct gdbarch *gdbarch = regcache->arch (); |
607685ec YQ |
295 | |
296 | /* Make sure REGS can hold all VFP registers contents on both aarch64 | |
297 | and arm. */ | |
350fab54 | 298 | gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); |
9d19df75 | 299 | |
e38504b3 | 300 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
301 | |
302 | iovec.iov_base = ®s; | |
9d19df75 | 303 | |
607685ec YQ |
304 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
305 | { | |
350fab54 | 306 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
607685ec YQ |
307 | |
308 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); | |
309 | if (ret < 0) | |
310 | perror_with_name (_("Unable to fetch VFP registers.")); | |
311 | ||
312 | aarch32_vfp_regcache_supply (regcache, (gdb_byte *) ®s, 32); | |
313 | } | |
314 | else | |
315 | { | |
316 | int regno; | |
317 | ||
318 | iovec.iov_len = sizeof (regs); | |
9d19df75 | 319 | |
607685ec YQ |
320 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
321 | if (ret < 0) | |
322 | perror_with_name (_("Unable to fetch vFP/SIMD registers.")); | |
9d19df75 | 323 | |
607685ec | 324 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
73e1c03f | 325 | regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]); |
607685ec | 326 | |
73e1c03f SM |
327 | regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr); |
328 | regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr); | |
607685ec | 329 | } |
9d19df75 MS |
330 | } |
331 | ||
332 | /* Store to the current thread the valid fp/simd register | |
333 | values in the GDB's register array. */ | |
334 | ||
335 | static void | |
336 | store_fpregs_to_thread (const struct regcache *regcache) | |
337 | { | |
607685ec | 338 | int ret, tid; |
9d19df75 MS |
339 | elf_fpregset_t regs; |
340 | struct iovec iovec; | |
ac7936df | 341 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 342 | |
607685ec YQ |
343 | /* Make sure REGS can hold all VFP registers contents on both aarch64 |
344 | and arm. */ | |
350fab54 | 345 | gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); |
e38504b3 | 346 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
347 | |
348 | iovec.iov_base = ®s; | |
9d19df75 | 349 | |
607685ec YQ |
350 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
351 | { | |
350fab54 | 352 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
9d19df75 | 353 | |
607685ec YQ |
354 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
355 | if (ret < 0) | |
356 | perror_with_name (_("Unable to fetch VFP registers.")); | |
9d19df75 | 357 | |
607685ec YQ |
358 | aarch32_vfp_regcache_collect (regcache, (gdb_byte *) ®s, 32); |
359 | } | |
360 | else | |
361 | { | |
362 | int regno; | |
9d19df75 | 363 | |
607685ec YQ |
364 | iovec.iov_len = sizeof (regs); |
365 | ||
366 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
367 | if (ret < 0) | |
368 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
369 | ||
370 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
0ec9f114 | 371 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 SM |
372 | regcache->raw_collect |
373 | (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
607685ec | 374 | |
0ec9f114 | 375 | if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM)) |
34a79281 | 376 | regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
0ec9f114 | 377 | if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM)) |
34a79281 | 378 | regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
607685ec YQ |
379 | } |
380 | ||
381 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
382 | { | |
383 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec); | |
384 | if (ret < 0) | |
385 | perror_with_name (_("Unable to store VFP registers.")); | |
386 | } | |
387 | else | |
388 | { | |
389 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
390 | if (ret < 0) | |
391 | perror_with_name (_("Unable to store FP/SIMD registers.")); | |
392 | } | |
9d19df75 MS |
393 | } |
394 | ||
e9902bfc AH |
395 | /* Fill GDB's register array with the sve register values |
396 | from the current thread. */ | |
397 | ||
398 | static void | |
399 | fetch_sveregs_from_thread (struct regcache *regcache) | |
400 | { | |
401 | std::unique_ptr<gdb_byte[]> base | |
e38504b3 | 402 | = aarch64_sve_get_sveregs (regcache->ptid ().lwp ()); |
e9902bfc AH |
403 | aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ()); |
404 | } | |
405 | ||
406 | /* Store to the current thread the valid sve register | |
407 | values in the GDB's register array. */ | |
408 | ||
409 | static void | |
410 | store_sveregs_to_thread (struct regcache *regcache) | |
411 | { | |
412 | int ret; | |
413 | struct iovec iovec; | |
e38504b3 | 414 | int tid = regcache->ptid ().lwp (); |
e9902bfc | 415 | |
48574d91 AH |
416 | /* First store vector length to the thread. This is done first to ensure the |
417 | ptrace buffers read from the kernel are the correct size. */ | |
418 | if (!aarch64_sve_set_vq (tid, regcache)) | |
419 | perror_with_name (_("Unable to set VG register.")); | |
420 | ||
e9902bfc AH |
421 | /* Obtain a dump of SVE registers from ptrace. */ |
422 | std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid); | |
423 | ||
424 | /* Overwrite with regcache state. */ | |
425 | aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ()); | |
426 | ||
427 | /* Write back to the kernel. */ | |
428 | iovec.iov_base = base.get (); | |
429 | iovec.iov_len = ((struct user_sve_header *) base.get ())->size; | |
430 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec); | |
431 | ||
432 | if (ret < 0) | |
433 | perror_with_name (_("Unable to store sve registers")); | |
434 | } | |
435 | ||
76bed0fd AH |
436 | /* Fill GDB's register array with the pointer authentication mask values from |
437 | the current thread. */ | |
438 | ||
439 | static void | |
440 | fetch_pauth_masks_from_thread (struct regcache *regcache) | |
441 | { | |
442 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); | |
443 | int ret; | |
444 | struct iovec iovec; | |
445 | uint64_t pauth_regset[2] = {0, 0}; | |
446 | int tid = regcache->ptid ().lwp (); | |
447 | ||
448 | iovec.iov_base = &pauth_regset; | |
449 | iovec.iov_len = sizeof (pauth_regset); | |
450 | ||
451 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec); | |
452 | if (ret != 0) | |
453 | perror_with_name (_("unable to fetch pauth registers.")); | |
454 | ||
455 | regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base), | |
456 | &pauth_regset[0]); | |
457 | regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base), | |
458 | &pauth_regset[1]); | |
459 | } | |
460 | ||
f6ac5f3d | 461 | /* Implement the "fetch_registers" target_ops method. */ |
9d19df75 | 462 | |
f6ac5f3d PA |
463 | void |
464 | aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, | |
465 | int regno) | |
9d19df75 | 466 | { |
e9902bfc AH |
467 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
468 | ||
9d19df75 MS |
469 | if (regno == -1) |
470 | { | |
471 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
472 | if (tdep->has_sve ()) |
473 | fetch_sveregs_from_thread (regcache); | |
474 | else | |
475 | fetch_fpregs_from_thread (regcache); | |
76bed0fd AH |
476 | |
477 | if (tdep->has_pauth ()) | |
478 | fetch_pauth_masks_from_thread (regcache); | |
9d19df75 MS |
479 | } |
480 | else if (regno < AARCH64_V0_REGNUM) | |
481 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
482 | else if (tdep->has_sve ()) |
483 | fetch_sveregs_from_thread (regcache); | |
9d19df75 MS |
484 | else |
485 | fetch_fpregs_from_thread (regcache); | |
76bed0fd AH |
486 | |
487 | if (tdep->has_pauth ()) | |
488 | { | |
489 | if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) | |
490 | || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) | |
491 | fetch_pauth_masks_from_thread (regcache); | |
492 | } | |
9d19df75 MS |
493 | } |
494 | ||
f6ac5f3d | 495 | /* Implement the "store_registers" target_ops method. */ |
9d19df75 | 496 | |
f6ac5f3d PA |
497 | void |
498 | aarch64_linux_nat_target::store_registers (struct regcache *regcache, | |
499 | int regno) | |
9d19df75 | 500 | { |
e9902bfc AH |
501 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
502 | ||
9d19df75 MS |
503 | if (regno == -1) |
504 | { | |
505 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
506 | if (tdep->has_sve ()) |
507 | store_sveregs_to_thread (regcache); | |
508 | else | |
509 | store_fpregs_to_thread (regcache); | |
9d19df75 MS |
510 | } |
511 | else if (regno < AARCH64_V0_REGNUM) | |
512 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
513 | else if (tdep->has_sve ()) |
514 | store_sveregs_to_thread (regcache); | |
9d19df75 MS |
515 | else |
516 | store_fpregs_to_thread (regcache); | |
517 | } | |
518 | ||
519 | /* Fill register REGNO (if it is a general-purpose register) in | |
520 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
521 | do this for all registers. */ | |
522 | ||
523 | void | |
524 | fill_gregset (const struct regcache *regcache, | |
525 | gdb_gregset_t *gregsetp, int regno) | |
526 | { | |
d4d793bf AA |
527 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
528 | regno, (gdb_byte *) gregsetp, | |
529 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
530 | } |
531 | ||
532 | /* Fill GDB's register array with the general-purpose register values | |
533 | in *GREGSETP. */ | |
534 | ||
535 | void | |
536 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
537 | { | |
d4d793bf AA |
538 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
539 | (const gdb_byte *) gregsetp, | |
540 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
541 | } |
542 | ||
543 | /* Fill register REGNO (if it is a floating-point register) in | |
544 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
545 | do this for all registers. */ | |
546 | ||
547 | void | |
548 | fill_fpregset (const struct regcache *regcache, | |
549 | gdb_fpregset_t *fpregsetp, int regno) | |
550 | { | |
d4d793bf AA |
551 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
552 | regno, (gdb_byte *) fpregsetp, | |
553 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
554 | } |
555 | ||
556 | /* Fill GDB's register array with the floating-point register values | |
557 | in *FPREGSETP. */ | |
558 | ||
559 | void | |
560 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
561 | { | |
d4d793bf AA |
562 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
563 | (const gdb_byte *) fpregsetp, | |
564 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
565 | } |
566 | ||
d6c44983 YZ |
567 | /* linux_nat_new_fork hook. */ |
568 | ||
135340af PA |
569 | void |
570 | aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent, | |
571 | pid_t child_pid) | |
d6c44983 YZ |
572 | { |
573 | pid_t parent_pid; | |
574 | struct aarch64_debug_reg_state *parent_state; | |
575 | struct aarch64_debug_reg_state *child_state; | |
576 | ||
577 | /* NULL means no watchpoint has ever been set in the parent. In | |
578 | that case, there's nothing to do. */ | |
579 | if (parent->arch_private == NULL) | |
580 | return; | |
581 | ||
582 | /* GDB core assumes the child inherits the watchpoints/hw | |
583 | breakpoints of the parent, and will remove them all from the | |
584 | forked off process. Copy the debug registers mirrors into the | |
585 | new process so that all breakpoints and watchpoints can be | |
586 | removed together. */ | |
587 | ||
e99b03dc | 588 | parent_pid = parent->ptid.pid (); |
d6c44983 YZ |
589 | parent_state = aarch64_get_debug_reg_state (parent_pid); |
590 | child_state = aarch64_get_debug_reg_state (child_pid); | |
591 | *child_state = *parent_state; | |
592 | } | |
9d19df75 MS |
593 | \f |
594 | ||
595 | /* Called by libthread_db. Returns a pointer to the thread local | |
596 | storage (or its descriptor). */ | |
597 | ||
598 | ps_err_e | |
754653a7 | 599 | ps_get_thread_area (struct ps_prochandle *ph, |
9d19df75 MS |
600 | lwpid_t lwpid, int idx, void **base) |
601 | { | |
a0cc84cd YQ |
602 | int is_64bit_p |
603 | = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64); | |
9d19df75 | 604 | |
a0cc84cd | 605 | return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p); |
9d19df75 MS |
606 | } |
607 | \f | |
608 | ||
f6ac5f3d | 609 | /* Implement the "post_startup_inferior" target_ops method. */ |
9d19df75 | 610 | |
f6ac5f3d PA |
611 | void |
612 | aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid) | |
9d19df75 | 613 | { |
e99b03dc TT |
614 | low_forget_process (ptid.pid ()); |
615 | aarch64_linux_get_debug_reg_capacity (ptid.pid ()); | |
f6ac5f3d | 616 | linux_nat_target::post_startup_inferior (ptid); |
9d19df75 MS |
617 | } |
618 | ||
8363f9d5 RB |
619 | /* Implement the "post_attach" target_ops method. */ |
620 | ||
621 | void | |
622 | aarch64_linux_nat_target::post_attach (int pid) | |
623 | { | |
624 | low_forget_process (pid); | |
625 | /* Set the hardware debug register capacity. If | |
626 | aarch64_linux_get_debug_reg_capacity is not called | |
627 | (as it is in aarch64_linux_child_post_startup_inferior) then | |
628 | software watchpoints will be used instead of hardware | |
629 | watchpoints when attaching to a target. */ | |
630 | aarch64_linux_get_debug_reg_capacity (pid); | |
631 | linux_nat_target::post_attach (pid); | |
632 | } | |
633 | ||
607685ec YQ |
634 | extern struct target_desc *tdesc_arm_with_neon; |
635 | ||
f6ac5f3d | 636 | /* Implement the "read_description" target_ops method. */ |
9d19df75 | 637 | |
f6ac5f3d PA |
638 | const struct target_desc * |
639 | aarch64_linux_nat_target::read_description () | |
9d19df75 | 640 | { |
6f67973b | 641 | int ret, tid; |
350fab54 | 642 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
6f67973b | 643 | struct iovec iovec; |
607685ec | 644 | |
e38504b3 | 645 | tid = inferior_ptid.lwp (); |
607685ec | 646 | |
6f67973b | 647 | iovec.iov_base = regbuf; |
350fab54 | 648 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
607685ec | 649 | |
6f67973b YQ |
650 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
651 | if (ret == 0) | |
652 | return tdesc_arm_with_neon; | |
6dc0ebde | 653 | |
0f83012e | 654 | CORE_ADDR hwcap = linux_get_hwcap (this); |
ee4fbcfa | 655 | |
0f83012e AH |
656 | return aarch64_read_description (aarch64_sve_get_vq (tid), |
657 | hwcap & AARCH64_HWCAP_PACA); | |
9d19df75 MS |
658 | } |
659 | ||
ade90bde YQ |
660 | /* Convert a native/host siginfo object, into/from the siginfo in the |
661 | layout of the inferiors' architecture. Returns true if any | |
662 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
663 | from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to | |
664 | INF. */ | |
665 | ||
135340af PA |
666 | bool |
667 | aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, | |
668 | int direction) | |
ade90bde YQ |
669 | { |
670 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); | |
671 | ||
672 | /* Is the inferior 32-bit? If so, then do fixup the siginfo | |
673 | object. */ | |
674 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
675 | { | |
676 | if (direction == 0) | |
677 | aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, | |
678 | native); | |
679 | else | |
680 | aarch64_siginfo_from_compat_siginfo (native, | |
681 | (struct compat_siginfo *) inf); | |
682 | ||
135340af | 683 | return true; |
ade90bde YQ |
684 | } |
685 | ||
135340af | 686 | return false; |
ade90bde YQ |
687 | } |
688 | ||
9d19df75 MS |
689 | /* Returns the number of hardware watchpoints of type TYPE that we can |
690 | set. Value is positive if we can set CNT watchpoints, zero if | |
691 | setting watchpoints of type TYPE is not supported, and negative if | |
692 | CNT is more than the maximum number of watchpoints of type TYPE | |
693 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
694 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
695 | CNT is the number of such watchpoints used so far (including this | |
696 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
c2fbdc59 | 697 | currently enabled. */ |
9d19df75 | 698 | |
f6ac5f3d PA |
699 | int |
700 | aarch64_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
701 | int cnt, int othertype) | |
9d19df75 | 702 | { |
c2fbdc59 YQ |
703 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
704 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
705 | { | |
706 | if (aarch64_num_wp_regs == 0) | |
707 | return 0; | |
708 | } | |
709 | else if (type == bp_hardware_breakpoint) | |
710 | { | |
711 | if (aarch64_num_bp_regs == 0) | |
712 | return 0; | |
713 | } | |
714 | else | |
715 | gdb_assert_not_reached ("unexpected breakpoint type"); | |
716 | ||
717 | /* We always return 1 here because we don't have enough information | |
718 | about possible overlap of addresses that they want to watch. As an | |
719 | extreme example, consider the case where all the watchpoints watch | |
720 | the same address and the same region length: then we can handle a | |
721 | virtually unlimited number of watchpoints, due to debug register | |
722 | sharing implemented via reference counts. */ | |
9d19df75 MS |
723 | return 1; |
724 | } | |
725 | ||
0d5ed153 | 726 | /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. |
9d19df75 MS |
727 | Return 0 on success, -1 on failure. */ |
728 | ||
f6ac5f3d PA |
729 | int |
730 | aarch64_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
731 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
732 | { |
733 | int ret; | |
0d5ed153 | 734 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
8d689ee5 | 735 | int len; |
2ecd81c2 | 736 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de | 737 | struct aarch64_debug_reg_state *state |
e99b03dc | 738 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 739 | |
8d689ee5 YQ |
740 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
741 | ||
c5e92cca | 742 | if (show_debug_regs) |
9d19df75 MS |
743 | fprintf_unfiltered |
744 | (gdb_stdlog, | |
745 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
746 | (unsigned long) addr, len); | |
747 | ||
c67ca4de | 748 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 749 | |
c5e92cca | 750 | if (show_debug_regs) |
d6c44983 | 751 | { |
d6c44983 | 752 | aarch64_show_debug_reg_state (state, |
2fd0f80d | 753 | "insert_hw_breakpoint", addr, len, type); |
d6c44983 | 754 | } |
9d19df75 MS |
755 | |
756 | return ret; | |
757 | } | |
758 | ||
759 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. | |
760 | Return 0 on success, -1 on failure. */ | |
761 | ||
f6ac5f3d PA |
762 | int |
763 | aarch64_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
764 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
765 | { |
766 | int ret; | |
767 | CORE_ADDR addr = bp_tgt->placed_address; | |
8d689ee5 | 768 | int len = 4; |
2ecd81c2 | 769 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de | 770 | struct aarch64_debug_reg_state *state |
e99b03dc | 771 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 772 | |
8d689ee5 YQ |
773 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
774 | ||
c5e92cca | 775 | if (show_debug_regs) |
9d19df75 MS |
776 | fprintf_unfiltered |
777 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
778 | (unsigned long) addr, len); | |
779 | ||
c67ca4de | 780 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 781 | |
c5e92cca | 782 | if (show_debug_regs) |
d6c44983 | 783 | { |
d6c44983 YZ |
784 | aarch64_show_debug_reg_state (state, |
785 | "remove_hw_watchpoint", addr, len, type); | |
786 | } | |
9d19df75 MS |
787 | |
788 | return ret; | |
789 | } | |
790 | ||
f6ac5f3d | 791 | /* Implement the "insert_watchpoint" target_ops method. |
9d19df75 MS |
792 | |
793 | Insert a watchpoint to watch a memory region which starts at | |
794 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
795 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
796 | ||
f6ac5f3d PA |
797 | int |
798 | aarch64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
799 | enum target_hw_bp_type type, | |
800 | struct expression *cond) | |
9d19df75 MS |
801 | { |
802 | int ret; | |
c67ca4de | 803 | struct aarch64_debug_reg_state *state |
e99b03dc | 804 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 805 | |
c5e92cca | 806 | if (show_debug_regs) |
9d19df75 MS |
807 | fprintf_unfiltered (gdb_stdlog, |
808 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
809 | (unsigned long) addr, len); | |
810 | ||
811 | gdb_assert (type != hw_execute); | |
812 | ||
c67ca4de | 813 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 814 | |
c5e92cca | 815 | if (show_debug_regs) |
d6c44983 | 816 | { |
d6c44983 YZ |
817 | aarch64_show_debug_reg_state (state, |
818 | "insert_watchpoint", addr, len, type); | |
819 | } | |
9d19df75 MS |
820 | |
821 | return ret; | |
822 | } | |
823 | ||
f6ac5f3d | 824 | /* Implement the "remove_watchpoint" target_ops method. |
9d19df75 MS |
825 | Remove a watchpoint that watched the memory region which starts at |
826 | address ADDR, whose length is LEN bytes, and for accesses of the | |
827 | type TYPE. Return 0 on success, -1 on failure. */ | |
828 | ||
f6ac5f3d PA |
829 | int |
830 | aarch64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
831 | enum target_hw_bp_type type, | |
832 | struct expression *cond) | |
9d19df75 MS |
833 | { |
834 | int ret; | |
c67ca4de | 835 | struct aarch64_debug_reg_state *state |
e99b03dc | 836 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 837 | |
c5e92cca | 838 | if (show_debug_regs) |
9d19df75 MS |
839 | fprintf_unfiltered (gdb_stdlog, |
840 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
841 | (unsigned long) addr, len); | |
842 | ||
843 | gdb_assert (type != hw_execute); | |
844 | ||
c67ca4de | 845 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 846 | |
c5e92cca | 847 | if (show_debug_regs) |
d6c44983 | 848 | { |
d6c44983 YZ |
849 | aarch64_show_debug_reg_state (state, |
850 | "remove_watchpoint", addr, len, type); | |
851 | } | |
9d19df75 MS |
852 | |
853 | return ret; | |
854 | } | |
855 | ||
f6ac5f3d | 856 | /* Implement the "region_ok_for_hw_watchpoint" target_ops method. */ |
9d19df75 | 857 | |
f6ac5f3d PA |
858 | int |
859 | aarch64_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
9d19df75 | 860 | { |
39edd165 | 861 | return aarch64_linux_region_ok_for_watchpoint (addr, len); |
9d19df75 MS |
862 | } |
863 | ||
f6ac5f3d | 864 | /* Implement the "stopped_data_address" target_ops method. */ |
9d19df75 | 865 | |
57810aa7 | 866 | bool |
f6ac5f3d | 867 | aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
9d19df75 MS |
868 | { |
869 | siginfo_t siginfo; | |
cf4088a9 | 870 | int i; |
9d19df75 MS |
871 | struct aarch64_debug_reg_state *state; |
872 | ||
873 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 874 | return false; |
9d19df75 MS |
875 | |
876 | /* This must be a hardware breakpoint. */ | |
877 | if (siginfo.si_signo != SIGTRAP | |
878 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
57810aa7 | 879 | return false; |
9d19df75 MS |
880 | |
881 | /* Check if the address matches any watched address. */ | |
e99b03dc | 882 | state = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 MS |
883 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
884 | { | |
a3b60e45 JK |
885 | const unsigned int offset |
886 | = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]); | |
9d19df75 MS |
887 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
888 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
a3b60e45 JK |
889 | const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset; |
890 | const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8); | |
891 | const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i]; | |
9d19df75 MS |
892 | |
893 | if (state->dr_ref_count_wp[i] | |
894 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
a3b60e45 | 895 | && addr_trap >= addr_watch_aligned |
9d19df75 MS |
896 | && addr_trap < addr_watch + len) |
897 | { | |
a3b60e45 JK |
898 | /* ADDR_TRAP reports the first address of the memory range |
899 | accessed by the CPU, regardless of what was the memory | |
900 | range watched. Thus, a large CPU access that straddles | |
901 | the ADDR_WATCH..ADDR_WATCH+LEN range may result in an | |
902 | ADDR_TRAP that is lower than the | |
903 | ADDR_WATCH..ADDR_WATCH+LEN range. E.g.: | |
904 | ||
905 | addr: | 4 | 5 | 6 | 7 | 8 | | |
906 | |---- range watched ----| | |
907 | |----------- range accessed ------------| | |
908 | ||
909 | In this case, ADDR_TRAP will be 4. | |
910 | ||
911 | To match a watchpoint known to GDB core, we must never | |
912 | report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN | |
913 | range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false | |
914 | positive on kernels older than 4.10. See PR | |
915 | external/20207. */ | |
916 | *addr_p = addr_orig; | |
57810aa7 | 917 | return true; |
9d19df75 MS |
918 | } |
919 | } | |
920 | ||
57810aa7 | 921 | return false; |
9d19df75 MS |
922 | } |
923 | ||
f6ac5f3d | 924 | /* Implement the "stopped_by_watchpoint" target_ops method. */ |
9d19df75 | 925 | |
57810aa7 | 926 | bool |
f6ac5f3d | 927 | aarch64_linux_nat_target::stopped_by_watchpoint () |
9d19df75 MS |
928 | { |
929 | CORE_ADDR addr; | |
930 | ||
f6ac5f3d | 931 | return stopped_data_address (&addr); |
9d19df75 MS |
932 | } |
933 | ||
f6ac5f3d | 934 | /* Implement the "watchpoint_addr_within_range" target_ops method. */ |
9d19df75 | 935 | |
57810aa7 | 936 | bool |
f6ac5f3d PA |
937 | aarch64_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
938 | CORE_ADDR start, int length) | |
9d19df75 MS |
939 | { |
940 | return start <= addr && start + length - 1 >= addr; | |
941 | } | |
942 | ||
f6ac5f3d | 943 | /* Implement the "can_do_single_step" target_ops method. */ |
750ce8d1 | 944 | |
f6ac5f3d PA |
945 | int |
946 | aarch64_linux_nat_target::can_do_single_step () | |
750ce8d1 YQ |
947 | { |
948 | return 1; | |
949 | } | |
950 | ||
4da037ef AH |
951 | /* Implement the "thread_architecture" target_ops method. */ |
952 | ||
953 | struct gdbarch * | |
954 | aarch64_linux_nat_target::thread_architecture (ptid_t ptid) | |
955 | { | |
956 | /* Return the gdbarch for the current thread. If the vector length has | |
957 | changed since the last time this was called, then do a further lookup. */ | |
958 | ||
959 | uint64_t vq = aarch64_sve_get_vq (ptid.lwp ()); | |
960 | ||
961 | /* Find the current gdbarch the same way as process_stratum_target. Only | |
962 | return it if the current vector length matches the one in the tdep. */ | |
963 | inferior *inf = find_inferior_ptid (ptid); | |
964 | gdb_assert (inf != NULL); | |
965 | if (vq == gdbarch_tdep (inf->gdbarch)->vq) | |
966 | return inf->gdbarch; | |
967 | ||
968 | /* We reach here if the vector length for the thread is different from its | |
969 | value at process start. Lookup gdbarch via info (potentially creating a | |
970 | new one), stashing the vector length inside id. Use -1 for when SVE | |
971 | unavailable, to distinguish from an unset value of 0. */ | |
972 | struct gdbarch_info info; | |
973 | gdbarch_info_init (&info); | |
974 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_spu, bfd_mach_spu); | |
975 | info.id = (int *) (vq == 0 ? -1 : vq); | |
976 | return gdbarch_find_by_info (info); | |
977 | } | |
978 | ||
9d19df75 MS |
979 | /* Define AArch64 maintenance commands. */ |
980 | ||
981 | static void | |
982 | add_show_debug_regs_command (void) | |
983 | { | |
984 | /* A maintenance command to enable printing the internal DRi mirror | |
985 | variables. */ | |
986 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
c5e92cca | 987 | &show_debug_regs, _("\ |
9d19df75 MS |
988 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ |
989 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ | |
990 | Use \"on\" to enable, \"off\" to disable.\n\ | |
991 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
992 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
993 | triggers a breakpoint or watchpoint."), | |
994 | NULL, | |
995 | NULL, | |
996 | &maintenance_set_cmdlist, | |
997 | &maintenance_show_cmdlist); | |
998 | } | |
999 | ||
9d19df75 MS |
1000 | void |
1001 | _initialize_aarch64_linux_nat (void) | |
1002 | { | |
9d19df75 MS |
1003 | add_show_debug_regs_command (); |
1004 | ||
9d19df75 | 1005 | /* Register the target. */ |
f6ac5f3d | 1006 | linux_target = &the_aarch64_linux_nat_target; |
d9f719f1 | 1007 | add_inf_child_target (&the_aarch64_linux_nat_target); |
9d19df75 | 1008 | } |