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9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
3 | Copyright (C) 2011-2013 Free Software Foundation, Inc. | |
4 | Contributed by ARM Ltd. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "inferior.h" | |
24 | #include "gdbcore.h" | |
25 | #include "regcache.h" | |
26 | #include "linux-nat.h" | |
27 | #include "target-descriptions.h" | |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "aarch64-tdep.h" | |
31 | #include "aarch64-linux-tdep.h" | |
32 | #include "elf/common.h" | |
33 | ||
34 | #include <sys/ptrace.h> | |
35 | #include <sys/utsname.h> | |
36 | ||
37 | #include "gregset.h" | |
38 | ||
39 | #include "features/aarch64.c" | |
40 | ||
41 | /* Defines ps_err_e, struct ps_prochandle. */ | |
42 | #include "gdb_proc_service.h" | |
43 | ||
44 | #ifndef TRAP_HWBKPT | |
45 | #define TRAP_HWBKPT 0x0004 | |
46 | #endif | |
47 | ||
48 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which | |
49 | case we may be tracing more than one process at a time. In that | |
50 | case, inferior_ptid will contain the main process ID and the | |
51 | individual thread (process) ID. get_thread_id () is used to get | |
52 | the thread id if it's available, and the process id otherwise. */ | |
53 | ||
54 | static int | |
55 | get_thread_id (ptid_t ptid) | |
56 | { | |
57 | int tid = TIDGET (ptid); | |
58 | ||
59 | if (0 == tid) | |
60 | tid = PIDGET (ptid); | |
61 | return tid; | |
62 | } | |
63 | ||
64 | /* Macro definitions, data structures, and code for the hardware | |
65 | breakpoint and hardware watchpoint support follow. We use the | |
66 | following abbreviations throughout the code: | |
67 | ||
68 | hw - hardware | |
69 | bp - breakpoint | |
70 | wp - watchpoint */ | |
71 | ||
72 | /* Maximum number of hardware breakpoint and watchpoint registers. | |
73 | Neither of these values may exceed the width of dr_changed_t | |
74 | measured in bits. */ | |
75 | ||
76 | #define AARCH64_HBP_MAX_NUM 16 | |
77 | #define AARCH64_HWP_MAX_NUM 16 | |
78 | ||
79 | /* Alignment requirement in bytes for addresses written to | |
80 | hardware breakpoint and watchpoint value registers. | |
81 | ||
82 | A ptrace call attempting to set an address that does not meet the | |
83 | alignment criteria will fail. Limited support has been provided in | |
84 | this port for unaligned watchpoints, such that from a GDB user | |
85 | perspective, an unaligned watchpoint may be requested. | |
86 | ||
87 | This is achieved by minimally enlarging the watched area to meet the | |
88 | alignment requirement, and if necessary, splitting the watchpoint | |
89 | over several hardware watchpoint registers. */ | |
90 | ||
91 | #define AARCH64_HBP_ALIGNMENT 4 | |
92 | #define AARCH64_HWP_ALIGNMENT 8 | |
93 | ||
94 | /* The maximum length of a memory region that can be watched by one | |
95 | hardware watchpoint register. */ | |
96 | ||
97 | #define AARCH64_HWP_MAX_LEN_PER_REG 8 | |
98 | ||
99 | /* ptrace hardware breakpoint resource info is formatted as follows: | |
100 | ||
101 | 31 24 16 8 0 | |
102 | +---------------+--------------+---------------+---------------+ | |
103 | | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | | |
104 | +---------------+--------------+---------------+---------------+ */ | |
105 | ||
106 | ||
107 | /* Macros to extract fields from the hardware debug information word. */ | |
108 | #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) | |
109 | #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) | |
110 | ||
111 | /* Macro for the expected version of the ARMv8-A debug architecture. */ | |
112 | #define AARCH64_DEBUG_ARCH_V8 0x6 | |
113 | ||
114 | /* Number of hardware breakpoints/watchpoints the target supports. | |
115 | They are initialized with values obtained via the ptrace calls | |
116 | with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ | |
117 | ||
118 | static int aarch64_num_bp_regs; | |
119 | static int aarch64_num_wp_regs; | |
120 | ||
121 | /* Debugging of hardware breakpoint/watchpoint support. */ | |
122 | ||
123 | static int debug_hw_points; | |
124 | ||
125 | /* Each bit of a variable of this type is used to indicate whether a | |
126 | hardware breakpoint or watchpoint setting has been changed since | |
127 | the last update. | |
128 | ||
129 | Bit N corresponds to the Nth hardware breakpoint or watchpoint | |
130 | setting which is managed in aarch64_debug_reg_state, where N is | |
131 | valid between 0 and the total number of the hardware breakpoint or | |
132 | watchpoint debug registers minus 1. | |
133 | ||
134 | When bit N is 1, the corresponding breakpoint or watchpoint setting | |
135 | has changed, and therefore the corresponding hardware debug | |
136 | register needs to be updated via the ptrace interface. | |
137 | ||
138 | In the per-thread arch-specific data area, we define two such | |
139 | variables for per-thread hardware breakpoint and watchpoint | |
140 | settings respectively. | |
141 | ||
142 | This type is part of the mechanism which helps reduce the number of | |
143 | ptrace calls to the kernel, i.e. avoid asking the kernel to write | |
144 | to the debug registers with unchanged values. */ | |
145 | ||
6eb04473 | 146 | typedef unsigned LONGEST dr_changed_t; |
9d19df75 MS |
147 | |
148 | /* Set each of the lower M bits of X to 1; assert X is wide enough. */ | |
149 | ||
150 | #define DR_MARK_ALL_CHANGED(x, m) \ | |
151 | do \ | |
152 | { \ | |
153 | gdb_assert (sizeof ((x)) * 8 >= (m)); \ | |
154 | (x) = (((dr_changed_t)1 << (m)) - 1); \ | |
155 | } while (0) | |
156 | ||
157 | #define DR_MARK_N_CHANGED(x, n) \ | |
158 | do \ | |
159 | { \ | |
160 | (x) |= ((dr_changed_t)1 << (n)); \ | |
161 | } while (0) | |
162 | ||
163 | #define DR_CLEAR_CHANGED(x) \ | |
164 | do \ | |
165 | { \ | |
166 | (x) = 0; \ | |
167 | } while (0) | |
168 | ||
169 | #define DR_HAS_CHANGED(x) ((x) != 0) | |
170 | #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) | |
171 | ||
172 | /* Structure for managing the hardware breakpoint/watchpoint resources. | |
173 | DR_ADDR_* stores the address, DR_CTRL_* stores the control register | |
174 | content, and DR_REF_COUNT_* counts the numbers of references to the | |
175 | corresponding bp/wp, by which way the limited hardware resources | |
176 | are not wasted on duplicated bp/wp settings (though so far gdb has | |
177 | done a good job by not sending duplicated bp/wp requests). */ | |
178 | ||
179 | struct aarch64_debug_reg_state | |
180 | { | |
181 | /* hardware breakpoint */ | |
182 | CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; | |
183 | unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; | |
184 | unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; | |
185 | ||
186 | /* hardware watchpoint */ | |
187 | CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; | |
188 | unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; | |
189 | unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; | |
190 | }; | |
191 | ||
192 | /* Clear the reference counts and forget everything we knew about the | |
193 | debug registers. */ | |
194 | ||
195 | static void | |
196 | aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state) | |
197 | { | |
198 | int i; | |
199 | ||
200 | for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i) | |
201 | { | |
202 | state->dr_addr_bp[i] = 0; | |
203 | state->dr_ctrl_bp[i] = 0; | |
204 | state->dr_ref_count_bp[i] = 0; | |
205 | } | |
206 | ||
207 | for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i) | |
208 | { | |
209 | state->dr_addr_wp[i] = 0; | |
210 | state->dr_ctrl_wp[i] = 0; | |
211 | state->dr_ref_count_wp[i] = 0; | |
212 | } | |
213 | } | |
214 | ||
215 | /* Per-inferior data key. */ | |
216 | static const struct inferior_data *aarch64_inferior_data; | |
217 | ||
218 | /* Per-inferior data. */ | |
219 | struct aarch64_inferior_data | |
220 | { | |
221 | /* Copy of AArch64 hardware debug registers for performance reasons. */ | |
222 | struct aarch64_debug_reg_state state; | |
223 | }; | |
224 | ||
225 | /* Per-inferior hook for register_inferior_data_with_cleanup. */ | |
226 | ||
227 | static void | |
228 | aarch64_inferior_data_cleanup (struct inferior *inf, void *arg) | |
229 | { | |
230 | struct aarch64_inferior_data *inf_data = arg; | |
231 | ||
232 | xfree (inf_data); | |
233 | } | |
234 | ||
235 | /* Get data specific for INFERIOR_PTID LWP. Return special data area | |
236 | for processes being detached. */ | |
237 | ||
238 | static struct aarch64_inferior_data * | |
239 | aarch64_inferior_data_get (void) | |
240 | { | |
241 | struct inferior *inf = current_inferior (); | |
242 | struct aarch64_inferior_data *inf_data; | |
243 | ||
244 | inf_data = inferior_data (inf, aarch64_inferior_data); | |
245 | if (inf_data == NULL) | |
246 | { | |
247 | inf_data = xzalloc (sizeof (*inf_data)); | |
248 | set_inferior_data (inf, aarch64_inferior_data, inf_data); | |
249 | } | |
250 | ||
251 | return inf_data; | |
252 | } | |
253 | ||
254 | /* Get debug registers state for INFERIOR_PTID, see | |
255 | aarch64_inferior_data_get. */ | |
256 | ||
257 | static struct aarch64_debug_reg_state * | |
258 | aarch64_get_debug_reg_state (void) | |
259 | { | |
260 | return &aarch64_inferior_data_get ()->state; | |
261 | } | |
262 | ||
263 | /* Per-thread arch-specific data we want to keep. */ | |
264 | ||
265 | struct arch_lwp_info | |
266 | { | |
267 | /* When bit N is 1, it indicates the Nth hardware breakpoint or | |
268 | watchpoint register pair needs to be updated when the thread is | |
269 | resumed; see aarch64_linux_prepare_to_resume. */ | |
270 | dr_changed_t dr_changed_bp; | |
271 | dr_changed_t dr_changed_wp; | |
272 | }; | |
273 | ||
274 | /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint | |
275 | registers with data from *STATE. */ | |
276 | ||
277 | static void | |
278 | aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, | |
279 | int tid, int watchpoint) | |
280 | { | |
281 | int i, count; | |
282 | struct iovec iov; | |
283 | struct user_hwdebug_state regs; | |
284 | const CORE_ADDR *addr; | |
285 | const unsigned int *ctrl; | |
286 | ||
287 | iov.iov_base = ®s; | |
288 | iov.iov_len = sizeof (regs); | |
289 | count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; | |
290 | addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; | |
291 | ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; | |
292 | ||
293 | for (i = 0; i < count; i++) | |
294 | { | |
295 | regs.dbg_regs[i].addr = addr[i]; | |
296 | regs.dbg_regs[i].ctrl = ctrl[i]; | |
297 | } | |
298 | ||
299 | if (ptrace (PTRACE_SETREGSET, tid, | |
300 | watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, | |
301 | (void *) &iov)) | |
302 | error (_("Unexpected error setting hardware debug registers")); | |
303 | } | |
304 | ||
305 | struct aarch64_dr_update_callback_param | |
306 | { | |
307 | int is_watchpoint; | |
308 | unsigned int idx; | |
309 | }; | |
310 | ||
311 | /* Callback for linux_nat_iterate_watchpoint_lwps. Records the | |
312 | information about the change of one hardware breakpoint/watchpoint | |
313 | setting for the thread LWP. | |
314 | The information is passed in via PTR. | |
315 | N.B. The actual updating of hardware debug registers is not | |
316 | carried out until the moment the thread is resumed. */ | |
317 | ||
318 | static int | |
319 | debug_reg_change_callback (struct lwp_info *lwp, void *ptr) | |
320 | { | |
321 | struct aarch64_dr_update_callback_param *param_p | |
322 | = (struct aarch64_dr_update_callback_param *) ptr; | |
323 | int pid = get_thread_id (lwp->ptid); | |
324 | int idx = param_p->idx; | |
325 | int is_watchpoint = param_p->is_watchpoint; | |
326 | struct arch_lwp_info *info = lwp->arch_private; | |
327 | dr_changed_t *dr_changed_ptr; | |
328 | dr_changed_t dr_changed; | |
329 | ||
330 | if (info == NULL) | |
331 | info = lwp->arch_private = XCNEW (struct arch_lwp_info); | |
332 | ||
333 | if (debug_hw_points) | |
334 | { | |
335 | fprintf_unfiltered (gdb_stdlog, | |
336 | "debug_reg_change_callback: \n\tOn entry:\n"); | |
337 | fprintf_unfiltered (gdb_stdlog, | |
1d3ffd6b MS |
338 | "\tpid%d, dr_changed_bp=0x%s, " |
339 | "dr_changed_wp=0x%s\n", | |
340 | pid, phex (info->dr_changed_bp, 8), | |
341 | phex (info->dr_changed_wp, 8)); | |
9d19df75 MS |
342 | } |
343 | ||
344 | dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp | |
345 | : &info->dr_changed_bp; | |
346 | dr_changed = *dr_changed_ptr; | |
347 | ||
348 | gdb_assert (idx >= 0 | |
349 | && (idx <= (is_watchpoint ? aarch64_num_wp_regs | |
350 | : aarch64_num_bp_regs))); | |
351 | ||
352 | /* The actual update is done later just before resuming the lwp, | |
353 | we just mark that one register pair needs updating. */ | |
354 | DR_MARK_N_CHANGED (dr_changed, idx); | |
355 | *dr_changed_ptr = dr_changed; | |
356 | ||
357 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
358 | we can update its debug registers. */ | |
359 | if (!lwp->stopped) | |
360 | linux_stop_lwp (lwp); | |
361 | ||
362 | if (debug_hw_points) | |
363 | { | |
364 | fprintf_unfiltered (gdb_stdlog, | |
1d3ffd6b MS |
365 | "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, " |
366 | "dr_changed_wp=0x%s\n", | |
367 | pid, phex (info->dr_changed_bp, 8), | |
368 | phex (info->dr_changed_wp, 8)); | |
9d19df75 MS |
369 | } |
370 | ||
371 | /* Continue the iteration. */ | |
372 | return 0; | |
373 | } | |
374 | ||
375 | /* Notify each thread that their IDXth breakpoint/watchpoint register | |
376 | pair needs to be updated. The message will be recorded in each | |
377 | thread's arch-specific data area, the actual updating will be done | |
378 | when the thread is resumed. */ | |
379 | ||
380 | static void | |
381 | aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, | |
382 | int is_watchpoint, unsigned int idx) | |
383 | { | |
384 | struct aarch64_dr_update_callback_param param; | |
385 | ||
386 | param.is_watchpoint = is_watchpoint; | |
387 | param.idx = idx; | |
388 | ||
389 | linux_nat_iterate_watchpoint_lwps (debug_reg_change_callback, | |
390 | (void *) ¶m); | |
391 | } | |
392 | ||
393 | /* Print the values of the cached breakpoint/watchpoint registers. */ | |
394 | ||
395 | static void | |
396 | aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, | |
397 | const char *func, CORE_ADDR addr, | |
398 | int len, int type) | |
399 | { | |
400 | int i; | |
401 | ||
402 | fprintf_unfiltered (gdb_stdlog, "%s", func); | |
403 | if (addr || len) | |
404 | fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)", | |
405 | (unsigned long) addr, len, | |
406 | type == hw_write ? "hw-write-watchpoint" | |
407 | : (type == hw_read ? "hw-read-watchpoint" | |
408 | : (type == hw_access ? "hw-access-watchpoint" | |
409 | : (type == hw_execute ? "hw-breakpoint" | |
410 | : "??unknown??")))); | |
411 | fprintf_unfiltered (gdb_stdlog, ":\n"); | |
412 | ||
413 | fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n"); | |
414 | for (i = 0; i < aarch64_num_bp_regs; i++) | |
415 | fprintf_unfiltered (gdb_stdlog, | |
416 | "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", | |
417 | i, state->dr_addr_bp[i], | |
418 | state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); | |
419 | ||
420 | fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n"); | |
421 | for (i = 0; i < aarch64_num_wp_regs; i++) | |
422 | fprintf_unfiltered (gdb_stdlog, | |
423 | "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", | |
424 | i, state->dr_addr_wp[i], | |
425 | state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); | |
426 | } | |
427 | ||
428 | /* Fill GDB's register array with the general-purpose register values | |
429 | from the current thread. */ | |
430 | ||
431 | static void | |
432 | fetch_gregs_from_thread (struct regcache *regcache) | |
433 | { | |
434 | int ret, regno, tid; | |
435 | elf_gregset_t regs; | |
436 | struct iovec iovec; | |
437 | ||
438 | tid = get_thread_id (inferior_ptid); | |
439 | ||
440 | iovec.iov_base = ®s; | |
441 | iovec.iov_len = sizeof (regs); | |
442 | ||
443 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
444 | if (ret < 0) | |
445 | perror_with_name (_("Unable to fetch general registers.")); | |
446 | ||
447 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
448 | regcache_raw_supply (regcache, regno, | |
449 | (char *) ®s[regno - AARCH64_X0_REGNUM]); | |
450 | } | |
451 | ||
452 | /* Store to the current thread the valid general-purpose register | |
453 | values in the GDB's register array. */ | |
454 | ||
455 | static void | |
456 | store_gregs_to_thread (const struct regcache *regcache) | |
457 | { | |
458 | int ret, regno, tid; | |
459 | elf_gregset_t regs; | |
460 | struct iovec iovec; | |
461 | ||
462 | tid = get_thread_id (inferior_ptid); | |
463 | ||
464 | iovec.iov_base = ®s; | |
465 | iovec.iov_len = sizeof (regs); | |
466 | ||
467 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
468 | if (ret < 0) | |
469 | perror_with_name (_("Unable to fetch general registers.")); | |
470 | ||
471 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
472 | if (REG_VALID == regcache_register_status (regcache, regno)) | |
473 | regcache_raw_collect (regcache, regno, | |
474 | (char *) ®s[regno - AARCH64_X0_REGNUM]); | |
475 | ||
476 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
477 | if (ret < 0) | |
478 | perror_with_name (_("Unable to store general registers.")); | |
479 | } | |
480 | ||
481 | /* Fill GDB's register array with the fp/simd register values | |
482 | from the current thread. */ | |
483 | ||
484 | static void | |
485 | fetch_fpregs_from_thread (struct regcache *regcache) | |
486 | { | |
487 | int ret, regno, tid; | |
488 | elf_fpregset_t regs; | |
489 | struct iovec iovec; | |
490 | ||
491 | tid = get_thread_id (inferior_ptid); | |
492 | ||
493 | iovec.iov_base = ®s; | |
494 | iovec.iov_len = sizeof (regs); | |
495 | ||
496 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
497 | if (ret < 0) | |
498 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
499 | ||
500 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
501 | regcache_raw_supply (regcache, regno, | |
502 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
503 | ||
504 | regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); | |
505 | regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); | |
506 | } | |
507 | ||
508 | /* Store to the current thread the valid fp/simd register | |
509 | values in the GDB's register array. */ | |
510 | ||
511 | static void | |
512 | store_fpregs_to_thread (const struct regcache *regcache) | |
513 | { | |
514 | int ret, regno, tid; | |
515 | elf_fpregset_t regs; | |
516 | struct iovec iovec; | |
517 | ||
518 | tid = get_thread_id (inferior_ptid); | |
519 | ||
520 | iovec.iov_base = ®s; | |
521 | iovec.iov_len = sizeof (regs); | |
522 | ||
523 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
524 | if (ret < 0) | |
525 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
526 | ||
527 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
528 | if (REG_VALID == regcache_register_status (regcache, regno)) | |
529 | regcache_raw_collect (regcache, regno, | |
530 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
531 | ||
532 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM)) | |
533 | regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); | |
534 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM)) | |
535 | regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); | |
536 | ||
537 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
538 | if (ret < 0) | |
539 | perror_with_name (_("Unable to store FP/SIMD registers.")); | |
540 | } | |
541 | ||
542 | /* Implement the "to_fetch_register" target_ops method. */ | |
543 | ||
544 | static void | |
545 | aarch64_linux_fetch_inferior_registers (struct target_ops *ops, | |
546 | struct regcache *regcache, | |
547 | int regno) | |
548 | { | |
549 | if (regno == -1) | |
550 | { | |
551 | fetch_gregs_from_thread (regcache); | |
552 | fetch_fpregs_from_thread (regcache); | |
553 | } | |
554 | else if (regno < AARCH64_V0_REGNUM) | |
555 | fetch_gregs_from_thread (regcache); | |
556 | else | |
557 | fetch_fpregs_from_thread (regcache); | |
558 | } | |
559 | ||
560 | /* Implement the "to_store_register" target_ops method. */ | |
561 | ||
562 | static void | |
563 | aarch64_linux_store_inferior_registers (struct target_ops *ops, | |
564 | struct regcache *regcache, | |
565 | int regno) | |
566 | { | |
567 | if (regno == -1) | |
568 | { | |
569 | store_gregs_to_thread (regcache); | |
570 | store_fpregs_to_thread (regcache); | |
571 | } | |
572 | else if (regno < AARCH64_V0_REGNUM) | |
573 | store_gregs_to_thread (regcache); | |
574 | else | |
575 | store_fpregs_to_thread (regcache); | |
576 | } | |
577 | ||
578 | /* Fill register REGNO (if it is a general-purpose register) in | |
579 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
580 | do this for all registers. */ | |
581 | ||
582 | void | |
583 | fill_gregset (const struct regcache *regcache, | |
584 | gdb_gregset_t *gregsetp, int regno) | |
585 | { | |
586 | gdb_byte *gregs_buf = (gdb_byte *) gregsetp; | |
587 | int i; | |
588 | ||
589 | for (i = AARCH64_X0_REGNUM; i <= AARCH64_CPSR_REGNUM; i++) | |
590 | if (regno == -1 || regno == i) | |
591 | regcache_raw_collect (regcache, i, | |
592 | gregs_buf + X_REGISTER_SIZE | |
593 | * (i - AARCH64_X0_REGNUM)); | |
594 | } | |
595 | ||
596 | /* Fill GDB's register array with the general-purpose register values | |
597 | in *GREGSETP. */ | |
598 | ||
599 | void | |
600 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
601 | { | |
602 | aarch64_linux_supply_gregset (regcache, (const gdb_byte *) gregsetp); | |
603 | } | |
604 | ||
605 | /* Fill register REGNO (if it is a floating-point register) in | |
606 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
607 | do this for all registers. */ | |
608 | ||
609 | void | |
610 | fill_fpregset (const struct regcache *regcache, | |
611 | gdb_fpregset_t *fpregsetp, int regno) | |
612 | { | |
613 | gdb_byte *fpregs_buf = (gdb_byte *) fpregsetp; | |
614 | int i; | |
615 | ||
616 | for (i = AARCH64_V0_REGNUM; i <= AARCH64_V31_REGNUM; i++) | |
617 | if (regno == -1 || regno == i) | |
618 | regcache_raw_collect (regcache, i, | |
619 | fpregs_buf + V_REGISTER_SIZE | |
620 | * (i - AARCH64_V0_REGNUM)); | |
621 | ||
622 | if (regno == -1 || regno == AARCH64_FPSR_REGNUM) | |
623 | regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, | |
624 | fpregs_buf + V_REGISTER_SIZE * 32); | |
625 | ||
626 | if (regno == -1 || regno == AARCH64_FPCR_REGNUM) | |
627 | regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, | |
628 | fpregs_buf + V_REGISTER_SIZE * 32 + 4); | |
629 | } | |
630 | ||
631 | /* Fill GDB's register array with the floating-point register values | |
632 | in *FPREGSETP. */ | |
633 | ||
634 | void | |
635 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
636 | { | |
637 | aarch64_linux_supply_fpregset (regcache, (const gdb_byte *) fpregsetp); | |
638 | } | |
639 | ||
640 | /* Called when resuming a thread. | |
641 | The hardware debug registers are updated when there is any change. */ | |
642 | ||
643 | static void | |
644 | aarch64_linux_prepare_to_resume (struct lwp_info *lwp) | |
645 | { | |
646 | struct arch_lwp_info *info = lwp->arch_private; | |
647 | ||
648 | /* NULL means this is the main thread still going through the shell, | |
649 | or, no watchpoint has been set yet. In that case, there's | |
650 | nothing to do. */ | |
651 | if (info == NULL) | |
652 | return; | |
653 | ||
654 | if (DR_HAS_CHANGED (info->dr_changed_bp) | |
655 | || DR_HAS_CHANGED (info->dr_changed_wp)) | |
656 | { | |
657 | int tid = GET_LWP (lwp->ptid); | |
658 | struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state (); | |
659 | ||
660 | if (debug_hw_points) | |
661 | fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid); | |
662 | ||
663 | /* Watchpoints. */ | |
664 | if (DR_HAS_CHANGED (info->dr_changed_wp)) | |
665 | { | |
666 | aarch64_linux_set_debug_regs (state, tid, 1); | |
667 | DR_CLEAR_CHANGED (info->dr_changed_wp); | |
668 | } | |
669 | ||
670 | /* Breakpoints. */ | |
671 | if (DR_HAS_CHANGED (info->dr_changed_bp)) | |
672 | { | |
673 | aarch64_linux_set_debug_regs (state, tid, 0); | |
674 | DR_CLEAR_CHANGED (info->dr_changed_bp); | |
675 | } | |
676 | } | |
677 | } | |
678 | ||
679 | static void | |
680 | aarch64_linux_new_thread (struct lwp_info *lp) | |
681 | { | |
682 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
683 | ||
684 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
685 | for this thread need to be initialized. */ | |
686 | DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); | |
687 | DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); | |
688 | ||
689 | lp->arch_private = info; | |
690 | } | |
691 | \f | |
692 | ||
693 | /* Called by libthread_db. Returns a pointer to the thread local | |
694 | storage (or its descriptor). */ | |
695 | ||
696 | ps_err_e | |
697 | ps_get_thread_area (const struct ps_prochandle *ph, | |
698 | lwpid_t lwpid, int idx, void **base) | |
699 | { | |
700 | struct iovec iovec; | |
701 | uint64_t reg; | |
702 | ||
703 | iovec.iov_base = ® | |
704 | iovec.iov_len = sizeof (reg); | |
705 | ||
706 | if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) | |
707 | return PS_ERR; | |
708 | ||
709 | /* IDX is the bias from the thread pointer to the beginning of the | |
710 | thread descriptor. It has to be subtracted due to implementation | |
711 | quirks in libthread_db. */ | |
712 | *base = (void *) (reg - idx); | |
713 | ||
714 | return PS_OK; | |
715 | } | |
716 | \f | |
717 | ||
718 | /* Get the hardware debug register capacity information. */ | |
719 | ||
720 | static void | |
721 | aarch64_linux_get_debug_reg_capacity (void) | |
722 | { | |
723 | int tid; | |
724 | struct iovec iov; | |
725 | struct user_hwdebug_state dreg_state; | |
726 | ||
727 | tid = get_thread_id (inferior_ptid); | |
728 | iov.iov_base = &dreg_state; | |
729 | iov.iov_len = sizeof (dreg_state); | |
730 | ||
731 | /* Get hardware watchpoint register info. */ | |
732 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0 | |
733 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
734 | { | |
735 | aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
736 | if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) | |
737 | { | |
1d3ffd6b MS |
738 | warning (_("Unexpected number of hardware watchpoint registers" |
739 | " reported by ptrace, got %d, expected %d."), | |
9d19df75 MS |
740 | aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); |
741 | aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; | |
742 | } | |
743 | } | |
744 | else | |
745 | { | |
1d3ffd6b MS |
746 | warning (_("Unable to determine the number of hardware watchpoints" |
747 | " available.")); | |
9d19df75 MS |
748 | aarch64_num_wp_regs = 0; |
749 | } | |
750 | ||
751 | /* Get hardware breakpoint register info. */ | |
752 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0 | |
753 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
754 | { | |
755 | aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
756 | if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) | |
757 | { | |
1d3ffd6b MS |
758 | warning (_("Unexpected number of hardware breakpoint registers" |
759 | " reported by ptrace, got %d, expected %d."), | |
9d19df75 MS |
760 | aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); |
761 | aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; | |
762 | } | |
763 | } | |
764 | else | |
765 | { | |
1d3ffd6b MS |
766 | warning (_("Unable to determine the number of hardware breakpoints" |
767 | " available.")); | |
9d19df75 MS |
768 | aarch64_num_bp_regs = 0; |
769 | } | |
770 | } | |
771 | ||
772 | static void (*super_post_startup_inferior) (ptid_t ptid); | |
773 | ||
774 | /* Implement the "to_post_startup_inferior" target_ops method. */ | |
775 | ||
776 | static void | |
777 | aarch64_linux_child_post_startup_inferior (ptid_t ptid) | |
778 | { | |
779 | struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state (); | |
780 | ||
781 | aarch64_init_debug_reg_state (state); | |
782 | aarch64_linux_get_debug_reg_capacity (); | |
783 | super_post_startup_inferior (ptid); | |
784 | } | |
785 | ||
786 | /* Implement the "to_read_description" target_ops method. */ | |
787 | ||
788 | static const struct target_desc * | |
789 | aarch64_linux_read_description (struct target_ops *ops) | |
790 | { | |
791 | initialize_tdesc_aarch64 (); | |
792 | return tdesc_aarch64; | |
793 | } | |
794 | ||
795 | /* Given the (potentially unaligned) watchpoint address in ADDR and | |
796 | length in LEN, return the aligned address and aligned length in | |
797 | *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned | |
798 | aligned address and length will be valid values to write to the | |
799 | hardware watchpoint value and control registers. | |
800 | ||
801 | The given watchpoint may get truncated if more than one hardware | |
802 | register is needed to cover the watched region. *NEXT_ADDR_P | |
803 | and *NEXT_LEN_P, if non-NULL, will return the address and length | |
804 | of the remaining part of the watchpoint (which can be processed | |
805 | by calling this routine again to generate another aligned address | |
806 | and length pair. | |
807 | ||
808 | See the comment above the function of the same name in | |
809 | gdbserver/linux-aarch64-low.c for more information. */ | |
810 | ||
811 | static void | |
812 | aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, | |
813 | int *aligned_len_p, CORE_ADDR *next_addr_p, | |
814 | int *next_len_p) | |
815 | { | |
816 | int aligned_len; | |
817 | unsigned int offset; | |
818 | CORE_ADDR aligned_addr; | |
819 | const unsigned int alignment = AARCH64_HWP_ALIGNMENT; | |
820 | const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; | |
821 | ||
822 | /* As assumed by the algorithm. */ | |
823 | gdb_assert (alignment == max_wp_len); | |
824 | ||
825 | if (len <= 0) | |
826 | return; | |
827 | ||
828 | /* Address to be put into the hardware watchpoint value register | |
829 | must be aligned. */ | |
830 | offset = addr & (alignment - 1); | |
831 | aligned_addr = addr - offset; | |
832 | ||
833 | gdb_assert (offset >= 0 && offset < alignment); | |
834 | gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); | |
835 | gdb_assert (offset + len > 0); | |
836 | ||
837 | if (offset + len >= max_wp_len) | |
838 | { | |
839 | /* Need more than one watchpoint registers; truncate it at the | |
840 | alignment boundary. */ | |
841 | aligned_len = max_wp_len; | |
842 | len -= (max_wp_len - offset); | |
843 | addr += (max_wp_len - offset); | |
844 | gdb_assert ((addr & (alignment - 1)) == 0); | |
845 | } | |
846 | else | |
847 | { | |
848 | /* Find the smallest valid length that is large enough to | |
849 | accommodate this watchpoint. */ | |
850 | static const unsigned char | |
851 | aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = | |
852 | { 1, 2, 4, 4, 8, 8, 8, 8 }; | |
853 | ||
854 | aligned_len = aligned_len_array[offset + len - 1]; | |
855 | addr += len; | |
856 | len = 0; | |
857 | } | |
858 | ||
859 | if (aligned_addr_p) | |
860 | *aligned_addr_p = aligned_addr; | |
861 | if (aligned_len_p) | |
862 | *aligned_len_p = aligned_len; | |
863 | if (next_addr_p) | |
864 | *next_addr_p = addr; | |
865 | if (next_len_p) | |
866 | *next_len_p = len; | |
867 | } | |
868 | ||
869 | /* Returns the number of hardware watchpoints of type TYPE that we can | |
870 | set. Value is positive if we can set CNT watchpoints, zero if | |
871 | setting watchpoints of type TYPE is not supported, and negative if | |
872 | CNT is more than the maximum number of watchpoints of type TYPE | |
873 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
874 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
875 | CNT is the number of such watchpoints used so far (including this | |
876 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
877 | currently enabled. | |
878 | ||
879 | We always return 1 here because we don't have enough information | |
880 | about possible overlap of addresses that they want to watch. As an | |
881 | extreme example, consider the case where all the watchpoints watch | |
882 | the same address and the same region length: then we can handle a | |
883 | virtually unlimited number of watchpoints, due to debug register | |
884 | sharing implemented via reference counts. */ | |
885 | ||
886 | static int | |
887 | aarch64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
888 | { | |
889 | return 1; | |
890 | } | |
891 | ||
892 | /* ptrace expects control registers to be formatted as follows: | |
893 | ||
894 | 31 13 5 3 1 0 | |
895 | +--------------------------------+----------+------+------+----+ | |
896 | | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | | |
897 | +--------------------------------+----------+------+------+----+ | |
898 | ||
899 | The TYPE field is ignored for breakpoints. */ | |
900 | ||
901 | #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) | |
902 | #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) | |
903 | ||
904 | /* Utility function that returns the length in bytes of a watchpoint | |
905 | according to the content of a hardware debug control register CTRL. | |
906 | Note that the kernel currently only supports the following Byte | |
907 | Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means | |
908 | that for a hardware watchpoint, its valid length can only be 1 | |
909 | byte, 2 bytes, 4 bytes or 8 bytes. */ | |
910 | ||
911 | static inline unsigned int | |
912 | aarch64_watchpoint_length (unsigned int ctrl) | |
913 | { | |
914 | switch (DR_CONTROL_LENGTH (ctrl)) | |
915 | { | |
916 | case 0x01: | |
917 | return 1; | |
918 | case 0x03: | |
919 | return 2; | |
920 | case 0x0f: | |
921 | return 4; | |
922 | case 0xff: | |
923 | return 8; | |
924 | default: | |
925 | return 0; | |
926 | } | |
927 | } | |
928 | ||
929 | /* Given the hardware breakpoint or watchpoint type TYPE and its | |
930 | length LEN, return the expected encoding for a hardware | |
931 | breakpoint/watchpoint control register. */ | |
932 | ||
933 | static unsigned int | |
934 | aarch64_point_encode_ctrl_reg (int type, int len) | |
935 | { | |
936 | unsigned int ctrl, ttype; | |
937 | ||
938 | /* type */ | |
939 | switch (type) | |
940 | { | |
941 | case hw_write: | |
942 | ttype = 2; | |
943 | break; | |
944 | case hw_read: | |
945 | ttype = 1; | |
946 | break; | |
947 | case hw_access: | |
948 | ttype = 3; | |
949 | break; | |
950 | case hw_execute: | |
951 | ttype = 0; | |
952 | break; | |
953 | default: | |
954 | perror_with_name (_("Unrecognized breakpoint/watchpoint type")); | |
955 | } | |
956 | ctrl = ttype << 3; | |
957 | ||
958 | /* length bitmask */ | |
959 | ctrl |= ((1 << len) - 1) << 5; | |
960 | /* enabled at el0 */ | |
961 | ctrl |= (2 << 1) | 1; | |
962 | ||
963 | return ctrl; | |
964 | } | |
965 | ||
966 | /* Addresses to be written to the hardware breakpoint and watchpoint | |
967 | value registers need to be aligned; the alignment is 4-byte and | |
968 | 8-type respectively. Linux kernel rejects any non-aligned address | |
969 | it receives from the related ptrace call. Furthermore, the kernel | |
970 | currently only supports the following Byte Address Select (BAS) | |
971 | values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware | |
972 | watchpoint to be accepted by the kernel (via ptrace call), its | |
973 | valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. | |
974 | Despite these limitations, the unaligned watchpoint is supported in | |
975 | this port. | |
976 | ||
977 | Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ | |
978 | ||
979 | static int | |
980 | aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) | |
981 | { | |
982 | unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT | |
983 | : AARCH64_HBP_ALIGNMENT; | |
984 | ||
985 | if (addr & (alignment - 1)) | |
986 | return 0; | |
987 | ||
988 | if (len != 8 && len != 4 && len != 2 && len != 1) | |
989 | return 0; | |
990 | ||
991 | return 1; | |
992 | } | |
993 | ||
994 | /* Record the insertion of one breakpoint/watchpoint, as represented | |
995 | by ADDR and CTRL, in the cached debug register state area *STATE. */ | |
996 | ||
997 | static int | |
998 | aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, | |
999 | int type, CORE_ADDR addr, int len) | |
1000 | { | |
1001 | int i, idx, num_regs, is_watchpoint; | |
1002 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
1003 | CORE_ADDR *dr_addr_p; | |
1004 | ||
1005 | /* Set up state pointers. */ | |
1006 | is_watchpoint = (type != hw_execute); | |
1007 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
1008 | if (is_watchpoint) | |
1009 | { | |
1010 | num_regs = aarch64_num_wp_regs; | |
1011 | dr_addr_p = state->dr_addr_wp; | |
1012 | dr_ctrl_p = state->dr_ctrl_wp; | |
1013 | dr_ref_count = state->dr_ref_count_wp; | |
1014 | } | |
1015 | else | |
1016 | { | |
1017 | num_regs = aarch64_num_bp_regs; | |
1018 | dr_addr_p = state->dr_addr_bp; | |
1019 | dr_ctrl_p = state->dr_ctrl_bp; | |
1020 | dr_ref_count = state->dr_ref_count_bp; | |
1021 | } | |
1022 | ||
1023 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
1024 | ||
1025 | /* Find an existing or free register in our cache. */ | |
1026 | idx = -1; | |
1027 | for (i = 0; i < num_regs; ++i) | |
1028 | { | |
1029 | if ((dr_ctrl_p[i] & 1) == 0) | |
1030 | { | |
1031 | gdb_assert (dr_ref_count[i] == 0); | |
1032 | idx = i; | |
1033 | /* no break; continue hunting for an existing one. */ | |
1034 | } | |
1035 | else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
1036 | { | |
1037 | gdb_assert (dr_ref_count[i] != 0); | |
1038 | idx = i; | |
1039 | break; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* No space. */ | |
1044 | if (idx == -1) | |
1045 | return -1; | |
1046 | ||
1047 | /* Update our cache. */ | |
1048 | if ((dr_ctrl_p[idx] & 1) == 0) | |
1049 | { | |
1050 | /* new entry */ | |
1051 | dr_addr_p[idx] = addr; | |
1052 | dr_ctrl_p[idx] = ctrl; | |
1053 | dr_ref_count[idx] = 1; | |
1054 | /* Notify the change. */ | |
1055 | aarch64_notify_debug_reg_change (state, is_watchpoint, idx); | |
1056 | } | |
1057 | else | |
1058 | { | |
1059 | /* existing entry */ | |
1060 | dr_ref_count[idx]++; | |
1061 | } | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | /* Record the removal of one breakpoint/watchpoint, as represented by | |
1067 | ADDR and CTRL, in the cached debug register state area *STATE. */ | |
1068 | ||
1069 | static int | |
1070 | aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, | |
1071 | int type, CORE_ADDR addr, int len) | |
1072 | { | |
1073 | int i, num_regs, is_watchpoint; | |
1074 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
1075 | CORE_ADDR *dr_addr_p; | |
1076 | ||
1077 | /* Set up state pointers. */ | |
1078 | is_watchpoint = (type != hw_execute); | |
1079 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
1080 | if (is_watchpoint) | |
1081 | { | |
1082 | num_regs = aarch64_num_wp_regs; | |
1083 | dr_addr_p = state->dr_addr_wp; | |
1084 | dr_ctrl_p = state->dr_ctrl_wp; | |
1085 | dr_ref_count = state->dr_ref_count_wp; | |
1086 | } | |
1087 | else | |
1088 | { | |
1089 | num_regs = aarch64_num_bp_regs; | |
1090 | dr_addr_p = state->dr_addr_bp; | |
1091 | dr_ctrl_p = state->dr_ctrl_bp; | |
1092 | dr_ref_count = state->dr_ref_count_bp; | |
1093 | } | |
1094 | ||
1095 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
1096 | ||
1097 | /* Find the entry that matches the ADDR and CTRL. */ | |
1098 | for (i = 0; i < num_regs; ++i) | |
1099 | if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
1100 | { | |
1101 | gdb_assert (dr_ref_count[i] != 0); | |
1102 | break; | |
1103 | } | |
1104 | ||
1105 | /* Not found. */ | |
1106 | if (i == num_regs) | |
1107 | return -1; | |
1108 | ||
1109 | /* Clear our cache. */ | |
1110 | if (--dr_ref_count[i] == 0) | |
1111 | { | |
1112 | /* Clear the enable bit. */ | |
1113 | ctrl &= ~1; | |
1114 | dr_addr_p[i] = 0; | |
1115 | dr_ctrl_p[i] = ctrl; | |
1116 | /* Notify the change. */ | |
1117 | aarch64_notify_debug_reg_change (state, is_watchpoint, i); | |
1118 | } | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | /* Implement insertion and removal of a single breakpoint. */ | |
1124 | ||
1125 | static int | |
1126 | aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert) | |
1127 | { | |
1128 | struct aarch64_debug_reg_state *state; | |
1129 | ||
1130 | /* The hardware breakpoint on AArch64 should always be 4-byte | |
1131 | aligned. */ | |
1132 | if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) | |
1133 | return -1; | |
1134 | ||
1135 | state = aarch64_get_debug_reg_state (); | |
1136 | ||
1137 | if (is_insert) | |
1138 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
1139 | else | |
1140 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
1141 | } | |
1142 | ||
1143 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. | |
1144 | Return 0 on success, -1 on failure. */ | |
1145 | ||
1146 | static int | |
1147 | aarch64_linux_insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1148 | struct bp_target_info *bp_tgt) | |
1149 | { | |
1150 | int ret; | |
1151 | CORE_ADDR addr = bp_tgt->placed_address; | |
1152 | const int len = 4; | |
1153 | const int type = hw_execute; | |
1154 | ||
1155 | if (debug_hw_points) | |
1156 | fprintf_unfiltered | |
1157 | (gdb_stdlog, | |
1158 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
1159 | (unsigned long) addr, len); | |
1160 | ||
1161 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */); | |
1162 | ||
1163 | if (debug_hw_points > 1) | |
1164 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), | |
1165 | "insert_hw_watchpoint", addr, len, type); | |
1166 | ||
1167 | return ret; | |
1168 | } | |
1169 | ||
1170 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. | |
1171 | Return 0 on success, -1 on failure. */ | |
1172 | ||
1173 | static int | |
1174 | aarch64_linux_remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1175 | struct bp_target_info *bp_tgt) | |
1176 | { | |
1177 | int ret; | |
1178 | CORE_ADDR addr = bp_tgt->placed_address; | |
1179 | const int len = 4; | |
1180 | const int type = hw_execute; | |
1181 | ||
1182 | if (debug_hw_points) | |
1183 | fprintf_unfiltered | |
1184 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
1185 | (unsigned long) addr, len); | |
1186 | ||
1187 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */); | |
1188 | ||
1189 | if (debug_hw_points > 1) | |
1190 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), | |
1191 | "remove_hw_watchpoint", addr, len, type); | |
1192 | ||
1193 | return ret; | |
1194 | } | |
1195 | ||
1196 | /* This is essentially the same as aarch64_handle_breakpoint, apart | |
1197 | from that it is an aligned watchpoint to be handled. */ | |
1198 | ||
1199 | static int | |
1200 | aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len, | |
1201 | int is_insert) | |
1202 | { | |
1203 | struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state (); | |
1204 | ||
1205 | if (is_insert) | |
1206 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
1207 | else | |
1208 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
1209 | } | |
1210 | ||
1211 | /* Insert/remove unaligned watchpoint by calling | |
1212 | aarch64_align_watchpoint repeatedly until the whole watched region, | |
1213 | as represented by ADDR and LEN, has been properly aligned and ready | |
1214 | to be written to one or more hardware watchpoint registers. | |
1215 | IS_INSERT indicates whether this is an insertion or a deletion. | |
1216 | Return 0 if succeed. */ | |
1217 | ||
1218 | static int | |
1219 | aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len, | |
1220 | int is_insert) | |
1221 | { | |
1222 | struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state (); | |
1223 | ||
1224 | while (len > 0) | |
1225 | { | |
1226 | CORE_ADDR aligned_addr; | |
1227 | int aligned_len, ret; | |
1228 | ||
1229 | aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, | |
1230 | &addr, &len); | |
1231 | ||
1232 | if (is_insert) | |
1233 | ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, | |
1234 | aligned_len); | |
1235 | else | |
1236 | ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, | |
1237 | aligned_len); | |
1238 | ||
1239 | if (debug_hw_points) | |
1240 | fprintf_unfiltered (gdb_stdlog, | |
1241 | "handle_unaligned_watchpoint: is_insert: %d\n" | |
1242 | " aligned_addr: 0x%08lx, aligned_len: %d\n" | |
1243 | " next_addr: 0x%08lx, next_len: %d\n", | |
1244 | is_insert, aligned_addr, aligned_len, addr, len); | |
1245 | ||
1246 | if (ret != 0) | |
1247 | return ret; | |
1248 | } | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | /* Implements insertion and removal of a single watchpoint. */ | |
1254 | ||
1255 | static int | |
1256 | aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert) | |
1257 | { | |
1258 | if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) | |
1259 | return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert); | |
1260 | else | |
1261 | return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert); | |
1262 | } | |
1263 | ||
1264 | /* Implement the "to_insert_watchpoint" target_ops method. | |
1265 | ||
1266 | Insert a watchpoint to watch a memory region which starts at | |
1267 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
1268 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
1269 | ||
1270 | static int | |
1271 | aarch64_linux_insert_watchpoint (CORE_ADDR addr, int len, int type, | |
1272 | struct expression *cond) | |
1273 | { | |
1274 | int ret; | |
1275 | ||
1276 | if (debug_hw_points) | |
1277 | fprintf_unfiltered (gdb_stdlog, | |
1278 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
1279 | (unsigned long) addr, len); | |
1280 | ||
1281 | gdb_assert (type != hw_execute); | |
1282 | ||
1283 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */); | |
1284 | ||
1285 | if (debug_hw_points > 1) | |
1286 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), | |
1287 | "insert_watchpoint", addr, len, type); | |
1288 | ||
1289 | return ret; | |
1290 | } | |
1291 | ||
1292 | /* Implement the "to_remove_watchpoint" target_ops method. | |
1293 | Remove a watchpoint that watched the memory region which starts at | |
1294 | address ADDR, whose length is LEN bytes, and for accesses of the | |
1295 | type TYPE. Return 0 on success, -1 on failure. */ | |
1296 | ||
1297 | static int | |
1298 | aarch64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type, | |
1299 | struct expression *cond) | |
1300 | { | |
1301 | int ret; | |
1302 | ||
1303 | if (debug_hw_points) | |
1304 | fprintf_unfiltered (gdb_stdlog, | |
1305 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
1306 | (unsigned long) addr, len); | |
1307 | ||
1308 | gdb_assert (type != hw_execute); | |
1309 | ||
1310 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */); | |
1311 | ||
1312 | if (debug_hw_points > 1) | |
1313 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), | |
1314 | "remove_watchpoint", addr, len, type); | |
1315 | ||
1316 | return ret; | |
1317 | } | |
1318 | ||
1319 | /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */ | |
1320 | ||
1321 | static int | |
1322 | aarch64_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
1323 | { | |
1324 | CORE_ADDR aligned_addr; | |
1325 | ||
1326 | /* Can not set watchpoints for zero or negative lengths. */ | |
1327 | if (len <= 0) | |
1328 | return 0; | |
1329 | ||
1330 | /* Must have hardware watchpoint debug register(s). */ | |
1331 | if (aarch64_num_wp_regs == 0) | |
1332 | return 0; | |
1333 | ||
1334 | /* We support unaligned watchpoint address and arbitrary length, | |
1335 | as long as the size of the whole watched area after alignment | |
1336 | doesn't exceed size of the total area that all watchpoint debug | |
1337 | registers can watch cooperatively. | |
1338 | ||
1339 | This is a very relaxed rule, but unfortunately there are | |
1340 | limitations, e.g. false-positive hits, due to limited support of | |
1341 | hardware debug registers in the kernel. See comment above | |
1342 | aarch64_align_watchpoint for more information. */ | |
1343 | ||
1344 | aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1); | |
1345 | if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG | |
1346 | < addr + len) | |
1347 | return 0; | |
1348 | ||
1349 | /* All tests passed so we are likely to be able to set the watchpoint. | |
1350 | The reason that it is 'likely' rather than 'must' is because | |
1351 | we don't check the current usage of the watchpoint registers, and | |
1352 | there may not be enough registers available for this watchpoint. | |
1353 | Ideally we should check the cached debug register state, however | |
1354 | the checking is costly. */ | |
1355 | return 1; | |
1356 | } | |
1357 | ||
1358 | /* Implement the "to_stopped_data_address" target_ops method. */ | |
1359 | ||
1360 | static int | |
1361 | aarch64_linux_stopped_data_address (struct target_ops *target, | |
1362 | CORE_ADDR *addr_p) | |
1363 | { | |
1364 | siginfo_t siginfo; | |
1365 | int i, tid; | |
1366 | struct aarch64_debug_reg_state *state; | |
1367 | ||
1368 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1369 | return 0; | |
1370 | ||
1371 | /* This must be a hardware breakpoint. */ | |
1372 | if (siginfo.si_signo != SIGTRAP | |
1373 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
1374 | return 0; | |
1375 | ||
1376 | /* Check if the address matches any watched address. */ | |
1377 | state = aarch64_get_debug_reg_state (); | |
1378 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) | |
1379 | { | |
1380 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); | |
1381 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
1382 | const CORE_ADDR addr_watch = state->dr_addr_wp[i]; | |
1383 | ||
1384 | if (state->dr_ref_count_wp[i] | |
1385 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
1386 | && addr_trap >= addr_watch | |
1387 | && addr_trap < addr_watch + len) | |
1388 | { | |
1389 | *addr_p = addr_trap; | |
1390 | return 1; | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | /* Implement the "to_stopped_by_watchpoint" target_ops method. */ | |
1398 | ||
1399 | static int | |
1400 | aarch64_linux_stopped_by_watchpoint (void) | |
1401 | { | |
1402 | CORE_ADDR addr; | |
1403 | ||
1404 | return aarch64_linux_stopped_data_address (¤t_target, &addr); | |
1405 | } | |
1406 | ||
1407 | /* Implement the "to_watchpoint_addr_within_range" target_ops method. */ | |
1408 | ||
1409 | static int | |
1410 | aarch64_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1411 | CORE_ADDR addr, | |
1412 | CORE_ADDR start, int length) | |
1413 | { | |
1414 | return start <= addr && start + length - 1 >= addr; | |
1415 | } | |
1416 | ||
1417 | /* Define AArch64 maintenance commands. */ | |
1418 | ||
1419 | static void | |
1420 | add_show_debug_regs_command (void) | |
1421 | { | |
1422 | /* A maintenance command to enable printing the internal DRi mirror | |
1423 | variables. */ | |
1424 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
1425 | &debug_hw_points, _("\ | |
1426 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ | |
1427 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ | |
1428 | Use \"on\" to enable, \"off\" to disable.\n\ | |
1429 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
1430 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
1431 | triggers a breakpoint or watchpoint."), | |
1432 | NULL, | |
1433 | NULL, | |
1434 | &maintenance_set_cmdlist, | |
1435 | &maintenance_show_cmdlist); | |
1436 | } | |
1437 | ||
1438 | /* -Wmissing-prototypes. */ | |
1439 | void _initialize_aarch64_linux_nat (void); | |
1440 | ||
1441 | void | |
1442 | _initialize_aarch64_linux_nat (void) | |
1443 | { | |
1444 | struct target_ops *t; | |
1445 | ||
1446 | /* Fill in the generic GNU/Linux methods. */ | |
1447 | t = linux_target (); | |
1448 | ||
1449 | add_show_debug_regs_command (); | |
1450 | ||
1451 | /* Add our register access methods. */ | |
1452 | t->to_fetch_registers = aarch64_linux_fetch_inferior_registers; | |
1453 | t->to_store_registers = aarch64_linux_store_inferior_registers; | |
1454 | ||
1455 | t->to_read_description = aarch64_linux_read_description; | |
1456 | ||
1457 | t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint; | |
1458 | t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint; | |
1459 | t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint; | |
1460 | t->to_region_ok_for_hw_watchpoint = | |
1461 | aarch64_linux_region_ok_for_hw_watchpoint; | |
1462 | t->to_insert_watchpoint = aarch64_linux_insert_watchpoint; | |
1463 | t->to_remove_watchpoint = aarch64_linux_remove_watchpoint; | |
1464 | t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint; | |
1465 | t->to_stopped_data_address = aarch64_linux_stopped_data_address; | |
1466 | t->to_watchpoint_addr_within_range = | |
1467 | aarch64_linux_watchpoint_addr_within_range; | |
1468 | if (aarch64_inferior_data == NULL) | |
1469 | aarch64_inferior_data | |
1470 | = register_inferior_data_with_cleanup (NULL, | |
1471 | aarch64_inferior_data_cleanup); | |
1472 | ||
1473 | /* Override the GNU/Linux inferior startup hook. */ | |
1474 | super_post_startup_inferior = t->to_post_startup_inferior; | |
1475 | t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior; | |
1476 | ||
1477 | /* Register the target. */ | |
1478 | linux_nat_add_target (t); | |
1479 | linux_nat_set_new_thread (t, aarch64_linux_new_thread); | |
1480 | linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume); | |
1481 | } |