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gdb: Don't reorder line table entries too much when sorting.
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
b811d2c2 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
07b287a0
MS		 24#include "gdbcmd.h"
25#include "gdbcore.h"
4de283e4 26#include "dis-asm.h"
d55e5aa6
TT		 27#include "regcache.h"
28#include "reggroups.h"
4de283e4
TT		 29#include "value.h"
30#include "arch-utils.h"
31#include "osabi.h"
32#include "frame-unwind.h"
33#include "frame-base.h"
d55e5aa6 34#include "trad-frame.h"
4de283e4
TT		 35#include "objfiles.h"
36#include "dwarf2.h"
37#include "dwarf2-frame.h"
38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
07b287a0 41#include "user-regs.h"
4de283e4 42#include "ax-gdb.h"
268a13a5 43#include "gdbsupport/selftest.h"
4de283e4
TT		 44
45#include "aarch64-tdep.h"
46#include "aarch64-ravenscar-thread.h"
47
4de283e4
TT		 48#include "record.h"
49#include "record-full.h"
50#include "arch/aarch64-insn.h"
0d12e84c 51#include "gdbarch.h"
4de283e4
TT		 52
53#include "opcode/aarch64.h"
54#include <algorithm>
f77ee802
YQ		 55
56#define submask(x) ((1L << ((x) + 1)) - 1)
57#define bit(obj,st) (((obj) >> (st)) & 1)
58#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
59
ea92689a
AH		 60/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
61 four members. */
62#define HA_MAX_NUM_FLDS 4
63
95228a0d 64/* All possible aarch64 target descriptors. */
6dc0ebde 65struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/];
95228a0d 66
07b287a0
MS		 67/* The standard register names, and all the valid aliases for them. */
68static const struct
69{
70 const char *const name;
71 int regnum;
72} aarch64_register_aliases[] =
73{
74 /* 64-bit register names. */
75 {"fp", AARCH64_FP_REGNUM},
76 {"lr", AARCH64_LR_REGNUM},
77 {"sp", AARCH64_SP_REGNUM},
78
79 /* 32-bit register names. */
80 {"w0", AARCH64_X0_REGNUM + 0},
81 {"w1", AARCH64_X0_REGNUM + 1},
82 {"w2", AARCH64_X0_REGNUM + 2},
83 {"w3", AARCH64_X0_REGNUM + 3},
84 {"w4", AARCH64_X0_REGNUM + 4},
85 {"w5", AARCH64_X0_REGNUM + 5},
86 {"w6", AARCH64_X0_REGNUM + 6},
87 {"w7", AARCH64_X0_REGNUM + 7},
88 {"w8", AARCH64_X0_REGNUM + 8},
89 {"w9", AARCH64_X0_REGNUM + 9},
90 {"w10", AARCH64_X0_REGNUM + 10},
91 {"w11", AARCH64_X0_REGNUM + 11},
92 {"w12", AARCH64_X0_REGNUM + 12},
93 {"w13", AARCH64_X0_REGNUM + 13},
94 {"w14", AARCH64_X0_REGNUM + 14},
95 {"w15", AARCH64_X0_REGNUM + 15},
96 {"w16", AARCH64_X0_REGNUM + 16},
97 {"w17", AARCH64_X0_REGNUM + 17},
98 {"w18", AARCH64_X0_REGNUM + 18},
99 {"w19", AARCH64_X0_REGNUM + 19},
100 {"w20", AARCH64_X0_REGNUM + 20},
101 {"w21", AARCH64_X0_REGNUM + 21},
102 {"w22", AARCH64_X0_REGNUM + 22},
103 {"w23", AARCH64_X0_REGNUM + 23},
104 {"w24", AARCH64_X0_REGNUM + 24},
105 {"w25", AARCH64_X0_REGNUM + 25},
106 {"w26", AARCH64_X0_REGNUM + 26},
107 {"w27", AARCH64_X0_REGNUM + 27},
108 {"w28", AARCH64_X0_REGNUM + 28},
109 {"w29", AARCH64_X0_REGNUM + 29},
110 {"w30", AARCH64_X0_REGNUM + 30},
111
112 /* specials */
113 {"ip0", AARCH64_X0_REGNUM + 16},
114 {"ip1", AARCH64_X0_REGNUM + 17}
115};
116
117/* The required core 'R' registers. */
118static const char *const aarch64_r_register_names[] =
119{
120 /* These registers must appear in consecutive RAW register number
121 order and they must begin with AARCH64_X0_REGNUM! */
122 "x0", "x1", "x2", "x3",
123 "x4", "x5", "x6", "x7",
124 "x8", "x9", "x10", "x11",
125 "x12", "x13", "x14", "x15",
126 "x16", "x17", "x18", "x19",
127 "x20", "x21", "x22", "x23",
128 "x24", "x25", "x26", "x27",
129 "x28", "x29", "x30", "sp",
130 "pc", "cpsr"
131};
132
133/* The FP/SIMD 'V' registers. */
134static const char *const aarch64_v_register_names[] =
135{
136 /* These registers must appear in consecutive RAW register number
137 order and they must begin with AARCH64_V0_REGNUM! */
138 "v0", "v1", "v2", "v3",
139 "v4", "v5", "v6", "v7",
140 "v8", "v9", "v10", "v11",
141 "v12", "v13", "v14", "v15",
142 "v16", "v17", "v18", "v19",
143 "v20", "v21", "v22", "v23",
144 "v24", "v25", "v26", "v27",
145 "v28", "v29", "v30", "v31",
146 "fpsr",
147 "fpcr"
148};
149
739e8682
AH		 150/* The SVE 'Z' and 'P' registers. */
151static const char *const aarch64_sve_register_names[] =
152{
153 /* These registers must appear in consecutive RAW register number
154 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
155 "z0", "z1", "z2", "z3",
156 "z4", "z5", "z6", "z7",
157 "z8", "z9", "z10", "z11",
158 "z12", "z13", "z14", "z15",
159 "z16", "z17", "z18", "z19",
160 "z20", "z21", "z22", "z23",
161 "z24", "z25", "z26", "z27",
162 "z28", "z29", "z30", "z31",
163 "fpsr", "fpcr",
164 "p0", "p1", "p2", "p3",
165 "p4", "p5", "p6", "p7",
166 "p8", "p9", "p10", "p11",
167 "p12", "p13", "p14", "p15",
168 "ffr", "vg"
169};
170
76bed0fd
AH		 171static const char *const aarch64_pauth_register_names[] =
172{
173 /* Authentication mask for data pointer. */
174 "pauth_dmask",
175 /* Authentication mask for code pointer. */
176 "pauth_cmask"
177};
178
07b287a0
MS		 179/* AArch64 prologue cache structure. */
180struct aarch64_prologue_cache
181{
db634143
PL		 182 /* The program counter at the start of the function. It is used to
183 identify this frame as a prologue frame. */
184 CORE_ADDR func;
185
186 /* The program counter at the time this frame was created; i.e. where
187 this function was called from. It is used to identify this frame as a
188 stub frame. */
189 CORE_ADDR prev_pc;
190
07b287a0
MS		 191 /* The stack pointer at the time this frame was created; i.e. the
192 caller's stack pointer when this function was called. It is used
193 to identify this frame. */
194 CORE_ADDR prev_sp;
195
7dfa3edc
PL		 196 /* Is the target available to read from? */
197 int available_p;
198
07b287a0
MS		 199 /* The frame base for this frame is just prev_sp - frame size.
200 FRAMESIZE is the distance from the frame pointer to the
201 initial stack pointer. */
202 int framesize;
203
204 /* The register used to hold the frame pointer for this frame. */
205 int framereg;
206
207 /* Saved register offsets. */
208 struct trad_frame_saved_reg *saved_regs;
209};
210
07b287a0
MS		 211static void
212show_aarch64_debug (struct ui_file *file, int from_tty,
213 struct cmd_list_element *c, const char *value)
214{
215 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
216}
217
ffdbe864
YQ		 218namespace {
219
4d9a9006
YQ		 220/* Abstract instruction reader. */
221
222class abstract_instruction_reader
223{
224public:
225 /* Read in one instruction. */
226 virtual ULONGEST read (CORE_ADDR memaddr, int len,
227 enum bfd_endian byte_order) = 0;
228};
229
230/* Instruction reader from real target. */
231
232class instruction_reader : public abstract_instruction_reader
233{
234 public:
235 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 236 override
4d9a9006 237 {
fc2f703e 238 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 239 }
240};
241
ffdbe864
YQ		 242} // namespace
243
3d31bc39
AH		 244/* If address signing is enabled, mask off the signature bits from the link
245 register, which is passed by value in ADDR, using the register values in
246 THIS_FRAME. */
11e1b75f
AH		 247
248static CORE_ADDR
3d31bc39
AH		 249aarch64_frame_unmask_lr (struct gdbarch_tdep *tdep,
250 struct frame_info *this_frame, CORE_ADDR addr)
11e1b75f
AH		 251{
252 if (tdep->has_pauth ()
253 && frame_unwind_register_unsigned (this_frame,
254 tdep->pauth_ra_state_regnum))
255 {
256 int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
257 CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
258 addr = addr & ~cmask;
3d31bc39
AH		 259
260 /* Record in the frame that the link register required unmasking. */
261 set_frame_previous_pc_masked (this_frame);
11e1b75f
AH		 262 }
263
264 return addr;
265}
266
aa7ca1bb
AH		 267/* Implement the "get_pc_address_flags" gdbarch method. */
268
269static std::string
270aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
271{
272 if (pc != 0 && get_frame_pc_masked (frame))
273 return "PAC";
274
275 return "";
276}
277
07b287a0
MS		 278/* Analyze a prologue, looking for a recognizable stack frame
279 and frame pointer. Scan until we encounter a store that could
280 clobber the stack frame unexpectedly, or an unknown instruction. */
281
282static CORE_ADDR
283aarch64_analyze_prologue (struct gdbarch *gdbarch,
284 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 285 struct aarch64_prologue_cache *cache,
286 abstract_instruction_reader& reader)
07b287a0
MS		 287{
288 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
289 int i;
187f5d00
YQ		 290 /* Track X registers and D registers in prologue. */
291 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 292
187f5d00 293 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 294 regs[i] = pv_register (i, 0);
f7b7ed97 295 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 296
297 for (; start < limit; start += 4)
298 {
299 uint32_t insn;
d9ebcbce 300 aarch64_inst inst;
07b287a0 301
4d9a9006 302 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 303
561a72d4 304 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 305 break;
306
307 if (inst.opcode->iclass == addsub_imm
308 && (inst.opcode->op == OP_ADD
309 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 310 {
d9ebcbce
YQ		 311 unsigned rd = inst.operands[0].reg.regno;
312 unsigned rn = inst.operands[1].reg.regno;
313
314 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
315 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
316 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
317 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
318
319 if (inst.opcode->op == OP_ADD)
320 {
321 regs[rd] = pv_add_constant (regs[rn],
322 inst.operands[2].imm.value);
323 }
324 else
325 {
326 regs[rd] = pv_add_constant (regs[rn],
327 -inst.operands[2].imm.value);
328 }
329 }
330 else if (inst.opcode->iclass == pcreladdr
331 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
332 {
333 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
334 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
335
336 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 337 }
d9ebcbce 338 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 339 {
340 /* Stop analysis on branch. */
341 break;
342 }
d9ebcbce 343 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 344 {
345 /* Stop analysis on branch. */
346 break;
347 }
d9ebcbce 348 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 349 {
350 /* Stop analysis on branch. */
351 break;
352 }
d9ebcbce 353 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 354 {
355 /* Stop analysis on branch. */
356 break;
357 }
d9ebcbce
YQ		 358 else if (inst.opcode->op == OP_MOVZ)
359 {
360 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
361 regs[inst.operands[0].reg.regno] = pv_unknown ();
362 }
363 else if (inst.opcode->iclass == log_shift
364 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 365 {
d9ebcbce
YQ		 366 unsigned rd = inst.operands[0].reg.regno;
367 unsigned rn = inst.operands[1].reg.regno;
368 unsigned rm = inst.operands[2].reg.regno;
369
370 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
371 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
372 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
373
374 if (inst.operands[2].shifter.amount == 0
375 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 376 regs[rd] = regs[rm];
377 else
378 {
379 if (aarch64_debug)
b277c936
PL		 380 {
381 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 382 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 383 core_addr_to_string_nz (start), insn);
384 }
07b287a0
MS		 385 break;
386 }
387 }
d9ebcbce 388 else if (inst.opcode->op == OP_STUR)
07b287a0 389 {
d9ebcbce
YQ		 390 unsigned rt = inst.operands[0].reg.regno;
391 unsigned rn = inst.operands[1].addr.base_regno;
75faf5c4 392 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce
YQ		 393
394 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
395 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
396 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
397 gdb_assert (!inst.operands[1].addr.offset.is_reg);
398
75faf5c4
AH		 399 stack.store
400 (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
401 size, regs[rt]);
07b287a0 402 }
d9ebcbce 403 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 404 || (inst.opcode->iclass == ldstpair_indexed
405 && inst.operands[2].addr.preind))
d9ebcbce 406 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 407 {
03bcd739 408 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 409 unsigned rt1;
410 unsigned rt2;
d9ebcbce
YQ		 411 unsigned rn = inst.operands[2].addr.base_regno;
412 int32_t imm = inst.operands[2].addr.offset.imm;
75faf5c4 413 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce 414
187f5d00
YQ		 415 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
416 || inst.operands[0].type == AARCH64_OPND_Ft);
417 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
418 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 419 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
420 gdb_assert (!inst.operands[2].addr.offset.is_reg);
421
07b287a0
MS		 422 /* If recording this store would invalidate the store area
423 (perhaps because rn is not known) then we should abandon
424 further prologue analysis. */
f7b7ed97 425 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 426 break;
427
f7b7ed97 428 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 429 break;
430
187f5d00
YQ		 431 rt1 = inst.operands[0].reg.regno;
432 rt2 = inst.operands[1].reg.regno;
433 if (inst.operands[0].type == AARCH64_OPND_Ft)
434 {
187f5d00
YQ		 435 rt1 += AARCH64_X_REGISTER_COUNT;
436 rt2 += AARCH64_X_REGISTER_COUNT;
437 }
438
75faf5c4
AH		 439 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
440 stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
14ac654f 441
d9ebcbce 442 if (inst.operands[2].addr.writeback)
93d96012 443 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 444
07b287a0 445 }
432ec081
YQ		 446 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
447 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
448 && (inst.opcode->op == OP_STR_POS
449 || inst.opcode->op == OP_STRF_POS)))
450 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
451 && strcmp ("str", inst.opcode->name) == 0)
452 {
453 /* STR (immediate) */
454 unsigned int rt = inst.operands[0].reg.regno;
455 int32_t imm = inst.operands[1].addr.offset.imm;
456 unsigned int rn = inst.operands[1].addr.base_regno;
75faf5c4 457 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
432ec081
YQ		 458 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
459 || inst.operands[0].type == AARCH64_OPND_Ft);
460
461 if (inst.operands[0].type == AARCH64_OPND_Ft)
75faf5c4 462 rt += AARCH64_X_REGISTER_COUNT;
432ec081 463
75faf5c4 464 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
432ec081
YQ		 465 if (inst.operands[1].addr.writeback)
466 regs[rn] = pv_add_constant (regs[rn], imm);
467 }
d9ebcbce 468 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 469 {
470 /* Stop analysis on branch. */
471 break;
472 }
17e116a7
AH		 473 else if (inst.opcode->iclass == ic_system)
474 {
475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
476 int ra_state_val = 0;
477
478 if (insn == 0xd503233f /* paciasp. */
479 || insn == 0xd503237f /* pacibsp. */)
480 {
481 /* Return addresses are mangled. */
482 ra_state_val = 1;
483 }
484 else if (insn == 0xd50323bf /* autiasp. */
485 || insn == 0xd50323ff /* autibsp. */)
486 {
487 /* Return addresses are not mangled. */
488 ra_state_val = 0;
489 }
490 else
491 {
492 if (aarch64_debug)
493 debug_printf ("aarch64: prologue analysis gave up addr=%s"
494 " opcode=0x%x (iclass)\n",
495 core_addr_to_string_nz (start), insn);
496 break;
497 }
498
499 if (tdep->has_pauth () && cache != nullptr)
500 trad_frame_set_value (cache->saved_regs,
501 tdep->pauth_ra_state_regnum,
502 ra_state_val);
503 }
07b287a0
MS		 504 else
505 {
506 if (aarch64_debug)
b277c936 507 {
0a0da556 508 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 509 " opcode=0x%x\n",
510 core_addr_to_string_nz (start), insn);
511 }
07b287a0
MS		 512 break;
513 }
514 }
515
516 if (cache == NULL)
f7b7ed97 517 return start;
07b287a0
MS		 518
519 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
520 {
521 /* Frame pointer is fp. Frame size is constant. */
522 cache->framereg = AARCH64_FP_REGNUM;
523 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
524 }
525 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
526 {
527 /* Try the stack pointer. */
528 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
529 cache->framereg = AARCH64_SP_REGNUM;
530 }
531 else
532 {
533 /* We're just out of luck. We don't know where the frame is. */
534 cache->framereg = -1;
535 cache->framesize = 0;
536 }
537
538 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
539 {
540 CORE_ADDR offset;
541
f7b7ed97 542 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 543 cache->saved_regs[i].addr = offset;
544 }
545
187f5d00
YQ		 546 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
547 {
548 int regnum = gdbarch_num_regs (gdbarch);
549 CORE_ADDR offset;
550
f7b7ed97
TT		 551 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
552 &offset))
187f5d00
YQ		 553 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
554 }
555
07b287a0
MS		 556 return start;
557}
558
4d9a9006
YQ		 559static CORE_ADDR
560aarch64_analyze_prologue (struct gdbarch *gdbarch,
561 CORE_ADDR start, CORE_ADDR limit,
562 struct aarch64_prologue_cache *cache)
563{
564 instruction_reader reader;
565
566 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
567 reader);
568}
569
570#if GDB_SELF_TEST
571
572namespace selftests {
573
574/* Instruction reader from manually cooked instruction sequences. */
575
576class instruction_reader_test : public abstract_instruction_reader
577{
578public:
579 template<size_t SIZE>
580 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
581 : m_insns (insns), m_insns_size (SIZE)
582 {}
583
584 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 585 override
4d9a9006
YQ		 586 {
587 SELF_CHECK (len == 4);
588 SELF_CHECK (memaddr % 4 == 0);
589 SELF_CHECK (memaddr / 4 < m_insns_size);
590
591 return m_insns[memaddr / 4];
592 }
593
594private:
595 const uint32_t *m_insns;
596 size_t m_insns_size;
597};
598
599static void
600aarch64_analyze_prologue_test (void)
601{
602 struct gdbarch_info info;
603
604 gdbarch_info_init (&info);
605 info.bfd_arch_info = bfd_scan_arch ("aarch64");
606
607 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
608 SELF_CHECK (gdbarch != NULL);
609
17e116a7
AH		 610 struct aarch64_prologue_cache cache;
611 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
612
613 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
614
4d9a9006
YQ		 615 /* Test the simple prologue in which frame pointer is used. */
616 {
4d9a9006
YQ		 617 static const uint32_t insns[] = {
618 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
619 0x910003fd, /* mov x29, sp */
620 0x97ffffe6, /* bl 0x400580 */
621 };
622 instruction_reader_test reader (insns);
623
624 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
625 SELF_CHECK (end == 4 * 2);
626
627 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
628 SELF_CHECK (cache.framesize == 272);
629
630 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
631 {
632 if (i == AARCH64_FP_REGNUM)
633 SELF_CHECK (cache.saved_regs[i].addr == -272);
634 else if (i == AARCH64_LR_REGNUM)
635 SELF_CHECK (cache.saved_regs[i].addr == -264);
636 else
637 SELF_CHECK (cache.saved_regs[i].addr == -1);
638 }
639
640 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
641 {
642 int regnum = gdbarch_num_regs (gdbarch);
643
644 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
645 == -1);
646 }
647 }
432ec081
YQ		 648
649 /* Test a prologue in which STR is used and frame pointer is not
650 used. */
651 {
432ec081
YQ		 652 static const uint32_t insns[] = {
653 0xf81d0ff3, /* str x19, [sp, #-48]! */
654 0xb9002fe0, /* str w0, [sp, #44] */
655 0xf90013e1, /* str x1, [sp, #32]*/
656 0xfd000fe0, /* str d0, [sp, #24] */
657 0xaa0203f3, /* mov x19, x2 */
658 0xf94013e0, /* ldr x0, [sp, #32] */
659 };
660 instruction_reader_test reader (insns);
661
68811f8f 662 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
432ec081
YQ		 663 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
664
665 SELF_CHECK (end == 4 * 5);
666
667 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
668 SELF_CHECK (cache.framesize == 48);
669
670 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
671 {
672 if (i == 1)
673 SELF_CHECK (cache.saved_regs[i].addr == -16);
674 else if (i == 19)
675 SELF_CHECK (cache.saved_regs[i].addr == -48);
676 else
677 SELF_CHECK (cache.saved_regs[i].addr == -1);
678 }
679
680 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
681 {
682 int regnum = gdbarch_num_regs (gdbarch);
683
684 if (i == 0)
685 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
686 == -24);
687 else
688 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
689 == -1);
690 }
691 }
17e116a7
AH		 692
693 /* Test a prologue in which there is a return address signing instruction. */
694 if (tdep->has_pauth ())
695 {
696 static const uint32_t insns[] = {
697 0xd503233f, /* paciasp */
698 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
699 0x910003fd, /* mov x29, sp */
700 0xf801c3f3, /* str x19, [sp, #28] */
701 0xb9401fa0, /* ldr x19, [x29, #28] */
702 };
703 instruction_reader_test reader (insns);
704
68811f8f 705 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
17e116a7
AH		 706 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
707 reader);
708
709 SELF_CHECK (end == 4 * 4);
710 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
711 SELF_CHECK (cache.framesize == 48);
712
713 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
714 {
715 if (i == 19)
716 SELF_CHECK (cache.saved_regs[i].addr == -20);
717 else if (i == AARCH64_FP_REGNUM)
718 SELF_CHECK (cache.saved_regs[i].addr == -48);
719 else if (i == AARCH64_LR_REGNUM)
720 SELF_CHECK (cache.saved_regs[i].addr == -40);
721 else
722 SELF_CHECK (cache.saved_regs[i].addr == -1);
723 }
724
725 if (tdep->has_pauth ())
726 {
727 SELF_CHECK (trad_frame_value_p (cache.saved_regs,
728 tdep->pauth_ra_state_regnum));
729 SELF_CHECK (cache.saved_regs[tdep->pauth_ra_state_regnum].addr == 1);
730 }
731 }
4d9a9006
YQ		 732}
733} // namespace selftests
734#endif /* GDB_SELF_TEST */
735
07b287a0
MS		 736/* Implement the "skip_prologue" gdbarch method. */
737
738static CORE_ADDR
739aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
740{
07b287a0 741 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 742
743 /* See if we can determine the end of the prologue via the symbol
744 table. If so, then return either PC, or the PC after the
745 prologue, whichever is greater. */
746 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
747 {
748 CORE_ADDR post_prologue_pc
749 = skip_prologue_using_sal (gdbarch, func_addr);
750
751 if (post_prologue_pc != 0)
325fac50 752 return std::max (pc, post_prologue_pc);
07b287a0
MS		 753 }
754
755 /* Can't determine prologue from the symbol table, need to examine
756 instructions. */
757
758 /* Find an upper limit on the function prologue using the debug
759 information. If the debug information could not be used to
760 provide that bound, then use an arbitrary large number as the
761 upper bound. */
762 limit_pc = skip_prologue_using_sal (gdbarch, pc);
763 if (limit_pc == 0)
764 limit_pc = pc + 128; /* Magic. */
765
766 /* Try disassembling prologue. */
767 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
768}
769
770/* Scan the function prologue for THIS_FRAME and populate the prologue
771 cache CACHE. */
772
773static void
774aarch64_scan_prologue (struct frame_info *this_frame,
775 struct aarch64_prologue_cache *cache)
776{
777 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
778 CORE_ADDR prologue_start;
779 CORE_ADDR prologue_end;
780 CORE_ADDR prev_pc = get_frame_pc (this_frame);
781 struct gdbarch *gdbarch = get_frame_arch (this_frame);
782
db634143
PL		 783 cache->prev_pc = prev_pc;
784
07b287a0
MS		 785 /* Assume we do not find a frame. */
786 cache->framereg = -1;
787 cache->framesize = 0;
788
789 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
790 &prologue_end))
791 {
792 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
793
794 if (sal.line == 0)
795 {
796 /* No line info so use the current PC. */
797 prologue_end = prev_pc;
798 }
799 else if (sal.end < prologue_end)
800 {
801 /* The next line begins after the function end. */
802 prologue_end = sal.end;
803 }
804
325fac50 805 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 806 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
807 }
808 else
809 {
810 CORE_ADDR frame_loc;
07b287a0
MS		 811
812 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
813 if (frame_loc == 0)
814 return;
815
816 cache->framereg = AARCH64_FP_REGNUM;
817 cache->framesize = 16;
818 cache->saved_regs[29].addr = 0;
819 cache->saved_regs[30].addr = 8;
820 }
821}
822
7dfa3edc
PL		 823/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
824 function may throw an exception if the inferior's registers or memory is
825 not available. */
07b287a0 826
7dfa3edc
PL		 827static void
828aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
829 struct aarch64_prologue_cache *cache)
07b287a0 830{
07b287a0
MS		 831 CORE_ADDR unwound_fp;
832 int reg;
833
07b287a0
MS		 834 aarch64_scan_prologue (this_frame, cache);
835
836 if (cache->framereg == -1)
7dfa3edc 837 return;
07b287a0
MS		 838
839 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
840 if (unwound_fp == 0)
7dfa3edc 841 return;
07b287a0
MS		 842
843 cache->prev_sp = unwound_fp + cache->framesize;
844
845 /* Calculate actual addresses of saved registers using offsets
846 determined by aarch64_analyze_prologue. */
847 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
848 if (trad_frame_addr_p (cache->saved_regs, reg))
849 cache->saved_regs[reg].addr += cache->prev_sp;
850
db634143
PL		 851 cache->func = get_frame_func (this_frame);
852
7dfa3edc
PL		 853 cache->available_p = 1;
854}
855
856/* Allocate and fill in *THIS_CACHE with information about the prologue of
857 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
858 Return a pointer to the current aarch64_prologue_cache in
859 *THIS_CACHE. */
860
861static struct aarch64_prologue_cache *
862aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
863{
864 struct aarch64_prologue_cache *cache;
865
866 if (*this_cache != NULL)
9a3c8263 867 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 868
869 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
870 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
871 *this_cache = cache;
872
a70b8144 873 try
7dfa3edc
PL		 874 {
875 aarch64_make_prologue_cache_1 (this_frame, cache);
876 }
230d2906 877 catch (const gdb_exception_error &ex)
7dfa3edc
PL		 878 {
879 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 880 throw;
7dfa3edc 881 }
7dfa3edc 882
07b287a0
MS		 883 return cache;
884}
885
7dfa3edc
PL		 886/* Implement the "stop_reason" frame_unwind method. */
887
888static enum unwind_stop_reason
889aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
890 void **this_cache)
891{
892 struct aarch64_prologue_cache *cache
893 = aarch64_make_prologue_cache (this_frame, this_cache);
894
895 if (!cache->available_p)
896 return UNWIND_UNAVAILABLE;
897
898 /* Halt the backtrace at "_start". */
899 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
900 return UNWIND_OUTERMOST;
901
902 /* We've hit a wall, stop. */
903 if (cache->prev_sp == 0)
904 return UNWIND_OUTERMOST;
905
906 return UNWIND_NO_REASON;
907}
908
07b287a0
MS		 909/* Our frame ID for a normal frame is the current function's starting
910 PC and the caller's SP when we were called. */
911
912static void
913aarch64_prologue_this_id (struct frame_info *this_frame,
914 void **this_cache, struct frame_id *this_id)
915{
7c8edfae
PL		 916 struct aarch64_prologue_cache *cache
917 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 918
7dfa3edc
PL		 919 if (!cache->available_p)
920 *this_id = frame_id_build_unavailable_stack (cache->func);
921 else
922 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 923}
924
925/* Implement the "prev_register" frame_unwind method. */
926
927static struct value *
928aarch64_prologue_prev_register (struct frame_info *this_frame,
929 void **this_cache, int prev_regnum)
930{
7c8edfae
PL		 931 struct aarch64_prologue_cache *cache
932 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 933
934 /* If we are asked to unwind the PC, then we need to return the LR
935 instead. The prologue may save PC, but it will point into this
936 frame's prologue, not the next frame's resume location. */
937 if (prev_regnum == AARCH64_PC_REGNUM)
938 {
939 CORE_ADDR lr;
17e116a7
AH		 940 struct gdbarch *gdbarch = get_frame_arch (this_frame);
941 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 942
943 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
17e116a7
AH		 944
945 if (tdep->has_pauth ()
946 && trad_frame_value_p (cache->saved_regs,
947 tdep->pauth_ra_state_regnum))
3d31bc39 948 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
17e116a7 949
07b287a0
MS		 950 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
951 }
952
953 /* SP is generally not saved to the stack, but this frame is
954 identified by the next frame's stack pointer at the time of the
955 call. The value was already reconstructed into PREV_SP. */
956 /*
957 +----------+ ^
958 | saved lr | |
959 +->| saved fp |--+
960 | | |
961 | | | <- Previous SP
962 | +----------+
963 | | saved lr |
964 +--| saved fp |<- FP
965 | |
966 | |<- SP
967 +----------+ */
968 if (prev_regnum == AARCH64_SP_REGNUM)
969 return frame_unwind_got_constant (this_frame, prev_regnum,
970 cache->prev_sp);
971
972 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
973 prev_regnum);
974}
975
976/* AArch64 prologue unwinder. */
977struct frame_unwind aarch64_prologue_unwind =
978{
979 NORMAL_FRAME,
7dfa3edc 980 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 981 aarch64_prologue_this_id,
982 aarch64_prologue_prev_register,
983 NULL,
984 default_frame_sniffer
985};
986
8b61f75d
PL		 987/* Allocate and fill in *THIS_CACHE with information about the prologue of
988 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
989 Return a pointer to the current aarch64_prologue_cache in
990 *THIS_CACHE. */
07b287a0
MS		 991
992static struct aarch64_prologue_cache *
8b61f75d 993aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 994{
07b287a0 995 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 996
997 if (*this_cache != NULL)
9a3c8263 998 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 999
1000 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1001 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 1002 *this_cache = cache;
07b287a0 1003
a70b8144 1004 try
02a2a705
PL		 1005 {
1006 cache->prev_sp = get_frame_register_unsigned (this_frame,
1007 AARCH64_SP_REGNUM);
1008 cache->prev_pc = get_frame_pc (this_frame);
1009 cache->available_p = 1;
1010 }
230d2906 1011 catch (const gdb_exception_error &ex)
02a2a705
PL		 1012 {
1013 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1014 throw;
02a2a705 1015 }
07b287a0
MS		 1016
1017 return cache;
1018}
1019
02a2a705
PL		 1020/* Implement the "stop_reason" frame_unwind method. */
1021
1022static enum unwind_stop_reason
1023aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
1024 void **this_cache)
1025{
1026 struct aarch64_prologue_cache *cache
1027 = aarch64_make_stub_cache (this_frame, this_cache);
1028
1029 if (!cache->available_p)
1030 return UNWIND_UNAVAILABLE;
1031
1032 return UNWIND_NO_REASON;
1033}
1034
07b287a0
MS		 1035/* Our frame ID for a stub frame is the current SP and LR. */
1036
1037static void
1038aarch64_stub_this_id (struct frame_info *this_frame,
1039 void **this_cache, struct frame_id *this_id)
1040{
8b61f75d
PL		 1041 struct aarch64_prologue_cache *cache
1042 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 1043
02a2a705
PL		 1044 if (cache->available_p)
1045 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
1046 else
1047 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 1048}
1049
1050/* Implement the "sniffer" frame_unwind method. */
1051
1052static int
1053aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
1054 struct frame_info *this_frame,
1055 void **this_prologue_cache)
1056{
1057 CORE_ADDR addr_in_block;
1058 gdb_byte dummy[4];
1059
1060 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 1061 if (in_plt_section (addr_in_block)
07b287a0
MS		 1062 /* We also use the stub winder if the target memory is unreadable
1063 to avoid having the prologue unwinder trying to read it. */
1064 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1065 return 1;
1066
1067 return 0;
1068}
1069
1070/* AArch64 stub unwinder. */
1071struct frame_unwind aarch64_stub_unwind =
1072{
1073 NORMAL_FRAME,
02a2a705 1074 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 1075 aarch64_stub_this_id,
1076 aarch64_prologue_prev_register,
1077 NULL,
1078 aarch64_stub_unwind_sniffer
1079};
1080
1081/* Return the frame base address of *THIS_FRAME. */
1082
1083static CORE_ADDR
1084aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1085{
7c8edfae
PL		 1086 struct aarch64_prologue_cache *cache
1087 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1088
1089 return cache->prev_sp - cache->framesize;
1090}
1091
1092/* AArch64 default frame base information. */
1093struct frame_base aarch64_normal_base =
1094{
1095 &aarch64_prologue_unwind,
1096 aarch64_normal_frame_base,
1097 aarch64_normal_frame_base,
1098 aarch64_normal_frame_base
1099};
1100
07b287a0
MS		 1101/* Return the value of the REGNUM register in the previous frame of
1102 *THIS_FRAME. */
1103
1104static struct value *
1105aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1106 void **this_cache, int regnum)
1107{
11e1b75f 1108 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
07b287a0
MS		 1109 CORE_ADDR lr;
1110
1111 switch (regnum)
1112 {
1113 case AARCH64_PC_REGNUM:
1114 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
3d31bc39 1115 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
07b287a0
MS		 1116 return frame_unwind_got_constant (this_frame, regnum, lr);
1117
1118 default:
1119 internal_error (__FILE__, __LINE__,
1120 _("Unexpected register %d"), regnum);
1121 }
1122}
1123
11e1b75f
AH		 1124static const unsigned char op_lit0 = DW_OP_lit0;
1125static const unsigned char op_lit1 = DW_OP_lit1;
1126
07b287a0
MS		 1127/* Implement the "init_reg" dwarf2_frame_ops method. */
1128
1129static void
1130aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1131 struct dwarf2_frame_state_reg *reg,
1132 struct frame_info *this_frame)
1133{
11e1b75f
AH		 1134 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1135
07b287a0
MS		 1136 switch (regnum)
1137 {
1138 case AARCH64_PC_REGNUM:
1139 reg->how = DWARF2_FRAME_REG_FN;
1140 reg->loc.fn = aarch64_dwarf2_prev_register;
11e1b75f
AH		 1141 return;
1142
07b287a0
MS		 1143 case AARCH64_SP_REGNUM:
1144 reg->how = DWARF2_FRAME_REG_CFA;
11e1b75f
AH		 1145 return;
1146 }
1147
1148 /* Init pauth registers. */
1149 if (tdep->has_pauth ())
1150 {
1151 if (regnum == tdep->pauth_ra_state_regnum)
1152 {
1153 /* Initialize RA_STATE to zero. */
1154 reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1155 reg->loc.exp.start = &op_lit0;
1156 reg->loc.exp.len = 1;
1157 return;
1158 }
1159 else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
1160 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
1161 {
1162 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1163 return;
1164 }
07b287a0
MS		 1165 }
1166}
1167
11e1b75f
AH		 1168/* Implement the execute_dwarf_cfa_vendor_op method. */
1169
1170static bool
1171aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1172 struct dwarf2_frame_state *fs)
1173{
1174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1175 struct dwarf2_frame_state_reg *ra_state;
1176
8fca4da0 1177 if (op == DW_CFA_AARCH64_negate_ra_state)
11e1b75f 1178 {
8fca4da0
AH		 1179 /* On systems without pauth, treat as a nop. */
1180 if (!tdep->has_pauth ())
1181 return true;
1182
11e1b75f
AH		 1183 /* Allocate RA_STATE column if it's not allocated yet. */
1184 fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
1185
1186 /* Toggle the status of RA_STATE between 0 and 1. */
1187 ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
1188 ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1189
1190 if (ra_state->loc.exp.start == nullptr
1191 || ra_state->loc.exp.start == &op_lit0)
1192 ra_state->loc.exp.start = &op_lit1;
1193 else
1194 ra_state->loc.exp.start = &op_lit0;
1195
1196 ra_state->loc.exp.len = 1;
1197
1198 return true;
1199 }
1200
1201 return false;
1202}
1203
07b287a0
MS		 1204/* When arguments must be pushed onto the stack, they go on in reverse
1205 order. The code below implements a FILO (stack) to do this. */
1206
89055eaa 1207struct stack_item_t
07b287a0 1208{
c3c87445
YQ		 1209 /* Value to pass on stack. It can be NULL if this item is for stack
1210 padding. */
7c543f7b 1211 const gdb_byte *data;
07b287a0
MS		 1212
1213 /* Size in bytes of value to pass on stack. */
1214 int len;
89055eaa 1215};
07b287a0 1216
b907456c
AB		 1217/* Implement the gdbarch type alignment method, overrides the generic
1218 alignment algorithm for anything that is aarch64 specific. */
07b287a0 1219
b907456c
AB		 1220static ULONGEST
1221aarch64_type_align (gdbarch *gdbarch, struct type *t)
07b287a0 1222{
07b287a0 1223 t = check_typedef (t);
b907456c 1224 if (TYPE_CODE (t) == TYPE_CODE_ARRAY && TYPE_VECTOR (t))
07b287a0 1225 {
b907456c
AB		 1226 /* Use the natural alignment for vector types (the same for
1227 scalar type), but the maximum alignment is 128-bit. */
1228 if (TYPE_LENGTH (t) > 16)
1229 return 16;
238f2452 1230 else
b907456c 1231 return TYPE_LENGTH (t);
07b287a0 1232 }
b907456c
AB		 1233
1234 /* Allow the common code to calculate the alignment. */
1235 return 0;
07b287a0
MS		 1236}
1237
ea92689a
AH		 1238/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1239
1240 Return the number of register required, or -1 on failure.
1241
1242 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1243 to the element, else fail if the type of this element does not match the
1244 existing value. */
1245
1246static int
1247aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1248 struct type **fundamental_type)
1249{
1250 if (type == nullptr)
1251 return -1;
1252
1253 switch (TYPE_CODE (type))
1254 {
1255 case TYPE_CODE_FLT:
1256 if (TYPE_LENGTH (type) > 16)
1257 return -1;
1258
1259 if (*fundamental_type == nullptr)
1260 *fundamental_type = type;
1261 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1262 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1263 return -1;
1264
1265 return 1;
1266
1267 case TYPE_CODE_COMPLEX:
1268 {
1269 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1270 if (TYPE_LENGTH (target_type) > 16)
1271 return -1;
1272
1273 if (*fundamental_type == nullptr)
1274 *fundamental_type = target_type;
1275 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1276 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1277 return -1;
1278
1279 return 2;
1280 }
1281
1282 case TYPE_CODE_ARRAY:
1283 {
1284 if (TYPE_VECTOR (type))
1285 {
1286 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1287 return -1;
1288
1289 if (*fundamental_type == nullptr)
1290 *fundamental_type = type;
1291 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1292 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1293 return -1;
1294
1295 return 1;
1296 }
1297 else
1298 {
1299 struct type *target_type = TYPE_TARGET_TYPE (type);
1300 int count = aapcs_is_vfp_call_or_return_candidate_1
1301 (target_type, fundamental_type);
1302
1303 if (count == -1)
1304 return count;
1305
d4718d5c 1306 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1307 return count;
1308 }
1309 }
1310
1311 case TYPE_CODE_STRUCT:
1312 case TYPE_CODE_UNION:
1313 {
1314 int count = 0;
1315
1316 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1317 {
353229bf
AH		 1318 /* Ignore any static fields. */
1319 if (field_is_static (&TYPE_FIELD (type, i)))
1320 continue;
1321
ea92689a
AH		 1322 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1323
1324 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1325 (member, fundamental_type);
1326 if (sub_count == -1)
1327 return -1;
1328 count += sub_count;
1329 }
73021deb
AH		 1330
1331 /* Ensure there is no padding between the fields (allowing for empty
1332 zero length structs) */
1333 int ftype_length = (*fundamental_type == nullptr)
1334 ? 0 : TYPE_LENGTH (*fundamental_type);
1335 if (count * ftype_length != TYPE_LENGTH (type))
1336 return -1;
1337
ea92689a
AH		 1338 return count;
1339 }
1340
1341 default:
1342 break;
1343 }
1344
1345 return -1;
1346}
1347
1348/* Return true if an argument, whose type is described by TYPE, can be passed or
1349 returned in simd/fp registers, providing enough parameter passing registers
1350 are available. This is as described in the AAPCS64.
1351
1352 Upon successful return, *COUNT returns the number of needed registers,
1353 *FUNDAMENTAL_TYPE contains the type of those registers.
1354
1355 Candidate as per the AAPCS64 5.4.2.C is either a:
1356 - float.
1357 - short-vector.
1358 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1359 all the members are floats and has at most 4 members.
1360 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1361 all the members are short vectors and has at most 4 members.
1362 - Complex (7.1.1)
1363
1364 Note that HFAs and HVAs can include nested structures and arrays. */
1365
0e745c60 1366static bool
ea92689a
AH		 1367aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1368 struct type **fundamental_type)
1369{
1370 if (type == nullptr)
1371 return false;
1372
1373 *fundamental_type = nullptr;
1374
1375 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1376 fundamental_type);
1377
1378 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1379 {
1380 *count = ag_count;
1381 return true;
1382 }
1383 else
1384 return false;
1385}
1386
07b287a0
MS		 1387/* AArch64 function call information structure. */
1388struct aarch64_call_info
1389{
1390 /* the current argument number. */
89055eaa 1391 unsigned argnum = 0;
07b287a0
MS		 1392
1393 /* The next general purpose register number, equivalent to NGRN as
1394 described in the AArch64 Procedure Call Standard. */
89055eaa 1395 unsigned ngrn = 0;
07b287a0
MS		 1396
1397 /* The next SIMD and floating point register number, equivalent to
1398 NSRN as described in the AArch64 Procedure Call Standard. */
89055eaa 1399 unsigned nsrn = 0;
07b287a0
MS		 1400
1401 /* The next stacked argument address, equivalent to NSAA as
1402 described in the AArch64 Procedure Call Standard. */
89055eaa 1403 unsigned nsaa = 0;
07b287a0
MS		 1404
1405 /* Stack item vector. */
89055eaa 1406 std::vector<stack_item_t> si;
07b287a0
MS		 1407};
1408
1409/* Pass a value in a sequence of consecutive X registers. The caller
30baf67b 1410 is responsible for ensuring sufficient registers are available. */
07b287a0
MS		 1411
1412static void
1413pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1414 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1415 struct value *arg)
07b287a0
MS		 1416{
1417 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1418 int len = TYPE_LENGTH (type);
1419 enum type_code typecode = TYPE_CODE (type);
1420 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1421 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1422
1423 info->argnum++;
1424
1425 while (len > 0)
1426 {
1427 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1428 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1429 byte_order);
1430
1431
1432 /* Adjust sub-word struct/union args when big-endian. */
1433 if (byte_order == BFD_ENDIAN_BIG
1434 && partial_len < X_REGISTER_SIZE
1435 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1436 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1437
1438 if (aarch64_debug)
b277c936
PL		 1439 {
1440 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1441 gdbarch_register_name (gdbarch, regnum),
1442 phex (regval, X_REGISTER_SIZE));
1443 }
07b287a0
MS		 1444 regcache_cooked_write_unsigned (regcache, regnum, regval);
1445 len -= partial_len;
1446 buf += partial_len;
1447 regnum++;
1448 }
1449}
1450
1451/* Attempt to marshall a value in a V register. Return 1 if
1452 successful, or 0 if insufficient registers are available. This
1453 function, unlike the equivalent pass_in_x() function does not
1454 handle arguments spread across multiple registers. */
1455
1456static int
1457pass_in_v (struct gdbarch *gdbarch,
1458 struct regcache *regcache,
1459 struct aarch64_call_info *info,
0735fddd 1460 int len, const bfd_byte *buf)
07b287a0
MS		 1461{
1462 if (info->nsrn < 8)
1463 {
07b287a0 1464 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1465 /* Enough space for a full vector register. */
1466 gdb_byte reg[register_size (gdbarch, regnum)];
1467 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1468
1469 info->argnum++;
1470 info->nsrn++;
1471
0735fddd
YQ		 1472 memset (reg, 0, sizeof (reg));
1473 /* PCS C.1, the argument is allocated to the least significant
1474 bits of V register. */
1475 memcpy (reg, buf, len);
b66f5587 1476 regcache->cooked_write (regnum, reg);
0735fddd 1477
07b287a0 1478 if (aarch64_debug)
b277c936
PL		 1479 {
1480 debug_printf ("arg %d in %s\n", info->argnum,
1481 gdbarch_register_name (gdbarch, regnum));
1482 }
07b287a0
MS		 1483 return 1;
1484 }
1485 info->nsrn = 8;
1486 return 0;
1487}
1488
1489/* Marshall an argument onto the stack. */
1490
1491static void
1492pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1493 struct value *arg)
07b287a0 1494{
8e80f9d1 1495 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1496 int len = TYPE_LENGTH (type);
1497 int align;
1498 stack_item_t item;
1499
1500 info->argnum++;
1501
b907456c 1502 align = type_align (type);
07b287a0
MS		 1503
1504 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1505 Natural alignment of the argument's type. */
1506 align = align_up (align, 8);
1507
1508 /* The AArch64 PCS requires at most doubleword alignment. */
1509 if (align > 16)
1510 align = 16;
1511
1512 if (aarch64_debug)
b277c936
PL		 1513 {
1514 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1515 info->nsaa);
1516 }
07b287a0
MS		 1517
1518 item.len = len;
1519 item.data = buf;
89055eaa 1520 info->si.push_back (item);
07b287a0
MS		 1521
1522 info->nsaa += len;
1523 if (info->nsaa & (align - 1))
1524 {
1525 /* Push stack alignment padding. */
1526 int pad = align - (info->nsaa & (align - 1));
1527
1528 item.len = pad;
c3c87445 1529 item.data = NULL;
07b287a0 1530
89055eaa 1531 info->si.push_back (item);
07b287a0
MS		 1532 info->nsaa += pad;
1533 }
1534}
1535
1536/* Marshall an argument into a sequence of one or more consecutive X
1537 registers or, if insufficient X registers are available then onto
1538 the stack. */
1539
1540static void
1541pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1542 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1543 struct value *arg)
07b287a0
MS		 1544{
1545 int len = TYPE_LENGTH (type);
1546 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1547
1548 /* PCS C.13 - Pass in registers if we have enough spare */
1549 if (info->ngrn + nregs <= 8)
1550 {
8e80f9d1 1551 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1552 info->ngrn += nregs;
1553 }
1554 else
1555 {
1556 info->ngrn = 8;
8e80f9d1 1557 pass_on_stack (info, type, arg);
07b287a0
MS		 1558 }
1559}
1560
0e745c60
AH		 1561/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1562 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1563 registers. A return value of false is an error state as the value will have
1564 been partially passed to the stack. */
1565static bool
1566pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1567 struct aarch64_call_info *info, struct type *arg_type,
1568 struct value *arg)
07b287a0 1569{
0e745c60
AH		 1570 switch (TYPE_CODE (arg_type))
1571 {
1572 case TYPE_CODE_FLT:
1573 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1574 value_contents (arg));
1575 break;
1576
1577 case TYPE_CODE_COMPLEX:
1578 {
1579 const bfd_byte *buf = value_contents (arg);
1580 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1581
1582 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1583 buf))
1584 return false;
1585
1586 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1587 buf + TYPE_LENGTH (target_type));
1588 }
1589
1590 case TYPE_CODE_ARRAY:
1591 if (TYPE_VECTOR (arg_type))
1592 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1593 value_contents (arg));
1594 /* fall through. */
1595
1596 case TYPE_CODE_STRUCT:
1597 case TYPE_CODE_UNION:
1598 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1599 {
353229bf
AH		 1600 /* Don't include static fields. */
1601 if (field_is_static (&TYPE_FIELD (arg_type, i)))
1602 continue;
1603
0e745c60
AH		 1604 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1605 struct type *field_type = check_typedef (value_type (field));
1606
1607 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1608 field))
1609 return false;
1610 }
1611 return true;
1612
1613 default:
1614 return false;
1615 }
07b287a0
MS		 1616}
1617
1618/* Implement the "push_dummy_call" gdbarch method. */
1619
1620static CORE_ADDR
1621aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1622 struct regcache *regcache, CORE_ADDR bp_addr,
1623 int nargs,
cf84fa6b
AH		 1624 struct value **args, CORE_ADDR sp,
1625 function_call_return_method return_method,
07b287a0
MS		 1626 CORE_ADDR struct_addr)
1627{
07b287a0 1628 int argnum;
07b287a0 1629 struct aarch64_call_info info;
07b287a0 1630
07b287a0
MS		 1631 /* We need to know what the type of the called function is in order
1632 to determine the number of named/anonymous arguments for the
1633 actual argument placement, and the return type in order to handle
1634 return value correctly.
1635
1636 The generic code above us views the decision of return in memory
1637 or return in registers as a two stage processes. The language
1638 handler is consulted first and may decide to return in memory (eg
1639 class with copy constructor returned by value), this will cause
1640 the generic code to allocate space AND insert an initial leading
1641 argument.
1642
1643 If the language code does not decide to pass in memory then the
1644 target code is consulted.
1645
1646 If the language code decides to pass in memory we want to move
1647 the pointer inserted as the initial argument from the argument
1648 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1649 register. */
07b287a0
MS		 1650
1651 /* Set the return address. For the AArch64, the return breakpoint
1652 is always at BP_ADDR. */
1653 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1654
38a72da0
AH		 1655 /* If we were given an initial argument for the return slot, lose it. */
1656 if (return_method == return_method_hidden_param)
07b287a0
MS		 1657 {
1658 args++;
1659 nargs--;
1660 }
1661
1662 /* The struct_return pointer occupies X8. */
38a72da0 1663 if (return_method != return_method_normal)
07b287a0
MS		 1664 {
1665 if (aarch64_debug)
b277c936
PL		 1666 {
1667 debug_printf ("struct return in %s = 0x%s\n",
1668 gdbarch_register_name (gdbarch,
1669 AARCH64_STRUCT_RETURN_REGNUM),
1670 paddress (gdbarch, struct_addr));
1671 }
07b287a0
MS		 1672 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1673 struct_addr);
1674 }
1675
1676 for (argnum = 0; argnum < nargs; argnum++)
1677 {
1678 struct value *arg = args[argnum];
0e745c60
AH		 1679 struct type *arg_type, *fundamental_type;
1680 int len, elements;
07b287a0
MS		 1681
1682 arg_type = check_typedef (value_type (arg));
1683 len = TYPE_LENGTH (arg_type);
1684
0e745c60
AH		 1685 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1686 if there are enough spare registers. */
1687 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1688 &fundamental_type))
1689 {
1690 if (info.nsrn + elements <= 8)
1691 {
1692 /* We know that we have sufficient registers available therefore
1693 this will never need to fallback to the stack. */
1694 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1695 arg))
1696 gdb_assert_not_reached ("Failed to push args");
1697 }
1698 else
1699 {
1700 info.nsrn = 8;
1701 pass_on_stack (&info, arg_type, arg);
1702 }
1703 continue;
1704 }
1705
07b287a0
MS		 1706 switch (TYPE_CODE (arg_type))
1707 {
1708 case TYPE_CODE_INT:
1709 case TYPE_CODE_BOOL:
1710 case TYPE_CODE_CHAR:
1711 case TYPE_CODE_RANGE:
1712 case TYPE_CODE_ENUM:
1713 if (len < 4)
1714 {
1715 /* Promote to 32 bit integer. */
1716 if (TYPE_UNSIGNED (arg_type))
1717 arg_type = builtin_type (gdbarch)->builtin_uint32;
1718 else
1719 arg_type = builtin_type (gdbarch)->builtin_int32;
1720 arg = value_cast (arg_type, arg);
1721 }
8e80f9d1 1722 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1723 break;
1724
07b287a0
MS		 1725 case TYPE_CODE_STRUCT:
1726 case TYPE_CODE_ARRAY:
1727 case TYPE_CODE_UNION:
0e745c60 1728 if (len > 16)
07b287a0
MS		 1729 {
1730 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1731 invisible reference. */
1732
1733 /* Allocate aligned storage. */
1734 sp = align_down (sp - len, 16);
1735
1736 /* Write the real data into the stack. */
1737 write_memory (sp, value_contents (arg), len);
1738
1739 /* Construct the indirection. */
1740 arg_type = lookup_pointer_type (arg_type);
1741 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1742 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1743 }
1744 else
1745 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1746 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1747 break;
1748
1749 default:
8e80f9d1 1750 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1751 break;
1752 }
1753 }
1754
1755 /* Make sure stack retains 16 byte alignment. */
1756 if (info.nsaa & 15)
1757 sp -= 16 - (info.nsaa & 15);
1758
89055eaa 1759 while (!info.si.empty ())
07b287a0 1760 {
89055eaa 1761 const stack_item_t &si = info.si.back ();
07b287a0 1762
89055eaa
TT		 1763 sp -= si.len;
1764 if (si.data != NULL)
1765 write_memory (sp, si.data, si.len);
1766 info.si.pop_back ();
07b287a0
MS		 1767 }
1768
07b287a0
MS		 1769 /* Finally, update the SP register. */
1770 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1771
1772 return sp;
1773}
1774
1775/* Implement the "frame_align" gdbarch method. */
1776
1777static CORE_ADDR
1778aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1779{
1780 /* Align the stack to sixteen bytes. */
1781 return sp & ~(CORE_ADDR) 15;
1782}
1783
1784/* Return the type for an AdvSISD Q register. */
1785
1786static struct type *
1787aarch64_vnq_type (struct gdbarch *gdbarch)
1788{
1789 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1790
1791 if (tdep->vnq_type == NULL)
1792 {
1793 struct type *t;
1794 struct type *elem;
1795
1796 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1797 TYPE_CODE_UNION);
1798
1799 elem = builtin_type (gdbarch)->builtin_uint128;
1800 append_composite_type_field (t, "u", elem);
1801
1802 elem = builtin_type (gdbarch)->builtin_int128;
1803 append_composite_type_field (t, "s", elem);
1804
1805 tdep->vnq_type = t;
1806 }
1807
1808 return tdep->vnq_type;
1809}
1810
1811/* Return the type for an AdvSISD D register. */
1812
1813static struct type *
1814aarch64_vnd_type (struct gdbarch *gdbarch)
1815{
1816 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1817
1818 if (tdep->vnd_type == NULL)
1819 {
1820 struct type *t;
1821 struct type *elem;
1822
1823 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1824 TYPE_CODE_UNION);
1825
1826 elem = builtin_type (gdbarch)->builtin_double;
1827 append_composite_type_field (t, "f", elem);
1828
1829 elem = builtin_type (gdbarch)->builtin_uint64;
1830 append_composite_type_field (t, "u", elem);
1831
1832 elem = builtin_type (gdbarch)->builtin_int64;
1833 append_composite_type_field (t, "s", elem);
1834
1835 tdep->vnd_type = t;
1836 }
1837
1838 return tdep->vnd_type;
1839}
1840
1841/* Return the type for an AdvSISD S register. */
1842
1843static struct type *
1844aarch64_vns_type (struct gdbarch *gdbarch)
1845{
1846 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1847
1848 if (tdep->vns_type == NULL)
1849 {
1850 struct type *t;
1851 struct type *elem;
1852
1853 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1854 TYPE_CODE_UNION);
1855
1856 elem = builtin_type (gdbarch)->builtin_float;
1857 append_composite_type_field (t, "f", elem);
1858
1859 elem = builtin_type (gdbarch)->builtin_uint32;
1860 append_composite_type_field (t, "u", elem);
1861
1862 elem = builtin_type (gdbarch)->builtin_int32;
1863 append_composite_type_field (t, "s", elem);
1864
1865 tdep->vns_type = t;
1866 }
1867
1868 return tdep->vns_type;
1869}
1870
1871/* Return the type for an AdvSISD H register. */
1872
1873static struct type *
1874aarch64_vnh_type (struct gdbarch *gdbarch)
1875{
1876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1877
1878 if (tdep->vnh_type == NULL)
1879 {
1880 struct type *t;
1881 struct type *elem;
1882
1883 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1884 TYPE_CODE_UNION);
1885
a6d0f249
AH		 1886 elem = builtin_type (gdbarch)->builtin_half;
1887 append_composite_type_field (t, "f", elem);
1888
07b287a0
MS		 1889 elem = builtin_type (gdbarch)->builtin_uint16;
1890 append_composite_type_field (t, "u", elem);
1891
1892 elem = builtin_type (gdbarch)->builtin_int16;
1893 append_composite_type_field (t, "s", elem);
1894
1895 tdep->vnh_type = t;
1896 }
1897
1898 return tdep->vnh_type;
1899}
1900
1901/* Return the type for an AdvSISD B register. */
1902
1903static struct type *
1904aarch64_vnb_type (struct gdbarch *gdbarch)
1905{
1906 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1907
1908 if (tdep->vnb_type == NULL)
1909 {
1910 struct type *t;
1911 struct type *elem;
1912
1913 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1914 TYPE_CODE_UNION);
1915
1916 elem = builtin_type (gdbarch)->builtin_uint8;
1917 append_composite_type_field (t, "u", elem);
1918
1919 elem = builtin_type (gdbarch)->builtin_int8;
1920 append_composite_type_field (t, "s", elem);
1921
1922 tdep->vnb_type = t;
1923 }
1924
1925 return tdep->vnb_type;
1926}
1927
63bad7b6
AH		 1928/* Return the type for an AdvSISD V register. */
1929
1930static struct type *
1931aarch64_vnv_type (struct gdbarch *gdbarch)
1932{
1933 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1934
1935 if (tdep->vnv_type == NULL)
1936 {
bffa1015
AH		 1937 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1938 slice from the non-pseudo vector registers. However NEON V registers
1939 are always vector registers, and need constructing as such. */
1940 const struct builtin_type *bt = builtin_type (gdbarch);
1941
63bad7b6
AH		 1942 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1943 TYPE_CODE_UNION);
1944
bffa1015
AH		 1945 struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1946 TYPE_CODE_UNION);
1947 append_composite_type_field (sub, "f",
1948 init_vector_type (bt->builtin_double, 2));
1949 append_composite_type_field (sub, "u",
1950 init_vector_type (bt->builtin_uint64, 2));
1951 append_composite_type_field (sub, "s",
1952 init_vector_type (bt->builtin_int64, 2));
1953 append_composite_type_field (t, "d", sub);
1954
1955 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1956 TYPE_CODE_UNION);
1957 append_composite_type_field (sub, "f",
1958 init_vector_type (bt->builtin_float, 4));
1959 append_composite_type_field (sub, "u",
1960 init_vector_type (bt->builtin_uint32, 4));
1961 append_composite_type_field (sub, "s",
1962 init_vector_type (bt->builtin_int32, 4));
1963 append_composite_type_field (t, "s", sub);
1964
1965 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1966 TYPE_CODE_UNION);
a6d0f249
AH		 1967 append_composite_type_field (sub, "f",
1968 init_vector_type (bt->builtin_half, 8));
bffa1015
AH		 1969 append_composite_type_field (sub, "u",
1970 init_vector_type (bt->builtin_uint16, 8));
1971 append_composite_type_field (sub, "s",
1972 init_vector_type (bt->builtin_int16, 8));
1973 append_composite_type_field (t, "h", sub);
1974
1975 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1976 TYPE_CODE_UNION);
1977 append_composite_type_field (sub, "u",
1978 init_vector_type (bt->builtin_uint8, 16));
1979 append_composite_type_field (sub, "s",
1980 init_vector_type (bt->builtin_int8, 16));
1981 append_composite_type_field (t, "b", sub);
1982
1983 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1984 TYPE_CODE_UNION);
1985 append_composite_type_field (sub, "u",
1986 init_vector_type (bt->builtin_uint128, 1));
1987 append_composite_type_field (sub, "s",
1988 init_vector_type (bt->builtin_int128, 1));
1989 append_composite_type_field (t, "q", sub);
63bad7b6
AH		 1990
1991 tdep->vnv_type = t;
1992 }
1993
1994 return tdep->vnv_type;
1995}
1996
07b287a0
MS		 1997/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1998
1999static int
2000aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
2001{
34dcc7cf
AH		 2002 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2003
07b287a0
MS		 2004 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
2005 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
2006
2007 if (reg == AARCH64_DWARF_SP)
2008 return AARCH64_SP_REGNUM;
2009
2010 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
2011 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
2012
65d4cada
AH		 2013 if (reg == AARCH64_DWARF_SVE_VG)
2014 return AARCH64_SVE_VG_REGNUM;
2015
2016 if (reg == AARCH64_DWARF_SVE_FFR)
2017 return AARCH64_SVE_FFR_REGNUM;
2018
2019 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
2020 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
2021
2022 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
2023 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
2024
34dcc7cf
AH		 2025 if (tdep->has_pauth ())
2026 {
2027 if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
2028 return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
2029
2030 if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
2031 return tdep->pauth_ra_state_regnum;
2032 }
2033
07b287a0
MS		 2034 return -1;
2035}
07b287a0
MS		 2036
2037/* Implement the "print_insn" gdbarch method. */
2038
2039static int
2040aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
2041{
2042 info->symbols = NULL;
6394c606 2043 return default_print_insn (memaddr, info);
07b287a0
MS		 2044}
2045
2046/* AArch64 BRK software debug mode instruction.
2047 Note that AArch64 code is always little-endian.
2048 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 2049constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 2050
04180708 2051typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 2052
2053/* Extract from an array REGS containing the (raw) register state a
2054 function return value of type TYPE, and copy that, in virtual
2055 format, into VALBUF. */
2056
2057static void
2058aarch64_extract_return_value (struct type *type, struct regcache *regs,
2059 gdb_byte *valbuf)
2060{
ac7936df 2061 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2062 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2063 int elements;
2064 struct type *fundamental_type;
07b287a0 2065
4f4aedeb
AH		 2066 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2067 &fundamental_type))
07b287a0 2068 {
4f4aedeb
AH		 2069 int len = TYPE_LENGTH (fundamental_type);
2070
2071 for (int i = 0; i < elements; i++)
2072 {
2073 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2074 /* Enough space for a full vector register. */
2075 gdb_byte buf[register_size (gdbarch, regno)];
2076 gdb_assert (len <= sizeof (buf));
4f4aedeb
AH		 2077
2078 if (aarch64_debug)
2079 {
2080 debug_printf ("read HFA or HVA return value element %d from %s\n",
2081 i + 1,
2082 gdbarch_register_name (gdbarch, regno));
2083 }
2084 regs->cooked_read (regno, buf);
07b287a0 2085
4f4aedeb
AH		 2086 memcpy (valbuf, buf, len);
2087 valbuf += len;
2088 }
07b287a0
MS		 2089 }
2090 else if (TYPE_CODE (type) == TYPE_CODE_INT
2091 || TYPE_CODE (type) == TYPE_CODE_CHAR
2092 || TYPE_CODE (type) == TYPE_CODE_BOOL
2093 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2094 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2095 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2096 {
6471e7d2 2097 /* If the type is a plain integer, then the access is
07b287a0
MS		 2098 straight-forward. Otherwise we have to play around a bit
2099 more. */
2100 int len = TYPE_LENGTH (type);
2101 int regno = AARCH64_X0_REGNUM;
2102 ULONGEST tmp;
2103
2104 while (len > 0)
2105 {
2106 /* By using store_unsigned_integer we avoid having to do
2107 anything special for small big-endian values. */
2108 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2109 store_unsigned_integer (valbuf,
2110 (len > X_REGISTER_SIZE
2111 ? X_REGISTER_SIZE : len), byte_order, tmp);
2112 len -= X_REGISTER_SIZE;
2113 valbuf += X_REGISTER_SIZE;
2114 }
2115 }
07b287a0
MS		 2116 else
2117 {
2118 /* For a structure or union the behaviour is as if the value had
2119 been stored to word-aligned memory and then loaded into
2120 registers with 64-bit load instruction(s). */
2121 int len = TYPE_LENGTH (type);
2122 int regno = AARCH64_X0_REGNUM;
2123 bfd_byte buf[X_REGISTER_SIZE];
2124
2125 while (len > 0)
2126 {
dca08e1f 2127 regs->cooked_read (regno++, buf);
07b287a0
MS		 2128 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2129 len -= X_REGISTER_SIZE;
2130 valbuf += X_REGISTER_SIZE;
2131 }
2132 }
2133}
2134
2135
2136/* Will a function return an aggregate type in memory or in a
2137 register? Return 0 if an aggregate type can be returned in a
2138 register, 1 if it must be returned in memory. */
2139
2140static int
2141aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2142{
f168693b 2143 type = check_typedef (type);
4f4aedeb
AH		 2144 int elements;
2145 struct type *fundamental_type;
07b287a0 2146
4f4aedeb
AH		 2147 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2148 &fundamental_type))
07b287a0 2149 {
cd635f74
YQ		 2150 /* v0-v7 are used to return values and one register is allocated
2151 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 2152 return 0;
2153 }
2154
2155 if (TYPE_LENGTH (type) > 16)
2156 {
2157 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2158 invisible reference. */
2159
2160 return 1;
2161 }
2162
2163 return 0;
2164}
2165
2166/* Write into appropriate registers a function return value of type
2167 TYPE, given in virtual format. */
2168
2169static void
2170aarch64_store_return_value (struct type *type, struct regcache *regs,
2171 const gdb_byte *valbuf)
2172{
ac7936df 2173 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2174 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2175 int elements;
2176 struct type *fundamental_type;
07b287a0 2177
4f4aedeb
AH		 2178 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2179 &fundamental_type))
07b287a0 2180 {
4f4aedeb
AH		 2181 int len = TYPE_LENGTH (fundamental_type);
2182
2183 for (int i = 0; i < elements; i++)
2184 {
2185 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2186 /* Enough space for a full vector register. */
2187 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2188 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb
AH		 2189
2190 if (aarch64_debug)
2191 {
2192 debug_printf ("write HFA or HVA return value element %d to %s\n",
2193 i + 1,
2194 gdbarch_register_name (gdbarch, regno));
2195 }
07b287a0 2196
4f4aedeb
AH		 2197 memcpy (tmpbuf, valbuf,
2198 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2199 regs->cooked_write (regno, tmpbuf);
2200 valbuf += len;
2201 }
07b287a0
MS		 2202 }
2203 else if (TYPE_CODE (type) == TYPE_CODE_INT
2204 || TYPE_CODE (type) == TYPE_CODE_CHAR
2205 || TYPE_CODE (type) == TYPE_CODE_BOOL
2206 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2207 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2208 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2209 {
2210 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2211 {
2212 /* Values of one word or less are zero/sign-extended and
2213 returned in r0. */
2214 bfd_byte tmpbuf[X_REGISTER_SIZE];
2215 LONGEST val = unpack_long (type, valbuf);
2216
2217 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2218 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2219 }
2220 else
2221 {
2222 /* Integral values greater than one word are stored in
2223 consecutive registers starting with r0. This will always
2224 be a multiple of the regiser size. */
2225 int len = TYPE_LENGTH (type);
2226 int regno = AARCH64_X0_REGNUM;
2227
2228 while (len > 0)
2229 {
b66f5587 2230 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2231 len -= X_REGISTER_SIZE;
2232 valbuf += X_REGISTER_SIZE;
2233 }
2234 }
2235 }
07b287a0
MS		 2236 else
2237 {
2238 /* For a structure or union the behaviour is as if the value had
2239 been stored to word-aligned memory and then loaded into
2240 registers with 64-bit load instruction(s). */
2241 int len = TYPE_LENGTH (type);
2242 int regno = AARCH64_X0_REGNUM;
2243 bfd_byte tmpbuf[X_REGISTER_SIZE];
2244
2245 while (len > 0)
2246 {
2247 memcpy (tmpbuf, valbuf,
2248 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2249 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2250 len -= X_REGISTER_SIZE;
2251 valbuf += X_REGISTER_SIZE;
2252 }
2253 }
2254}
2255
2256/* Implement the "return_value" gdbarch method. */
2257
2258static enum return_value_convention
2259aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2260 struct type *valtype, struct regcache *regcache,
2261 gdb_byte *readbuf, const gdb_byte *writebuf)
2262{
07b287a0
MS		 2263
2264 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2265 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2266 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2267 {
2268 if (aarch64_return_in_memory (gdbarch, valtype))
2269 {
2270 if (aarch64_debug)
b277c936 2271 debug_printf ("return value in memory\n");
07b287a0
MS		 2272 return RETURN_VALUE_STRUCT_CONVENTION;
2273 }
2274 }
2275
2276 if (writebuf)
2277 aarch64_store_return_value (valtype, regcache, writebuf);
2278
2279 if (readbuf)
2280 aarch64_extract_return_value (valtype, regcache, readbuf);
2281
2282 if (aarch64_debug)
b277c936 2283 debug_printf ("return value in registers\n");
07b287a0
MS		 2284
2285 return RETURN_VALUE_REGISTER_CONVENTION;
2286}
2287
2288/* Implement the "get_longjmp_target" gdbarch method. */
2289
2290static int
2291aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2292{
2293 CORE_ADDR jb_addr;
2294 gdb_byte buf[X_REGISTER_SIZE];
2295 struct gdbarch *gdbarch = get_frame_arch (frame);
2296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2297 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2298
2299 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2300
2301 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2302 X_REGISTER_SIZE))
2303 return 0;
2304
2305 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2306 return 1;
2307}
ea873d8e
PL		 2308
2309/* Implement the "gen_return_address" gdbarch method. */
2310
2311static void
2312aarch64_gen_return_address (struct gdbarch *gdbarch,
2313 struct agent_expr *ax, struct axs_value *value,
2314 CORE_ADDR scope)
2315{
2316 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2317 value->kind = axs_lvalue_register;
2318 value->u.reg = AARCH64_LR_REGNUM;
2319}
07b287a0
MS		 2320\f
2321
2322/* Return the pseudo register name corresponding to register regnum. */
2323
2324static const char *
2325aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2326{
63bad7b6
AH		 2327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2328
07b287a0
MS		 2329 static const char *const q_name[] =
2330 {
2331 "q0", "q1", "q2", "q3",
2332 "q4", "q5", "q6", "q7",
2333 "q8", "q9", "q10", "q11",
2334 "q12", "q13", "q14", "q15",
2335 "q16", "q17", "q18", "q19",
2336 "q20", "q21", "q22", "q23",
2337 "q24", "q25", "q26", "q27",
2338 "q28", "q29", "q30", "q31",
2339 };
2340
2341 static const char *const d_name[] =
2342 {
2343 "d0", "d1", "d2", "d3",
2344 "d4", "d5", "d6", "d7",
2345 "d8", "d9", "d10", "d11",
2346 "d12", "d13", "d14", "d15",
2347 "d16", "d17", "d18", "d19",
2348 "d20", "d21", "d22", "d23",
2349 "d24", "d25", "d26", "d27",
2350 "d28", "d29", "d30", "d31",
2351 };
2352
2353 static const char *const s_name[] =
2354 {
2355 "s0", "s1", "s2", "s3",
2356 "s4", "s5", "s6", "s7",
2357 "s8", "s9", "s10", "s11",
2358 "s12", "s13", "s14", "s15",
2359 "s16", "s17", "s18", "s19",
2360 "s20", "s21", "s22", "s23",
2361 "s24", "s25", "s26", "s27",
2362 "s28", "s29", "s30", "s31",
2363 };
2364
2365 static const char *const h_name[] =
2366 {
2367 "h0", "h1", "h2", "h3",
2368 "h4", "h5", "h6", "h7",
2369 "h8", "h9", "h10", "h11",
2370 "h12", "h13", "h14", "h15",
2371 "h16", "h17", "h18", "h19",
2372 "h20", "h21", "h22", "h23",
2373 "h24", "h25", "h26", "h27",
2374 "h28", "h29", "h30", "h31",
2375 };
2376
2377 static const char *const b_name[] =
2378 {
2379 "b0", "b1", "b2", "b3",
2380 "b4", "b5", "b6", "b7",
2381 "b8", "b9", "b10", "b11",
2382 "b12", "b13", "b14", "b15",
2383 "b16", "b17", "b18", "b19",
2384 "b20", "b21", "b22", "b23",
2385 "b24", "b25", "b26", "b27",
2386 "b28", "b29", "b30", "b31",
2387 };
2388
34dcc7cf 2389 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2390
34dcc7cf
AH		 2391 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2392 return q_name[p_regnum - AARCH64_Q0_REGNUM];
07b287a0 2393
34dcc7cf
AH		 2394 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2395 return d_name[p_regnum - AARCH64_D0_REGNUM];
07b287a0 2396
34dcc7cf
AH		 2397 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2398 return s_name[p_regnum - AARCH64_S0_REGNUM];
07b287a0 2399
34dcc7cf
AH		 2400 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2401 return h_name[p_regnum - AARCH64_H0_REGNUM];
07b287a0 2402
34dcc7cf
AH		 2403 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2404 return b_name[p_regnum - AARCH64_B0_REGNUM];
07b287a0 2405
63bad7b6
AH		 2406 if (tdep->has_sve ())
2407 {
2408 static const char *const sve_v_name[] =
2409 {
2410 "v0", "v1", "v2", "v3",
2411 "v4", "v5", "v6", "v7",
2412 "v8", "v9", "v10", "v11",
2413 "v12", "v13", "v14", "v15",
2414 "v16", "v17", "v18", "v19",
2415 "v20", "v21", "v22", "v23",
2416 "v24", "v25", "v26", "v27",
2417 "v28", "v29", "v30", "v31",
2418 };
2419
34dcc7cf
AH		 2420 if (p_regnum >= AARCH64_SVE_V0_REGNUM
2421 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2422 return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
63bad7b6
AH		 2423 }
2424
34dcc7cf
AH		 2425 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2426 prevents it from being read by methods such as
2427 mi_cmd_trace_frame_collected. */
2428 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2429 return "";
2430
07b287a0
MS		 2431 internal_error (__FILE__, __LINE__,
2432 _("aarch64_pseudo_register_name: bad register number %d"),
34dcc7cf 2433 p_regnum);
07b287a0
MS		 2434}
2435
2436/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2437
2438static struct type *
2439aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2440{
63bad7b6
AH		 2441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2442
34dcc7cf 2443 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2444
34dcc7cf 2445 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0
MS		 2446 return aarch64_vnq_type (gdbarch);
2447
34dcc7cf 2448 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2449 return aarch64_vnd_type (gdbarch);
2450
34dcc7cf 2451 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2452 return aarch64_vns_type (gdbarch);
2453
34dcc7cf 2454 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0
MS		 2455 return aarch64_vnh_type (gdbarch);
2456
34dcc7cf 2457 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0
MS		 2458 return aarch64_vnb_type (gdbarch);
2459
34dcc7cf
AH		 2460 if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2461 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6
AH		 2462 return aarch64_vnv_type (gdbarch);
2463
34dcc7cf
AH		 2464 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2465 return builtin_type (gdbarch)->builtin_uint64;
2466
07b287a0
MS		 2467 internal_error (__FILE__, __LINE__,
2468 _("aarch64_pseudo_register_type: bad register number %d"),
34dcc7cf 2469 p_regnum);
07b287a0
MS		 2470}
2471
2472/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2473
2474static int
2475aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2476 struct reggroup *group)
2477{
63bad7b6
AH		 2478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2479
34dcc7cf 2480 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2481
34dcc7cf 2482 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0 2483 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2484 else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2485 return (group == all_reggroup || group == vector_reggroup
2486 || group == float_reggroup);
34dcc7cf 2487 else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2488 return (group == all_reggroup || group == vector_reggroup
2489 || group == float_reggroup);
34dcc7cf 2490 else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0 2491 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2492 else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0 2493 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2494 else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2495 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6 2496 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2497 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2498 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2499 return 0;
07b287a0
MS		 2500
2501 return group == all_reggroup;
2502}
2503
3c5cd5c3
AH		 2504/* Helper for aarch64_pseudo_read_value. */
2505
2506static struct value *
63bad7b6
AH		 2507aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2508 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2509 int regsize, struct value *result_value)
2510{
3c5cd5c3
AH		 2511 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2512
63bad7b6
AH		 2513 /* Enough space for a full vector register. */
2514 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2515 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2516
3c5cd5c3
AH		 2517 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2518 mark_value_bytes_unavailable (result_value, 0,
2519 TYPE_LENGTH (value_type (result_value)));
2520 else
2521 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2522
3c5cd5c3
AH		 2523 return result_value;
2524 }
2525
07b287a0
MS		 2526/* Implement the "pseudo_register_read_value" gdbarch method. */
2527
2528static struct value *
3c5cd5c3 2529aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2530 int regnum)
2531{
63bad7b6 2532 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2533 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2534
07b287a0
MS		 2535 VALUE_LVAL (result_value) = lval_register;
2536 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2537
2538 regnum -= gdbarch_num_regs (gdbarch);
2539
2540 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2541 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2542 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2543 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2544
2545 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2546 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2547 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2548 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2549
2550 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2551 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2552 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2553 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2554
2555 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2556 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2557 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2558 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2559
2560 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2561 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2562 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2563 B_REGISTER_SIZE, result_value);
07b287a0 2564
63bad7b6
AH		 2565 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2566 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2567 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2568 regnum - AARCH64_SVE_V0_REGNUM,
2569 V_REGISTER_SIZE, result_value);
2570
07b287a0
MS		 2571 gdb_assert_not_reached ("regnum out of bound");
2572}
2573
3c5cd5c3 2574/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2575
2576static void
63bad7b6
AH		 2577aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2578 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2579{
3c5cd5c3 2580 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2581
63bad7b6
AH		 2582 /* Enough space for a full vector register. */
2583 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2584 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2585
07b287a0
MS		 2586 /* Ensure the register buffer is zero, we want gdb writes of the
2587 various 'scalar' pseudo registers to behavior like architectural
2588 writes, register width bytes are written the remainder are set to
2589 zero. */
63bad7b6 2590 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2591
3c5cd5c3
AH		 2592 memcpy (reg_buf, buf, regsize);
2593 regcache->raw_write (v_regnum, reg_buf);
2594}
2595
2596/* Implement the "pseudo_register_write" gdbarch method. */
2597
2598static void
2599aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2600 int regnum, const gdb_byte *buf)
2601{
63bad7b6 2602 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2603 regnum -= gdbarch_num_regs (gdbarch);
2604
2605 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2606 return aarch64_pseudo_write_1 (gdbarch, regcache,
2607 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2608 buf);
07b287a0
MS		 2609
2610 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2611 return aarch64_pseudo_write_1 (gdbarch, regcache,
2612 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2613 buf);
07b287a0
MS		 2614
2615 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2616 return aarch64_pseudo_write_1 (gdbarch, regcache,
2617 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2618 buf);
07b287a0
MS		 2619
2620 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2621 return aarch64_pseudo_write_1 (gdbarch, regcache,
2622 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2623 buf);
07b287a0
MS		 2624
2625 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2626 return aarch64_pseudo_write_1 (gdbarch, regcache,
2627 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2628 buf);
2629
2630 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2631 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2632 return aarch64_pseudo_write_1 (gdbarch, regcache,
2633 regnum - AARCH64_SVE_V0_REGNUM,
2634 V_REGISTER_SIZE, buf);
07b287a0
MS		 2635
2636 gdb_assert_not_reached ("regnum out of bound");
2637}
2638
07b287a0
MS		 2639/* Callback function for user_reg_add. */
2640
2641static struct value *
2642value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2643{
9a3c8263 2644 const int *reg_p = (const int *) baton;
07b287a0
MS		 2645
2646 return value_of_register (*reg_p, frame);
2647}
2648\f
2649
9404b58f
KM		 2650/* Implement the "software_single_step" gdbarch method, needed to
2651 single step through atomic sequences on AArch64. */
2652
a0ff9e1a 2653static std::vector<CORE_ADDR>
f5ea389a 2654aarch64_software_single_step (struct regcache *regcache)
9404b58f 2655{
ac7936df 2656 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2657 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2658 const int insn_size = 4;
2659 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2660 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2661 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2662 CORE_ADDR loc = pc;
2663 CORE_ADDR closing_insn = 0;
2664 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2665 byte_order_for_code);
2666 int index;
2667 int insn_count;
2668 int bc_insn_count = 0; /* Conditional branch instruction count. */
2669 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2670 aarch64_inst inst;
2671
561a72d4 2672 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2673 return {};
9404b58f
KM		 2674
2675 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2676 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2677 return {};
9404b58f
KM		 2678
2679 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2680 {
9404b58f
KM		 2681 loc += insn_size;
2682 insn = read_memory_unsigned_integer (loc, insn_size,
2683 byte_order_for_code);
2684
561a72d4 2685 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2686 return {};
9404b58f 2687 /* Check if the instruction is a conditional branch. */
f77ee802 2688 if (inst.opcode->iclass == condbranch)
9404b58f 2689 {
f77ee802
YQ		 2690 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2691
9404b58f 2692 if (bc_insn_count >= 1)
a0ff9e1a 2693 return {};
9404b58f
KM		 2694
2695 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2696 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2697
2698 bc_insn_count++;
2699 last_breakpoint++;
2700 }
2701
2702 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2703 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2704 {
2705 closing_insn = loc;
2706 break;
2707 }
2708 }
2709
2710 /* We didn't find a closing Store Exclusive instruction, fall back. */
2711 if (!closing_insn)
a0ff9e1a 2712 return {};
9404b58f
KM		 2713
2714 /* Insert breakpoint after the end of the atomic sequence. */
2715 breaks[0] = loc + insn_size;
2716
2717 /* Check for duplicated breakpoints, and also check that the second
2718 breakpoint is not within the atomic sequence. */
2719 if (last_breakpoint
2720 && (breaks[1] == breaks[0]
2721 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2722 last_breakpoint = 0;
2723
a0ff9e1a
SM		 2724 std::vector<CORE_ADDR> next_pcs;
2725
9404b58f
KM		 2726 /* Insert the breakpoint at the end of the sequence, and one at the
2727 destination of the conditional branch, if it exists. */
2728 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2729 next_pcs.push_back (breaks[index]);
9404b58f 2730
93f9a11f 2731 return next_pcs;
9404b58f
KM		 2732}
2733
cfba9872 2734struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2735{
2736 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2737 is being displaced stepping. */
f0c702d4 2738 bool cond = false;
b6542f81 2739
0c271889
LM		 2740 /* PC adjustment offset after displaced stepping. If 0, then we don't
2741 write the PC back, assuming the PC is already the right address. */
cfba9872 2742 int32_t pc_adjust = 0;
b6542f81
YQ		 2743};
2744
2745/* Data when visiting instructions for displaced stepping. */
2746
2747struct aarch64_displaced_step_data
2748{
2749 struct aarch64_insn_data base;
2750
2751 /* The address where the instruction will be executed at. */
2752 CORE_ADDR new_addr;
2753 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
e935475c 2754 uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
b6542f81
YQ		 2755 /* Number of instructions in INSN_BUF. */
2756 unsigned insn_count;
2757 /* Registers when doing displaced stepping. */
2758 struct regcache *regs;
2759
cfba9872 2760 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2761};
2762
2763/* Implementation of aarch64_insn_visitor method "b". */
2764
2765static void
2766aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2767 struct aarch64_insn_data *data)
2768{
2769 struct aarch64_displaced_step_data *dsd
2770 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2771 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2772
2773 if (can_encode_int32 (new_offset, 28))
2774 {
2775 /* Emit B rather than BL, because executing BL on a new address
2776 will get the wrong address into LR. In order to avoid this,
2777 we emit B, and update LR if the instruction is BL. */
2778 emit_b (dsd->insn_buf, 0, new_offset);
2779 dsd->insn_count++;
2780 }
2781 else
2782 {
2783 /* Write NOP. */
2784 emit_nop (dsd->insn_buf);
2785 dsd->insn_count++;
2786 dsd->dsc->pc_adjust = offset;
2787 }
2788
2789 if (is_bl)
2790 {
2791 /* Update LR. */
2792 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2793 data->insn_addr + 4);
2794 }
2795}
2796
2797/* Implementation of aarch64_insn_visitor method "b_cond". */
2798
2799static void
2800aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2801 struct aarch64_insn_data *data)
2802{
2803 struct aarch64_displaced_step_data *dsd
2804 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2805
2806 /* GDB has to fix up PC after displaced step this instruction
2807 differently according to the condition is true or false. Instead
2808 of checking COND against conditional flags, we can use
2809 the following instructions, and GDB can tell how to fix up PC
2810 according to the PC value.
2811
2812 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2813 INSN1 ;
2814 TAKEN:
2815 INSN2
2816 */
2817
2818 emit_bcond (dsd->insn_buf, cond, 8);
f0c702d4 2819 dsd->dsc->cond = true;
b6542f81
YQ		 2820 dsd->dsc->pc_adjust = offset;
2821 dsd->insn_count = 1;
2822}
2823
2824/* Dynamically allocate a new register. If we know the register
2825 statically, we should make it a global as above instead of using this
2826 helper function. */
2827
2828static struct aarch64_register
2829aarch64_register (unsigned num, int is64)
2830{
2831 return (struct aarch64_register) { num, is64 };
2832}
2833
2834/* Implementation of aarch64_insn_visitor method "cb". */
2835
2836static void
2837aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2838 const unsigned rn, int is64,
2839 struct aarch64_insn_data *data)
2840{
2841 struct aarch64_displaced_step_data *dsd
2842 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2843
2844 /* The offset is out of range for a compare and branch
2845 instruction. We can use the following instructions instead:
2846
2847 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2848 INSN1 ;
2849 TAKEN:
2850 INSN2
2851 */
2852 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2853 dsd->insn_count = 1;
f0c702d4 2854 dsd->dsc->cond = true;
b6542f81
YQ		 2855 dsd->dsc->pc_adjust = offset;
2856}
2857
2858/* Implementation of aarch64_insn_visitor method "tb". */
2859
2860static void
2861aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2862 const unsigned rt, unsigned bit,
2863 struct aarch64_insn_data *data)
2864{
2865 struct aarch64_displaced_step_data *dsd
2866 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2867
2868 /* The offset is out of range for a test bit and branch
2869 instruction We can use the following instructions instead:
2870
2871 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2872 INSN1 ;
2873 TAKEN:
2874 INSN2
2875
2876 */
2877 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2878 dsd->insn_count = 1;
f0c702d4 2879 dsd->dsc->cond = true;
b6542f81
YQ		 2880 dsd->dsc->pc_adjust = offset;
2881}
2882
2883/* Implementation of aarch64_insn_visitor method "adr". */
2884
2885static void
2886aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2887 const int is_adrp, struct aarch64_insn_data *data)
2888{
2889 struct aarch64_displaced_step_data *dsd
2890 = (struct aarch64_displaced_step_data *) data;
2891 /* We know exactly the address the ADR{P,} instruction will compute.
2892 We can just write it to the destination register. */
2893 CORE_ADDR address = data->insn_addr + offset;
2894
2895 if (is_adrp)
2896 {
2897 /* Clear the lower 12 bits of the offset to get the 4K page. */
2898 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2899 address & ~0xfff);
2900 }
2901 else
2902 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2903 address);
2904
2905 dsd->dsc->pc_adjust = 4;
2906 emit_nop (dsd->insn_buf);
2907 dsd->insn_count = 1;
2908}
2909
2910/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2911
2912static void
2913aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2914 const unsigned rt, const int is64,
2915 struct aarch64_insn_data *data)
2916{
2917 struct aarch64_displaced_step_data *dsd
2918 = (struct aarch64_displaced_step_data *) data;
2919 CORE_ADDR address = data->insn_addr + offset;
2920 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2921
2922 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2923 address);
2924
2925 if (is_sw)
2926 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2927 aarch64_register (rt, 1), zero);
2928 else
2929 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2930 aarch64_register (rt, 1), zero);
2931
2932 dsd->dsc->pc_adjust = 4;
2933}
2934
2935/* Implementation of aarch64_insn_visitor method "others". */
2936
2937static void
2938aarch64_displaced_step_others (const uint32_t insn,
2939 struct aarch64_insn_data *data)
2940{
2941 struct aarch64_displaced_step_data *dsd
2942 = (struct aarch64_displaced_step_data *) data;
2943
e1c587c3 2944 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2945 dsd->insn_count = 1;
2946
2947 if ((insn & 0xfffffc1f) == 0xd65f0000)
2948 {
2949 /* RET */
2950 dsd->dsc->pc_adjust = 0;
2951 }
2952 else
2953 dsd->dsc->pc_adjust = 4;
2954}
2955
2956static const struct aarch64_insn_visitor visitor =
2957{
2958 aarch64_displaced_step_b,
2959 aarch64_displaced_step_b_cond,
2960 aarch64_displaced_step_cb,
2961 aarch64_displaced_step_tb,
2962 aarch64_displaced_step_adr,
2963 aarch64_displaced_step_ldr_literal,
2964 aarch64_displaced_step_others,
2965};
2966
2967/* Implement the "displaced_step_copy_insn" gdbarch method. */
2968
2969struct displaced_step_closure *
2970aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2971 CORE_ADDR from, CORE_ADDR to,
2972 struct regcache *regs)
2973{
b6542f81
YQ		 2974 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2975 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2976 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 2977 aarch64_inst inst;
2978
561a72d4 2979 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 2980 return NULL;
b6542f81
YQ		 2981
2982 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 2983 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 2984 {
2985 /* We can't displaced step atomic sequences. */
2986 return NULL;
2987 }
2988
cfba9872
SM		 2989 std::unique_ptr<aarch64_displaced_step_closure> dsc
2990 (new aarch64_displaced_step_closure);
b6542f81
YQ		 2991 dsd.base.insn_addr = from;
2992 dsd.new_addr = to;
2993 dsd.regs = regs;
cfba9872 2994 dsd.dsc = dsc.get ();
034f1a81 2995 dsd.insn_count = 0;
b6542f81
YQ		 2996 aarch64_relocate_instruction (insn, &visitor,
2997 (struct aarch64_insn_data *) &dsd);
e935475c 2998 gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS);
b6542f81
YQ		 2999
3000 if (dsd.insn_count != 0)
3001 {
3002 int i;
3003
3004 /* Instruction can be relocated to scratch pad. Copy
3005 relocated instruction(s) there. */
3006 for (i = 0; i < dsd.insn_count; i++)
3007 {
3008 if (debug_displaced)
3009 {
3010 debug_printf ("displaced: writing insn ");
3011 debug_printf ("%.8x", dsd.insn_buf[i]);
3012 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
3013 }
3014 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
3015 (ULONGEST) dsd.insn_buf[i]);
3016 }
3017 }
3018 else
3019 {
b6542f81
YQ		 3020 dsc = NULL;
3021 }
3022
cfba9872 3023 return dsc.release ();
b6542f81
YQ		 3024}
3025
3026/* Implement the "displaced_step_fixup" gdbarch method. */
3027
3028void
3029aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 3030 struct displaced_step_closure *dsc_,
b6542f81
YQ		 3031 CORE_ADDR from, CORE_ADDR to,
3032 struct regcache *regs)
3033{
cfba9872
SM		 3034 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
3035
0c271889
LM		 3036 ULONGEST pc;
3037
3038 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
3039
1ab139e5
LM		 3040 if (debug_displaced)
3041 debug_printf ("Displaced: PC after stepping: %s (was %s).\n",
3042 paddress (gdbarch, pc), paddress (gdbarch, to));
3043
b6542f81
YQ		 3044 if (dsc->cond)
3045 {
1ab139e5
LM		 3046 if (debug_displaced)
3047 debug_printf ("Displaced: [Conditional] pc_adjust before: %d\n",
3048 dsc->pc_adjust);
3049
b6542f81
YQ		 3050 if (pc - to == 8)
3051 {
3052 /* Condition is true. */
3053 }
3054 else if (pc - to == 4)
3055 {
3056 /* Condition is false. */
3057 dsc->pc_adjust = 4;
3058 }
3059 else
3060 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
1ab139e5
LM		 3061
3062 if (debug_displaced)
3063 debug_printf ("Displaced: [Conditional] pc_adjust after: %d\n",
3064 dsc->pc_adjust);
b6542f81
YQ		 3065 }
3066
1ab139e5
LM		 3067 if (debug_displaced)
3068 debug_printf ("Displaced: %s PC by %d\n",
3069 dsc->pc_adjust? "adjusting" : "not adjusting",
3070 dsc->pc_adjust);
3071
3072
b6542f81
YQ		 3073 if (dsc->pc_adjust != 0)
3074 {
0c271889
LM		 3075 /* Make sure the previous instruction was executed (that is, the PC
3076 has changed). If the PC didn't change, then discard the adjustment
3077 offset. Otherwise we may skip an instruction before its execution
3078 took place. */
3079 if ((pc - to) == 0)
1ab139e5
LM		 3080 {
3081 if (debug_displaced)
3082 debug_printf ("Displaced: PC did not move. Discarding PC "
3083 "adjustment.\n");
3084 dsc->pc_adjust = 0;
3085 }
0c271889 3086
b6542f81
YQ		 3087 if (debug_displaced)
3088 {
1ab139e5 3089 debug_printf ("Displaced: fixup: set PC to %s:%d\n",
b6542f81
YQ		 3090 paddress (gdbarch, from), dsc->pc_adjust);
3091 }
3092 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
3093 from + dsc->pc_adjust);
3094 }
3095}
3096
3097/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3098
3099int
3100aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
3101 struct displaced_step_closure *closure)
3102{
3103 return 1;
3104}
3105
95228a0d
AH		 3106/* Get the correct target description for the given VQ value.
3107 If VQ is zero then it is assumed SVE is not supported.
3108 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 3109
3110const target_desc *
6dc0ebde 3111aarch64_read_description (uint64_t vq, bool pauth_p)
da434ccb 3112{
95228a0d 3113 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 3114 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 3115 AARCH64_MAX_SVE_VQ);
3116
6dc0ebde 3117 struct target_desc *tdesc = tdesc_aarch64_list[vq][pauth_p];
da434ccb 3118
95228a0d
AH		 3119 if (tdesc == NULL)
3120 {
6dc0ebde
AH		 3121 tdesc = aarch64_create_target_description (vq, pauth_p);
3122 tdesc_aarch64_list[vq][pauth_p] = tdesc;
95228a0d 3123 }
da434ccb 3124
95228a0d 3125 return tdesc;
da434ccb
AH		 3126}
3127
ba2d2bb2
AH		 3128/* Return the VQ used when creating the target description TDESC. */
3129
1332a140 3130static uint64_t
ba2d2bb2
AH		 3131aarch64_get_tdesc_vq (const struct target_desc *tdesc)
3132{
3133 const struct tdesc_feature *feature_sve;
3134
3135 if (!tdesc_has_registers (tdesc))
3136 return 0;
3137
3138 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3139
3140 if (feature_sve == nullptr)
3141 return 0;
3142
12863263
AH		 3143 uint64_t vl = tdesc_register_bitsize (feature_sve,
3144 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 3145 return sve_vq_from_vl (vl);
3146}
3147
0ef8a082
AH		 3148/* Add all the expected register sets into GDBARCH. */
3149
3150static void
3151aarch64_add_reggroups (struct gdbarch *gdbarch)
3152{
3153 reggroup_add (gdbarch, general_reggroup);
3154 reggroup_add (gdbarch, float_reggroup);
3155 reggroup_add (gdbarch, system_reggroup);
3156 reggroup_add (gdbarch, vector_reggroup);
3157 reggroup_add (gdbarch, all_reggroup);
3158 reggroup_add (gdbarch, save_reggroup);
3159 reggroup_add (gdbarch, restore_reggroup);
3160}
ba2d2bb2 3161
76bed0fd
AH		 3162/* Implement the "cannot_store_register" gdbarch method. */
3163
3164static int
3165aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum)
3166{
3167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3168
3169 if (!tdep->has_pauth ())
3170 return 0;
3171
3172 /* Pointer authentication registers are read-only. */
3173 return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
3174 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base));
3175}
3176
07b287a0
MS		 3177/* Initialize the current architecture based on INFO. If possible,
3178 re-use an architecture from ARCHES, which is a list of
3179 architectures already created during this debugging session.
3180
3181 Called e.g. at program startup, when reading a core file, and when
3182 reading a binary file. */
3183
3184static struct gdbarch *
3185aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3186{
ccb8d7e8 3187 const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve;
76bed0fd 3188 const struct tdesc_feature *feature_pauth;
ccb8d7e8
AH		 3189 bool valid_p = true;
3190 int i, num_regs = 0, num_pseudo_regs = 0;
3191 int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
3192
4da037ef
AH		 3193 /* Use the vector length passed via the target info. Here -1 is used for no
3194 SVE, and 0 is unset. If unset then use the vector length from the existing
3195 tdesc. */
3196 uint64_t vq = 0;
3197 if (info.id == (int *) -1)
3198 vq = 0;
3199 else if (info.id != 0)
3200 vq = (uint64_t) info.id;
3201 else
3202 vq = aarch64_get_tdesc_vq (info.target_desc);
3203
3204 if (vq > AARCH64_MAX_SVE_VQ)
596179f7
SDJ		 3205 internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"),
3206 pulongest (vq), AARCH64_MAX_SVE_VQ);
4da037ef 3207
ccb8d7e8
AH		 3208 /* If there is already a candidate, use it. */
3209 for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
3210 best_arch != nullptr;
3211 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3212 {
3213 struct gdbarch_tdep *tdep = gdbarch_tdep (best_arch->gdbarch);
4da037ef 3214 if (tdep && tdep->vq == vq)
ccb8d7e8
AH		 3215 return best_arch->gdbarch;
3216 }
07b287a0 3217
4da037ef
AH		 3218 /* Ensure we always have a target descriptor, and that it is for the given VQ
3219 value. */
ccb8d7e8 3220 const struct target_desc *tdesc = info.target_desc;
4da037ef
AH		 3221 if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc))
3222 tdesc = aarch64_read_description (vq, false);
07b287a0
MS		 3223 gdb_assert (tdesc);
3224
ccb8d7e8 3225 feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
ba2d2bb2
AH		 3226 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
3227 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
76bed0fd 3228 feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
07b287a0 3229
ccb8d7e8
AH		 3230 if (feature_core == nullptr)
3231 return nullptr;
07b287a0 3232
ccb8d7e8 3233 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
07b287a0 3234
ba2d2bb2 3235 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 3236 and allocate their numbers. */
3237 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 3238 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
3239 AARCH64_X0_REGNUM + i,
3240 aarch64_r_register_names[i]);
07b287a0
MS		 3241
3242 num_regs = AARCH64_X0_REGNUM + i;
3243
ba2d2bb2 3244 /* Add the V registers. */
ccb8d7e8 3245 if (feature_fpu != nullptr)
07b287a0 3246 {
ccb8d7e8 3247 if (feature_sve != nullptr)
ba2d2bb2
AH		 3248 error (_("Program contains both fpu and SVE features."));
3249
3250 /* Validate the description provides the mandatory V registers
3251 and allocate their numbers. */
07b287a0 3252 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 3253 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
3254 AARCH64_V0_REGNUM + i,
3255 aarch64_v_register_names[i]);
07b287a0
MS		 3256
3257 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 3258 }
07b287a0 3259
ba2d2bb2 3260 /* Add the SVE registers. */
ccb8d7e8 3261 if (feature_sve != nullptr)
ba2d2bb2
AH		 3262 {
3263 /* Validate the description provides the mandatory SVE registers
3264 and allocate their numbers. */
3265 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3266 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3267 AARCH64_SVE_Z0_REGNUM + i,
3268 aarch64_sve_register_names[i]);
3269
3270 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3271 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3272 }
3273
ccb8d7e8 3274 if (feature_fpu != nullptr || feature_sve != nullptr)
ba2d2bb2 3275 {
07b287a0
MS		 3276 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3277 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3278 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3279 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3280 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3281 }
3282
76bed0fd
AH		 3283 /* Add the pauth registers. */
3284 if (feature_pauth != NULL)
3285 {
3286 first_pauth_regnum = num_regs;
34dcc7cf 3287 pauth_ra_state_offset = num_pseudo_regs;
76bed0fd
AH		 3288 /* Validate the descriptor provides the mandatory PAUTH registers and
3289 allocate their numbers. */
3290 for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
3291 valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data,
3292 first_pauth_regnum + i,
3293 aarch64_pauth_register_names[i]);
3294
3295 num_regs += i;
34dcc7cf 3296 num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
76bed0fd
AH		 3297 }
3298
07b287a0
MS		 3299 if (!valid_p)
3300 {
3301 tdesc_data_cleanup (tdesc_data);
ccb8d7e8 3302 return nullptr;
07b287a0
MS		 3303 }
3304
3305 /* AArch64 code is always little-endian. */
3306 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3307
ccb8d7e8
AH		 3308 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
3309 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
07b287a0
MS		 3310
3311 /* This should be low enough for everything. */
3312 tdep->lowest_pc = 0x20;
3313 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3314 tdep->jb_elt_size = 8;
4da037ef 3315 tdep->vq = vq;
76bed0fd 3316 tdep->pauth_reg_base = first_pauth_regnum;
34dcc7cf
AH		 3317 tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
3318 : pauth_ra_state_offset + num_regs;
3319
07b287a0
MS		 3320 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3321 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3322
07b287a0
MS		 3323 /* Advance PC across function entry code. */
3324 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3325
3326 /* The stack grows downward. */
3327 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3328
3329 /* Breakpoint manipulation. */
04180708
YQ		 3330 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3331 aarch64_breakpoint::kind_from_pc);
3332 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3333 aarch64_breakpoint::bp_from_kind);
07b287a0 3334 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3335 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3336
3337 /* Information about registers, etc. */
3338 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3339 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3340 set_gdbarch_num_regs (gdbarch, num_regs);
3341
3342 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3343 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3344 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3345 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3346 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3347 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3348 aarch64_pseudo_register_reggroup_p);
76bed0fd 3349 set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register);
07b287a0
MS		 3350
3351 /* ABI */
3352 set_gdbarch_short_bit (gdbarch, 16);
3353 set_gdbarch_int_bit (gdbarch, 32);
3354 set_gdbarch_float_bit (gdbarch, 32);
3355 set_gdbarch_double_bit (gdbarch, 64);
3356 set_gdbarch_long_double_bit (gdbarch, 128);
3357 set_gdbarch_long_bit (gdbarch, 64);
3358 set_gdbarch_long_long_bit (gdbarch, 64);
3359 set_gdbarch_ptr_bit (gdbarch, 64);
3360 set_gdbarch_char_signed (gdbarch, 0);
53375380 3361 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3362 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3363 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3364 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
b907456c 3365 set_gdbarch_type_align (gdbarch, aarch64_type_align);
07b287a0
MS		 3366
3367 /* Internal <-> external register number maps. */
3368 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3369
3370 /* Returning results. */
3371 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3372
3373 /* Disassembly. */
3374 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3375
3376 /* Virtual tables. */
3377 set_gdbarch_vbit_in_delta (gdbarch, 1);
3378
0ef8a082
AH		 3379 /* Register architecture. */
3380 aarch64_add_reggroups (gdbarch);
3381
07b287a0
MS		 3382 /* Hook in the ABI-specific overrides, if they have been registered. */
3383 info.target_desc = tdesc;
0dba2a6c 3384 info.tdesc_data = tdesc_data;
07b287a0
MS		 3385 gdbarch_init_osabi (info, gdbarch);
3386
3387 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
11e1b75f
AH		 3388 /* Register DWARF CFA vendor handler. */
3389 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
3390 aarch64_execute_dwarf_cfa_vendor_op);
07b287a0
MS		 3391
3392 /* Add some default predicates. */
3393 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3394 dwarf2_append_unwinders (gdbarch);
3395 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3396
3397 frame_base_set_default (gdbarch, &aarch64_normal_base);
3398
3399 /* Now we have tuned the configuration, set a few final things,
3400 based on what the OS ABI has told us. */
3401
3402 if (tdep->jb_pc >= 0)
3403 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3404
ea873d8e
PL		 3405 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3406
aa7ca1bb
AH		 3407 set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags);
3408
07b287a0
MS		 3409 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3410
3411 /* Add standard register aliases. */
3412 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3413 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3414 value_of_aarch64_user_reg,
3415 &aarch64_register_aliases[i].regnum);
3416
e8bf1ce4
JB		 3417 register_aarch64_ravenscar_ops (gdbarch);
3418
07b287a0
MS		 3419 return gdbarch;
3420}
3421
3422static void
3423aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3424{
3425 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3426
3427 if (tdep == NULL)
3428 return;
3429
3430 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3431 paddress (gdbarch, tdep->lowest_pc));
3432}
3433
0d4c07af 3434#if GDB_SELF_TEST
1e2b521d
YQ		 3435namespace selftests
3436{
3437static void aarch64_process_record_test (void);
3438}
0d4c07af 3439#endif
1e2b521d 3440
6c265988 3441void _initialize_aarch64_tdep ();
07b287a0 3442void
6c265988 3443_initialize_aarch64_tdep ()
07b287a0
MS		 3444{
3445 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3446 aarch64_dump_tdep);
3447
07b287a0
MS		 3448 /* Debug this file's internals. */
3449 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3450Set AArch64 debugging."), _("\
3451Show AArch64 debugging."), _("\
3452When on, AArch64 specific debugging is enabled."),
3453 NULL,
3454 show_aarch64_debug,
3455 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3456
3457#if GDB_SELF_TEST
1526853e
SM		 3458 selftests::register_test ("aarch64-analyze-prologue",
3459 selftests::aarch64_analyze_prologue_test);
3460 selftests::register_test ("aarch64-process-record",
3461 selftests::aarch64_process_record_test);
4d9a9006 3462#endif
07b287a0 3463}
99afc88b
OJ		 3464
3465/* AArch64 process record-replay related structures, defines etc. */
3466
99afc88b
OJ		 3467#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3468 do \
3469 { \
3470 unsigned int reg_len = LENGTH; \
3471 if (reg_len) \
3472 { \
3473 REGS = XNEWVEC (uint32_t, reg_len); \
3474 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3475 } \
3476 } \
3477 while (0)
3478
3479#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3480 do \
3481 { \
3482 unsigned int mem_len = LENGTH; \
3483 if (mem_len) \
3484 { \
3485 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3486 memcpy(&MEMS->len, &RECORD_BUF[0], \
3487 sizeof(struct aarch64_mem_r) * LENGTH); \
3488 } \
3489 } \
3490 while (0)
3491
3492/* AArch64 record/replay structures and enumerations. */
3493
3494struct aarch64_mem_r
3495{
3496 uint64_t len; /* Record length. */
3497 uint64_t addr; /* Memory address. */
3498};
3499
3500enum aarch64_record_result
3501{
3502 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3503 AARCH64_RECORD_UNSUPPORTED,
3504 AARCH64_RECORD_UNKNOWN
3505};
3506
3507typedef struct insn_decode_record_t
3508{
3509 struct gdbarch *gdbarch;
3510 struct regcache *regcache;
3511 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3512 uint32_t aarch64_insn; /* Insn to be recorded. */
3513 uint32_t mem_rec_count; /* Count of memory records. */
3514 uint32_t reg_rec_count; /* Count of register records. */
3515 uint32_t *aarch64_regs; /* Registers to be recorded. */
3516 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3517} insn_decode_record;
3518
3519/* Record handler for data processing - register instructions. */
3520
3521static unsigned int
3522aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3523{
3524 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3525 uint32_t record_buf[4];
3526
3527 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3528 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3529 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3530
3531 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3532 {
3533 uint8_t setflags;
3534
3535 /* Logical (shifted register). */
3536 if (insn_bits24_27 == 0x0a)
3537 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3538 /* Add/subtract. */
3539 else if (insn_bits24_27 == 0x0b)
3540 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3541 else
3542 return AARCH64_RECORD_UNKNOWN;
3543
3544 record_buf[0] = reg_rd;
3545 aarch64_insn_r->reg_rec_count = 1;
3546 if (setflags)
3547 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3548 }
3549 else
3550 {
3551 if (insn_bits24_27 == 0x0b)
3552 {
3553 /* Data-processing (3 source). */
3554 record_buf[0] = reg_rd;
3555 aarch64_insn_r->reg_rec_count = 1;
3556 }
3557 else if (insn_bits24_27 == 0x0a)
3558 {
3559 if (insn_bits21_23 == 0x00)
3560 {
3561 /* Add/subtract (with carry). */
3562 record_buf[0] = reg_rd;
3563 aarch64_insn_r->reg_rec_count = 1;
3564 if (bit (aarch64_insn_r->aarch64_insn, 29))
3565 {
3566 record_buf[1] = AARCH64_CPSR_REGNUM;
3567 aarch64_insn_r->reg_rec_count = 2;
3568 }
3569 }
3570 else if (insn_bits21_23 == 0x02)
3571 {
3572 /* Conditional compare (register) and conditional compare
3573 (immediate) instructions. */
3574 record_buf[0] = AARCH64_CPSR_REGNUM;
3575 aarch64_insn_r->reg_rec_count = 1;
3576 }
3577 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3578 {
85102364 3579 /* Conditional select. */
99afc88b
OJ		 3580 /* Data-processing (2 source). */
3581 /* Data-processing (1 source). */
3582 record_buf[0] = reg_rd;
3583 aarch64_insn_r->reg_rec_count = 1;
3584 }
3585 else
3586 return AARCH64_RECORD_UNKNOWN;
3587 }
3588 }
3589
3590 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3591 record_buf);
3592 return AARCH64_RECORD_SUCCESS;
3593}
3594
3595/* Record handler for data processing - immediate instructions. */
3596
3597static unsigned int
3598aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3599{
78cc6c2d 3600 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3601 uint32_t record_buf[4];
3602
3603 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3604 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3605 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3606
3607 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3608 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3609 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3610 {
3611 record_buf[0] = reg_rd;
3612 aarch64_insn_r->reg_rec_count = 1;
3613 }
3614 else if (insn_bits24_27 == 0x01)
3615 {
3616 /* Add/Subtract (immediate). */
3617 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3618 record_buf[0] = reg_rd;
3619 aarch64_insn_r->reg_rec_count = 1;
3620 if (setflags)
3621 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3622 }
3623 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3624 {
3625 /* Logical (immediate). */
3626 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3627 record_buf[0] = reg_rd;
3628 aarch64_insn_r->reg_rec_count = 1;
3629 if (setflags)
3630 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3631 }
3632 else
3633 return AARCH64_RECORD_UNKNOWN;
3634
3635 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3636 record_buf);
3637 return AARCH64_RECORD_SUCCESS;
3638}
3639
3640/* Record handler for branch, exception generation and system instructions. */
3641
3642static unsigned int
3643aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3644{
3645 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3646 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3647 uint32_t record_buf[4];
3648
3649 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3650 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3651 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3652
3653 if (insn_bits28_31 == 0x0d)
3654 {
3655 /* Exception generation instructions. */
3656 if (insn_bits24_27 == 0x04)
3657 {
5d98d3cd
YQ		 3658 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3659 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3660 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3661 {
3662 ULONGEST svc_number;
3663
3664 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3665 &svc_number);
3666 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3667 svc_number);
3668 }
3669 else
3670 return AARCH64_RECORD_UNSUPPORTED;
3671 }
3672 /* System instructions. */
3673 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3674 {
3675 uint32_t reg_rt, reg_crn;
3676
3677 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3678 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3679
3680 /* Record rt in case of sysl and mrs instructions. */
3681 if (bit (aarch64_insn_r->aarch64_insn, 21))
3682 {
3683 record_buf[0] = reg_rt;
3684 aarch64_insn_r->reg_rec_count = 1;
3685 }
3686 /* Record cpsr for hint and msr(immediate) instructions. */
3687 else if (reg_crn == 0x02 || reg_crn == 0x04)
3688 {
3689 record_buf[0] = AARCH64_CPSR_REGNUM;
3690 aarch64_insn_r->reg_rec_count = 1;
3691 }
3692 }
3693 /* Unconditional branch (register). */
3694 else if((insn_bits24_27 & 0x0e) == 0x06)
3695 {
3696 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3697 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3698 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3699 }
3700 else
3701 return AARCH64_RECORD_UNKNOWN;
3702 }
3703 /* Unconditional branch (immediate). */
3704 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3705 {
3706 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3707 if (bit (aarch64_insn_r->aarch64_insn, 31))
3708 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3709 }
3710 else
3711 /* Compare & branch (immediate), Test & branch (immediate) and
3712 Conditional branch (immediate). */
3713 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3714
3715 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3716 record_buf);
3717 return AARCH64_RECORD_SUCCESS;
3718}
3719
3720/* Record handler for advanced SIMD load and store instructions. */
3721
3722static unsigned int
3723aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3724{
3725 CORE_ADDR address;
3726 uint64_t addr_offset = 0;
3727 uint32_t record_buf[24];
3728 uint64_t record_buf_mem[24];
3729 uint32_t reg_rn, reg_rt;
3730 uint32_t reg_index = 0, mem_index = 0;
3731 uint8_t opcode_bits, size_bits;
3732
3733 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3734 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3735 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3736 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3737 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3738
3739 if (record_debug)
b277c936 3740 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3741
3742 /* Load/store single structure. */
3743 if (bit (aarch64_insn_r->aarch64_insn, 24))
3744 {
3745 uint8_t sindex, scale, selem, esize, replicate = 0;
3746 scale = opcode_bits >> 2;
3747 selem = ((opcode_bits & 0x02) |
3748 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3749 switch (scale)
3750 {
3751 case 1:
3752 if (size_bits & 0x01)
3753 return AARCH64_RECORD_UNKNOWN;
3754 break;
3755 case 2:
3756 if ((size_bits >> 1) & 0x01)
3757 return AARCH64_RECORD_UNKNOWN;
3758 if (size_bits & 0x01)
3759 {
3760 if (!((opcode_bits >> 1) & 0x01))
3761 scale = 3;
3762 else
3763 return AARCH64_RECORD_UNKNOWN;
3764 }
3765 break;
3766 case 3:
3767 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3768 {
3769 scale = size_bits;
3770 replicate = 1;
3771 break;
3772 }
3773 else
3774 return AARCH64_RECORD_UNKNOWN;
3775 default:
3776 break;
3777 }
3778 esize = 8 << scale;
3779 if (replicate)
3780 for (sindex = 0; sindex < selem; sindex++)
3781 {
3782 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3783 reg_rt = (reg_rt + 1) % 32;
3784 }
3785 else
3786 {
3787 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3788 {
3789 if (bit (aarch64_insn_r->aarch64_insn, 22))
3790 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3791 else
3792 {
3793 record_buf_mem[mem_index++] = esize / 8;
3794 record_buf_mem[mem_index++] = address + addr_offset;
3795 }
3796 addr_offset = addr_offset + (esize / 8);
3797 reg_rt = (reg_rt + 1) % 32;
3798 }
99afc88b
OJ		 3799 }
3800 }
3801 /* Load/store multiple structure. */
3802 else
3803 {
3804 uint8_t selem, esize, rpt, elements;
3805 uint8_t eindex, rindex;
3806
3807 esize = 8 << size_bits;
3808 if (bit (aarch64_insn_r->aarch64_insn, 30))
3809 elements = 128 / esize;
3810 else
3811 elements = 64 / esize;
3812
3813 switch (opcode_bits)
3814 {
3815 /*LD/ST4 (4 Registers). */
3816 case 0:
3817 rpt = 1;
3818 selem = 4;
3819 break;
3820 /*LD/ST1 (4 Registers). */
3821 case 2:
3822 rpt = 4;
3823 selem = 1;
3824 break;
3825 /*LD/ST3 (3 Registers). */
3826 case 4:
3827 rpt = 1;
3828 selem = 3;
3829 break;
3830 /*LD/ST1 (3 Registers). */
3831 case 6:
3832 rpt = 3;
3833 selem = 1;
3834 break;
3835 /*LD/ST1 (1 Register). */
3836 case 7:
3837 rpt = 1;
3838 selem = 1;
3839 break;
3840 /*LD/ST2 (2 Registers). */
3841 case 8:
3842 rpt = 1;
3843 selem = 2;
3844 break;
3845 /*LD/ST1 (2 Registers). */
3846 case 10:
3847 rpt = 2;
3848 selem = 1;
3849 break;
3850 default:
3851 return AARCH64_RECORD_UNSUPPORTED;
3852 break;
3853 }
3854 for (rindex = 0; rindex < rpt; rindex++)
3855 for (eindex = 0; eindex < elements; eindex++)
3856 {
3857 uint8_t reg_tt, sindex;
3858 reg_tt = (reg_rt + rindex) % 32;
3859 for (sindex = 0; sindex < selem; sindex++)
3860 {
3861 if (bit (aarch64_insn_r->aarch64_insn, 22))
3862 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3863 else
3864 {
3865 record_buf_mem[mem_index++] = esize / 8;
3866 record_buf_mem[mem_index++] = address + addr_offset;
3867 }
3868 addr_offset = addr_offset + (esize / 8);
3869 reg_tt = (reg_tt + 1) % 32;
3870 }
3871 }
3872 }
3873
3874 if (bit (aarch64_insn_r->aarch64_insn, 23))
3875 record_buf[reg_index++] = reg_rn;
3876
3877 aarch64_insn_r->reg_rec_count = reg_index;
3878 aarch64_insn_r->mem_rec_count = mem_index / 2;
3879 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3880 record_buf_mem);
3881 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3882 record_buf);
3883 return AARCH64_RECORD_SUCCESS;
3884}
3885
3886/* Record handler for load and store instructions. */
3887
3888static unsigned int
3889aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3890{
3891 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3892 uint8_t insn_bit23, insn_bit21;
3893 uint8_t opc, size_bits, ld_flag, vector_flag;
3894 uint32_t reg_rn, reg_rt, reg_rt2;
3895 uint64_t datasize, offset;
3896 uint32_t record_buf[8];
3897 uint64_t record_buf_mem[8];
3898 CORE_ADDR address;
3899
3900 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3901 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3902 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3903 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3904 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3905 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3906 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3907 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3908 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3909 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3910 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3911
3912 /* Load/store exclusive. */
3913 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3914 {
3915 if (record_debug)
b277c936 3916 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3917
3918 if (ld_flag)
3919 {
3920 record_buf[0] = reg_rt;
3921 aarch64_insn_r->reg_rec_count = 1;
3922 if (insn_bit21)
3923 {
3924 record_buf[1] = reg_rt2;
3925 aarch64_insn_r->reg_rec_count = 2;
3926 }
3927 }
3928 else
3929 {
3930 if (insn_bit21)
3931 datasize = (8 << size_bits) * 2;
3932 else
3933 datasize = (8 << size_bits);
3934 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3935 &address);
3936 record_buf_mem[0] = datasize / 8;
3937 record_buf_mem[1] = address;
3938 aarch64_insn_r->mem_rec_count = 1;
3939 if (!insn_bit23)
3940 {
3941 /* Save register rs. */
3942 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3943 aarch64_insn_r->reg_rec_count = 1;
3944 }
3945 }
3946 }
3947 /* Load register (literal) instructions decoding. */
3948 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3949 {
3950 if (record_debug)
b277c936 3951 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3952 if (vector_flag)
3953 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3954 else
3955 record_buf[0] = reg_rt;
3956 aarch64_insn_r->reg_rec_count = 1;
3957 }
3958 /* All types of load/store pair instructions decoding. */
3959 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3960 {
3961 if (record_debug)
b277c936 3962 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 3963
3964 if (ld_flag)
3965 {
3966 if (vector_flag)
3967 {
3968 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3969 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3970 }
3971 else
3972 {
3973 record_buf[0] = reg_rt;
3974 record_buf[1] = reg_rt2;
3975 }
3976 aarch64_insn_r->reg_rec_count = 2;
3977 }
3978 else
3979 {
3980 uint16_t imm7_off;
3981 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3982 if (!vector_flag)
3983 size_bits = size_bits >> 1;
3984 datasize = 8 << (2 + size_bits);
3985 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3986 offset = offset << (2 + size_bits);
3987 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3988 &address);
3989 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3990 {
3991 if (imm7_off & 0x40)
3992 address = address - offset;
3993 else
3994 address = address + offset;
3995 }
3996
3997 record_buf_mem[0] = datasize / 8;
3998 record_buf_mem[1] = address;
3999 record_buf_mem[2] = datasize / 8;
4000 record_buf_mem[3] = address + (datasize / 8);
4001 aarch64_insn_r->mem_rec_count = 2;
4002 }
4003 if (bit (aarch64_insn_r->aarch64_insn, 23))
4004 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4005 }
4006 /* Load/store register (unsigned immediate) instructions. */
4007 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
4008 {
4009 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4010 if (!(opc >> 1))
33877125
YQ		 4011 {
4012 if (opc & 0x01)
4013 ld_flag = 0x01;
4014 else
4015 ld_flag = 0x0;
4016 }
99afc88b 4017 else
33877125 4018 {
1e2b521d
YQ		 4019 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
4020 {
4021 /* PRFM (immediate) */
4022 return AARCH64_RECORD_SUCCESS;
4023 }
4024 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
4025 {
4026 /* LDRSW (immediate) */
4027 ld_flag = 0x1;
4028 }
33877125 4029 else
1e2b521d
YQ		 4030 {
4031 if (opc & 0x01)
4032 ld_flag = 0x01;
4033 else
4034 ld_flag = 0x0;
4035 }
33877125 4036 }
99afc88b
OJ		 4037
4038 if (record_debug)
4039 {
b277c936
PL		 4040 debug_printf ("Process record: load/store (unsigned immediate):"
4041 " size %x V %d opc %x\n", size_bits, vector_flag,
4042 opc);
99afc88b
OJ		 4043 }
4044
4045 if (!ld_flag)
4046 {
4047 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
4048 datasize = 8 << size_bits;
4049 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4050 &address);
4051 offset = offset << size_bits;
4052 address = address + offset;
4053
4054 record_buf_mem[0] = datasize >> 3;
4055 record_buf_mem[1] = address;
4056 aarch64_insn_r->mem_rec_count = 1;
4057 }
4058 else
4059 {
4060 if (vector_flag)
4061 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4062 else
4063 record_buf[0] = reg_rt;
4064 aarch64_insn_r->reg_rec_count = 1;
4065 }
4066 }
4067 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 4068 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4069 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 4070 {
4071 if (record_debug)
b277c936 4072 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 4073 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4074 if (!(opc >> 1))
4075 if (opc & 0x01)
4076 ld_flag = 0x01;
4077 else
4078 ld_flag = 0x0;
4079 else
4080 if (size_bits != 0x03)
4081 ld_flag = 0x01;
4082 else
4083 return AARCH64_RECORD_UNKNOWN;
4084
4085 if (!ld_flag)
4086 {
d9436c7c
PA		 4087 ULONGEST reg_rm_val;
4088
99afc88b
OJ		 4089 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
4090 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
4091 if (bit (aarch64_insn_r->aarch64_insn, 12))
4092 offset = reg_rm_val << size_bits;
4093 else
4094 offset = reg_rm_val;
4095 datasize = 8 << size_bits;
4096 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4097 &address);
4098 address = address + offset;
4099 record_buf_mem[0] = datasize >> 3;
4100 record_buf_mem[1] = address;
4101 aarch64_insn_r->mem_rec_count = 1;
4102 }
4103 else
4104 {
4105 if (vector_flag)
4106 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4107 else
4108 record_buf[0] = reg_rt;
4109 aarch64_insn_r->reg_rec_count = 1;
4110 }
4111 }
4112 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 4113 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4114 && !insn_bit21)
99afc88b
OJ		 4115 {
4116 if (record_debug)
4117 {
b277c936
PL		 4118 debug_printf ("Process record: load/store "
4119 "(immediate and unprivileged)\n");
99afc88b
OJ		 4120 }
4121 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4122 if (!(opc >> 1))
4123 if (opc & 0x01)
4124 ld_flag = 0x01;
4125 else
4126 ld_flag = 0x0;
4127 else
4128 if (size_bits != 0x03)
4129 ld_flag = 0x01;
4130 else
4131 return AARCH64_RECORD_UNKNOWN;
4132
4133 if (!ld_flag)
4134 {
4135 uint16_t imm9_off;
4136 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
4137 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
4138 datasize = 8 << size_bits;
4139 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4140 &address);
4141 if (insn_bits10_11 != 0x01)
4142 {
4143 if (imm9_off & 0x0100)
4144 address = address - offset;
4145 else
4146 address = address + offset;
4147 }
4148 record_buf_mem[0] = datasize >> 3;
4149 record_buf_mem[1] = address;
4150 aarch64_insn_r->mem_rec_count = 1;
4151 }
4152 else
4153 {
4154 if (vector_flag)
4155 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4156 else
4157 record_buf[0] = reg_rt;
4158 aarch64_insn_r->reg_rec_count = 1;
4159 }
4160 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
4161 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4162 }
4163 /* Advanced SIMD load/store instructions. */
4164 else
4165 return aarch64_record_asimd_load_store (aarch64_insn_r);
4166
4167 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
4168 record_buf_mem);
4169 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4170 record_buf);
4171 return AARCH64_RECORD_SUCCESS;
4172}
4173
4174/* Record handler for data processing SIMD and floating point instructions. */
4175
4176static unsigned int
4177aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
4178{
4179 uint8_t insn_bit21, opcode, rmode, reg_rd;
4180 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
4181 uint8_t insn_bits11_14;
4182 uint32_t record_buf[2];
4183
4184 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4185 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
4186 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4187 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
4188 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
4189 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
4190 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
4191 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4192 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4193
4194 if (record_debug)
b277c936 4195 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 4196
4197 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
4198 {
4199 /* Floating point - fixed point conversion instructions. */
4200 if (!insn_bit21)
4201 {
4202 if (record_debug)
b277c936 4203 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 4204
4205 if ((opcode >> 1) == 0x0 && rmode == 0x03)
4206 record_buf[0] = reg_rd;
4207 else
4208 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4209 }
4210 /* Floating point - conditional compare instructions. */
4211 else if (insn_bits10_11 == 0x01)
4212 {
4213 if (record_debug)
b277c936 4214 debug_printf ("FP - conditional compare");
99afc88b
OJ		 4215
4216 record_buf[0] = AARCH64_CPSR_REGNUM;
4217 }
4218 /* Floating point - data processing (2-source) and
4219 conditional select instructions. */
4220 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
4221 {
4222 if (record_debug)
b277c936 4223 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 4224
4225 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4226 }
4227 else if (insn_bits10_11 == 0x00)
4228 {
4229 /* Floating point - immediate instructions. */
4230 if ((insn_bits12_15 & 0x01) == 0x01
4231 || (insn_bits12_15 & 0x07) == 0x04)
4232 {
4233 if (record_debug)
b277c936 4234 debug_printf ("FP - immediate");
99afc88b
OJ		 4235 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4236 }
4237 /* Floating point - compare instructions. */
4238 else if ((insn_bits12_15 & 0x03) == 0x02)
4239 {
4240 if (record_debug)
b277c936 4241 debug_printf ("FP - immediate");
99afc88b
OJ		 4242 record_buf[0] = AARCH64_CPSR_REGNUM;
4243 }
4244 /* Floating point - integer conversions instructions. */
f62fce35 4245 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 4246 {
4247 /* Convert float to integer instruction. */
4248 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4249 {
4250 if (record_debug)
b277c936 4251 debug_printf ("float to int conversion");
99afc88b
OJ		 4252
4253 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4254 }
4255 /* Convert integer to float instruction. */
4256 else if ((opcode >> 1) == 0x01 && !rmode)
4257 {
4258 if (record_debug)
b277c936 4259 debug_printf ("int to float conversion");
99afc88b
OJ		 4260
4261 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4262 }
4263 /* Move float to integer instruction. */
4264 else if ((opcode >> 1) == 0x03)
4265 {
4266 if (record_debug)
b277c936 4267 debug_printf ("move float to int");
99afc88b
OJ		 4268
4269 if (!(opcode & 0x01))
4270 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4271 else
4272 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4273 }
f62fce35
YQ		 4274 else
4275 return AARCH64_RECORD_UNKNOWN;
99afc88b 4276 }
f62fce35
YQ		 4277 else
4278 return AARCH64_RECORD_UNKNOWN;
99afc88b 4279 }
f62fce35
YQ		 4280 else
4281 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4282 }
4283 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4284 {
4285 if (record_debug)
b277c936 4286 debug_printf ("SIMD copy");
99afc88b
OJ		 4287
4288 /* Advanced SIMD copy instructions. */
4289 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4290 && !bit (aarch64_insn_r->aarch64_insn, 15)
4291 && bit (aarch64_insn_r->aarch64_insn, 10))
4292 {
4293 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4294 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4295 else
4296 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4297 }
4298 else
4299 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4300 }
4301 /* All remaining floating point or advanced SIMD instructions. */
4302 else
4303 {
4304 if (record_debug)
b277c936 4305 debug_printf ("all remain");
99afc88b
OJ		 4306
4307 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4308 }
4309
4310 if (record_debug)
b277c936 4311 debug_printf ("\n");
99afc88b
OJ		 4312
4313 aarch64_insn_r->reg_rec_count++;
4314 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4315 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4316 record_buf);
4317 return AARCH64_RECORD_SUCCESS;
4318}
4319
4320/* Decodes insns type and invokes its record handler. */
4321
4322static unsigned int
4323aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4324{
4325 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4326
4327 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4328 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4329 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4330 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4331
4332 /* Data processing - immediate instructions. */
4333 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4334 return aarch64_record_data_proc_imm (aarch64_insn_r);
4335
4336 /* Branch, exception generation and system instructions. */
4337 if (ins_bit26 && !ins_bit27 && ins_bit28)
4338 return aarch64_record_branch_except_sys (aarch64_insn_r);
4339
4340 /* Load and store instructions. */
4341 if (!ins_bit25 && ins_bit27)
4342 return aarch64_record_load_store (aarch64_insn_r);
4343
4344 /* Data processing - register instructions. */
4345 if (ins_bit25 && !ins_bit26 && ins_bit27)
4346 return aarch64_record_data_proc_reg (aarch64_insn_r);
4347
4348 /* Data processing - SIMD and floating point instructions. */
4349 if (ins_bit25 && ins_bit26 && ins_bit27)
4350 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4351
4352 return AARCH64_RECORD_UNSUPPORTED;
4353}
4354
4355/* Cleans up local record registers and memory allocations. */
4356
4357static void
4358deallocate_reg_mem (insn_decode_record *record)
4359{
4360 xfree (record->aarch64_regs);
4361 xfree (record->aarch64_mems);
4362}
4363
1e2b521d
YQ		 4364#if GDB_SELF_TEST
4365namespace selftests {
4366
4367static void
4368aarch64_process_record_test (void)
4369{
4370 struct gdbarch_info info;
4371 uint32_t ret;
4372
4373 gdbarch_info_init (&info);
4374 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4375
4376 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4377 SELF_CHECK (gdbarch != NULL);
4378
4379 insn_decode_record aarch64_record;
4380
4381 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4382 aarch64_record.regcache = NULL;
4383 aarch64_record.this_addr = 0;
4384 aarch64_record.gdbarch = gdbarch;
4385
4386 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4387 aarch64_record.aarch64_insn = 0xf9800020;
4388 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4389 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4390 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4391 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4392
4393 deallocate_reg_mem (&aarch64_record);
4394}
4395
4396} // namespace selftests
4397#endif /* GDB_SELF_TEST */
4398
99afc88b
OJ		 4399/* Parse the current instruction and record the values of the registers and
4400 memory that will be changed in current instruction to record_arch_list
4401 return -1 if something is wrong. */
4402
4403int
4404aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4405 CORE_ADDR insn_addr)
4406{
4407 uint32_t rec_no = 0;
4408 uint8_t insn_size = 4;
4409 uint32_t ret = 0;
99afc88b
OJ		 4410 gdb_byte buf[insn_size];
4411 insn_decode_record aarch64_record;
4412
4413 memset (&buf[0], 0, insn_size);
4414 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4415 target_read_memory (insn_addr, &buf[0], insn_size);
4416 aarch64_record.aarch64_insn
4417 = (uint32_t) extract_unsigned_integer (&buf[0],
4418 insn_size,
4419 gdbarch_byte_order (gdbarch));
4420 aarch64_record.regcache = regcache;
4421 aarch64_record.this_addr = insn_addr;
4422 aarch64_record.gdbarch = gdbarch;
4423
4424 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4425 if (ret == AARCH64_RECORD_UNSUPPORTED)
4426 {
4427 printf_unfiltered (_("Process record does not support instruction "
4428 "0x%0x at address %s.\n"),
4429 aarch64_record.aarch64_insn,
4430 paddress (gdbarch, insn_addr));
4431 ret = -1;
4432 }
4433
4434 if (0 == ret)
4435 {
4436 /* Record registers. */
4437 record_full_arch_list_add_reg (aarch64_record.regcache,
4438 AARCH64_PC_REGNUM);
4439 /* Always record register CPSR. */
4440 record_full_arch_list_add_reg (aarch64_record.regcache,
4441 AARCH64_CPSR_REGNUM);
4442 if (aarch64_record.aarch64_regs)
4443 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4444 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4445 aarch64_record.aarch64_regs[rec_no]))
4446 ret = -1;
4447
4448 /* Record memories. */
4449 if (aarch64_record.aarch64_mems)
4450 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4451 if (record_full_arch_list_add_mem
4452 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4453 aarch64_record.aarch64_mems[rec_no].len))
4454 ret = -1;
4455
4456 if (record_full_arch_list_add_end ())
4457 ret = -1;
4458 }
4459
4460 deallocate_reg_mem (&aarch64_record);
4461 return ret;
4462}
GDB Binutils - Deliverables
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