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Move "watchdog" to remote.c
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
42a4f53d 3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
4de283e4 24#include "inferior.h"
07b287a0
MS		 25#include "gdbcmd.h"
26#include "gdbcore.h"
4de283e4 27#include "dis-asm.h"
d55e5aa6
TT		 28#include "regcache.h"
29#include "reggroups.h"
4de283e4
TT		 30#include "value.h"
31#include "arch-utils.h"
32#include "osabi.h"
33#include "frame-unwind.h"
34#include "frame-base.h"
d55e5aa6 35#include "trad-frame.h"
4de283e4
TT		 36#include "objfiles.h"
37#include "dwarf2.h"
38#include "dwarf2-frame.h"
39#include "gdbtypes.h"
40#include "prologue-value.h"
41#include "target-descriptions.h"
07b287a0 42#include "user-regs.h"
4de283e4
TT		 43#include "language.h"
44#include "infcall.h"
45#include "ax.h"
46#include "ax-gdb.h"
47#include "common/selftest.h"
48
49#include "aarch64-tdep.h"
50#include "aarch64-ravenscar-thread.h"
51
52#include "elf-bfd.h"
53#include "elf/aarch64.h"
54
55#include "common/vec.h"
56
57#include "record.h"
58#include "record-full.h"
59#include "arch/aarch64-insn.h"
60
61#include "opcode/aarch64.h"
62#include <algorithm>
f77ee802
YQ		 63
64#define submask(x) ((1L << ((x) + 1)) - 1)
65#define bit(obj,st) (((obj) >> (st)) & 1)
66#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
67
ea92689a
AH		 68/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
69 four members. */
70#define HA_MAX_NUM_FLDS 4
71
95228a0d 72/* All possible aarch64 target descriptors. */
6dc0ebde 73struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/];
95228a0d 74
07b287a0
MS		 75/* The standard register names, and all the valid aliases for them. */
76static const struct
77{
78 const char *const name;
79 int regnum;
80} aarch64_register_aliases[] =
81{
82 /* 64-bit register names. */
83 {"fp", AARCH64_FP_REGNUM},
84 {"lr", AARCH64_LR_REGNUM},
85 {"sp", AARCH64_SP_REGNUM},
86
87 /* 32-bit register names. */
88 {"w0", AARCH64_X0_REGNUM + 0},
89 {"w1", AARCH64_X0_REGNUM + 1},
90 {"w2", AARCH64_X0_REGNUM + 2},
91 {"w3", AARCH64_X0_REGNUM + 3},
92 {"w4", AARCH64_X0_REGNUM + 4},
93 {"w5", AARCH64_X0_REGNUM + 5},
94 {"w6", AARCH64_X0_REGNUM + 6},
95 {"w7", AARCH64_X0_REGNUM + 7},
96 {"w8", AARCH64_X0_REGNUM + 8},
97 {"w9", AARCH64_X0_REGNUM + 9},
98 {"w10", AARCH64_X0_REGNUM + 10},
99 {"w11", AARCH64_X0_REGNUM + 11},
100 {"w12", AARCH64_X0_REGNUM + 12},
101 {"w13", AARCH64_X0_REGNUM + 13},
102 {"w14", AARCH64_X0_REGNUM + 14},
103 {"w15", AARCH64_X0_REGNUM + 15},
104 {"w16", AARCH64_X0_REGNUM + 16},
105 {"w17", AARCH64_X0_REGNUM + 17},
106 {"w18", AARCH64_X0_REGNUM + 18},
107 {"w19", AARCH64_X0_REGNUM + 19},
108 {"w20", AARCH64_X0_REGNUM + 20},
109 {"w21", AARCH64_X0_REGNUM + 21},
110 {"w22", AARCH64_X0_REGNUM + 22},
111 {"w23", AARCH64_X0_REGNUM + 23},
112 {"w24", AARCH64_X0_REGNUM + 24},
113 {"w25", AARCH64_X0_REGNUM + 25},
114 {"w26", AARCH64_X0_REGNUM + 26},
115 {"w27", AARCH64_X0_REGNUM + 27},
116 {"w28", AARCH64_X0_REGNUM + 28},
117 {"w29", AARCH64_X0_REGNUM + 29},
118 {"w30", AARCH64_X0_REGNUM + 30},
119
120 /* specials */
121 {"ip0", AARCH64_X0_REGNUM + 16},
122 {"ip1", AARCH64_X0_REGNUM + 17}
123};
124
125/* The required core 'R' registers. */
126static const char *const aarch64_r_register_names[] =
127{
128 /* These registers must appear in consecutive RAW register number
129 order and they must begin with AARCH64_X0_REGNUM! */
130 "x0", "x1", "x2", "x3",
131 "x4", "x5", "x6", "x7",
132 "x8", "x9", "x10", "x11",
133 "x12", "x13", "x14", "x15",
134 "x16", "x17", "x18", "x19",
135 "x20", "x21", "x22", "x23",
136 "x24", "x25", "x26", "x27",
137 "x28", "x29", "x30", "sp",
138 "pc", "cpsr"
139};
140
141/* The FP/SIMD 'V' registers. */
142static const char *const aarch64_v_register_names[] =
143{
144 /* These registers must appear in consecutive RAW register number
145 order and they must begin with AARCH64_V0_REGNUM! */
146 "v0", "v1", "v2", "v3",
147 "v4", "v5", "v6", "v7",
148 "v8", "v9", "v10", "v11",
149 "v12", "v13", "v14", "v15",
150 "v16", "v17", "v18", "v19",
151 "v20", "v21", "v22", "v23",
152 "v24", "v25", "v26", "v27",
153 "v28", "v29", "v30", "v31",
154 "fpsr",
155 "fpcr"
156};
157
739e8682
AH		 158/* The SVE 'Z' and 'P' registers. */
159static const char *const aarch64_sve_register_names[] =
160{
161 /* These registers must appear in consecutive RAW register number
162 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
163 "z0", "z1", "z2", "z3",
164 "z4", "z5", "z6", "z7",
165 "z8", "z9", "z10", "z11",
166 "z12", "z13", "z14", "z15",
167 "z16", "z17", "z18", "z19",
168 "z20", "z21", "z22", "z23",
169 "z24", "z25", "z26", "z27",
170 "z28", "z29", "z30", "z31",
171 "fpsr", "fpcr",
172 "p0", "p1", "p2", "p3",
173 "p4", "p5", "p6", "p7",
174 "p8", "p9", "p10", "p11",
175 "p12", "p13", "p14", "p15",
176 "ffr", "vg"
177};
178
76bed0fd
AH		 179static const char *const aarch64_pauth_register_names[] =
180{
181 /* Authentication mask for data pointer. */
182 "pauth_dmask",
183 /* Authentication mask for code pointer. */
184 "pauth_cmask"
185};
186
07b287a0
MS		 187/* AArch64 prologue cache structure. */
188struct aarch64_prologue_cache
189{
db634143
PL		 190 /* The program counter at the start of the function. It is used to
191 identify this frame as a prologue frame. */
192 CORE_ADDR func;
193
194 /* The program counter at the time this frame was created; i.e. where
195 this function was called from. It is used to identify this frame as a
196 stub frame. */
197 CORE_ADDR prev_pc;
198
07b287a0
MS		 199 /* The stack pointer at the time this frame was created; i.e. the
200 caller's stack pointer when this function was called. It is used
201 to identify this frame. */
202 CORE_ADDR prev_sp;
203
7dfa3edc
PL		 204 /* Is the target available to read from? */
205 int available_p;
206
07b287a0
MS		 207 /* The frame base for this frame is just prev_sp - frame size.
208 FRAMESIZE is the distance from the frame pointer to the
209 initial stack pointer. */
210 int framesize;
211
212 /* The register used to hold the frame pointer for this frame. */
213 int framereg;
214
215 /* Saved register offsets. */
216 struct trad_frame_saved_reg *saved_regs;
217};
218
07b287a0
MS		 219static void
220show_aarch64_debug (struct ui_file *file, int from_tty,
221 struct cmd_list_element *c, const char *value)
222{
223 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
224}
225
ffdbe864
YQ		 226namespace {
227
4d9a9006
YQ		 228/* Abstract instruction reader. */
229
230class abstract_instruction_reader
231{
232public:
233 /* Read in one instruction. */
234 virtual ULONGEST read (CORE_ADDR memaddr, int len,
235 enum bfd_endian byte_order) = 0;
236};
237
238/* Instruction reader from real target. */
239
240class instruction_reader : public abstract_instruction_reader
241{
242 public:
243 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 244 override
4d9a9006 245 {
fc2f703e 246 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 247 }
248};
249
ffdbe864
YQ		 250} // namespace
251
11e1b75f
AH		 252/* If address signing is enabled, mask off the signature bits from ADDR, using
253 the register values in THIS_FRAME. */
254
255static CORE_ADDR
256aarch64_frame_unmask_address (struct gdbarch_tdep *tdep,
257 struct frame_info *this_frame,
258 CORE_ADDR addr)
259{
260 if (tdep->has_pauth ()
261 && frame_unwind_register_unsigned (this_frame,
262 tdep->pauth_ra_state_regnum))
263 {
264 int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
265 CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
266 addr = addr & ~cmask;
267 }
268
269 return addr;
270}
271
07b287a0
MS		 272/* Analyze a prologue, looking for a recognizable stack frame
273 and frame pointer. Scan until we encounter a store that could
274 clobber the stack frame unexpectedly, or an unknown instruction. */
275
276static CORE_ADDR
277aarch64_analyze_prologue (struct gdbarch *gdbarch,
278 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 279 struct aarch64_prologue_cache *cache,
280 abstract_instruction_reader& reader)
07b287a0
MS		 281{
282 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
283 int i;
187f5d00
YQ		 284 /* Track X registers and D registers in prologue. */
285 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 286
187f5d00 287 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 288 regs[i] = pv_register (i, 0);
f7b7ed97 289 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 290
291 for (; start < limit; start += 4)
292 {
293 uint32_t insn;
d9ebcbce 294 aarch64_inst inst;
07b287a0 295
4d9a9006 296 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 297
561a72d4 298 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 299 break;
300
301 if (inst.opcode->iclass == addsub_imm
302 && (inst.opcode->op == OP_ADD
303 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 304 {
d9ebcbce
YQ		 305 unsigned rd = inst.operands[0].reg.regno;
306 unsigned rn = inst.operands[1].reg.regno;
307
308 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
309 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
310 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
311 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
312
313 if (inst.opcode->op == OP_ADD)
314 {
315 regs[rd] = pv_add_constant (regs[rn],
316 inst.operands[2].imm.value);
317 }
318 else
319 {
320 regs[rd] = pv_add_constant (regs[rn],
321 -inst.operands[2].imm.value);
322 }
323 }
324 else if (inst.opcode->iclass == pcreladdr
325 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
326 {
327 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
328 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
329
330 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 331 }
d9ebcbce 332 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 333 {
334 /* Stop analysis on branch. */
335 break;
336 }
d9ebcbce 337 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 338 {
339 /* Stop analysis on branch. */
340 break;
341 }
d9ebcbce 342 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 343 {
344 /* Stop analysis on branch. */
345 break;
346 }
d9ebcbce 347 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 348 {
349 /* Stop analysis on branch. */
350 break;
351 }
d9ebcbce
YQ		 352 else if (inst.opcode->op == OP_MOVZ)
353 {
354 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
355 regs[inst.operands[0].reg.regno] = pv_unknown ();
356 }
357 else if (inst.opcode->iclass == log_shift
358 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 359 {
d9ebcbce
YQ		 360 unsigned rd = inst.operands[0].reg.regno;
361 unsigned rn = inst.operands[1].reg.regno;
362 unsigned rm = inst.operands[2].reg.regno;
363
364 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
365 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
366 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
367
368 if (inst.operands[2].shifter.amount == 0
369 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 370 regs[rd] = regs[rm];
371 else
372 {
373 if (aarch64_debug)
b277c936
PL		 374 {
375 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 376 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 377 core_addr_to_string_nz (start), insn);
378 }
07b287a0
MS		 379 break;
380 }
381 }
d9ebcbce 382 else if (inst.opcode->op == OP_STUR)
07b287a0 383 {
d9ebcbce
YQ		 384 unsigned rt = inst.operands[0].reg.regno;
385 unsigned rn = inst.operands[1].addr.base_regno;
386 int is64
387 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
388
389 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
390 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
391 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
392 gdb_assert (!inst.operands[1].addr.offset.is_reg);
393
f7b7ed97
TT		 394 stack.store (pv_add_constant (regs[rn],
395 inst.operands[1].addr.offset.imm),
396 is64 ? 8 : 4, regs[rt]);
07b287a0 397 }
d9ebcbce 398 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 399 || (inst.opcode->iclass == ldstpair_indexed
400 && inst.operands[2].addr.preind))
d9ebcbce 401 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 402 {
03bcd739 403 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 404 unsigned rt1;
405 unsigned rt2;
d9ebcbce
YQ		 406 unsigned rn = inst.operands[2].addr.base_regno;
407 int32_t imm = inst.operands[2].addr.offset.imm;
408
187f5d00
YQ		 409 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
410 || inst.operands[0].type == AARCH64_OPND_Ft);
411 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
412 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 413 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
414 gdb_assert (!inst.operands[2].addr.offset.is_reg);
415
07b287a0
MS		 416 /* If recording this store would invalidate the store area
417 (perhaps because rn is not known) then we should abandon
418 further prologue analysis. */
f7b7ed97 419 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 420 break;
421
f7b7ed97 422 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 423 break;
424
187f5d00
YQ		 425 rt1 = inst.operands[0].reg.regno;
426 rt2 = inst.operands[1].reg.regno;
427 if (inst.operands[0].type == AARCH64_OPND_Ft)
428 {
429 /* Only bottom 64-bit of each V register (D register) need
430 to be preserved. */
431 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
432 rt1 += AARCH64_X_REGISTER_COUNT;
433 rt2 += AARCH64_X_REGISTER_COUNT;
434 }
435
f7b7ed97
TT		 436 stack.store (pv_add_constant (regs[rn], imm), 8,
437 regs[rt1]);
438 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
439 regs[rt2]);
14ac654f 440
d9ebcbce 441 if (inst.operands[2].addr.writeback)
93d96012 442 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 443
07b287a0 444 }
432ec081
YQ		 445 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
446 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
447 && (inst.opcode->op == OP_STR_POS
448 || inst.opcode->op == OP_STRF_POS)))
449 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
450 && strcmp ("str", inst.opcode->name) == 0)
451 {
452 /* STR (immediate) */
453 unsigned int rt = inst.operands[0].reg.regno;
454 int32_t imm = inst.operands[1].addr.offset.imm;
455 unsigned int rn = inst.operands[1].addr.base_regno;
456 bool is64
457 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
458 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
459 || inst.operands[0].type == AARCH64_OPND_Ft);
460
461 if (inst.operands[0].type == AARCH64_OPND_Ft)
462 {
463 /* Only bottom 64-bit of each V register (D register) need
464 to be preserved. */
465 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
466 rt += AARCH64_X_REGISTER_COUNT;
467 }
468
f7b7ed97
TT		 469 stack.store (pv_add_constant (regs[rn], imm),
470 is64 ? 8 : 4, regs[rt]);
432ec081
YQ		 471 if (inst.operands[1].addr.writeback)
472 regs[rn] = pv_add_constant (regs[rn], imm);
473 }
d9ebcbce 474 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 475 {
476 /* Stop analysis on branch. */
477 break;
478 }
17e116a7
AH		 479 else if (inst.opcode->iclass == ic_system)
480 {
481 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
482 int ra_state_val = 0;
483
484 if (insn == 0xd503233f /* paciasp. */
485 || insn == 0xd503237f /* pacibsp. */)
486 {
487 /* Return addresses are mangled. */
488 ra_state_val = 1;
489 }
490 else if (insn == 0xd50323bf /* autiasp. */
491 || insn == 0xd50323ff /* autibsp. */)
492 {
493 /* Return addresses are not mangled. */
494 ra_state_val = 0;
495 }
496 else
497 {
498 if (aarch64_debug)
499 debug_printf ("aarch64: prologue analysis gave up addr=%s"
500 " opcode=0x%x (iclass)\n",
501 core_addr_to_string_nz (start), insn);
502 break;
503 }
504
505 if (tdep->has_pauth () && cache != nullptr)
506 trad_frame_set_value (cache->saved_regs,
507 tdep->pauth_ra_state_regnum,
508 ra_state_val);
509 }
07b287a0
MS		 510 else
511 {
512 if (aarch64_debug)
b277c936 513 {
0a0da556 514 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 515 " opcode=0x%x\n",
516 core_addr_to_string_nz (start), insn);
517 }
07b287a0
MS		 518 break;
519 }
520 }
521
522 if (cache == NULL)
f7b7ed97 523 return start;
07b287a0
MS		 524
525 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
526 {
527 /* Frame pointer is fp. Frame size is constant. */
528 cache->framereg = AARCH64_FP_REGNUM;
529 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
530 }
531 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
532 {
533 /* Try the stack pointer. */
534 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
535 cache->framereg = AARCH64_SP_REGNUM;
536 }
537 else
538 {
539 /* We're just out of luck. We don't know where the frame is. */
540 cache->framereg = -1;
541 cache->framesize = 0;
542 }
543
544 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
545 {
546 CORE_ADDR offset;
547
f7b7ed97 548 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 549 cache->saved_regs[i].addr = offset;
550 }
551
187f5d00
YQ		 552 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
553 {
554 int regnum = gdbarch_num_regs (gdbarch);
555 CORE_ADDR offset;
556
f7b7ed97
TT		 557 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
558 &offset))
187f5d00
YQ		 559 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
560 }
561
07b287a0
MS		 562 return start;
563}
564
4d9a9006
YQ		 565static CORE_ADDR
566aarch64_analyze_prologue (struct gdbarch *gdbarch,
567 CORE_ADDR start, CORE_ADDR limit,
568 struct aarch64_prologue_cache *cache)
569{
570 instruction_reader reader;
571
572 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
573 reader);
574}
575
576#if GDB_SELF_TEST
577
578namespace selftests {
579
580/* Instruction reader from manually cooked instruction sequences. */
581
582class instruction_reader_test : public abstract_instruction_reader
583{
584public:
585 template<size_t SIZE>
586 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
587 : m_insns (insns), m_insns_size (SIZE)
588 {}
589
590 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 591 override
4d9a9006
YQ		 592 {
593 SELF_CHECK (len == 4);
594 SELF_CHECK (memaddr % 4 == 0);
595 SELF_CHECK (memaddr / 4 < m_insns_size);
596
597 return m_insns[memaddr / 4];
598 }
599
600private:
601 const uint32_t *m_insns;
602 size_t m_insns_size;
603};
604
605static void
606aarch64_analyze_prologue_test (void)
607{
608 struct gdbarch_info info;
609
610 gdbarch_info_init (&info);
611 info.bfd_arch_info = bfd_scan_arch ("aarch64");
612
613 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
614 SELF_CHECK (gdbarch != NULL);
615
17e116a7
AH		 616 struct aarch64_prologue_cache cache;
617 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
618
619 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
620
4d9a9006
YQ		 621 /* Test the simple prologue in which frame pointer is used. */
622 {
4d9a9006
YQ		 623 static const uint32_t insns[] = {
624 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
625 0x910003fd, /* mov x29, sp */
626 0x97ffffe6, /* bl 0x400580 */
627 };
628 instruction_reader_test reader (insns);
629
630 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
631 SELF_CHECK (end == 4 * 2);
632
633 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
634 SELF_CHECK (cache.framesize == 272);
635
636 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
637 {
638 if (i == AARCH64_FP_REGNUM)
639 SELF_CHECK (cache.saved_regs[i].addr == -272);
640 else if (i == AARCH64_LR_REGNUM)
641 SELF_CHECK (cache.saved_regs[i].addr == -264);
642 else
643 SELF_CHECK (cache.saved_regs[i].addr == -1);
644 }
645
646 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
647 {
648 int regnum = gdbarch_num_regs (gdbarch);
649
650 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
651 == -1);
652 }
653 }
432ec081
YQ		 654
655 /* Test a prologue in which STR is used and frame pointer is not
656 used. */
657 {
432ec081
YQ		 658 static const uint32_t insns[] = {
659 0xf81d0ff3, /* str x19, [sp, #-48]! */
660 0xb9002fe0, /* str w0, [sp, #44] */
661 0xf90013e1, /* str x1, [sp, #32]*/
662 0xfd000fe0, /* str d0, [sp, #24] */
663 0xaa0203f3, /* mov x19, x2 */
664 0xf94013e0, /* ldr x0, [sp, #32] */
665 };
666 instruction_reader_test reader (insns);
667
68811f8f 668 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
432ec081
YQ		 669 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
670
671 SELF_CHECK (end == 4 * 5);
672
673 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
674 SELF_CHECK (cache.framesize == 48);
675
676 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
677 {
678 if (i == 1)
679 SELF_CHECK (cache.saved_regs[i].addr == -16);
680 else if (i == 19)
681 SELF_CHECK (cache.saved_regs[i].addr == -48);
682 else
683 SELF_CHECK (cache.saved_regs[i].addr == -1);
684 }
685
686 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
687 {
688 int regnum = gdbarch_num_regs (gdbarch);
689
690 if (i == 0)
691 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
692 == -24);
693 else
694 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
695 == -1);
696 }
697 }
17e116a7
AH		 698
699 /* Test a prologue in which there is a return address signing instruction. */
700 if (tdep->has_pauth ())
701 {
702 static const uint32_t insns[] = {
703 0xd503233f, /* paciasp */
704 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
705 0x910003fd, /* mov x29, sp */
706 0xf801c3f3, /* str x19, [sp, #28] */
707 0xb9401fa0, /* ldr x19, [x29, #28] */
708 };
709 instruction_reader_test reader (insns);
710
68811f8f 711 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
17e116a7
AH		 712 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
713 reader);
714
715 SELF_CHECK (end == 4 * 4);
716 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
717 SELF_CHECK (cache.framesize == 48);
718
719 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
720 {
721 if (i == 19)
722 SELF_CHECK (cache.saved_regs[i].addr == -20);
723 else if (i == AARCH64_FP_REGNUM)
724 SELF_CHECK (cache.saved_regs[i].addr == -48);
725 else if (i == AARCH64_LR_REGNUM)
726 SELF_CHECK (cache.saved_regs[i].addr == -40);
727 else
728 SELF_CHECK (cache.saved_regs[i].addr == -1);
729 }
730
731 if (tdep->has_pauth ())
732 {
733 SELF_CHECK (trad_frame_value_p (cache.saved_regs,
734 tdep->pauth_ra_state_regnum));
735 SELF_CHECK (cache.saved_regs[tdep->pauth_ra_state_regnum].addr == 1);
736 }
737 }
4d9a9006
YQ		 738}
739} // namespace selftests
740#endif /* GDB_SELF_TEST */
741
07b287a0
MS		 742/* Implement the "skip_prologue" gdbarch method. */
743
744static CORE_ADDR
745aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
746{
07b287a0 747 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 748
749 /* See if we can determine the end of the prologue via the symbol
750 table. If so, then return either PC, or the PC after the
751 prologue, whichever is greater. */
752 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
753 {
754 CORE_ADDR post_prologue_pc
755 = skip_prologue_using_sal (gdbarch, func_addr);
756
757 if (post_prologue_pc != 0)
325fac50 758 return std::max (pc, post_prologue_pc);
07b287a0
MS		 759 }
760
761 /* Can't determine prologue from the symbol table, need to examine
762 instructions. */
763
764 /* Find an upper limit on the function prologue using the debug
765 information. If the debug information could not be used to
766 provide that bound, then use an arbitrary large number as the
767 upper bound. */
768 limit_pc = skip_prologue_using_sal (gdbarch, pc);
769 if (limit_pc == 0)
770 limit_pc = pc + 128; /* Magic. */
771
772 /* Try disassembling prologue. */
773 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
774}
775
776/* Scan the function prologue for THIS_FRAME and populate the prologue
777 cache CACHE. */
778
779static void
780aarch64_scan_prologue (struct frame_info *this_frame,
781 struct aarch64_prologue_cache *cache)
782{
783 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
784 CORE_ADDR prologue_start;
785 CORE_ADDR prologue_end;
786 CORE_ADDR prev_pc = get_frame_pc (this_frame);
787 struct gdbarch *gdbarch = get_frame_arch (this_frame);
788
db634143
PL		 789 cache->prev_pc = prev_pc;
790
07b287a0
MS		 791 /* Assume we do not find a frame. */
792 cache->framereg = -1;
793 cache->framesize = 0;
794
795 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
796 &prologue_end))
797 {
798 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
799
800 if (sal.line == 0)
801 {
802 /* No line info so use the current PC. */
803 prologue_end = prev_pc;
804 }
805 else if (sal.end < prologue_end)
806 {
807 /* The next line begins after the function end. */
808 prologue_end = sal.end;
809 }
810
325fac50 811 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 812 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
813 }
814 else
815 {
816 CORE_ADDR frame_loc;
07b287a0
MS		 817
818 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
819 if (frame_loc == 0)
820 return;
821
822 cache->framereg = AARCH64_FP_REGNUM;
823 cache->framesize = 16;
824 cache->saved_regs[29].addr = 0;
825 cache->saved_regs[30].addr = 8;
826 }
827}
828
7dfa3edc
PL		 829/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
830 function may throw an exception if the inferior's registers or memory is
831 not available. */
07b287a0 832
7dfa3edc
PL		 833static void
834aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
835 struct aarch64_prologue_cache *cache)
07b287a0 836{
07b287a0
MS		 837 CORE_ADDR unwound_fp;
838 int reg;
839
07b287a0
MS		 840 aarch64_scan_prologue (this_frame, cache);
841
842 if (cache->framereg == -1)
7dfa3edc 843 return;
07b287a0
MS		 844
845 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
846 if (unwound_fp == 0)
7dfa3edc 847 return;
07b287a0
MS		 848
849 cache->prev_sp = unwound_fp + cache->framesize;
850
851 /* Calculate actual addresses of saved registers using offsets
852 determined by aarch64_analyze_prologue. */
853 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
854 if (trad_frame_addr_p (cache->saved_regs, reg))
855 cache->saved_regs[reg].addr += cache->prev_sp;
856
db634143
PL		 857 cache->func = get_frame_func (this_frame);
858
7dfa3edc
PL		 859 cache->available_p = 1;
860}
861
862/* Allocate and fill in *THIS_CACHE with information about the prologue of
863 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
864 Return a pointer to the current aarch64_prologue_cache in
865 *THIS_CACHE. */
866
867static struct aarch64_prologue_cache *
868aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
869{
870 struct aarch64_prologue_cache *cache;
871
872 if (*this_cache != NULL)
9a3c8263 873 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 874
875 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
876 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
877 *this_cache = cache;
878
a70b8144 879 try
7dfa3edc
PL		 880 {
881 aarch64_make_prologue_cache_1 (this_frame, cache);
882 }
230d2906 883 catch (const gdb_exception_error &ex)
7dfa3edc
PL		 884 {
885 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 886 throw;
7dfa3edc 887 }
7dfa3edc 888
07b287a0
MS		 889 return cache;
890}
891
7dfa3edc
PL		 892/* Implement the "stop_reason" frame_unwind method. */
893
894static enum unwind_stop_reason
895aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
896 void **this_cache)
897{
898 struct aarch64_prologue_cache *cache
899 = aarch64_make_prologue_cache (this_frame, this_cache);
900
901 if (!cache->available_p)
902 return UNWIND_UNAVAILABLE;
903
904 /* Halt the backtrace at "_start". */
905 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
906 return UNWIND_OUTERMOST;
907
908 /* We've hit a wall, stop. */
909 if (cache->prev_sp == 0)
910 return UNWIND_OUTERMOST;
911
912 return UNWIND_NO_REASON;
913}
914
07b287a0
MS		 915/* Our frame ID for a normal frame is the current function's starting
916 PC and the caller's SP when we were called. */
917
918static void
919aarch64_prologue_this_id (struct frame_info *this_frame,
920 void **this_cache, struct frame_id *this_id)
921{
7c8edfae
PL		 922 struct aarch64_prologue_cache *cache
923 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 924
7dfa3edc
PL		 925 if (!cache->available_p)
926 *this_id = frame_id_build_unavailable_stack (cache->func);
927 else
928 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 929}
930
931/* Implement the "prev_register" frame_unwind method. */
932
933static struct value *
934aarch64_prologue_prev_register (struct frame_info *this_frame,
935 void **this_cache, int prev_regnum)
936{
7c8edfae
PL		 937 struct aarch64_prologue_cache *cache
938 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 939
940 /* If we are asked to unwind the PC, then we need to return the LR
941 instead. The prologue may save PC, but it will point into this
942 frame's prologue, not the next frame's resume location. */
943 if (prev_regnum == AARCH64_PC_REGNUM)
944 {
945 CORE_ADDR lr;
17e116a7
AH		 946 struct gdbarch *gdbarch = get_frame_arch (this_frame);
947 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 948
949 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
17e116a7
AH		 950
951 if (tdep->has_pauth ()
952 && trad_frame_value_p (cache->saved_regs,
953 tdep->pauth_ra_state_regnum))
954 lr = aarch64_frame_unmask_address (tdep, this_frame, lr);
955
07b287a0
MS		 956 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
957 }
958
959 /* SP is generally not saved to the stack, but this frame is
960 identified by the next frame's stack pointer at the time of the
961 call. The value was already reconstructed into PREV_SP. */
962 /*
963 +----------+ ^
964 | saved lr | |
965 +->| saved fp |--+
966 | | |
967 | | | <- Previous SP
968 | +----------+
969 | | saved lr |
970 +--| saved fp |<- FP
971 | |
972 | |<- SP
973 +----------+ */
974 if (prev_regnum == AARCH64_SP_REGNUM)
975 return frame_unwind_got_constant (this_frame, prev_regnum,
976 cache->prev_sp);
977
978 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
979 prev_regnum);
980}
981
982/* AArch64 prologue unwinder. */
983struct frame_unwind aarch64_prologue_unwind =
984{
985 NORMAL_FRAME,
7dfa3edc 986 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 987 aarch64_prologue_this_id,
988 aarch64_prologue_prev_register,
989 NULL,
990 default_frame_sniffer
991};
992
8b61f75d
PL		 993/* Allocate and fill in *THIS_CACHE with information about the prologue of
994 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
995 Return a pointer to the current aarch64_prologue_cache in
996 *THIS_CACHE. */
07b287a0
MS		 997
998static struct aarch64_prologue_cache *
8b61f75d 999aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 1000{
07b287a0 1001 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 1002
1003 if (*this_cache != NULL)
9a3c8263 1004 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 1005
1006 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1007 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 1008 *this_cache = cache;
07b287a0 1009
a70b8144 1010 try
02a2a705
PL		 1011 {
1012 cache->prev_sp = get_frame_register_unsigned (this_frame,
1013 AARCH64_SP_REGNUM);
1014 cache->prev_pc = get_frame_pc (this_frame);
1015 cache->available_p = 1;
1016 }
230d2906 1017 catch (const gdb_exception_error &ex)
02a2a705
PL		 1018 {
1019 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1020 throw;
02a2a705 1021 }
07b287a0
MS		 1022
1023 return cache;
1024}
1025
02a2a705
PL		 1026/* Implement the "stop_reason" frame_unwind method. */
1027
1028static enum unwind_stop_reason
1029aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
1030 void **this_cache)
1031{
1032 struct aarch64_prologue_cache *cache
1033 = aarch64_make_stub_cache (this_frame, this_cache);
1034
1035 if (!cache->available_p)
1036 return UNWIND_UNAVAILABLE;
1037
1038 return UNWIND_NO_REASON;
1039}
1040
07b287a0
MS		 1041/* Our frame ID for a stub frame is the current SP and LR. */
1042
1043static void
1044aarch64_stub_this_id (struct frame_info *this_frame,
1045 void **this_cache, struct frame_id *this_id)
1046{
8b61f75d
PL		 1047 struct aarch64_prologue_cache *cache
1048 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 1049
02a2a705
PL		 1050 if (cache->available_p)
1051 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
1052 else
1053 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 1054}
1055
1056/* Implement the "sniffer" frame_unwind method. */
1057
1058static int
1059aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
1060 struct frame_info *this_frame,
1061 void **this_prologue_cache)
1062{
1063 CORE_ADDR addr_in_block;
1064 gdb_byte dummy[4];
1065
1066 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 1067 if (in_plt_section (addr_in_block)
07b287a0
MS		 1068 /* We also use the stub winder if the target memory is unreadable
1069 to avoid having the prologue unwinder trying to read it. */
1070 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1071 return 1;
1072
1073 return 0;
1074}
1075
1076/* AArch64 stub unwinder. */
1077struct frame_unwind aarch64_stub_unwind =
1078{
1079 NORMAL_FRAME,
02a2a705 1080 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 1081 aarch64_stub_this_id,
1082 aarch64_prologue_prev_register,
1083 NULL,
1084 aarch64_stub_unwind_sniffer
1085};
1086
1087/* Return the frame base address of *THIS_FRAME. */
1088
1089static CORE_ADDR
1090aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1091{
7c8edfae
PL		 1092 struct aarch64_prologue_cache *cache
1093 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1094
1095 return cache->prev_sp - cache->framesize;
1096}
1097
1098/* AArch64 default frame base information. */
1099struct frame_base aarch64_normal_base =
1100{
1101 &aarch64_prologue_unwind,
1102 aarch64_normal_frame_base,
1103 aarch64_normal_frame_base,
1104 aarch64_normal_frame_base
1105};
1106
07b287a0
MS		 1107/* Return the value of the REGNUM register in the previous frame of
1108 *THIS_FRAME. */
1109
1110static struct value *
1111aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1112 void **this_cache, int regnum)
1113{
11e1b75f 1114 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
07b287a0
MS		 1115 CORE_ADDR lr;
1116
1117 switch (regnum)
1118 {
1119 case AARCH64_PC_REGNUM:
1120 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
11e1b75f 1121 lr = aarch64_frame_unmask_address (tdep, this_frame, lr);
07b287a0
MS		 1122 return frame_unwind_got_constant (this_frame, regnum, lr);
1123
1124 default:
1125 internal_error (__FILE__, __LINE__,
1126 _("Unexpected register %d"), regnum);
1127 }
1128}
1129
11e1b75f
AH		 1130static const unsigned char op_lit0 = DW_OP_lit0;
1131static const unsigned char op_lit1 = DW_OP_lit1;
1132
07b287a0
MS		 1133/* Implement the "init_reg" dwarf2_frame_ops method. */
1134
1135static void
1136aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1137 struct dwarf2_frame_state_reg *reg,
1138 struct frame_info *this_frame)
1139{
11e1b75f
AH		 1140 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1141
07b287a0
MS		 1142 switch (regnum)
1143 {
1144 case AARCH64_PC_REGNUM:
1145 reg->how = DWARF2_FRAME_REG_FN;
1146 reg->loc.fn = aarch64_dwarf2_prev_register;
11e1b75f
AH		 1147 return;
1148
07b287a0
MS		 1149 case AARCH64_SP_REGNUM:
1150 reg->how = DWARF2_FRAME_REG_CFA;
11e1b75f
AH		 1151 return;
1152 }
1153
1154 /* Init pauth registers. */
1155 if (tdep->has_pauth ())
1156 {
1157 if (regnum == tdep->pauth_ra_state_regnum)
1158 {
1159 /* Initialize RA_STATE to zero. */
1160 reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1161 reg->loc.exp.start = &op_lit0;
1162 reg->loc.exp.len = 1;
1163 return;
1164 }
1165 else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
1166 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
1167 {
1168 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1169 return;
1170 }
07b287a0
MS		 1171 }
1172}
1173
11e1b75f
AH		 1174/* Implement the execute_dwarf_cfa_vendor_op method. */
1175
1176static bool
1177aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1178 struct dwarf2_frame_state *fs)
1179{
1180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1181 struct dwarf2_frame_state_reg *ra_state;
1182
1183 if (tdep->has_pauth () && op == DW_CFA_AARCH64_negate_ra_state)
1184 {
1185 /* Allocate RA_STATE column if it's not allocated yet. */
1186 fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
1187
1188 /* Toggle the status of RA_STATE between 0 and 1. */
1189 ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
1190 ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1191
1192 if (ra_state->loc.exp.start == nullptr
1193 || ra_state->loc.exp.start == &op_lit0)
1194 ra_state->loc.exp.start = &op_lit1;
1195 else
1196 ra_state->loc.exp.start = &op_lit0;
1197
1198 ra_state->loc.exp.len = 1;
1199
1200 return true;
1201 }
1202
1203 return false;
1204}
1205
07b287a0
MS		 1206/* When arguments must be pushed onto the stack, they go on in reverse
1207 order. The code below implements a FILO (stack) to do this. */
1208
89055eaa 1209struct stack_item_t
07b287a0 1210{
c3c87445
YQ		 1211 /* Value to pass on stack. It can be NULL if this item is for stack
1212 padding. */
7c543f7b 1213 const gdb_byte *data;
07b287a0
MS		 1214
1215 /* Size in bytes of value to pass on stack. */
1216 int len;
89055eaa 1217};
07b287a0 1218
b907456c
AB		 1219/* Implement the gdbarch type alignment method, overrides the generic
1220 alignment algorithm for anything that is aarch64 specific. */
07b287a0 1221
b907456c
AB		 1222static ULONGEST
1223aarch64_type_align (gdbarch *gdbarch, struct type *t)
07b287a0 1224{
07b287a0 1225 t = check_typedef (t);
b907456c 1226 if (TYPE_CODE (t) == TYPE_CODE_ARRAY && TYPE_VECTOR (t))
07b287a0 1227 {
b907456c
AB		 1228 /* Use the natural alignment for vector types (the same for
1229 scalar type), but the maximum alignment is 128-bit. */
1230 if (TYPE_LENGTH (t) > 16)
1231 return 16;
238f2452 1232 else
b907456c 1233 return TYPE_LENGTH (t);
07b287a0 1234 }
b907456c
AB		 1235
1236 /* Allow the common code to calculate the alignment. */
1237 return 0;
07b287a0
MS		 1238}
1239
ea92689a
AH		 1240/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1241
1242 Return the number of register required, or -1 on failure.
1243
1244 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1245 to the element, else fail if the type of this element does not match the
1246 existing value. */
1247
1248static int
1249aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1250 struct type **fundamental_type)
1251{
1252 if (type == nullptr)
1253 return -1;
1254
1255 switch (TYPE_CODE (type))
1256 {
1257 case TYPE_CODE_FLT:
1258 if (TYPE_LENGTH (type) > 16)
1259 return -1;
1260
1261 if (*fundamental_type == nullptr)
1262 *fundamental_type = type;
1263 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1264 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1265 return -1;
1266
1267 return 1;
1268
1269 case TYPE_CODE_COMPLEX:
1270 {
1271 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1272 if (TYPE_LENGTH (target_type) > 16)
1273 return -1;
1274
1275 if (*fundamental_type == nullptr)
1276 *fundamental_type = target_type;
1277 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1278 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1279 return -1;
1280
1281 return 2;
1282 }
1283
1284 case TYPE_CODE_ARRAY:
1285 {
1286 if (TYPE_VECTOR (type))
1287 {
1288 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1289 return -1;
1290
1291 if (*fundamental_type == nullptr)
1292 *fundamental_type = type;
1293 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1294 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1295 return -1;
1296
1297 return 1;
1298 }
1299 else
1300 {
1301 struct type *target_type = TYPE_TARGET_TYPE (type);
1302 int count = aapcs_is_vfp_call_or_return_candidate_1
1303 (target_type, fundamental_type);
1304
1305 if (count == -1)
1306 return count;
1307
d4718d5c 1308 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1309 return count;
1310 }
1311 }
1312
1313 case TYPE_CODE_STRUCT:
1314 case TYPE_CODE_UNION:
1315 {
1316 int count = 0;
1317
1318 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1319 {
353229bf
AH		 1320 /* Ignore any static fields. */
1321 if (field_is_static (&TYPE_FIELD (type, i)))
1322 continue;
1323
ea92689a
AH		 1324 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1325
1326 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1327 (member, fundamental_type);
1328 if (sub_count == -1)
1329 return -1;
1330 count += sub_count;
1331 }
73021deb
AH		 1332
1333 /* Ensure there is no padding between the fields (allowing for empty
1334 zero length structs) */
1335 int ftype_length = (*fundamental_type == nullptr)
1336 ? 0 : TYPE_LENGTH (*fundamental_type);
1337 if (count * ftype_length != TYPE_LENGTH (type))
1338 return -1;
1339
ea92689a
AH		 1340 return count;
1341 }
1342
1343 default:
1344 break;
1345 }
1346
1347 return -1;
1348}
1349
1350/* Return true if an argument, whose type is described by TYPE, can be passed or
1351 returned in simd/fp registers, providing enough parameter passing registers
1352 are available. This is as described in the AAPCS64.
1353
1354 Upon successful return, *COUNT returns the number of needed registers,
1355 *FUNDAMENTAL_TYPE contains the type of those registers.
1356
1357 Candidate as per the AAPCS64 5.4.2.C is either a:
1358 - float.
1359 - short-vector.
1360 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1361 all the members are floats and has at most 4 members.
1362 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1363 all the members are short vectors and has at most 4 members.
1364 - Complex (7.1.1)
1365
1366 Note that HFAs and HVAs can include nested structures and arrays. */
1367
0e745c60 1368static bool
ea92689a
AH		 1369aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1370 struct type **fundamental_type)
1371{
1372 if (type == nullptr)
1373 return false;
1374
1375 *fundamental_type = nullptr;
1376
1377 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1378 fundamental_type);
1379
1380 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1381 {
1382 *count = ag_count;
1383 return true;
1384 }
1385 else
1386 return false;
1387}
1388
07b287a0
MS		 1389/* AArch64 function call information structure. */
1390struct aarch64_call_info
1391{
1392 /* the current argument number. */
89055eaa 1393 unsigned argnum = 0;
07b287a0
MS		 1394
1395 /* The next general purpose register number, equivalent to NGRN as
1396 described in the AArch64 Procedure Call Standard. */
89055eaa 1397 unsigned ngrn = 0;
07b287a0
MS		 1398
1399 /* The next SIMD and floating point register number, equivalent to
1400 NSRN as described in the AArch64 Procedure Call Standard. */
89055eaa 1401 unsigned nsrn = 0;
07b287a0
MS		 1402
1403 /* The next stacked argument address, equivalent to NSAA as
1404 described in the AArch64 Procedure Call Standard. */
89055eaa 1405 unsigned nsaa = 0;
07b287a0
MS		 1406
1407 /* Stack item vector. */
89055eaa 1408 std::vector<stack_item_t> si;
07b287a0
MS		 1409};
1410
1411/* Pass a value in a sequence of consecutive X registers. The caller
1412 is responsbile for ensuring sufficient registers are available. */
1413
1414static void
1415pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1416 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1417 struct value *arg)
07b287a0
MS		 1418{
1419 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1420 int len = TYPE_LENGTH (type);
1421 enum type_code typecode = TYPE_CODE (type);
1422 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1423 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1424
1425 info->argnum++;
1426
1427 while (len > 0)
1428 {
1429 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1430 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1431 byte_order);
1432
1433
1434 /* Adjust sub-word struct/union args when big-endian. */
1435 if (byte_order == BFD_ENDIAN_BIG
1436 && partial_len < X_REGISTER_SIZE
1437 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1438 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1439
1440 if (aarch64_debug)
b277c936
PL		 1441 {
1442 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1443 gdbarch_register_name (gdbarch, regnum),
1444 phex (regval, X_REGISTER_SIZE));
1445 }
07b287a0
MS		 1446 regcache_cooked_write_unsigned (regcache, regnum, regval);
1447 len -= partial_len;
1448 buf += partial_len;
1449 regnum++;
1450 }
1451}
1452
1453/* Attempt to marshall a value in a V register. Return 1 if
1454 successful, or 0 if insufficient registers are available. This
1455 function, unlike the equivalent pass_in_x() function does not
1456 handle arguments spread across multiple registers. */
1457
1458static int
1459pass_in_v (struct gdbarch *gdbarch,
1460 struct regcache *regcache,
1461 struct aarch64_call_info *info,
0735fddd 1462 int len, const bfd_byte *buf)
07b287a0
MS		 1463{
1464 if (info->nsrn < 8)
1465 {
07b287a0 1466 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1467 /* Enough space for a full vector register. */
1468 gdb_byte reg[register_size (gdbarch, regnum)];
1469 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1470
1471 info->argnum++;
1472 info->nsrn++;
1473
0735fddd
YQ		 1474 memset (reg, 0, sizeof (reg));
1475 /* PCS C.1, the argument is allocated to the least significant
1476 bits of V register. */
1477 memcpy (reg, buf, len);
b66f5587 1478 regcache->cooked_write (regnum, reg);
0735fddd 1479
07b287a0 1480 if (aarch64_debug)
b277c936
PL		 1481 {
1482 debug_printf ("arg %d in %s\n", info->argnum,
1483 gdbarch_register_name (gdbarch, regnum));
1484 }
07b287a0
MS		 1485 return 1;
1486 }
1487 info->nsrn = 8;
1488 return 0;
1489}
1490
1491/* Marshall an argument onto the stack. */
1492
1493static void
1494pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1495 struct value *arg)
07b287a0 1496{
8e80f9d1 1497 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1498 int len = TYPE_LENGTH (type);
1499 int align;
1500 stack_item_t item;
1501
1502 info->argnum++;
1503
b907456c 1504 align = type_align (type);
07b287a0
MS		 1505
1506 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1507 Natural alignment of the argument's type. */
1508 align = align_up (align, 8);
1509
1510 /* The AArch64 PCS requires at most doubleword alignment. */
1511 if (align > 16)
1512 align = 16;
1513
1514 if (aarch64_debug)
b277c936
PL		 1515 {
1516 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1517 info->nsaa);
1518 }
07b287a0
MS		 1519
1520 item.len = len;
1521 item.data = buf;
89055eaa 1522 info->si.push_back (item);
07b287a0
MS		 1523
1524 info->nsaa += len;
1525 if (info->nsaa & (align - 1))
1526 {
1527 /* Push stack alignment padding. */
1528 int pad = align - (info->nsaa & (align - 1));
1529
1530 item.len = pad;
c3c87445 1531 item.data = NULL;
07b287a0 1532
89055eaa 1533 info->si.push_back (item);
07b287a0
MS		 1534 info->nsaa += pad;
1535 }
1536}
1537
1538/* Marshall an argument into a sequence of one or more consecutive X
1539 registers or, if insufficient X registers are available then onto
1540 the stack. */
1541
1542static void
1543pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1544 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1545 struct value *arg)
07b287a0
MS		 1546{
1547 int len = TYPE_LENGTH (type);
1548 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1549
1550 /* PCS C.13 - Pass in registers if we have enough spare */
1551 if (info->ngrn + nregs <= 8)
1552 {
8e80f9d1 1553 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1554 info->ngrn += nregs;
1555 }
1556 else
1557 {
1558 info->ngrn = 8;
8e80f9d1 1559 pass_on_stack (info, type, arg);
07b287a0
MS		 1560 }
1561}
1562
0e745c60
AH		 1563/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1564 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1565 registers. A return value of false is an error state as the value will have
1566 been partially passed to the stack. */
1567static bool
1568pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1569 struct aarch64_call_info *info, struct type *arg_type,
1570 struct value *arg)
07b287a0 1571{
0e745c60
AH		 1572 switch (TYPE_CODE (arg_type))
1573 {
1574 case TYPE_CODE_FLT:
1575 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1576 value_contents (arg));
1577 break;
1578
1579 case TYPE_CODE_COMPLEX:
1580 {
1581 const bfd_byte *buf = value_contents (arg);
1582 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1583
1584 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1585 buf))
1586 return false;
1587
1588 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1589 buf + TYPE_LENGTH (target_type));
1590 }
1591
1592 case TYPE_CODE_ARRAY:
1593 if (TYPE_VECTOR (arg_type))
1594 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1595 value_contents (arg));
1596 /* fall through. */
1597
1598 case TYPE_CODE_STRUCT:
1599 case TYPE_CODE_UNION:
1600 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1601 {
353229bf
AH		 1602 /* Don't include static fields. */
1603 if (field_is_static (&TYPE_FIELD (arg_type, i)))
1604 continue;
1605
0e745c60
AH		 1606 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1607 struct type *field_type = check_typedef (value_type (field));
1608
1609 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1610 field))
1611 return false;
1612 }
1613 return true;
1614
1615 default:
1616 return false;
1617 }
07b287a0
MS		 1618}
1619
1620/* Implement the "push_dummy_call" gdbarch method. */
1621
1622static CORE_ADDR
1623aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1624 struct regcache *regcache, CORE_ADDR bp_addr,
1625 int nargs,
cf84fa6b
AH		 1626 struct value **args, CORE_ADDR sp,
1627 function_call_return_method return_method,
07b287a0
MS		 1628 CORE_ADDR struct_addr)
1629{
07b287a0 1630 int argnum;
07b287a0 1631 struct aarch64_call_info info;
07b287a0 1632
07b287a0
MS		 1633 /* We need to know what the type of the called function is in order
1634 to determine the number of named/anonymous arguments for the
1635 actual argument placement, and the return type in order to handle
1636 return value correctly.
1637
1638 The generic code above us views the decision of return in memory
1639 or return in registers as a two stage processes. The language
1640 handler is consulted first and may decide to return in memory (eg
1641 class with copy constructor returned by value), this will cause
1642 the generic code to allocate space AND insert an initial leading
1643 argument.
1644
1645 If the language code does not decide to pass in memory then the
1646 target code is consulted.
1647
1648 If the language code decides to pass in memory we want to move
1649 the pointer inserted as the initial argument from the argument
1650 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1651 register. */
07b287a0
MS		 1652
1653 /* Set the return address. For the AArch64, the return breakpoint
1654 is always at BP_ADDR. */
1655 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1656
38a72da0
AH		 1657 /* If we were given an initial argument for the return slot, lose it. */
1658 if (return_method == return_method_hidden_param)
07b287a0
MS		 1659 {
1660 args++;
1661 nargs--;
1662 }
1663
1664 /* The struct_return pointer occupies X8. */
38a72da0 1665 if (return_method != return_method_normal)
07b287a0
MS		 1666 {
1667 if (aarch64_debug)
b277c936
PL		 1668 {
1669 debug_printf ("struct return in %s = 0x%s\n",
1670 gdbarch_register_name (gdbarch,
1671 AARCH64_STRUCT_RETURN_REGNUM),
1672 paddress (gdbarch, struct_addr));
1673 }
07b287a0
MS		 1674 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1675 struct_addr);
1676 }
1677
1678 for (argnum = 0; argnum < nargs; argnum++)
1679 {
1680 struct value *arg = args[argnum];
0e745c60
AH		 1681 struct type *arg_type, *fundamental_type;
1682 int len, elements;
07b287a0
MS		 1683
1684 arg_type = check_typedef (value_type (arg));
1685 len = TYPE_LENGTH (arg_type);
1686
0e745c60
AH		 1687 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1688 if there are enough spare registers. */
1689 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1690 &fundamental_type))
1691 {
1692 if (info.nsrn + elements <= 8)
1693 {
1694 /* We know that we have sufficient registers available therefore
1695 this will never need to fallback to the stack. */
1696 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1697 arg))
1698 gdb_assert_not_reached ("Failed to push args");
1699 }
1700 else
1701 {
1702 info.nsrn = 8;
1703 pass_on_stack (&info, arg_type, arg);
1704 }
1705 continue;
1706 }
1707
07b287a0
MS		 1708 switch (TYPE_CODE (arg_type))
1709 {
1710 case TYPE_CODE_INT:
1711 case TYPE_CODE_BOOL:
1712 case TYPE_CODE_CHAR:
1713 case TYPE_CODE_RANGE:
1714 case TYPE_CODE_ENUM:
1715 if (len < 4)
1716 {
1717 /* Promote to 32 bit integer. */
1718 if (TYPE_UNSIGNED (arg_type))
1719 arg_type = builtin_type (gdbarch)->builtin_uint32;
1720 else
1721 arg_type = builtin_type (gdbarch)->builtin_int32;
1722 arg = value_cast (arg_type, arg);
1723 }
8e80f9d1 1724 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1725 break;
1726
07b287a0
MS		 1727 case TYPE_CODE_STRUCT:
1728 case TYPE_CODE_ARRAY:
1729 case TYPE_CODE_UNION:
0e745c60 1730 if (len > 16)
07b287a0
MS		 1731 {
1732 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1733 invisible reference. */
1734
1735 /* Allocate aligned storage. */
1736 sp = align_down (sp - len, 16);
1737
1738 /* Write the real data into the stack. */
1739 write_memory (sp, value_contents (arg), len);
1740
1741 /* Construct the indirection. */
1742 arg_type = lookup_pointer_type (arg_type);
1743 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1744 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1745 }
1746 else
1747 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1748 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1749 break;
1750
1751 default:
8e80f9d1 1752 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1753 break;
1754 }
1755 }
1756
1757 /* Make sure stack retains 16 byte alignment. */
1758 if (info.nsaa & 15)
1759 sp -= 16 - (info.nsaa & 15);
1760
89055eaa 1761 while (!info.si.empty ())
07b287a0 1762 {
89055eaa 1763 const stack_item_t &si = info.si.back ();
07b287a0 1764
89055eaa
TT		 1765 sp -= si.len;
1766 if (si.data != NULL)
1767 write_memory (sp, si.data, si.len);
1768 info.si.pop_back ();
07b287a0
MS		 1769 }
1770
07b287a0
MS		 1771 /* Finally, update the SP register. */
1772 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1773
1774 return sp;
1775}
1776
1777/* Implement the "frame_align" gdbarch method. */
1778
1779static CORE_ADDR
1780aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1781{
1782 /* Align the stack to sixteen bytes. */
1783 return sp & ~(CORE_ADDR) 15;
1784}
1785
1786/* Return the type for an AdvSISD Q register. */
1787
1788static struct type *
1789aarch64_vnq_type (struct gdbarch *gdbarch)
1790{
1791 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1792
1793 if (tdep->vnq_type == NULL)
1794 {
1795 struct type *t;
1796 struct type *elem;
1797
1798 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1799 TYPE_CODE_UNION);
1800
1801 elem = builtin_type (gdbarch)->builtin_uint128;
1802 append_composite_type_field (t, "u", elem);
1803
1804 elem = builtin_type (gdbarch)->builtin_int128;
1805 append_composite_type_field (t, "s", elem);
1806
1807 tdep->vnq_type = t;
1808 }
1809
1810 return tdep->vnq_type;
1811}
1812
1813/* Return the type for an AdvSISD D register. */
1814
1815static struct type *
1816aarch64_vnd_type (struct gdbarch *gdbarch)
1817{
1818 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1819
1820 if (tdep->vnd_type == NULL)
1821 {
1822 struct type *t;
1823 struct type *elem;
1824
1825 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1826 TYPE_CODE_UNION);
1827
1828 elem = builtin_type (gdbarch)->builtin_double;
1829 append_composite_type_field (t, "f", elem);
1830
1831 elem = builtin_type (gdbarch)->builtin_uint64;
1832 append_composite_type_field (t, "u", elem);
1833
1834 elem = builtin_type (gdbarch)->builtin_int64;
1835 append_composite_type_field (t, "s", elem);
1836
1837 tdep->vnd_type = t;
1838 }
1839
1840 return tdep->vnd_type;
1841}
1842
1843/* Return the type for an AdvSISD S register. */
1844
1845static struct type *
1846aarch64_vns_type (struct gdbarch *gdbarch)
1847{
1848 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1849
1850 if (tdep->vns_type == NULL)
1851 {
1852 struct type *t;
1853 struct type *elem;
1854
1855 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1856 TYPE_CODE_UNION);
1857
1858 elem = builtin_type (gdbarch)->builtin_float;
1859 append_composite_type_field (t, "f", elem);
1860
1861 elem = builtin_type (gdbarch)->builtin_uint32;
1862 append_composite_type_field (t, "u", elem);
1863
1864 elem = builtin_type (gdbarch)->builtin_int32;
1865 append_composite_type_field (t, "s", elem);
1866
1867 tdep->vns_type = t;
1868 }
1869
1870 return tdep->vns_type;
1871}
1872
1873/* Return the type for an AdvSISD H register. */
1874
1875static struct type *
1876aarch64_vnh_type (struct gdbarch *gdbarch)
1877{
1878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1879
1880 if (tdep->vnh_type == NULL)
1881 {
1882 struct type *t;
1883 struct type *elem;
1884
1885 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1886 TYPE_CODE_UNION);
1887
1888 elem = builtin_type (gdbarch)->builtin_uint16;
1889 append_composite_type_field (t, "u", elem);
1890
1891 elem = builtin_type (gdbarch)->builtin_int16;
1892 append_composite_type_field (t, "s", elem);
1893
1894 tdep->vnh_type = t;
1895 }
1896
1897 return tdep->vnh_type;
1898}
1899
1900/* Return the type for an AdvSISD B register. */
1901
1902static struct type *
1903aarch64_vnb_type (struct gdbarch *gdbarch)
1904{
1905 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1906
1907 if (tdep->vnb_type == NULL)
1908 {
1909 struct type *t;
1910 struct type *elem;
1911
1912 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1913 TYPE_CODE_UNION);
1914
1915 elem = builtin_type (gdbarch)->builtin_uint8;
1916 append_composite_type_field (t, "u", elem);
1917
1918 elem = builtin_type (gdbarch)->builtin_int8;
1919 append_composite_type_field (t, "s", elem);
1920
1921 tdep->vnb_type = t;
1922 }
1923
1924 return tdep->vnb_type;
1925}
1926
63bad7b6
AH		 1927/* Return the type for an AdvSISD V register. */
1928
1929static struct type *
1930aarch64_vnv_type (struct gdbarch *gdbarch)
1931{
1932 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1933
1934 if (tdep->vnv_type == NULL)
1935 {
bffa1015
AH		 1936 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1937 slice from the non-pseudo vector registers. However NEON V registers
1938 are always vector registers, and need constructing as such. */
1939 const struct builtin_type *bt = builtin_type (gdbarch);
1940
63bad7b6
AH		 1941 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1942 TYPE_CODE_UNION);
1943
bffa1015
AH		 1944 struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1945 TYPE_CODE_UNION);
1946 append_composite_type_field (sub, "f",
1947 init_vector_type (bt->builtin_double, 2));
1948 append_composite_type_field (sub, "u",
1949 init_vector_type (bt->builtin_uint64, 2));
1950 append_composite_type_field (sub, "s",
1951 init_vector_type (bt->builtin_int64, 2));
1952 append_composite_type_field (t, "d", sub);
1953
1954 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1955 TYPE_CODE_UNION);
1956 append_composite_type_field (sub, "f",
1957 init_vector_type (bt->builtin_float, 4));
1958 append_composite_type_field (sub, "u",
1959 init_vector_type (bt->builtin_uint32, 4));
1960 append_composite_type_field (sub, "s",
1961 init_vector_type (bt->builtin_int32, 4));
1962 append_composite_type_field (t, "s", sub);
1963
1964 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1965 TYPE_CODE_UNION);
1966 append_composite_type_field (sub, "u",
1967 init_vector_type (bt->builtin_uint16, 8));
1968 append_composite_type_field (sub, "s",
1969 init_vector_type (bt->builtin_int16, 8));
1970 append_composite_type_field (t, "h", sub);
1971
1972 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1973 TYPE_CODE_UNION);
1974 append_composite_type_field (sub, "u",
1975 init_vector_type (bt->builtin_uint8, 16));
1976 append_composite_type_field (sub, "s",
1977 init_vector_type (bt->builtin_int8, 16));
1978 append_composite_type_field (t, "b", sub);
1979
1980 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1981 TYPE_CODE_UNION);
1982 append_composite_type_field (sub, "u",
1983 init_vector_type (bt->builtin_uint128, 1));
1984 append_composite_type_field (sub, "s",
1985 init_vector_type (bt->builtin_int128, 1));
1986 append_composite_type_field (t, "q", sub);
63bad7b6
AH		 1987
1988 tdep->vnv_type = t;
1989 }
1990
1991 return tdep->vnv_type;
1992}
1993
07b287a0
MS		 1994/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1995
1996static int
1997aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1998{
34dcc7cf
AH		 1999 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2000
07b287a0
MS		 2001 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
2002 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
2003
2004 if (reg == AARCH64_DWARF_SP)
2005 return AARCH64_SP_REGNUM;
2006
2007 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
2008 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
2009
65d4cada
AH		 2010 if (reg == AARCH64_DWARF_SVE_VG)
2011 return AARCH64_SVE_VG_REGNUM;
2012
2013 if (reg == AARCH64_DWARF_SVE_FFR)
2014 return AARCH64_SVE_FFR_REGNUM;
2015
2016 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
2017 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
2018
2019 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
2020 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
2021
34dcc7cf
AH		 2022 if (tdep->has_pauth ())
2023 {
2024 if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
2025 return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
2026
2027 if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
2028 return tdep->pauth_ra_state_regnum;
2029 }
2030
07b287a0
MS		 2031 return -1;
2032}
07b287a0
MS		 2033
2034/* Implement the "print_insn" gdbarch method. */
2035
2036static int
2037aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
2038{
2039 info->symbols = NULL;
6394c606 2040 return default_print_insn (memaddr, info);
07b287a0
MS		 2041}
2042
2043/* AArch64 BRK software debug mode instruction.
2044 Note that AArch64 code is always little-endian.
2045 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 2046constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 2047
04180708 2048typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 2049
2050/* Extract from an array REGS containing the (raw) register state a
2051 function return value of type TYPE, and copy that, in virtual
2052 format, into VALBUF. */
2053
2054static void
2055aarch64_extract_return_value (struct type *type, struct regcache *regs,
2056 gdb_byte *valbuf)
2057{
ac7936df 2058 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2059 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2060 int elements;
2061 struct type *fundamental_type;
07b287a0 2062
4f4aedeb
AH		 2063 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2064 &fundamental_type))
07b287a0 2065 {
4f4aedeb
AH		 2066 int len = TYPE_LENGTH (fundamental_type);
2067
2068 for (int i = 0; i < elements; i++)
2069 {
2070 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2071 /* Enough space for a full vector register. */
2072 gdb_byte buf[register_size (gdbarch, regno)];
2073 gdb_assert (len <= sizeof (buf));
4f4aedeb
AH		 2074
2075 if (aarch64_debug)
2076 {
2077 debug_printf ("read HFA or HVA return value element %d from %s\n",
2078 i + 1,
2079 gdbarch_register_name (gdbarch, regno));
2080 }
2081 regs->cooked_read (regno, buf);
07b287a0 2082
4f4aedeb
AH		 2083 memcpy (valbuf, buf, len);
2084 valbuf += len;
2085 }
07b287a0
MS		 2086 }
2087 else if (TYPE_CODE (type) == TYPE_CODE_INT
2088 || TYPE_CODE (type) == TYPE_CODE_CHAR
2089 || TYPE_CODE (type) == TYPE_CODE_BOOL
2090 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2091 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2092 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2093 {
6471e7d2 2094 /* If the type is a plain integer, then the access is
07b287a0
MS		 2095 straight-forward. Otherwise we have to play around a bit
2096 more. */
2097 int len = TYPE_LENGTH (type);
2098 int regno = AARCH64_X0_REGNUM;
2099 ULONGEST tmp;
2100
2101 while (len > 0)
2102 {
2103 /* By using store_unsigned_integer we avoid having to do
2104 anything special for small big-endian values. */
2105 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2106 store_unsigned_integer (valbuf,
2107 (len > X_REGISTER_SIZE
2108 ? X_REGISTER_SIZE : len), byte_order, tmp);
2109 len -= X_REGISTER_SIZE;
2110 valbuf += X_REGISTER_SIZE;
2111 }
2112 }
07b287a0
MS		 2113 else
2114 {
2115 /* For a structure or union the behaviour is as if the value had
2116 been stored to word-aligned memory and then loaded into
2117 registers with 64-bit load instruction(s). */
2118 int len = TYPE_LENGTH (type);
2119 int regno = AARCH64_X0_REGNUM;
2120 bfd_byte buf[X_REGISTER_SIZE];
2121
2122 while (len > 0)
2123 {
dca08e1f 2124 regs->cooked_read (regno++, buf);
07b287a0
MS		 2125 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2126 len -= X_REGISTER_SIZE;
2127 valbuf += X_REGISTER_SIZE;
2128 }
2129 }
2130}
2131
2132
2133/* Will a function return an aggregate type in memory or in a
2134 register? Return 0 if an aggregate type can be returned in a
2135 register, 1 if it must be returned in memory. */
2136
2137static int
2138aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2139{
f168693b 2140 type = check_typedef (type);
4f4aedeb
AH		 2141 int elements;
2142 struct type *fundamental_type;
07b287a0 2143
4f4aedeb
AH		 2144 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2145 &fundamental_type))
07b287a0 2146 {
cd635f74
YQ		 2147 /* v0-v7 are used to return values and one register is allocated
2148 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 2149 return 0;
2150 }
2151
2152 if (TYPE_LENGTH (type) > 16)
2153 {
2154 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2155 invisible reference. */
2156
2157 return 1;
2158 }
2159
2160 return 0;
2161}
2162
2163/* Write into appropriate registers a function return value of type
2164 TYPE, given in virtual format. */
2165
2166static void
2167aarch64_store_return_value (struct type *type, struct regcache *regs,
2168 const gdb_byte *valbuf)
2169{
ac7936df 2170 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2171 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2172 int elements;
2173 struct type *fundamental_type;
07b287a0 2174
4f4aedeb
AH		 2175 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2176 &fundamental_type))
07b287a0 2177 {
4f4aedeb
AH		 2178 int len = TYPE_LENGTH (fundamental_type);
2179
2180 for (int i = 0; i < elements; i++)
2181 {
2182 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2183 /* Enough space for a full vector register. */
2184 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2185 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb
AH		 2186
2187 if (aarch64_debug)
2188 {
2189 debug_printf ("write HFA or HVA return value element %d to %s\n",
2190 i + 1,
2191 gdbarch_register_name (gdbarch, regno));
2192 }
07b287a0 2193
4f4aedeb
AH		 2194 memcpy (tmpbuf, valbuf,
2195 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2196 regs->cooked_write (regno, tmpbuf);
2197 valbuf += len;
2198 }
07b287a0
MS		 2199 }
2200 else if (TYPE_CODE (type) == TYPE_CODE_INT
2201 || TYPE_CODE (type) == TYPE_CODE_CHAR
2202 || TYPE_CODE (type) == TYPE_CODE_BOOL
2203 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2204 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2205 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2206 {
2207 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2208 {
2209 /* Values of one word or less are zero/sign-extended and
2210 returned in r0. */
2211 bfd_byte tmpbuf[X_REGISTER_SIZE];
2212 LONGEST val = unpack_long (type, valbuf);
2213
2214 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2215 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2216 }
2217 else
2218 {
2219 /* Integral values greater than one word are stored in
2220 consecutive registers starting with r0. This will always
2221 be a multiple of the regiser size. */
2222 int len = TYPE_LENGTH (type);
2223 int regno = AARCH64_X0_REGNUM;
2224
2225 while (len > 0)
2226 {
b66f5587 2227 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2228 len -= X_REGISTER_SIZE;
2229 valbuf += X_REGISTER_SIZE;
2230 }
2231 }
2232 }
07b287a0
MS		 2233 else
2234 {
2235 /* For a structure or union the behaviour is as if the value had
2236 been stored to word-aligned memory and then loaded into
2237 registers with 64-bit load instruction(s). */
2238 int len = TYPE_LENGTH (type);
2239 int regno = AARCH64_X0_REGNUM;
2240 bfd_byte tmpbuf[X_REGISTER_SIZE];
2241
2242 while (len > 0)
2243 {
2244 memcpy (tmpbuf, valbuf,
2245 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2246 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2247 len -= X_REGISTER_SIZE;
2248 valbuf += X_REGISTER_SIZE;
2249 }
2250 }
2251}
2252
2253/* Implement the "return_value" gdbarch method. */
2254
2255static enum return_value_convention
2256aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2257 struct type *valtype, struct regcache *regcache,
2258 gdb_byte *readbuf, const gdb_byte *writebuf)
2259{
07b287a0
MS		 2260
2261 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2262 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2263 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2264 {
2265 if (aarch64_return_in_memory (gdbarch, valtype))
2266 {
2267 if (aarch64_debug)
b277c936 2268 debug_printf ("return value in memory\n");
07b287a0
MS		 2269 return RETURN_VALUE_STRUCT_CONVENTION;
2270 }
2271 }
2272
2273 if (writebuf)
2274 aarch64_store_return_value (valtype, regcache, writebuf);
2275
2276 if (readbuf)
2277 aarch64_extract_return_value (valtype, regcache, readbuf);
2278
2279 if (aarch64_debug)
b277c936 2280 debug_printf ("return value in registers\n");
07b287a0
MS		 2281
2282 return RETURN_VALUE_REGISTER_CONVENTION;
2283}
2284
2285/* Implement the "get_longjmp_target" gdbarch method. */
2286
2287static int
2288aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2289{
2290 CORE_ADDR jb_addr;
2291 gdb_byte buf[X_REGISTER_SIZE];
2292 struct gdbarch *gdbarch = get_frame_arch (frame);
2293 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2294 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2295
2296 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2297
2298 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2299 X_REGISTER_SIZE))
2300 return 0;
2301
2302 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2303 return 1;
2304}
ea873d8e
PL		 2305
2306/* Implement the "gen_return_address" gdbarch method. */
2307
2308static void
2309aarch64_gen_return_address (struct gdbarch *gdbarch,
2310 struct agent_expr *ax, struct axs_value *value,
2311 CORE_ADDR scope)
2312{
2313 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2314 value->kind = axs_lvalue_register;
2315 value->u.reg = AARCH64_LR_REGNUM;
2316}
07b287a0
MS		 2317\f
2318
2319/* Return the pseudo register name corresponding to register regnum. */
2320
2321static const char *
2322aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2323{
63bad7b6
AH		 2324 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2325
07b287a0
MS		 2326 static const char *const q_name[] =
2327 {
2328 "q0", "q1", "q2", "q3",
2329 "q4", "q5", "q6", "q7",
2330 "q8", "q9", "q10", "q11",
2331 "q12", "q13", "q14", "q15",
2332 "q16", "q17", "q18", "q19",
2333 "q20", "q21", "q22", "q23",
2334 "q24", "q25", "q26", "q27",
2335 "q28", "q29", "q30", "q31",
2336 };
2337
2338 static const char *const d_name[] =
2339 {
2340 "d0", "d1", "d2", "d3",
2341 "d4", "d5", "d6", "d7",
2342 "d8", "d9", "d10", "d11",
2343 "d12", "d13", "d14", "d15",
2344 "d16", "d17", "d18", "d19",
2345 "d20", "d21", "d22", "d23",
2346 "d24", "d25", "d26", "d27",
2347 "d28", "d29", "d30", "d31",
2348 };
2349
2350 static const char *const s_name[] =
2351 {
2352 "s0", "s1", "s2", "s3",
2353 "s4", "s5", "s6", "s7",
2354 "s8", "s9", "s10", "s11",
2355 "s12", "s13", "s14", "s15",
2356 "s16", "s17", "s18", "s19",
2357 "s20", "s21", "s22", "s23",
2358 "s24", "s25", "s26", "s27",
2359 "s28", "s29", "s30", "s31",
2360 };
2361
2362 static const char *const h_name[] =
2363 {
2364 "h0", "h1", "h2", "h3",
2365 "h4", "h5", "h6", "h7",
2366 "h8", "h9", "h10", "h11",
2367 "h12", "h13", "h14", "h15",
2368 "h16", "h17", "h18", "h19",
2369 "h20", "h21", "h22", "h23",
2370 "h24", "h25", "h26", "h27",
2371 "h28", "h29", "h30", "h31",
2372 };
2373
2374 static const char *const b_name[] =
2375 {
2376 "b0", "b1", "b2", "b3",
2377 "b4", "b5", "b6", "b7",
2378 "b8", "b9", "b10", "b11",
2379 "b12", "b13", "b14", "b15",
2380 "b16", "b17", "b18", "b19",
2381 "b20", "b21", "b22", "b23",
2382 "b24", "b25", "b26", "b27",
2383 "b28", "b29", "b30", "b31",
2384 };
2385
34dcc7cf 2386 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2387
34dcc7cf
AH		 2388 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2389 return q_name[p_regnum - AARCH64_Q0_REGNUM];
07b287a0 2390
34dcc7cf
AH		 2391 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2392 return d_name[p_regnum - AARCH64_D0_REGNUM];
07b287a0 2393
34dcc7cf
AH		 2394 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2395 return s_name[p_regnum - AARCH64_S0_REGNUM];
07b287a0 2396
34dcc7cf
AH		 2397 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2398 return h_name[p_regnum - AARCH64_H0_REGNUM];
07b287a0 2399
34dcc7cf
AH		 2400 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2401 return b_name[p_regnum - AARCH64_B0_REGNUM];
07b287a0 2402
63bad7b6
AH		 2403 if (tdep->has_sve ())
2404 {
2405 static const char *const sve_v_name[] =
2406 {
2407 "v0", "v1", "v2", "v3",
2408 "v4", "v5", "v6", "v7",
2409 "v8", "v9", "v10", "v11",
2410 "v12", "v13", "v14", "v15",
2411 "v16", "v17", "v18", "v19",
2412 "v20", "v21", "v22", "v23",
2413 "v24", "v25", "v26", "v27",
2414 "v28", "v29", "v30", "v31",
2415 };
2416
34dcc7cf
AH		 2417 if (p_regnum >= AARCH64_SVE_V0_REGNUM
2418 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2419 return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
63bad7b6
AH		 2420 }
2421
34dcc7cf
AH		 2422 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2423 prevents it from being read by methods such as
2424 mi_cmd_trace_frame_collected. */
2425 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2426 return "";
2427
07b287a0
MS		 2428 internal_error (__FILE__, __LINE__,
2429 _("aarch64_pseudo_register_name: bad register number %d"),
34dcc7cf 2430 p_regnum);
07b287a0
MS		 2431}
2432
2433/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2434
2435static struct type *
2436aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2437{
63bad7b6
AH		 2438 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2439
34dcc7cf 2440 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2441
34dcc7cf 2442 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0
MS		 2443 return aarch64_vnq_type (gdbarch);
2444
34dcc7cf 2445 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2446 return aarch64_vnd_type (gdbarch);
2447
34dcc7cf 2448 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2449 return aarch64_vns_type (gdbarch);
2450
34dcc7cf 2451 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0
MS		 2452 return aarch64_vnh_type (gdbarch);
2453
34dcc7cf 2454 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0
MS		 2455 return aarch64_vnb_type (gdbarch);
2456
34dcc7cf
AH		 2457 if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2458 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6
AH		 2459 return aarch64_vnv_type (gdbarch);
2460
34dcc7cf
AH		 2461 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2462 return builtin_type (gdbarch)->builtin_uint64;
2463
07b287a0
MS		 2464 internal_error (__FILE__, __LINE__,
2465 _("aarch64_pseudo_register_type: bad register number %d"),
34dcc7cf 2466 p_regnum);
07b287a0
MS		 2467}
2468
2469/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2470
2471static int
2472aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2473 struct reggroup *group)
2474{
63bad7b6
AH		 2475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2476
34dcc7cf 2477 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2478
34dcc7cf 2479 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0 2480 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2481 else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2482 return (group == all_reggroup || group == vector_reggroup
2483 || group == float_reggroup);
34dcc7cf 2484 else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2485 return (group == all_reggroup || group == vector_reggroup
2486 || group == float_reggroup);
34dcc7cf 2487 else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0 2488 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2489 else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0 2490 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2491 else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2492 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6 2493 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2494 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2495 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2496 return 0;
07b287a0
MS		 2497
2498 return group == all_reggroup;
2499}
2500
3c5cd5c3
AH		 2501/* Helper for aarch64_pseudo_read_value. */
2502
2503static struct value *
63bad7b6
AH		 2504aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2505 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2506 int regsize, struct value *result_value)
2507{
3c5cd5c3
AH		 2508 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2509
63bad7b6
AH		 2510 /* Enough space for a full vector register. */
2511 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2512 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2513
3c5cd5c3
AH		 2514 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2515 mark_value_bytes_unavailable (result_value, 0,
2516 TYPE_LENGTH (value_type (result_value)));
2517 else
2518 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2519
3c5cd5c3
AH		 2520 return result_value;
2521 }
2522
07b287a0
MS		 2523/* Implement the "pseudo_register_read_value" gdbarch method. */
2524
2525static struct value *
3c5cd5c3 2526aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2527 int regnum)
2528{
63bad7b6 2529 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2530 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2531
07b287a0
MS		 2532 VALUE_LVAL (result_value) = lval_register;
2533 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2534
2535 regnum -= gdbarch_num_regs (gdbarch);
2536
2537 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2538 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2539 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2540 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2541
2542 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2543 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2544 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2545 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2546
2547 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2548 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2549 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2550 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2551
2552 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2553 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2554 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2555 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2556
2557 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2558 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2559 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2560 B_REGISTER_SIZE, result_value);
07b287a0 2561
63bad7b6
AH		 2562 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2563 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2564 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2565 regnum - AARCH64_SVE_V0_REGNUM,
2566 V_REGISTER_SIZE, result_value);
2567
07b287a0
MS		 2568 gdb_assert_not_reached ("regnum out of bound");
2569}
2570
3c5cd5c3 2571/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2572
2573static void
63bad7b6
AH		 2574aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2575 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2576{
3c5cd5c3 2577 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2578
63bad7b6
AH		 2579 /* Enough space for a full vector register. */
2580 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2581 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2582
07b287a0
MS		 2583 /* Ensure the register buffer is zero, we want gdb writes of the
2584 various 'scalar' pseudo registers to behavior like architectural
2585 writes, register width bytes are written the remainder are set to
2586 zero. */
63bad7b6 2587 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2588
3c5cd5c3
AH		 2589 memcpy (reg_buf, buf, regsize);
2590 regcache->raw_write (v_regnum, reg_buf);
2591}
2592
2593/* Implement the "pseudo_register_write" gdbarch method. */
2594
2595static void
2596aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2597 int regnum, const gdb_byte *buf)
2598{
63bad7b6 2599 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2600 regnum -= gdbarch_num_regs (gdbarch);
2601
2602 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2603 return aarch64_pseudo_write_1 (gdbarch, regcache,
2604 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2605 buf);
07b287a0
MS		 2606
2607 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2608 return aarch64_pseudo_write_1 (gdbarch, regcache,
2609 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2610 buf);
07b287a0
MS		 2611
2612 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2613 return aarch64_pseudo_write_1 (gdbarch, regcache,
2614 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2615 buf);
07b287a0
MS		 2616
2617 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2618 return aarch64_pseudo_write_1 (gdbarch, regcache,
2619 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2620 buf);
07b287a0
MS		 2621
2622 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2623 return aarch64_pseudo_write_1 (gdbarch, regcache,
2624 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2625 buf);
2626
2627 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2628 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2629 return aarch64_pseudo_write_1 (gdbarch, regcache,
2630 regnum - AARCH64_SVE_V0_REGNUM,
2631 V_REGISTER_SIZE, buf);
07b287a0
MS		 2632
2633 gdb_assert_not_reached ("regnum out of bound");
2634}
2635
07b287a0
MS		 2636/* Callback function for user_reg_add. */
2637
2638static struct value *
2639value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2640{
9a3c8263 2641 const int *reg_p = (const int *) baton;
07b287a0
MS		 2642
2643 return value_of_register (*reg_p, frame);
2644}
2645\f
2646
9404b58f
KM		 2647/* Implement the "software_single_step" gdbarch method, needed to
2648 single step through atomic sequences on AArch64. */
2649
a0ff9e1a 2650static std::vector<CORE_ADDR>
f5ea389a 2651aarch64_software_single_step (struct regcache *regcache)
9404b58f 2652{
ac7936df 2653 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2654 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2655 const int insn_size = 4;
2656 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2657 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2658 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2659 CORE_ADDR loc = pc;
2660 CORE_ADDR closing_insn = 0;
2661 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2662 byte_order_for_code);
2663 int index;
2664 int insn_count;
2665 int bc_insn_count = 0; /* Conditional branch instruction count. */
2666 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2667 aarch64_inst inst;
2668
561a72d4 2669 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2670 return {};
9404b58f
KM		 2671
2672 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2673 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2674 return {};
9404b58f
KM		 2675
2676 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2677 {
9404b58f
KM		 2678 loc += insn_size;
2679 insn = read_memory_unsigned_integer (loc, insn_size,
2680 byte_order_for_code);
2681
561a72d4 2682 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2683 return {};
9404b58f 2684 /* Check if the instruction is a conditional branch. */
f77ee802 2685 if (inst.opcode->iclass == condbranch)
9404b58f 2686 {
f77ee802
YQ		 2687 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2688
9404b58f 2689 if (bc_insn_count >= 1)
a0ff9e1a 2690 return {};
9404b58f
KM		 2691
2692 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2693 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2694
2695 bc_insn_count++;
2696 last_breakpoint++;
2697 }
2698
2699 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2700 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2701 {
2702 closing_insn = loc;
2703 break;
2704 }
2705 }
2706
2707 /* We didn't find a closing Store Exclusive instruction, fall back. */
2708 if (!closing_insn)
a0ff9e1a 2709 return {};
9404b58f
KM		 2710
2711 /* Insert breakpoint after the end of the atomic sequence. */
2712 breaks[0] = loc + insn_size;
2713
2714 /* Check for duplicated breakpoints, and also check that the second
2715 breakpoint is not within the atomic sequence. */
2716 if (last_breakpoint
2717 && (breaks[1] == breaks[0]
2718 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2719 last_breakpoint = 0;
2720
a0ff9e1a
SM		 2721 std::vector<CORE_ADDR> next_pcs;
2722
9404b58f
KM		 2723 /* Insert the breakpoint at the end of the sequence, and one at the
2724 destination of the conditional branch, if it exists. */
2725 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2726 next_pcs.push_back (breaks[index]);
9404b58f 2727
93f9a11f 2728 return next_pcs;
9404b58f
KM		 2729}
2730
cfba9872 2731struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2732{
2733 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2734 is being displaced stepping. */
cfba9872 2735 int cond = 0;
b6542f81
YQ		 2736
2737 /* PC adjustment offset after displaced stepping. */
cfba9872 2738 int32_t pc_adjust = 0;
b6542f81
YQ		 2739};
2740
2741/* Data when visiting instructions for displaced stepping. */
2742
2743struct aarch64_displaced_step_data
2744{
2745 struct aarch64_insn_data base;
2746
2747 /* The address where the instruction will be executed at. */
2748 CORE_ADDR new_addr;
2749 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2750 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2751 /* Number of instructions in INSN_BUF. */
2752 unsigned insn_count;
2753 /* Registers when doing displaced stepping. */
2754 struct regcache *regs;
2755
cfba9872 2756 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2757};
2758
2759/* Implementation of aarch64_insn_visitor method "b". */
2760
2761static void
2762aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2763 struct aarch64_insn_data *data)
2764{
2765 struct aarch64_displaced_step_data *dsd
2766 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2767 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2768
2769 if (can_encode_int32 (new_offset, 28))
2770 {
2771 /* Emit B rather than BL, because executing BL on a new address
2772 will get the wrong address into LR. In order to avoid this,
2773 we emit B, and update LR if the instruction is BL. */
2774 emit_b (dsd->insn_buf, 0, new_offset);
2775 dsd->insn_count++;
2776 }
2777 else
2778 {
2779 /* Write NOP. */
2780 emit_nop (dsd->insn_buf);
2781 dsd->insn_count++;
2782 dsd->dsc->pc_adjust = offset;
2783 }
2784
2785 if (is_bl)
2786 {
2787 /* Update LR. */
2788 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2789 data->insn_addr + 4);
2790 }
2791}
2792
2793/* Implementation of aarch64_insn_visitor method "b_cond". */
2794
2795static void
2796aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2797 struct aarch64_insn_data *data)
2798{
2799 struct aarch64_displaced_step_data *dsd
2800 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2801
2802 /* GDB has to fix up PC after displaced step this instruction
2803 differently according to the condition is true or false. Instead
2804 of checking COND against conditional flags, we can use
2805 the following instructions, and GDB can tell how to fix up PC
2806 according to the PC value.
2807
2808 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2809 INSN1 ;
2810 TAKEN:
2811 INSN2
2812 */
2813
2814 emit_bcond (dsd->insn_buf, cond, 8);
2815 dsd->dsc->cond = 1;
2816 dsd->dsc->pc_adjust = offset;
2817 dsd->insn_count = 1;
2818}
2819
2820/* Dynamically allocate a new register. If we know the register
2821 statically, we should make it a global as above instead of using this
2822 helper function. */
2823
2824static struct aarch64_register
2825aarch64_register (unsigned num, int is64)
2826{
2827 return (struct aarch64_register) { num, is64 };
2828}
2829
2830/* Implementation of aarch64_insn_visitor method "cb". */
2831
2832static void
2833aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2834 const unsigned rn, int is64,
2835 struct aarch64_insn_data *data)
2836{
2837 struct aarch64_displaced_step_data *dsd
2838 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2839
2840 /* The offset is out of range for a compare and branch
2841 instruction. We can use the following instructions instead:
2842
2843 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2844 INSN1 ;
2845 TAKEN:
2846 INSN2
2847 */
2848 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2849 dsd->insn_count = 1;
2850 dsd->dsc->cond = 1;
2851 dsd->dsc->pc_adjust = offset;
2852}
2853
2854/* Implementation of aarch64_insn_visitor method "tb". */
2855
2856static void
2857aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2858 const unsigned rt, unsigned bit,
2859 struct aarch64_insn_data *data)
2860{
2861 struct aarch64_displaced_step_data *dsd
2862 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2863
2864 /* The offset is out of range for a test bit and branch
2865 instruction We can use the following instructions instead:
2866
2867 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2868 INSN1 ;
2869 TAKEN:
2870 INSN2
2871
2872 */
2873 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2874 dsd->insn_count = 1;
2875 dsd->dsc->cond = 1;
2876 dsd->dsc->pc_adjust = offset;
2877}
2878
2879/* Implementation of aarch64_insn_visitor method "adr". */
2880
2881static void
2882aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2883 const int is_adrp, struct aarch64_insn_data *data)
2884{
2885 struct aarch64_displaced_step_data *dsd
2886 = (struct aarch64_displaced_step_data *) data;
2887 /* We know exactly the address the ADR{P,} instruction will compute.
2888 We can just write it to the destination register. */
2889 CORE_ADDR address = data->insn_addr + offset;
2890
2891 if (is_adrp)
2892 {
2893 /* Clear the lower 12 bits of the offset to get the 4K page. */
2894 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2895 address & ~0xfff);
2896 }
2897 else
2898 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2899 address);
2900
2901 dsd->dsc->pc_adjust = 4;
2902 emit_nop (dsd->insn_buf);
2903 dsd->insn_count = 1;
2904}
2905
2906/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2907
2908static void
2909aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2910 const unsigned rt, const int is64,
2911 struct aarch64_insn_data *data)
2912{
2913 struct aarch64_displaced_step_data *dsd
2914 = (struct aarch64_displaced_step_data *) data;
2915 CORE_ADDR address = data->insn_addr + offset;
2916 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2917
2918 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2919 address);
2920
2921 if (is_sw)
2922 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2923 aarch64_register (rt, 1), zero);
2924 else
2925 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2926 aarch64_register (rt, 1), zero);
2927
2928 dsd->dsc->pc_adjust = 4;
2929}
2930
2931/* Implementation of aarch64_insn_visitor method "others". */
2932
2933static void
2934aarch64_displaced_step_others (const uint32_t insn,
2935 struct aarch64_insn_data *data)
2936{
2937 struct aarch64_displaced_step_data *dsd
2938 = (struct aarch64_displaced_step_data *) data;
2939
e1c587c3 2940 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2941 dsd->insn_count = 1;
2942
2943 if ((insn & 0xfffffc1f) == 0xd65f0000)
2944 {
2945 /* RET */
2946 dsd->dsc->pc_adjust = 0;
2947 }
2948 else
2949 dsd->dsc->pc_adjust = 4;
2950}
2951
2952static const struct aarch64_insn_visitor visitor =
2953{
2954 aarch64_displaced_step_b,
2955 aarch64_displaced_step_b_cond,
2956 aarch64_displaced_step_cb,
2957 aarch64_displaced_step_tb,
2958 aarch64_displaced_step_adr,
2959 aarch64_displaced_step_ldr_literal,
2960 aarch64_displaced_step_others,
2961};
2962
2963/* Implement the "displaced_step_copy_insn" gdbarch method. */
2964
2965struct displaced_step_closure *
2966aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2967 CORE_ADDR from, CORE_ADDR to,
2968 struct regcache *regs)
2969{
b6542f81
YQ		 2970 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2971 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2972 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 2973 aarch64_inst inst;
2974
561a72d4 2975 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 2976 return NULL;
b6542f81
YQ		 2977
2978 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 2979 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 2980 {
2981 /* We can't displaced step atomic sequences. */
2982 return NULL;
2983 }
2984
cfba9872
SM		 2985 std::unique_ptr<aarch64_displaced_step_closure> dsc
2986 (new aarch64_displaced_step_closure);
b6542f81
YQ		 2987 dsd.base.insn_addr = from;
2988 dsd.new_addr = to;
2989 dsd.regs = regs;
cfba9872 2990 dsd.dsc = dsc.get ();
034f1a81 2991 dsd.insn_count = 0;
b6542f81
YQ		 2992 aarch64_relocate_instruction (insn, &visitor,
2993 (struct aarch64_insn_data *) &dsd);
2994 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2995
2996 if (dsd.insn_count != 0)
2997 {
2998 int i;
2999
3000 /* Instruction can be relocated to scratch pad. Copy
3001 relocated instruction(s) there. */
3002 for (i = 0; i < dsd.insn_count; i++)
3003 {
3004 if (debug_displaced)
3005 {
3006 debug_printf ("displaced: writing insn ");
3007 debug_printf ("%.8x", dsd.insn_buf[i]);
3008 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
3009 }
3010 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
3011 (ULONGEST) dsd.insn_buf[i]);
3012 }
3013 }
3014 else
3015 {
b6542f81
YQ		 3016 dsc = NULL;
3017 }
3018
cfba9872 3019 return dsc.release ();
b6542f81
YQ		 3020}
3021
3022/* Implement the "displaced_step_fixup" gdbarch method. */
3023
3024void
3025aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 3026 struct displaced_step_closure *dsc_,
b6542f81
YQ		 3027 CORE_ADDR from, CORE_ADDR to,
3028 struct regcache *regs)
3029{
cfba9872
SM		 3030 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
3031
b6542f81
YQ		 3032 if (dsc->cond)
3033 {
3034 ULONGEST pc;
3035
3036 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
3037 if (pc - to == 8)
3038 {
3039 /* Condition is true. */
3040 }
3041 else if (pc - to == 4)
3042 {
3043 /* Condition is false. */
3044 dsc->pc_adjust = 4;
3045 }
3046 else
3047 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3048 }
3049
3050 if (dsc->pc_adjust != 0)
3051 {
3052 if (debug_displaced)
3053 {
3054 debug_printf ("displaced: fixup: set PC to %s:%d\n",
3055 paddress (gdbarch, from), dsc->pc_adjust);
3056 }
3057 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
3058 from + dsc->pc_adjust);
3059 }
3060}
3061
3062/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3063
3064int
3065aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
3066 struct displaced_step_closure *closure)
3067{
3068 return 1;
3069}
3070
95228a0d
AH		 3071/* Get the correct target description for the given VQ value.
3072 If VQ is zero then it is assumed SVE is not supported.
3073 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 3074
3075const target_desc *
6dc0ebde 3076aarch64_read_description (uint64_t vq, bool pauth_p)
da434ccb 3077{
95228a0d 3078 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 3079 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 3080 AARCH64_MAX_SVE_VQ);
3081
6dc0ebde 3082 struct target_desc *tdesc = tdesc_aarch64_list[vq][pauth_p];
da434ccb 3083
95228a0d
AH		 3084 if (tdesc == NULL)
3085 {
6dc0ebde
AH		 3086 tdesc = aarch64_create_target_description (vq, pauth_p);
3087 tdesc_aarch64_list[vq][pauth_p] = tdesc;
95228a0d 3088 }
da434ccb 3089
95228a0d 3090 return tdesc;
da434ccb
AH		 3091}
3092
ba2d2bb2
AH		 3093/* Return the VQ used when creating the target description TDESC. */
3094
1332a140 3095static uint64_t
ba2d2bb2
AH		 3096aarch64_get_tdesc_vq (const struct target_desc *tdesc)
3097{
3098 const struct tdesc_feature *feature_sve;
3099
3100 if (!tdesc_has_registers (tdesc))
3101 return 0;
3102
3103 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3104
3105 if (feature_sve == nullptr)
3106 return 0;
3107
12863263
AH		 3108 uint64_t vl = tdesc_register_bitsize (feature_sve,
3109 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 3110 return sve_vq_from_vl (vl);
3111}
3112
0ef8a082
AH		 3113/* Add all the expected register sets into GDBARCH. */
3114
3115static void
3116aarch64_add_reggroups (struct gdbarch *gdbarch)
3117{
3118 reggroup_add (gdbarch, general_reggroup);
3119 reggroup_add (gdbarch, float_reggroup);
3120 reggroup_add (gdbarch, system_reggroup);
3121 reggroup_add (gdbarch, vector_reggroup);
3122 reggroup_add (gdbarch, all_reggroup);
3123 reggroup_add (gdbarch, save_reggroup);
3124 reggroup_add (gdbarch, restore_reggroup);
3125}
ba2d2bb2 3126
76bed0fd
AH		 3127/* Implement the "cannot_store_register" gdbarch method. */
3128
3129static int
3130aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum)
3131{
3132 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3133
3134 if (!tdep->has_pauth ())
3135 return 0;
3136
3137 /* Pointer authentication registers are read-only. */
3138 return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
3139 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base));
3140}
3141
07b287a0
MS		 3142/* Initialize the current architecture based on INFO. If possible,
3143 re-use an architecture from ARCHES, which is a list of
3144 architectures already created during this debugging session.
3145
3146 Called e.g. at program startup, when reading a core file, and when
3147 reading a binary file. */
3148
3149static struct gdbarch *
3150aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3151{
ccb8d7e8 3152 const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve;
76bed0fd 3153 const struct tdesc_feature *feature_pauth;
ccb8d7e8
AH		 3154 bool valid_p = true;
3155 int i, num_regs = 0, num_pseudo_regs = 0;
3156 int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
3157
4da037ef
AH		 3158 /* Use the vector length passed via the target info. Here -1 is used for no
3159 SVE, and 0 is unset. If unset then use the vector length from the existing
3160 tdesc. */
3161 uint64_t vq = 0;
3162 if (info.id == (int *) -1)
3163 vq = 0;
3164 else if (info.id != 0)
3165 vq = (uint64_t) info.id;
3166 else
3167 vq = aarch64_get_tdesc_vq (info.target_desc);
3168
3169 if (vq > AARCH64_MAX_SVE_VQ)
596179f7
SDJ		 3170 internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"),
3171 pulongest (vq), AARCH64_MAX_SVE_VQ);
4da037ef 3172
ccb8d7e8
AH		 3173 /* If there is already a candidate, use it. */
3174 for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
3175 best_arch != nullptr;
3176 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3177 {
3178 struct gdbarch_tdep *tdep = gdbarch_tdep (best_arch->gdbarch);
4da037ef 3179 if (tdep && tdep->vq == vq)
ccb8d7e8
AH		 3180 return best_arch->gdbarch;
3181 }
07b287a0 3182
4da037ef
AH		 3183 /* Ensure we always have a target descriptor, and that it is for the given VQ
3184 value. */
ccb8d7e8 3185 const struct target_desc *tdesc = info.target_desc;
4da037ef
AH		 3186 if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc))
3187 tdesc = aarch64_read_description (vq, false);
07b287a0
MS		 3188 gdb_assert (tdesc);
3189
ccb8d7e8 3190 feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
ba2d2bb2
AH		 3191 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
3192 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
76bed0fd 3193 feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
07b287a0 3194
ccb8d7e8
AH		 3195 if (feature_core == nullptr)
3196 return nullptr;
07b287a0 3197
ccb8d7e8 3198 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
07b287a0 3199
ba2d2bb2 3200 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 3201 and allocate their numbers. */
3202 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 3203 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
3204 AARCH64_X0_REGNUM + i,
3205 aarch64_r_register_names[i]);
07b287a0
MS		 3206
3207 num_regs = AARCH64_X0_REGNUM + i;
3208
ba2d2bb2 3209 /* Add the V registers. */
ccb8d7e8 3210 if (feature_fpu != nullptr)
07b287a0 3211 {
ccb8d7e8 3212 if (feature_sve != nullptr)
ba2d2bb2
AH		 3213 error (_("Program contains both fpu and SVE features."));
3214
3215 /* Validate the description provides the mandatory V registers
3216 and allocate their numbers. */
07b287a0 3217 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 3218 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
3219 AARCH64_V0_REGNUM + i,
3220 aarch64_v_register_names[i]);
07b287a0
MS		 3221
3222 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 3223 }
07b287a0 3224
ba2d2bb2 3225 /* Add the SVE registers. */
ccb8d7e8 3226 if (feature_sve != nullptr)
ba2d2bb2
AH		 3227 {
3228 /* Validate the description provides the mandatory SVE registers
3229 and allocate their numbers. */
3230 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3231 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3232 AARCH64_SVE_Z0_REGNUM + i,
3233 aarch64_sve_register_names[i]);
3234
3235 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3236 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3237 }
3238
ccb8d7e8 3239 if (feature_fpu != nullptr || feature_sve != nullptr)
ba2d2bb2 3240 {
07b287a0
MS		 3241 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3242 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3243 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3244 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3245 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3246 }
3247
76bed0fd
AH		 3248 /* Add the pauth registers. */
3249 if (feature_pauth != NULL)
3250 {
3251 first_pauth_regnum = num_regs;
34dcc7cf 3252 pauth_ra_state_offset = num_pseudo_regs;
76bed0fd
AH		 3253 /* Validate the descriptor provides the mandatory PAUTH registers and
3254 allocate their numbers. */
3255 for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
3256 valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data,
3257 first_pauth_regnum + i,
3258 aarch64_pauth_register_names[i]);
3259
3260 num_regs += i;
34dcc7cf 3261 num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
76bed0fd
AH		 3262 }
3263
07b287a0
MS		 3264 if (!valid_p)
3265 {
3266 tdesc_data_cleanup (tdesc_data);
ccb8d7e8 3267 return nullptr;
07b287a0
MS		 3268 }
3269
3270 /* AArch64 code is always little-endian. */
3271 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3272
ccb8d7e8
AH		 3273 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
3274 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
07b287a0
MS		 3275
3276 /* This should be low enough for everything. */
3277 tdep->lowest_pc = 0x20;
3278 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3279 tdep->jb_elt_size = 8;
4da037ef 3280 tdep->vq = vq;
76bed0fd 3281 tdep->pauth_reg_base = first_pauth_regnum;
34dcc7cf
AH		 3282 tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
3283 : pauth_ra_state_offset + num_regs;
3284
07b287a0
MS		 3285 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3286 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3287
07b287a0
MS		 3288 /* Advance PC across function entry code. */
3289 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3290
3291 /* The stack grows downward. */
3292 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3293
3294 /* Breakpoint manipulation. */
04180708
YQ		 3295 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3296 aarch64_breakpoint::kind_from_pc);
3297 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3298 aarch64_breakpoint::bp_from_kind);
07b287a0 3299 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3300 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3301
3302 /* Information about registers, etc. */
3303 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3304 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3305 set_gdbarch_num_regs (gdbarch, num_regs);
3306
3307 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3308 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3309 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3310 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3311 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3312 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3313 aarch64_pseudo_register_reggroup_p);
76bed0fd 3314 set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register);
07b287a0
MS		 3315
3316 /* ABI */
3317 set_gdbarch_short_bit (gdbarch, 16);
3318 set_gdbarch_int_bit (gdbarch, 32);
3319 set_gdbarch_float_bit (gdbarch, 32);
3320 set_gdbarch_double_bit (gdbarch, 64);
3321 set_gdbarch_long_double_bit (gdbarch, 128);
3322 set_gdbarch_long_bit (gdbarch, 64);
3323 set_gdbarch_long_long_bit (gdbarch, 64);
3324 set_gdbarch_ptr_bit (gdbarch, 64);
3325 set_gdbarch_char_signed (gdbarch, 0);
53375380 3326 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3327 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3328 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3329 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
b907456c 3330 set_gdbarch_type_align (gdbarch, aarch64_type_align);
07b287a0
MS		 3331
3332 /* Internal <-> external register number maps. */
3333 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3334
3335 /* Returning results. */
3336 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3337
3338 /* Disassembly. */
3339 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3340
3341 /* Virtual tables. */
3342 set_gdbarch_vbit_in_delta (gdbarch, 1);
3343
0ef8a082
AH		 3344 /* Register architecture. */
3345 aarch64_add_reggroups (gdbarch);
3346
07b287a0
MS		 3347 /* Hook in the ABI-specific overrides, if they have been registered. */
3348 info.target_desc = tdesc;
0dba2a6c 3349 info.tdesc_data = tdesc_data;
07b287a0
MS		 3350 gdbarch_init_osabi (info, gdbarch);
3351
3352 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
11e1b75f
AH		 3353 /* Register DWARF CFA vendor handler. */
3354 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
3355 aarch64_execute_dwarf_cfa_vendor_op);
07b287a0
MS		 3356
3357 /* Add some default predicates. */
3358 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3359 dwarf2_append_unwinders (gdbarch);
3360 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3361
3362 frame_base_set_default (gdbarch, &aarch64_normal_base);
3363
3364 /* Now we have tuned the configuration, set a few final things,
3365 based on what the OS ABI has told us. */
3366
3367 if (tdep->jb_pc >= 0)
3368 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3369
ea873d8e
PL		 3370 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3371
07b287a0
MS		 3372 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3373
3374 /* Add standard register aliases. */
3375 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3376 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3377 value_of_aarch64_user_reg,
3378 &aarch64_register_aliases[i].regnum);
3379
e8bf1ce4
JB		 3380 register_aarch64_ravenscar_ops (gdbarch);
3381
07b287a0
MS		 3382 return gdbarch;
3383}
3384
3385static void
3386aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3387{
3388 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3389
3390 if (tdep == NULL)
3391 return;
3392
3393 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3394 paddress (gdbarch, tdep->lowest_pc));
3395}
3396
0d4c07af 3397#if GDB_SELF_TEST
1e2b521d
YQ		 3398namespace selftests
3399{
3400static void aarch64_process_record_test (void);
3401}
0d4c07af 3402#endif
1e2b521d 3403
07b287a0
MS		 3404void
3405_initialize_aarch64_tdep (void)
3406{
3407 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3408 aarch64_dump_tdep);
3409
07b287a0
MS		 3410 /* Debug this file's internals. */
3411 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3412Set AArch64 debugging."), _("\
3413Show AArch64 debugging."), _("\
3414When on, AArch64 specific debugging is enabled."),
3415 NULL,
3416 show_aarch64_debug,
3417 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3418
3419#if GDB_SELF_TEST
1526853e
SM		 3420 selftests::register_test ("aarch64-analyze-prologue",
3421 selftests::aarch64_analyze_prologue_test);
3422 selftests::register_test ("aarch64-process-record",
3423 selftests::aarch64_process_record_test);
6654d750 3424 selftests::record_xml_tdesc ("aarch64.xml",
6dc0ebde 3425 aarch64_create_target_description (0, false));
4d9a9006 3426#endif
07b287a0 3427}
99afc88b
OJ		 3428
3429/* AArch64 process record-replay related structures, defines etc. */
3430
99afc88b
OJ		 3431#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3432 do \
3433 { \
3434 unsigned int reg_len = LENGTH; \
3435 if (reg_len) \
3436 { \
3437 REGS = XNEWVEC (uint32_t, reg_len); \
3438 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3439 } \
3440 } \
3441 while (0)
3442
3443#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3444 do \
3445 { \
3446 unsigned int mem_len = LENGTH; \
3447 if (mem_len) \
3448 { \
3449 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3450 memcpy(&MEMS->len, &RECORD_BUF[0], \
3451 sizeof(struct aarch64_mem_r) * LENGTH); \
3452 } \
3453 } \
3454 while (0)
3455
3456/* AArch64 record/replay structures and enumerations. */
3457
3458struct aarch64_mem_r
3459{
3460 uint64_t len; /* Record length. */
3461 uint64_t addr; /* Memory address. */
3462};
3463
3464enum aarch64_record_result
3465{
3466 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3467 AARCH64_RECORD_UNSUPPORTED,
3468 AARCH64_RECORD_UNKNOWN
3469};
3470
3471typedef struct insn_decode_record_t
3472{
3473 struct gdbarch *gdbarch;
3474 struct regcache *regcache;
3475 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3476 uint32_t aarch64_insn; /* Insn to be recorded. */
3477 uint32_t mem_rec_count; /* Count of memory records. */
3478 uint32_t reg_rec_count; /* Count of register records. */
3479 uint32_t *aarch64_regs; /* Registers to be recorded. */
3480 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3481} insn_decode_record;
3482
3483/* Record handler for data processing - register instructions. */
3484
3485static unsigned int
3486aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3487{
3488 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3489 uint32_t record_buf[4];
3490
3491 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3492 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3493 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3494
3495 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3496 {
3497 uint8_t setflags;
3498
3499 /* Logical (shifted register). */
3500 if (insn_bits24_27 == 0x0a)
3501 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3502 /* Add/subtract. */
3503 else if (insn_bits24_27 == 0x0b)
3504 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3505 else
3506 return AARCH64_RECORD_UNKNOWN;
3507
3508 record_buf[0] = reg_rd;
3509 aarch64_insn_r->reg_rec_count = 1;
3510 if (setflags)
3511 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3512 }
3513 else
3514 {
3515 if (insn_bits24_27 == 0x0b)
3516 {
3517 /* Data-processing (3 source). */
3518 record_buf[0] = reg_rd;
3519 aarch64_insn_r->reg_rec_count = 1;
3520 }
3521 else if (insn_bits24_27 == 0x0a)
3522 {
3523 if (insn_bits21_23 == 0x00)
3524 {
3525 /* Add/subtract (with carry). */
3526 record_buf[0] = reg_rd;
3527 aarch64_insn_r->reg_rec_count = 1;
3528 if (bit (aarch64_insn_r->aarch64_insn, 29))
3529 {
3530 record_buf[1] = AARCH64_CPSR_REGNUM;
3531 aarch64_insn_r->reg_rec_count = 2;
3532 }
3533 }
3534 else if (insn_bits21_23 == 0x02)
3535 {
3536 /* Conditional compare (register) and conditional compare
3537 (immediate) instructions. */
3538 record_buf[0] = AARCH64_CPSR_REGNUM;
3539 aarch64_insn_r->reg_rec_count = 1;
3540 }
3541 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3542 {
3543 /* CConditional select. */
3544 /* Data-processing (2 source). */
3545 /* Data-processing (1 source). */
3546 record_buf[0] = reg_rd;
3547 aarch64_insn_r->reg_rec_count = 1;
3548 }
3549 else
3550 return AARCH64_RECORD_UNKNOWN;
3551 }
3552 }
3553
3554 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3555 record_buf);
3556 return AARCH64_RECORD_SUCCESS;
3557}
3558
3559/* Record handler for data processing - immediate instructions. */
3560
3561static unsigned int
3562aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3563{
78cc6c2d 3564 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3565 uint32_t record_buf[4];
3566
3567 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3568 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3569 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3570
3571 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3572 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3573 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3574 {
3575 record_buf[0] = reg_rd;
3576 aarch64_insn_r->reg_rec_count = 1;
3577 }
3578 else if (insn_bits24_27 == 0x01)
3579 {
3580 /* Add/Subtract (immediate). */
3581 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3582 record_buf[0] = reg_rd;
3583 aarch64_insn_r->reg_rec_count = 1;
3584 if (setflags)
3585 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3586 }
3587 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3588 {
3589 /* Logical (immediate). */
3590 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3591 record_buf[0] = reg_rd;
3592 aarch64_insn_r->reg_rec_count = 1;
3593 if (setflags)
3594 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3595 }
3596 else
3597 return AARCH64_RECORD_UNKNOWN;
3598
3599 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3600 record_buf);
3601 return AARCH64_RECORD_SUCCESS;
3602}
3603
3604/* Record handler for branch, exception generation and system instructions. */
3605
3606static unsigned int
3607aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3608{
3609 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3610 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3611 uint32_t record_buf[4];
3612
3613 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3614 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3615 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3616
3617 if (insn_bits28_31 == 0x0d)
3618 {
3619 /* Exception generation instructions. */
3620 if (insn_bits24_27 == 0x04)
3621 {
5d98d3cd
YQ		 3622 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3623 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3624 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3625 {
3626 ULONGEST svc_number;
3627
3628 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3629 &svc_number);
3630 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3631 svc_number);
3632 }
3633 else
3634 return AARCH64_RECORD_UNSUPPORTED;
3635 }
3636 /* System instructions. */
3637 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3638 {
3639 uint32_t reg_rt, reg_crn;
3640
3641 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3642 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3643
3644 /* Record rt in case of sysl and mrs instructions. */
3645 if (bit (aarch64_insn_r->aarch64_insn, 21))
3646 {
3647 record_buf[0] = reg_rt;
3648 aarch64_insn_r->reg_rec_count = 1;
3649 }
3650 /* Record cpsr for hint and msr(immediate) instructions. */
3651 else if (reg_crn == 0x02 || reg_crn == 0x04)
3652 {
3653 record_buf[0] = AARCH64_CPSR_REGNUM;
3654 aarch64_insn_r->reg_rec_count = 1;
3655 }
3656 }
3657 /* Unconditional branch (register). */
3658 else if((insn_bits24_27 & 0x0e) == 0x06)
3659 {
3660 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3661 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3662 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3663 }
3664 else
3665 return AARCH64_RECORD_UNKNOWN;
3666 }
3667 /* Unconditional branch (immediate). */
3668 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3669 {
3670 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3671 if (bit (aarch64_insn_r->aarch64_insn, 31))
3672 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3673 }
3674 else
3675 /* Compare & branch (immediate), Test & branch (immediate) and
3676 Conditional branch (immediate). */
3677 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3678
3679 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3680 record_buf);
3681 return AARCH64_RECORD_SUCCESS;
3682}
3683
3684/* Record handler for advanced SIMD load and store instructions. */
3685
3686static unsigned int
3687aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3688{
3689 CORE_ADDR address;
3690 uint64_t addr_offset = 0;
3691 uint32_t record_buf[24];
3692 uint64_t record_buf_mem[24];
3693 uint32_t reg_rn, reg_rt;
3694 uint32_t reg_index = 0, mem_index = 0;
3695 uint8_t opcode_bits, size_bits;
3696
3697 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3698 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3699 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3700 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3701 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3702
3703 if (record_debug)
b277c936 3704 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3705
3706 /* Load/store single structure. */
3707 if (bit (aarch64_insn_r->aarch64_insn, 24))
3708 {
3709 uint8_t sindex, scale, selem, esize, replicate = 0;
3710 scale = opcode_bits >> 2;
3711 selem = ((opcode_bits & 0x02) |
3712 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3713 switch (scale)
3714 {
3715 case 1:
3716 if (size_bits & 0x01)
3717 return AARCH64_RECORD_UNKNOWN;
3718 break;
3719 case 2:
3720 if ((size_bits >> 1) & 0x01)
3721 return AARCH64_RECORD_UNKNOWN;
3722 if (size_bits & 0x01)
3723 {
3724 if (!((opcode_bits >> 1) & 0x01))
3725 scale = 3;
3726 else
3727 return AARCH64_RECORD_UNKNOWN;
3728 }
3729 break;
3730 case 3:
3731 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3732 {
3733 scale = size_bits;
3734 replicate = 1;
3735 break;
3736 }
3737 else
3738 return AARCH64_RECORD_UNKNOWN;
3739 default:
3740 break;
3741 }
3742 esize = 8 << scale;
3743 if (replicate)
3744 for (sindex = 0; sindex < selem; sindex++)
3745 {
3746 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3747 reg_rt = (reg_rt + 1) % 32;
3748 }
3749 else
3750 {
3751 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3752 {
3753 if (bit (aarch64_insn_r->aarch64_insn, 22))
3754 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3755 else
3756 {
3757 record_buf_mem[mem_index++] = esize / 8;
3758 record_buf_mem[mem_index++] = address + addr_offset;
3759 }
3760 addr_offset = addr_offset + (esize / 8);
3761 reg_rt = (reg_rt + 1) % 32;
3762 }
99afc88b
OJ		 3763 }
3764 }
3765 /* Load/store multiple structure. */
3766 else
3767 {
3768 uint8_t selem, esize, rpt, elements;
3769 uint8_t eindex, rindex;
3770
3771 esize = 8 << size_bits;
3772 if (bit (aarch64_insn_r->aarch64_insn, 30))
3773 elements = 128 / esize;
3774 else
3775 elements = 64 / esize;
3776
3777 switch (opcode_bits)
3778 {
3779 /*LD/ST4 (4 Registers). */
3780 case 0:
3781 rpt = 1;
3782 selem = 4;
3783 break;
3784 /*LD/ST1 (4 Registers). */
3785 case 2:
3786 rpt = 4;
3787 selem = 1;
3788 break;
3789 /*LD/ST3 (3 Registers). */
3790 case 4:
3791 rpt = 1;
3792 selem = 3;
3793 break;
3794 /*LD/ST1 (3 Registers). */
3795 case 6:
3796 rpt = 3;
3797 selem = 1;
3798 break;
3799 /*LD/ST1 (1 Register). */
3800 case 7:
3801 rpt = 1;
3802 selem = 1;
3803 break;
3804 /*LD/ST2 (2 Registers). */
3805 case 8:
3806 rpt = 1;
3807 selem = 2;
3808 break;
3809 /*LD/ST1 (2 Registers). */
3810 case 10:
3811 rpt = 2;
3812 selem = 1;
3813 break;
3814 default:
3815 return AARCH64_RECORD_UNSUPPORTED;
3816 break;
3817 }
3818 for (rindex = 0; rindex < rpt; rindex++)
3819 for (eindex = 0; eindex < elements; eindex++)
3820 {
3821 uint8_t reg_tt, sindex;
3822 reg_tt = (reg_rt + rindex) % 32;
3823 for (sindex = 0; sindex < selem; sindex++)
3824 {
3825 if (bit (aarch64_insn_r->aarch64_insn, 22))
3826 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3827 else
3828 {
3829 record_buf_mem[mem_index++] = esize / 8;
3830 record_buf_mem[mem_index++] = address + addr_offset;
3831 }
3832 addr_offset = addr_offset + (esize / 8);
3833 reg_tt = (reg_tt + 1) % 32;
3834 }
3835 }
3836 }
3837
3838 if (bit (aarch64_insn_r->aarch64_insn, 23))
3839 record_buf[reg_index++] = reg_rn;
3840
3841 aarch64_insn_r->reg_rec_count = reg_index;
3842 aarch64_insn_r->mem_rec_count = mem_index / 2;
3843 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3844 record_buf_mem);
3845 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3846 record_buf);
3847 return AARCH64_RECORD_SUCCESS;
3848}
3849
3850/* Record handler for load and store instructions. */
3851
3852static unsigned int
3853aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3854{
3855 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3856 uint8_t insn_bit23, insn_bit21;
3857 uint8_t opc, size_bits, ld_flag, vector_flag;
3858 uint32_t reg_rn, reg_rt, reg_rt2;
3859 uint64_t datasize, offset;
3860 uint32_t record_buf[8];
3861 uint64_t record_buf_mem[8];
3862 CORE_ADDR address;
3863
3864 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3865 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3866 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3867 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3868 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3869 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3870 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3871 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3872 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3873 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3874 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3875
3876 /* Load/store exclusive. */
3877 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3878 {
3879 if (record_debug)
b277c936 3880 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3881
3882 if (ld_flag)
3883 {
3884 record_buf[0] = reg_rt;
3885 aarch64_insn_r->reg_rec_count = 1;
3886 if (insn_bit21)
3887 {
3888 record_buf[1] = reg_rt2;
3889 aarch64_insn_r->reg_rec_count = 2;
3890 }
3891 }
3892 else
3893 {
3894 if (insn_bit21)
3895 datasize = (8 << size_bits) * 2;
3896 else
3897 datasize = (8 << size_bits);
3898 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3899 &address);
3900 record_buf_mem[0] = datasize / 8;
3901 record_buf_mem[1] = address;
3902 aarch64_insn_r->mem_rec_count = 1;
3903 if (!insn_bit23)
3904 {
3905 /* Save register rs. */
3906 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3907 aarch64_insn_r->reg_rec_count = 1;
3908 }
3909 }
3910 }
3911 /* Load register (literal) instructions decoding. */
3912 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3913 {
3914 if (record_debug)
b277c936 3915 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3916 if (vector_flag)
3917 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3918 else
3919 record_buf[0] = reg_rt;
3920 aarch64_insn_r->reg_rec_count = 1;
3921 }
3922 /* All types of load/store pair instructions decoding. */
3923 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3924 {
3925 if (record_debug)
b277c936 3926 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 3927
3928 if (ld_flag)
3929 {
3930 if (vector_flag)
3931 {
3932 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3933 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3934 }
3935 else
3936 {
3937 record_buf[0] = reg_rt;
3938 record_buf[1] = reg_rt2;
3939 }
3940 aarch64_insn_r->reg_rec_count = 2;
3941 }
3942 else
3943 {
3944 uint16_t imm7_off;
3945 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3946 if (!vector_flag)
3947 size_bits = size_bits >> 1;
3948 datasize = 8 << (2 + size_bits);
3949 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3950 offset = offset << (2 + size_bits);
3951 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3952 &address);
3953 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3954 {
3955 if (imm7_off & 0x40)
3956 address = address - offset;
3957 else
3958 address = address + offset;
3959 }
3960
3961 record_buf_mem[0] = datasize / 8;
3962 record_buf_mem[1] = address;
3963 record_buf_mem[2] = datasize / 8;
3964 record_buf_mem[3] = address + (datasize / 8);
3965 aarch64_insn_r->mem_rec_count = 2;
3966 }
3967 if (bit (aarch64_insn_r->aarch64_insn, 23))
3968 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3969 }
3970 /* Load/store register (unsigned immediate) instructions. */
3971 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3972 {
3973 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3974 if (!(opc >> 1))
33877125
YQ		 3975 {
3976 if (opc & 0x01)
3977 ld_flag = 0x01;
3978 else
3979 ld_flag = 0x0;
3980 }
99afc88b 3981 else
33877125 3982 {
1e2b521d
YQ		 3983 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3984 {
3985 /* PRFM (immediate) */
3986 return AARCH64_RECORD_SUCCESS;
3987 }
3988 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3989 {
3990 /* LDRSW (immediate) */
3991 ld_flag = 0x1;
3992 }
33877125 3993 else
1e2b521d
YQ		 3994 {
3995 if (opc & 0x01)
3996 ld_flag = 0x01;
3997 else
3998 ld_flag = 0x0;
3999 }
33877125 4000 }
99afc88b
OJ		 4001
4002 if (record_debug)
4003 {
b277c936
PL		 4004 debug_printf ("Process record: load/store (unsigned immediate):"
4005 " size %x V %d opc %x\n", size_bits, vector_flag,
4006 opc);
99afc88b
OJ		 4007 }
4008
4009 if (!ld_flag)
4010 {
4011 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
4012 datasize = 8 << size_bits;
4013 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4014 &address);
4015 offset = offset << size_bits;
4016 address = address + offset;
4017
4018 record_buf_mem[0] = datasize >> 3;
4019 record_buf_mem[1] = address;
4020 aarch64_insn_r->mem_rec_count = 1;
4021 }
4022 else
4023 {
4024 if (vector_flag)
4025 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4026 else
4027 record_buf[0] = reg_rt;
4028 aarch64_insn_r->reg_rec_count = 1;
4029 }
4030 }
4031 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 4032 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4033 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 4034 {
4035 if (record_debug)
b277c936 4036 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 4037 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4038 if (!(opc >> 1))
4039 if (opc & 0x01)
4040 ld_flag = 0x01;
4041 else
4042 ld_flag = 0x0;
4043 else
4044 if (size_bits != 0x03)
4045 ld_flag = 0x01;
4046 else
4047 return AARCH64_RECORD_UNKNOWN;
4048
4049 if (!ld_flag)
4050 {
d9436c7c
PA		 4051 ULONGEST reg_rm_val;
4052
99afc88b
OJ		 4053 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
4054 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
4055 if (bit (aarch64_insn_r->aarch64_insn, 12))
4056 offset = reg_rm_val << size_bits;
4057 else
4058 offset = reg_rm_val;
4059 datasize = 8 << size_bits;
4060 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4061 &address);
4062 address = address + offset;
4063 record_buf_mem[0] = datasize >> 3;
4064 record_buf_mem[1] = address;
4065 aarch64_insn_r->mem_rec_count = 1;
4066 }
4067 else
4068 {
4069 if (vector_flag)
4070 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4071 else
4072 record_buf[0] = reg_rt;
4073 aarch64_insn_r->reg_rec_count = 1;
4074 }
4075 }
4076 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 4077 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4078 && !insn_bit21)
99afc88b
OJ		 4079 {
4080 if (record_debug)
4081 {
b277c936
PL		 4082 debug_printf ("Process record: load/store "
4083 "(immediate and unprivileged)\n");
99afc88b
OJ		 4084 }
4085 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4086 if (!(opc >> 1))
4087 if (opc & 0x01)
4088 ld_flag = 0x01;
4089 else
4090 ld_flag = 0x0;
4091 else
4092 if (size_bits != 0x03)
4093 ld_flag = 0x01;
4094 else
4095 return AARCH64_RECORD_UNKNOWN;
4096
4097 if (!ld_flag)
4098 {
4099 uint16_t imm9_off;
4100 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
4101 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
4102 datasize = 8 << size_bits;
4103 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4104 &address);
4105 if (insn_bits10_11 != 0x01)
4106 {
4107 if (imm9_off & 0x0100)
4108 address = address - offset;
4109 else
4110 address = address + offset;
4111 }
4112 record_buf_mem[0] = datasize >> 3;
4113 record_buf_mem[1] = address;
4114 aarch64_insn_r->mem_rec_count = 1;
4115 }
4116 else
4117 {
4118 if (vector_flag)
4119 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4120 else
4121 record_buf[0] = reg_rt;
4122 aarch64_insn_r->reg_rec_count = 1;
4123 }
4124 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
4125 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4126 }
4127 /* Advanced SIMD load/store instructions. */
4128 else
4129 return aarch64_record_asimd_load_store (aarch64_insn_r);
4130
4131 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
4132 record_buf_mem);
4133 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4134 record_buf);
4135 return AARCH64_RECORD_SUCCESS;
4136}
4137
4138/* Record handler for data processing SIMD and floating point instructions. */
4139
4140static unsigned int
4141aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
4142{
4143 uint8_t insn_bit21, opcode, rmode, reg_rd;
4144 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
4145 uint8_t insn_bits11_14;
4146 uint32_t record_buf[2];
4147
4148 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4149 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
4150 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4151 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
4152 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
4153 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
4154 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
4155 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4156 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4157
4158 if (record_debug)
b277c936 4159 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 4160
4161 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
4162 {
4163 /* Floating point - fixed point conversion instructions. */
4164 if (!insn_bit21)
4165 {
4166 if (record_debug)
b277c936 4167 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 4168
4169 if ((opcode >> 1) == 0x0 && rmode == 0x03)
4170 record_buf[0] = reg_rd;
4171 else
4172 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4173 }
4174 /* Floating point - conditional compare instructions. */
4175 else if (insn_bits10_11 == 0x01)
4176 {
4177 if (record_debug)
b277c936 4178 debug_printf ("FP - conditional compare");
99afc88b
OJ		 4179
4180 record_buf[0] = AARCH64_CPSR_REGNUM;
4181 }
4182 /* Floating point - data processing (2-source) and
4183 conditional select instructions. */
4184 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
4185 {
4186 if (record_debug)
b277c936 4187 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 4188
4189 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4190 }
4191 else if (insn_bits10_11 == 0x00)
4192 {
4193 /* Floating point - immediate instructions. */
4194 if ((insn_bits12_15 & 0x01) == 0x01
4195 || (insn_bits12_15 & 0x07) == 0x04)
4196 {
4197 if (record_debug)
b277c936 4198 debug_printf ("FP - immediate");
99afc88b
OJ		 4199 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4200 }
4201 /* Floating point - compare instructions. */
4202 else if ((insn_bits12_15 & 0x03) == 0x02)
4203 {
4204 if (record_debug)
b277c936 4205 debug_printf ("FP - immediate");
99afc88b
OJ		 4206 record_buf[0] = AARCH64_CPSR_REGNUM;
4207 }
4208 /* Floating point - integer conversions instructions. */
f62fce35 4209 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 4210 {
4211 /* Convert float to integer instruction. */
4212 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4213 {
4214 if (record_debug)
b277c936 4215 debug_printf ("float to int conversion");
99afc88b
OJ		 4216
4217 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4218 }
4219 /* Convert integer to float instruction. */
4220 else if ((opcode >> 1) == 0x01 && !rmode)
4221 {
4222 if (record_debug)
b277c936 4223 debug_printf ("int to float conversion");
99afc88b
OJ		 4224
4225 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4226 }
4227 /* Move float to integer instruction. */
4228 else if ((opcode >> 1) == 0x03)
4229 {
4230 if (record_debug)
b277c936 4231 debug_printf ("move float to int");
99afc88b
OJ		 4232
4233 if (!(opcode & 0x01))
4234 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4235 else
4236 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4237 }
f62fce35
YQ		 4238 else
4239 return AARCH64_RECORD_UNKNOWN;
99afc88b 4240 }
f62fce35
YQ		 4241 else
4242 return AARCH64_RECORD_UNKNOWN;
99afc88b 4243 }
f62fce35
YQ		 4244 else
4245 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4246 }
4247 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4248 {
4249 if (record_debug)
b277c936 4250 debug_printf ("SIMD copy");
99afc88b
OJ		 4251
4252 /* Advanced SIMD copy instructions. */
4253 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4254 && !bit (aarch64_insn_r->aarch64_insn, 15)
4255 && bit (aarch64_insn_r->aarch64_insn, 10))
4256 {
4257 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4258 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4259 else
4260 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4261 }
4262 else
4263 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4264 }
4265 /* All remaining floating point or advanced SIMD instructions. */
4266 else
4267 {
4268 if (record_debug)
b277c936 4269 debug_printf ("all remain");
99afc88b
OJ		 4270
4271 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4272 }
4273
4274 if (record_debug)
b277c936 4275 debug_printf ("\n");
99afc88b
OJ		 4276
4277 aarch64_insn_r->reg_rec_count++;
4278 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4279 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4280 record_buf);
4281 return AARCH64_RECORD_SUCCESS;
4282}
4283
4284/* Decodes insns type and invokes its record handler. */
4285
4286static unsigned int
4287aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4288{
4289 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4290
4291 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4292 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4293 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4294 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4295
4296 /* Data processing - immediate instructions. */
4297 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4298 return aarch64_record_data_proc_imm (aarch64_insn_r);
4299
4300 /* Branch, exception generation and system instructions. */
4301 if (ins_bit26 && !ins_bit27 && ins_bit28)
4302 return aarch64_record_branch_except_sys (aarch64_insn_r);
4303
4304 /* Load and store instructions. */
4305 if (!ins_bit25 && ins_bit27)
4306 return aarch64_record_load_store (aarch64_insn_r);
4307
4308 /* Data processing - register instructions. */
4309 if (ins_bit25 && !ins_bit26 && ins_bit27)
4310 return aarch64_record_data_proc_reg (aarch64_insn_r);
4311
4312 /* Data processing - SIMD and floating point instructions. */
4313 if (ins_bit25 && ins_bit26 && ins_bit27)
4314 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4315
4316 return AARCH64_RECORD_UNSUPPORTED;
4317}
4318
4319/* Cleans up local record registers and memory allocations. */
4320
4321static void
4322deallocate_reg_mem (insn_decode_record *record)
4323{
4324 xfree (record->aarch64_regs);
4325 xfree (record->aarch64_mems);
4326}
4327
1e2b521d
YQ		 4328#if GDB_SELF_TEST
4329namespace selftests {
4330
4331static void
4332aarch64_process_record_test (void)
4333{
4334 struct gdbarch_info info;
4335 uint32_t ret;
4336
4337 gdbarch_info_init (&info);
4338 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4339
4340 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4341 SELF_CHECK (gdbarch != NULL);
4342
4343 insn_decode_record aarch64_record;
4344
4345 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4346 aarch64_record.regcache = NULL;
4347 aarch64_record.this_addr = 0;
4348 aarch64_record.gdbarch = gdbarch;
4349
4350 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4351 aarch64_record.aarch64_insn = 0xf9800020;
4352 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4353 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4354 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4355 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4356
4357 deallocate_reg_mem (&aarch64_record);
4358}
4359
4360} // namespace selftests
4361#endif /* GDB_SELF_TEST */
4362
99afc88b
OJ		 4363/* Parse the current instruction and record the values of the registers and
4364 memory that will be changed in current instruction to record_arch_list
4365 return -1 if something is wrong. */
4366
4367int
4368aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4369 CORE_ADDR insn_addr)
4370{
4371 uint32_t rec_no = 0;
4372 uint8_t insn_size = 4;
4373 uint32_t ret = 0;
99afc88b
OJ		 4374 gdb_byte buf[insn_size];
4375 insn_decode_record aarch64_record;
4376
4377 memset (&buf[0], 0, insn_size);
4378 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4379 target_read_memory (insn_addr, &buf[0], insn_size);
4380 aarch64_record.aarch64_insn
4381 = (uint32_t) extract_unsigned_integer (&buf[0],
4382 insn_size,
4383 gdbarch_byte_order (gdbarch));
4384 aarch64_record.regcache = regcache;
4385 aarch64_record.this_addr = insn_addr;
4386 aarch64_record.gdbarch = gdbarch;
4387
4388 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4389 if (ret == AARCH64_RECORD_UNSUPPORTED)
4390 {
4391 printf_unfiltered (_("Process record does not support instruction "
4392 "0x%0x at address %s.\n"),
4393 aarch64_record.aarch64_insn,
4394 paddress (gdbarch, insn_addr));
4395 ret = -1;
4396 }
4397
4398 if (0 == ret)
4399 {
4400 /* Record registers. */
4401 record_full_arch_list_add_reg (aarch64_record.regcache,
4402 AARCH64_PC_REGNUM);
4403 /* Always record register CPSR. */
4404 record_full_arch_list_add_reg (aarch64_record.regcache,
4405 AARCH64_CPSR_REGNUM);
4406 if (aarch64_record.aarch64_regs)
4407 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4408 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4409 aarch64_record.aarch64_regs[rec_no]))
4410 ret = -1;
4411
4412 /* Record memories. */
4413 if (aarch64_record.aarch64_mems)
4414 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4415 if (record_full_arch_list_add_mem
4416 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4417 aarch64_record.aarch64_mems[rec_no].len))
4418 ret = -1;
4419
4420 if (record_full_arch_list_add_end ())
4421 ret = -1;
4422 }
4423
4424 deallocate_reg_mem (&aarch64_record);
4425 return ret;
4426}
GDB Binutils - Deliverables
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