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gdb: add type::is_unsigned / type::set_is_unsigned
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
b811d2c2 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
07b287a0
MS		 24#include "gdbcmd.h"
25#include "gdbcore.h"
4de283e4 26#include "dis-asm.h"
d55e5aa6
TT		 27#include "regcache.h"
28#include "reggroups.h"
4de283e4
TT		 29#include "value.h"
30#include "arch-utils.h"
31#include "osabi.h"
32#include "frame-unwind.h"
33#include "frame-base.h"
d55e5aa6 34#include "trad-frame.h"
4de283e4
TT		 35#include "objfiles.h"
36#include "dwarf2.h"
82ca8957 37#include "dwarf2/frame.h"
4de283e4
TT		 38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
07b287a0 41#include "user-regs.h"
4de283e4 42#include "ax-gdb.h"
268a13a5 43#include "gdbsupport/selftest.h"
4de283e4
TT		 44
45#include "aarch64-tdep.h"
46#include "aarch64-ravenscar-thread.h"
47
4de283e4
TT		 48#include "record.h"
49#include "record-full.h"
50#include "arch/aarch64-insn.h"
0d12e84c 51#include "gdbarch.h"
4de283e4
TT		 52
53#include "opcode/aarch64.h"
54#include <algorithm>
f77ee802
YQ		 55
56#define submask(x) ((1L << ((x) + 1)) - 1)
57#define bit(obj,st) (((obj) >> (st)) & 1)
58#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
59
ea92689a
AH		 60/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
61 four members. */
62#define HA_MAX_NUM_FLDS 4
63
95228a0d 64/* All possible aarch64 target descriptors. */
6dc0ebde 65struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/];
95228a0d 66
07b287a0
MS		 67/* The standard register names, and all the valid aliases for them. */
68static const struct
69{
70 const char *const name;
71 int regnum;
72} aarch64_register_aliases[] =
73{
74 /* 64-bit register names. */
75 {"fp", AARCH64_FP_REGNUM},
76 {"lr", AARCH64_LR_REGNUM},
77 {"sp", AARCH64_SP_REGNUM},
78
79 /* 32-bit register names. */
80 {"w0", AARCH64_X0_REGNUM + 0},
81 {"w1", AARCH64_X0_REGNUM + 1},
82 {"w2", AARCH64_X0_REGNUM + 2},
83 {"w3", AARCH64_X0_REGNUM + 3},
84 {"w4", AARCH64_X0_REGNUM + 4},
85 {"w5", AARCH64_X0_REGNUM + 5},
86 {"w6", AARCH64_X0_REGNUM + 6},
87 {"w7", AARCH64_X0_REGNUM + 7},
88 {"w8", AARCH64_X0_REGNUM + 8},
89 {"w9", AARCH64_X0_REGNUM + 9},
90 {"w10", AARCH64_X0_REGNUM + 10},
91 {"w11", AARCH64_X0_REGNUM + 11},
92 {"w12", AARCH64_X0_REGNUM + 12},
93 {"w13", AARCH64_X0_REGNUM + 13},
94 {"w14", AARCH64_X0_REGNUM + 14},
95 {"w15", AARCH64_X0_REGNUM + 15},
96 {"w16", AARCH64_X0_REGNUM + 16},
97 {"w17", AARCH64_X0_REGNUM + 17},
98 {"w18", AARCH64_X0_REGNUM + 18},
99 {"w19", AARCH64_X0_REGNUM + 19},
100 {"w20", AARCH64_X0_REGNUM + 20},
101 {"w21", AARCH64_X0_REGNUM + 21},
102 {"w22", AARCH64_X0_REGNUM + 22},
103 {"w23", AARCH64_X0_REGNUM + 23},
104 {"w24", AARCH64_X0_REGNUM + 24},
105 {"w25", AARCH64_X0_REGNUM + 25},
106 {"w26", AARCH64_X0_REGNUM + 26},
107 {"w27", AARCH64_X0_REGNUM + 27},
108 {"w28", AARCH64_X0_REGNUM + 28},
109 {"w29", AARCH64_X0_REGNUM + 29},
110 {"w30", AARCH64_X0_REGNUM + 30},
111
112 /* specials */
113 {"ip0", AARCH64_X0_REGNUM + 16},
114 {"ip1", AARCH64_X0_REGNUM + 17}
115};
116
117/* The required core 'R' registers. */
118static const char *const aarch64_r_register_names[] =
119{
120 /* These registers must appear in consecutive RAW register number
121 order and they must begin with AARCH64_X0_REGNUM! */
122 "x0", "x1", "x2", "x3",
123 "x4", "x5", "x6", "x7",
124 "x8", "x9", "x10", "x11",
125 "x12", "x13", "x14", "x15",
126 "x16", "x17", "x18", "x19",
127 "x20", "x21", "x22", "x23",
128 "x24", "x25", "x26", "x27",
129 "x28", "x29", "x30", "sp",
130 "pc", "cpsr"
131};
132
133/* The FP/SIMD 'V' registers. */
134static const char *const aarch64_v_register_names[] =
135{
136 /* These registers must appear in consecutive RAW register number
137 order and they must begin with AARCH64_V0_REGNUM! */
138 "v0", "v1", "v2", "v3",
139 "v4", "v5", "v6", "v7",
140 "v8", "v9", "v10", "v11",
141 "v12", "v13", "v14", "v15",
142 "v16", "v17", "v18", "v19",
143 "v20", "v21", "v22", "v23",
144 "v24", "v25", "v26", "v27",
145 "v28", "v29", "v30", "v31",
146 "fpsr",
147 "fpcr"
148};
149
739e8682
AH		 150/* The SVE 'Z' and 'P' registers. */
151static const char *const aarch64_sve_register_names[] =
152{
153 /* These registers must appear in consecutive RAW register number
154 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
155 "z0", "z1", "z2", "z3",
156 "z4", "z5", "z6", "z7",
157 "z8", "z9", "z10", "z11",
158 "z12", "z13", "z14", "z15",
159 "z16", "z17", "z18", "z19",
160 "z20", "z21", "z22", "z23",
161 "z24", "z25", "z26", "z27",
162 "z28", "z29", "z30", "z31",
163 "fpsr", "fpcr",
164 "p0", "p1", "p2", "p3",
165 "p4", "p5", "p6", "p7",
166 "p8", "p9", "p10", "p11",
167 "p12", "p13", "p14", "p15",
168 "ffr", "vg"
169};
170
76bed0fd
AH		 171static const char *const aarch64_pauth_register_names[] =
172{
173 /* Authentication mask for data pointer. */
174 "pauth_dmask",
175 /* Authentication mask for code pointer. */
176 "pauth_cmask"
177};
178
07b287a0
MS		 179/* AArch64 prologue cache structure. */
180struct aarch64_prologue_cache
181{
db634143
PL		 182 /* The program counter at the start of the function. It is used to
183 identify this frame as a prologue frame. */
184 CORE_ADDR func;
185
186 /* The program counter at the time this frame was created; i.e. where
187 this function was called from. It is used to identify this frame as a
188 stub frame. */
189 CORE_ADDR prev_pc;
190
07b287a0
MS		 191 /* The stack pointer at the time this frame was created; i.e. the
192 caller's stack pointer when this function was called. It is used
193 to identify this frame. */
194 CORE_ADDR prev_sp;
195
7dfa3edc
PL		 196 /* Is the target available to read from? */
197 int available_p;
198
07b287a0
MS		 199 /* The frame base for this frame is just prev_sp - frame size.
200 FRAMESIZE is the distance from the frame pointer to the
201 initial stack pointer. */
202 int framesize;
203
204 /* The register used to hold the frame pointer for this frame. */
205 int framereg;
206
207 /* Saved register offsets. */
208 struct trad_frame_saved_reg *saved_regs;
209};
210
07b287a0
MS		 211static void
212show_aarch64_debug (struct ui_file *file, int from_tty,
213 struct cmd_list_element *c, const char *value)
214{
215 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
216}
217
ffdbe864
YQ		 218namespace {
219
4d9a9006
YQ		 220/* Abstract instruction reader. */
221
222class abstract_instruction_reader
223{
224public:
225 /* Read in one instruction. */
226 virtual ULONGEST read (CORE_ADDR memaddr, int len,
227 enum bfd_endian byte_order) = 0;
228};
229
230/* Instruction reader from real target. */
231
232class instruction_reader : public abstract_instruction_reader
233{
234 public:
235 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 236 override
4d9a9006 237 {
fc2f703e 238 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 239 }
240};
241
ffdbe864
YQ		 242} // namespace
243
3d31bc39
AH		 244/* If address signing is enabled, mask off the signature bits from the link
245 register, which is passed by value in ADDR, using the register values in
246 THIS_FRAME. */
11e1b75f
AH		 247
248static CORE_ADDR
3d31bc39
AH		 249aarch64_frame_unmask_lr (struct gdbarch_tdep *tdep,
250 struct frame_info *this_frame, CORE_ADDR addr)
11e1b75f
AH		 251{
252 if (tdep->has_pauth ()
253 && frame_unwind_register_unsigned (this_frame,
254 tdep->pauth_ra_state_regnum))
255 {
256 int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
257 CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
258 addr = addr & ~cmask;
3d31bc39
AH		 259
260 /* Record in the frame that the link register required unmasking. */
261 set_frame_previous_pc_masked (this_frame);
11e1b75f
AH		 262 }
263
264 return addr;
265}
266
aa7ca1bb
AH		 267/* Implement the "get_pc_address_flags" gdbarch method. */
268
269static std::string
270aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
271{
272 if (pc != 0 && get_frame_pc_masked (frame))
273 return "PAC";
274
275 return "";
276}
277
07b287a0
MS		 278/* Analyze a prologue, looking for a recognizable stack frame
279 and frame pointer. Scan until we encounter a store that could
280 clobber the stack frame unexpectedly, or an unknown instruction. */
281
282static CORE_ADDR
283aarch64_analyze_prologue (struct gdbarch *gdbarch,
284 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 285 struct aarch64_prologue_cache *cache,
286 abstract_instruction_reader& reader)
07b287a0
MS		 287{
288 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
289 int i;
f8e3fe0d
LM		 290
291 /* Whether the stack has been set. This should be true when we notice a SP
292 to FP move or if we are using the SP as the base register for storing
293 data, in case the FP is ommitted. */
294 bool seen_stack_set = false;
295
187f5d00
YQ		 296 /* Track X registers and D registers in prologue. */
297 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 298
187f5d00 299 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 300 regs[i] = pv_register (i, 0);
f7b7ed97 301 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 302
303 for (; start < limit; start += 4)
304 {
305 uint32_t insn;
d9ebcbce 306 aarch64_inst inst;
07b287a0 307
4d9a9006 308 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 309
561a72d4 310 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 311 break;
312
313 if (inst.opcode->iclass == addsub_imm
314 && (inst.opcode->op == OP_ADD
315 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 316 {
d9ebcbce
YQ		 317 unsigned rd = inst.operands[0].reg.regno;
318 unsigned rn = inst.operands[1].reg.regno;
319
320 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
321 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
322 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
323 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
324
325 if (inst.opcode->op == OP_ADD)
326 {
327 regs[rd] = pv_add_constant (regs[rn],
328 inst.operands[2].imm.value);
329 }
330 else
331 {
332 regs[rd] = pv_add_constant (regs[rn],
333 -inst.operands[2].imm.value);
334 }
f8e3fe0d
LM		 335
336 /* Did we move SP to FP? */
337 if (rn == AARCH64_SP_REGNUM && rd == AARCH64_FP_REGNUM)
338 seen_stack_set = true;
d9ebcbce
YQ		 339 }
340 else if (inst.opcode->iclass == pcreladdr
341 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
342 {
343 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
344 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
345
346 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 347 }
d9ebcbce 348 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 349 {
350 /* Stop analysis on branch. */
351 break;
352 }
d9ebcbce 353 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 354 {
355 /* Stop analysis on branch. */
356 break;
357 }
d9ebcbce 358 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 359 {
360 /* Stop analysis on branch. */
361 break;
362 }
d9ebcbce 363 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 364 {
365 /* Stop analysis on branch. */
366 break;
367 }
d9ebcbce
YQ		 368 else if (inst.opcode->op == OP_MOVZ)
369 {
370 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
f8e3fe0d
LM		 371
372 /* If this shows up before we set the stack, keep going. Otherwise
373 stop the analysis. */
374 if (seen_stack_set)
375 break;
376
d9ebcbce
YQ		 377 regs[inst.operands[0].reg.regno] = pv_unknown ();
378 }
379 else if (inst.opcode->iclass == log_shift
380 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 381 {
d9ebcbce
YQ		 382 unsigned rd = inst.operands[0].reg.regno;
383 unsigned rn = inst.operands[1].reg.regno;
384 unsigned rm = inst.operands[2].reg.regno;
385
386 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
387 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
388 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
389
390 if (inst.operands[2].shifter.amount == 0
391 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 392 regs[rd] = regs[rm];
393 else
394 {
395 if (aarch64_debug)
b277c936
PL		 396 {
397 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 398 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 399 core_addr_to_string_nz (start), insn);
400 }
07b287a0
MS		 401 break;
402 }
403 }
d9ebcbce 404 else if (inst.opcode->op == OP_STUR)
07b287a0 405 {
d9ebcbce
YQ		 406 unsigned rt = inst.operands[0].reg.regno;
407 unsigned rn = inst.operands[1].addr.base_regno;
75faf5c4 408 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce
YQ		 409
410 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
411 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
412 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
413 gdb_assert (!inst.operands[1].addr.offset.is_reg);
414
75faf5c4
AH		 415 stack.store
416 (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
417 size, regs[rt]);
f8e3fe0d
LM		 418
419 /* Are we storing with SP as a base? */
420 if (rn == AARCH64_SP_REGNUM)
421 seen_stack_set = true;
07b287a0 422 }
d9ebcbce 423 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 424 || (inst.opcode->iclass == ldstpair_indexed
425 && inst.operands[2].addr.preind))
d9ebcbce 426 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 427 {
03bcd739 428 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 429 unsigned rt1;
430 unsigned rt2;
d9ebcbce
YQ		 431 unsigned rn = inst.operands[2].addr.base_regno;
432 int32_t imm = inst.operands[2].addr.offset.imm;
75faf5c4 433 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce 434
187f5d00
YQ		 435 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
436 || inst.operands[0].type == AARCH64_OPND_Ft);
437 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
438 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 439 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
440 gdb_assert (!inst.operands[2].addr.offset.is_reg);
441
07b287a0
MS		 442 /* If recording this store would invalidate the store area
443 (perhaps because rn is not known) then we should abandon
444 further prologue analysis. */
f7b7ed97 445 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 446 break;
447
f7b7ed97 448 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 449 break;
450
187f5d00
YQ		 451 rt1 = inst.operands[0].reg.regno;
452 rt2 = inst.operands[1].reg.regno;
453 if (inst.operands[0].type == AARCH64_OPND_Ft)
454 {
187f5d00
YQ		 455 rt1 += AARCH64_X_REGISTER_COUNT;
456 rt2 += AARCH64_X_REGISTER_COUNT;
457 }
458
75faf5c4
AH		 459 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
460 stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
14ac654f 461
d9ebcbce 462 if (inst.operands[2].addr.writeback)
93d96012 463 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 464
f8e3fe0d
LM		 465 /* Ignore the instruction that allocates stack space and sets
466 the SP. */
467 if (rn == AARCH64_SP_REGNUM && !inst.operands[2].addr.writeback)
468 seen_stack_set = true;
07b287a0 469 }
432ec081
YQ		 470 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
471 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
472 && (inst.opcode->op == OP_STR_POS
473 || inst.opcode->op == OP_STRF_POS)))
474 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
475 && strcmp ("str", inst.opcode->name) == 0)
476 {
477 /* STR (immediate) */
478 unsigned int rt = inst.operands[0].reg.regno;
479 int32_t imm = inst.operands[1].addr.offset.imm;
480 unsigned int rn = inst.operands[1].addr.base_regno;
75faf5c4 481 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
432ec081
YQ		 482 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
483 || inst.operands[0].type == AARCH64_OPND_Ft);
484
485 if (inst.operands[0].type == AARCH64_OPND_Ft)
75faf5c4 486 rt += AARCH64_X_REGISTER_COUNT;
432ec081 487
75faf5c4 488 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
432ec081
YQ		 489 if (inst.operands[1].addr.writeback)
490 regs[rn] = pv_add_constant (regs[rn], imm);
f8e3fe0d
LM		 491
492 /* Are we storing with SP as a base? */
493 if (rn == AARCH64_SP_REGNUM)
494 seen_stack_set = true;
432ec081 495 }
d9ebcbce 496 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 497 {
498 /* Stop analysis on branch. */
499 break;
500 }
17e116a7
AH		 501 else if (inst.opcode->iclass == ic_system)
502 {
503 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
504 int ra_state_val = 0;
505
506 if (insn == 0xd503233f /* paciasp. */
507 || insn == 0xd503237f /* pacibsp. */)
508 {
509 /* Return addresses are mangled. */
510 ra_state_val = 1;
511 }
512 else if (insn == 0xd50323bf /* autiasp. */
513 || insn == 0xd50323ff /* autibsp. */)
514 {
515 /* Return addresses are not mangled. */
516 ra_state_val = 0;
517 }
518 else
519 {
520 if (aarch64_debug)
521 debug_printf ("aarch64: prologue analysis gave up addr=%s"
522 " opcode=0x%x (iclass)\n",
523 core_addr_to_string_nz (start), insn);
524 break;
525 }
526
527 if (tdep->has_pauth () && cache != nullptr)
528 trad_frame_set_value (cache->saved_regs,
529 tdep->pauth_ra_state_regnum,
530 ra_state_val);
531 }
07b287a0
MS		 532 else
533 {
534 if (aarch64_debug)
b277c936 535 {
0a0da556 536 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 537 " opcode=0x%x\n",
538 core_addr_to_string_nz (start), insn);
539 }
07b287a0
MS		 540 break;
541 }
542 }
543
544 if (cache == NULL)
f7b7ed97 545 return start;
07b287a0
MS		 546
547 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
548 {
549 /* Frame pointer is fp. Frame size is constant. */
550 cache->framereg = AARCH64_FP_REGNUM;
551 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
552 }
553 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
554 {
555 /* Try the stack pointer. */
556 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
557 cache->framereg = AARCH64_SP_REGNUM;
558 }
559 else
560 {
561 /* We're just out of luck. We don't know where the frame is. */
562 cache->framereg = -1;
563 cache->framesize = 0;
564 }
565
566 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
567 {
568 CORE_ADDR offset;
569
f7b7ed97 570 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 571 cache->saved_regs[i].addr = offset;
572 }
573
187f5d00
YQ		 574 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
575 {
576 int regnum = gdbarch_num_regs (gdbarch);
577 CORE_ADDR offset;
578
f7b7ed97
TT		 579 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
580 &offset))
187f5d00
YQ		 581 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
582 }
583
07b287a0
MS		 584 return start;
585}
586
4d9a9006
YQ		 587static CORE_ADDR
588aarch64_analyze_prologue (struct gdbarch *gdbarch,
589 CORE_ADDR start, CORE_ADDR limit,
590 struct aarch64_prologue_cache *cache)
591{
592 instruction_reader reader;
593
594 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
595 reader);
596}
597
598#if GDB_SELF_TEST
599
600namespace selftests {
601
602/* Instruction reader from manually cooked instruction sequences. */
603
604class instruction_reader_test : public abstract_instruction_reader
605{
606public:
607 template<size_t SIZE>
608 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
609 : m_insns (insns), m_insns_size (SIZE)
610 {}
611
612 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 613 override
4d9a9006
YQ		 614 {
615 SELF_CHECK (len == 4);
616 SELF_CHECK (memaddr % 4 == 0);
617 SELF_CHECK (memaddr / 4 < m_insns_size);
618
619 return m_insns[memaddr / 4];
620 }
621
622private:
623 const uint32_t *m_insns;
624 size_t m_insns_size;
625};
626
627static void
628aarch64_analyze_prologue_test (void)
629{
630 struct gdbarch_info info;
631
632 gdbarch_info_init (&info);
633 info.bfd_arch_info = bfd_scan_arch ("aarch64");
634
635 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
636 SELF_CHECK (gdbarch != NULL);
637
17e116a7
AH		 638 struct aarch64_prologue_cache cache;
639 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
640
641 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
642
4d9a9006
YQ		 643 /* Test the simple prologue in which frame pointer is used. */
644 {
4d9a9006
YQ		 645 static const uint32_t insns[] = {
646 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
647 0x910003fd, /* mov x29, sp */
648 0x97ffffe6, /* bl 0x400580 */
649 };
650 instruction_reader_test reader (insns);
651
652 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
653 SELF_CHECK (end == 4 * 2);
654
655 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
656 SELF_CHECK (cache.framesize == 272);
657
658 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
659 {
660 if (i == AARCH64_FP_REGNUM)
661 SELF_CHECK (cache.saved_regs[i].addr == -272);
662 else if (i == AARCH64_LR_REGNUM)
663 SELF_CHECK (cache.saved_regs[i].addr == -264);
664 else
665 SELF_CHECK (cache.saved_regs[i].addr == -1);
666 }
667
668 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
669 {
670 int regnum = gdbarch_num_regs (gdbarch);
671
672 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
673 == -1);
674 }
675 }
432ec081
YQ		 676
677 /* Test a prologue in which STR is used and frame pointer is not
678 used. */
679 {
432ec081
YQ		 680 static const uint32_t insns[] = {
681 0xf81d0ff3, /* str x19, [sp, #-48]! */
682 0xb9002fe0, /* str w0, [sp, #44] */
683 0xf90013e1, /* str x1, [sp, #32]*/
684 0xfd000fe0, /* str d0, [sp, #24] */
685 0xaa0203f3, /* mov x19, x2 */
686 0xf94013e0, /* ldr x0, [sp, #32] */
687 };
688 instruction_reader_test reader (insns);
689
68811f8f 690 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
432ec081
YQ		 691 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
692
693 SELF_CHECK (end == 4 * 5);
694
695 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
696 SELF_CHECK (cache.framesize == 48);
697
698 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
699 {
700 if (i == 1)
701 SELF_CHECK (cache.saved_regs[i].addr == -16);
702 else if (i == 19)
703 SELF_CHECK (cache.saved_regs[i].addr == -48);
704 else
705 SELF_CHECK (cache.saved_regs[i].addr == -1);
706 }
707
708 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
709 {
710 int regnum = gdbarch_num_regs (gdbarch);
711
712 if (i == 0)
713 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
714 == -24);
715 else
716 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
717 == -1);
718 }
719 }
17e116a7 720
f8e3fe0d
LM		 721 /* Test handling of movz before setting the frame pointer. */
722 {
723 static const uint32_t insns[] = {
724 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
725 0x52800020, /* mov w0, #0x1 */
726 0x910003fd, /* mov x29, sp */
727 0x528000a2, /* mov w2, #0x5 */
728 0x97fffff8, /* bl 6e4 */
729 };
730
731 instruction_reader_test reader (insns);
732
733 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
734 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
735
736 /* We should stop at the 4th instruction. */
737 SELF_CHECK (end == (4 - 1) * 4);
738 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
739 SELF_CHECK (cache.framesize == 16);
740 }
741
742 /* Test handling of movz/stp when using the stack pointer as frame
743 pointer. */
744 {
745 static const uint32_t insns[] = {
746 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
747 0x52800020, /* mov w0, #0x1 */
748 0x290207e0, /* stp w0, w1, [sp, #16] */
749 0xa9018fe2, /* stp x2, x3, [sp, #24] */
750 0x528000a2, /* mov w2, #0x5 */
751 0x97fffff8, /* bl 6e4 */
752 };
753
754 instruction_reader_test reader (insns);
755
756 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
757 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
758
759 /* We should stop at the 5th instruction. */
760 SELF_CHECK (end == (5 - 1) * 4);
761 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
762 SELF_CHECK (cache.framesize == 64);
763 }
764
765 /* Test handling of movz/str when using the stack pointer as frame
766 pointer */
767 {
768 static const uint32_t insns[] = {
769 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
770 0x52800020, /* mov w0, #0x1 */
771 0xb9002be4, /* str w4, [sp, #40] */
772 0xf9001be5, /* str x5, [sp, #48] */
773 0x528000a2, /* mov w2, #0x5 */
774 0x97fffff8, /* bl 6e4 */
775 };
776
777 instruction_reader_test reader (insns);
778
779 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
780 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
781
782 /* We should stop at the 5th instruction. */
783 SELF_CHECK (end == (5 - 1) * 4);
784 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
785 SELF_CHECK (cache.framesize == 64);
786 }
787
788 /* Test handling of movz/stur when using the stack pointer as frame
789 pointer. */
790 {
791 static const uint32_t insns[] = {
792 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
793 0x52800020, /* mov w0, #0x1 */
794 0xb80343e6, /* stur w6, [sp, #52] */
795 0xf80383e7, /* stur x7, [sp, #56] */
796 0x528000a2, /* mov w2, #0x5 */
797 0x97fffff8, /* bl 6e4 */
798 };
799
800 instruction_reader_test reader (insns);
801
802 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
803 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
804
805 /* We should stop at the 5th instruction. */
806 SELF_CHECK (end == (5 - 1) * 4);
807 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
808 SELF_CHECK (cache.framesize == 64);
809 }
810
811 /* Test handling of movz when there is no frame pointer set or no stack
812 pointer used. */
813 {
814 static const uint32_t insns[] = {
815 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
816 0x52800020, /* mov w0, #0x1 */
817 0x528000a2, /* mov w2, #0x5 */
818 0x97fffff8, /* bl 6e4 */
819 };
820
821 instruction_reader_test reader (insns);
822
823 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
824 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
825
826 /* We should stop at the 4th instruction. */
827 SELF_CHECK (end == (4 - 1) * 4);
828 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
829 SELF_CHECK (cache.framesize == 16);
830 }
831
17e116a7
AH		 832 /* Test a prologue in which there is a return address signing instruction. */
833 if (tdep->has_pauth ())
834 {
835 static const uint32_t insns[] = {
836 0xd503233f, /* paciasp */
837 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
838 0x910003fd, /* mov x29, sp */
839 0xf801c3f3, /* str x19, [sp, #28] */
840 0xb9401fa0, /* ldr x19, [x29, #28] */
841 };
842 instruction_reader_test reader (insns);
843
68811f8f 844 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
17e116a7
AH		 845 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
846 reader);
847
848 SELF_CHECK (end == 4 * 4);
849 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
850 SELF_CHECK (cache.framesize == 48);
851
852 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
853 {
854 if (i == 19)
855 SELF_CHECK (cache.saved_regs[i].addr == -20);
856 else if (i == AARCH64_FP_REGNUM)
857 SELF_CHECK (cache.saved_regs[i].addr == -48);
858 else if (i == AARCH64_LR_REGNUM)
859 SELF_CHECK (cache.saved_regs[i].addr == -40);
860 else
861 SELF_CHECK (cache.saved_regs[i].addr == -1);
862 }
863
864 if (tdep->has_pauth ())
865 {
866 SELF_CHECK (trad_frame_value_p (cache.saved_regs,
867 tdep->pauth_ra_state_regnum));
868 SELF_CHECK (cache.saved_regs[tdep->pauth_ra_state_regnum].addr == 1);
869 }
870 }
4d9a9006
YQ		 871}
872} // namespace selftests
873#endif /* GDB_SELF_TEST */
874
07b287a0
MS		 875/* Implement the "skip_prologue" gdbarch method. */
876
877static CORE_ADDR
878aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
879{
07b287a0 880 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 881
882 /* See if we can determine the end of the prologue via the symbol
883 table. If so, then return either PC, or the PC after the
884 prologue, whichever is greater. */
885 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
886 {
887 CORE_ADDR post_prologue_pc
888 = skip_prologue_using_sal (gdbarch, func_addr);
889
890 if (post_prologue_pc != 0)
325fac50 891 return std::max (pc, post_prologue_pc);
07b287a0
MS		 892 }
893
894 /* Can't determine prologue from the symbol table, need to examine
895 instructions. */
896
897 /* Find an upper limit on the function prologue using the debug
898 information. If the debug information could not be used to
899 provide that bound, then use an arbitrary large number as the
900 upper bound. */
901 limit_pc = skip_prologue_using_sal (gdbarch, pc);
902 if (limit_pc == 0)
903 limit_pc = pc + 128; /* Magic. */
904
905 /* Try disassembling prologue. */
906 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
907}
908
909/* Scan the function prologue for THIS_FRAME and populate the prologue
910 cache CACHE. */
911
912static void
913aarch64_scan_prologue (struct frame_info *this_frame,
914 struct aarch64_prologue_cache *cache)
915{
916 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
917 CORE_ADDR prologue_start;
918 CORE_ADDR prologue_end;
919 CORE_ADDR prev_pc = get_frame_pc (this_frame);
920 struct gdbarch *gdbarch = get_frame_arch (this_frame);
921
db634143
PL		 922 cache->prev_pc = prev_pc;
923
07b287a0
MS		 924 /* Assume we do not find a frame. */
925 cache->framereg = -1;
926 cache->framesize = 0;
927
928 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
929 &prologue_end))
930 {
931 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
932
933 if (sal.line == 0)
934 {
935 /* No line info so use the current PC. */
936 prologue_end = prev_pc;
937 }
938 else if (sal.end < prologue_end)
939 {
940 /* The next line begins after the function end. */
941 prologue_end = sal.end;
942 }
943
325fac50 944 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 945 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
946 }
947 else
948 {
949 CORE_ADDR frame_loc;
07b287a0
MS		 950
951 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
952 if (frame_loc == 0)
953 return;
954
955 cache->framereg = AARCH64_FP_REGNUM;
956 cache->framesize = 16;
957 cache->saved_regs[29].addr = 0;
958 cache->saved_regs[30].addr = 8;
959 }
960}
961
7dfa3edc
PL		 962/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
963 function may throw an exception if the inferior's registers or memory is
964 not available. */
07b287a0 965
7dfa3edc
PL		 966static void
967aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
968 struct aarch64_prologue_cache *cache)
07b287a0 969{
07b287a0
MS		 970 CORE_ADDR unwound_fp;
971 int reg;
972
07b287a0
MS		 973 aarch64_scan_prologue (this_frame, cache);
974
975 if (cache->framereg == -1)
7dfa3edc 976 return;
07b287a0
MS		 977
978 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
979 if (unwound_fp == 0)
7dfa3edc 980 return;
07b287a0
MS		 981
982 cache->prev_sp = unwound_fp + cache->framesize;
983
984 /* Calculate actual addresses of saved registers using offsets
985 determined by aarch64_analyze_prologue. */
986 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
987 if (trad_frame_addr_p (cache->saved_regs, reg))
988 cache->saved_regs[reg].addr += cache->prev_sp;
989
db634143
PL		 990 cache->func = get_frame_func (this_frame);
991
7dfa3edc
PL		 992 cache->available_p = 1;
993}
994
995/* Allocate and fill in *THIS_CACHE with information about the prologue of
996 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
997 Return a pointer to the current aarch64_prologue_cache in
998 *THIS_CACHE. */
999
1000static struct aarch64_prologue_cache *
1001aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
1002{
1003 struct aarch64_prologue_cache *cache;
1004
1005 if (*this_cache != NULL)
9a3c8263 1006 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 1007
1008 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1009 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1010 *this_cache = cache;
1011
a70b8144 1012 try
7dfa3edc
PL		 1013 {
1014 aarch64_make_prologue_cache_1 (this_frame, cache);
1015 }
230d2906 1016 catch (const gdb_exception_error &ex)
7dfa3edc
PL		 1017 {
1018 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1019 throw;
7dfa3edc 1020 }
7dfa3edc 1021
07b287a0
MS		 1022 return cache;
1023}
1024
7dfa3edc
PL		 1025/* Implement the "stop_reason" frame_unwind method. */
1026
1027static enum unwind_stop_reason
1028aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
1029 void **this_cache)
1030{
1031 struct aarch64_prologue_cache *cache
1032 = aarch64_make_prologue_cache (this_frame, this_cache);
1033
1034 if (!cache->available_p)
1035 return UNWIND_UNAVAILABLE;
1036
1037 /* Halt the backtrace at "_start". */
1038 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1039 return UNWIND_OUTERMOST;
1040
1041 /* We've hit a wall, stop. */
1042 if (cache->prev_sp == 0)
1043 return UNWIND_OUTERMOST;
1044
1045 return UNWIND_NO_REASON;
1046}
1047
07b287a0
MS		 1048/* Our frame ID for a normal frame is the current function's starting
1049 PC and the caller's SP when we were called. */
1050
1051static void
1052aarch64_prologue_this_id (struct frame_info *this_frame,
1053 void **this_cache, struct frame_id *this_id)
1054{
7c8edfae
PL		 1055 struct aarch64_prologue_cache *cache
1056 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 1057
7dfa3edc
PL		 1058 if (!cache->available_p)
1059 *this_id = frame_id_build_unavailable_stack (cache->func);
1060 else
1061 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 1062}
1063
1064/* Implement the "prev_register" frame_unwind method. */
1065
1066static struct value *
1067aarch64_prologue_prev_register (struct frame_info *this_frame,
1068 void **this_cache, int prev_regnum)
1069{
7c8edfae
PL		 1070 struct aarch64_prologue_cache *cache
1071 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1072
1073 /* If we are asked to unwind the PC, then we need to return the LR
1074 instead. The prologue may save PC, but it will point into this
1075 frame's prologue, not the next frame's resume location. */
1076 if (prev_regnum == AARCH64_PC_REGNUM)
1077 {
1078 CORE_ADDR lr;
17e116a7
AH		 1079 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1080 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 1081
1082 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
17e116a7
AH		 1083
1084 if (tdep->has_pauth ()
1085 && trad_frame_value_p (cache->saved_regs,
1086 tdep->pauth_ra_state_regnum))
3d31bc39 1087 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
17e116a7 1088
07b287a0
MS		 1089 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
1090 }
1091
1092 /* SP is generally not saved to the stack, but this frame is
1093 identified by the next frame's stack pointer at the time of the
1094 call. The value was already reconstructed into PREV_SP. */
1095 /*
1096 +----------+ ^
1097 | saved lr | |
1098 +->| saved fp |--+
1099 | | |
1100 | | | <- Previous SP
1101 | +----------+
1102 | | saved lr |
1103 +--| saved fp |<- FP
1104 | |
1105 | |<- SP
1106 +----------+ */
1107 if (prev_regnum == AARCH64_SP_REGNUM)
1108 return frame_unwind_got_constant (this_frame, prev_regnum,
1109 cache->prev_sp);
1110
1111 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1112 prev_regnum);
1113}
1114
1115/* AArch64 prologue unwinder. */
1116struct frame_unwind aarch64_prologue_unwind =
1117{
1118 NORMAL_FRAME,
7dfa3edc 1119 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 1120 aarch64_prologue_this_id,
1121 aarch64_prologue_prev_register,
1122 NULL,
1123 default_frame_sniffer
1124};
1125
8b61f75d
PL		 1126/* Allocate and fill in *THIS_CACHE with information about the prologue of
1127 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1128 Return a pointer to the current aarch64_prologue_cache in
1129 *THIS_CACHE. */
07b287a0
MS		 1130
1131static struct aarch64_prologue_cache *
8b61f75d 1132aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 1133{
07b287a0 1134 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 1135
1136 if (*this_cache != NULL)
9a3c8263 1137 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 1138
1139 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1140 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 1141 *this_cache = cache;
07b287a0 1142
a70b8144 1143 try
02a2a705
PL		 1144 {
1145 cache->prev_sp = get_frame_register_unsigned (this_frame,
1146 AARCH64_SP_REGNUM);
1147 cache->prev_pc = get_frame_pc (this_frame);
1148 cache->available_p = 1;
1149 }
230d2906 1150 catch (const gdb_exception_error &ex)
02a2a705
PL		 1151 {
1152 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1153 throw;
02a2a705 1154 }
07b287a0
MS		 1155
1156 return cache;
1157}
1158
02a2a705
PL		 1159/* Implement the "stop_reason" frame_unwind method. */
1160
1161static enum unwind_stop_reason
1162aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
1163 void **this_cache)
1164{
1165 struct aarch64_prologue_cache *cache
1166 = aarch64_make_stub_cache (this_frame, this_cache);
1167
1168 if (!cache->available_p)
1169 return UNWIND_UNAVAILABLE;
1170
1171 return UNWIND_NO_REASON;
1172}
1173
07b287a0
MS		 1174/* Our frame ID for a stub frame is the current SP and LR. */
1175
1176static void
1177aarch64_stub_this_id (struct frame_info *this_frame,
1178 void **this_cache, struct frame_id *this_id)
1179{
8b61f75d
PL		 1180 struct aarch64_prologue_cache *cache
1181 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 1182
02a2a705
PL		 1183 if (cache->available_p)
1184 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
1185 else
1186 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 1187}
1188
1189/* Implement the "sniffer" frame_unwind method. */
1190
1191static int
1192aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
1193 struct frame_info *this_frame,
1194 void **this_prologue_cache)
1195{
1196 CORE_ADDR addr_in_block;
1197 gdb_byte dummy[4];
1198
1199 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 1200 if (in_plt_section (addr_in_block)
07b287a0
MS		 1201 /* We also use the stub winder if the target memory is unreadable
1202 to avoid having the prologue unwinder trying to read it. */
1203 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1204 return 1;
1205
1206 return 0;
1207}
1208
1209/* AArch64 stub unwinder. */
1210struct frame_unwind aarch64_stub_unwind =
1211{
1212 NORMAL_FRAME,
02a2a705 1213 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 1214 aarch64_stub_this_id,
1215 aarch64_prologue_prev_register,
1216 NULL,
1217 aarch64_stub_unwind_sniffer
1218};
1219
1220/* Return the frame base address of *THIS_FRAME. */
1221
1222static CORE_ADDR
1223aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1224{
7c8edfae
PL		 1225 struct aarch64_prologue_cache *cache
1226 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1227
1228 return cache->prev_sp - cache->framesize;
1229}
1230
1231/* AArch64 default frame base information. */
1232struct frame_base aarch64_normal_base =
1233{
1234 &aarch64_prologue_unwind,
1235 aarch64_normal_frame_base,
1236 aarch64_normal_frame_base,
1237 aarch64_normal_frame_base
1238};
1239
07b287a0
MS		 1240/* Return the value of the REGNUM register in the previous frame of
1241 *THIS_FRAME. */
1242
1243static struct value *
1244aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1245 void **this_cache, int regnum)
1246{
11e1b75f 1247 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
07b287a0
MS		 1248 CORE_ADDR lr;
1249
1250 switch (regnum)
1251 {
1252 case AARCH64_PC_REGNUM:
1253 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
3d31bc39 1254 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
07b287a0
MS		 1255 return frame_unwind_got_constant (this_frame, regnum, lr);
1256
1257 default:
1258 internal_error (__FILE__, __LINE__,
1259 _("Unexpected register %d"), regnum);
1260 }
1261}
1262
11e1b75f
AH		 1263static const unsigned char op_lit0 = DW_OP_lit0;
1264static const unsigned char op_lit1 = DW_OP_lit1;
1265
07b287a0
MS		 1266/* Implement the "init_reg" dwarf2_frame_ops method. */
1267
1268static void
1269aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1270 struct dwarf2_frame_state_reg *reg,
1271 struct frame_info *this_frame)
1272{
11e1b75f
AH		 1273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1274
07b287a0
MS		 1275 switch (regnum)
1276 {
1277 case AARCH64_PC_REGNUM:
1278 reg->how = DWARF2_FRAME_REG_FN;
1279 reg->loc.fn = aarch64_dwarf2_prev_register;
11e1b75f
AH		 1280 return;
1281
07b287a0
MS		 1282 case AARCH64_SP_REGNUM:
1283 reg->how = DWARF2_FRAME_REG_CFA;
11e1b75f
AH		 1284 return;
1285 }
1286
1287 /* Init pauth registers. */
1288 if (tdep->has_pauth ())
1289 {
1290 if (regnum == tdep->pauth_ra_state_regnum)
1291 {
1292 /* Initialize RA_STATE to zero. */
1293 reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1294 reg->loc.exp.start = &op_lit0;
1295 reg->loc.exp.len = 1;
1296 return;
1297 }
1298 else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
1299 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
1300 {
1301 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1302 return;
1303 }
07b287a0
MS		 1304 }
1305}
1306
11e1b75f
AH		 1307/* Implement the execute_dwarf_cfa_vendor_op method. */
1308
1309static bool
1310aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1311 struct dwarf2_frame_state *fs)
1312{
1313 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1314 struct dwarf2_frame_state_reg *ra_state;
1315
8fca4da0 1316 if (op == DW_CFA_AARCH64_negate_ra_state)
11e1b75f 1317 {
8fca4da0
AH		 1318 /* On systems without pauth, treat as a nop. */
1319 if (!tdep->has_pauth ())
1320 return true;
1321
11e1b75f
AH		 1322 /* Allocate RA_STATE column if it's not allocated yet. */
1323 fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
1324
1325 /* Toggle the status of RA_STATE between 0 and 1. */
1326 ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
1327 ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1328
1329 if (ra_state->loc.exp.start == nullptr
1330 || ra_state->loc.exp.start == &op_lit0)
1331 ra_state->loc.exp.start = &op_lit1;
1332 else
1333 ra_state->loc.exp.start = &op_lit0;
1334
1335 ra_state->loc.exp.len = 1;
1336
1337 return true;
1338 }
1339
1340 return false;
1341}
1342
5133a315
LM		 1343/* Used for matching BRK instructions for AArch64. */
1344static constexpr uint32_t BRK_INSN_MASK = 0xffe0001f;
1345static constexpr uint32_t BRK_INSN_BASE = 0xd4200000;
1346
1347/* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1348
1349static bool
1350aarch64_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address)
1351{
1352 const uint32_t insn_len = 4;
1353 gdb_byte target_mem[4];
1354
1355 /* Enable the automatic memory restoration from breakpoints while
1356 we read the memory. Otherwise we may find temporary breakpoints, ones
1357 inserted by GDB, and flag them as permanent breakpoints. */
1358 scoped_restore restore_memory
1359 = make_scoped_restore_show_memory_breakpoints (0);
1360
1361 if (target_read_memory (address, target_mem, insn_len) == 0)
1362 {
1363 uint32_t insn =
1364 (uint32_t) extract_unsigned_integer (target_mem, insn_len,
1365 gdbarch_byte_order_for_code (gdbarch));
1366
1367 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1368 of such instructions with different immediate values. Different OS'
1369 may use a different variation, but they have the same outcome. */
1370 return ((insn & BRK_INSN_MASK) == BRK_INSN_BASE);
1371 }
1372
1373 return false;
1374}
1375
07b287a0
MS		 1376/* When arguments must be pushed onto the stack, they go on in reverse
1377 order. The code below implements a FILO (stack) to do this. */
1378
89055eaa 1379struct stack_item_t
07b287a0 1380{
c3c87445
YQ		 1381 /* Value to pass on stack. It can be NULL if this item is for stack
1382 padding. */
7c543f7b 1383 const gdb_byte *data;
07b287a0
MS		 1384
1385 /* Size in bytes of value to pass on stack. */
1386 int len;
89055eaa 1387};
07b287a0 1388
b907456c
AB		 1389/* Implement the gdbarch type alignment method, overrides the generic
1390 alignment algorithm for anything that is aarch64 specific. */
07b287a0 1391
b907456c
AB		 1392static ULONGEST
1393aarch64_type_align (gdbarch *gdbarch, struct type *t)
07b287a0 1394{
07b287a0 1395 t = check_typedef (t);
78134374 1396 if (t->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (t))
07b287a0 1397 {
b907456c
AB		 1398 /* Use the natural alignment for vector types (the same for
1399 scalar type), but the maximum alignment is 128-bit. */
1400 if (TYPE_LENGTH (t) > 16)
1401 return 16;
238f2452 1402 else
b907456c 1403 return TYPE_LENGTH (t);
07b287a0 1404 }
b907456c
AB		 1405
1406 /* Allow the common code to calculate the alignment. */
1407 return 0;
07b287a0
MS		 1408}
1409
ea92689a
AH		 1410/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1411
1412 Return the number of register required, or -1 on failure.
1413
1414 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1415 to the element, else fail if the type of this element does not match the
1416 existing value. */
1417
1418static int
1419aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1420 struct type **fundamental_type)
1421{
1422 if (type == nullptr)
1423 return -1;
1424
78134374 1425 switch (type->code ())
ea92689a
AH		 1426 {
1427 case TYPE_CODE_FLT:
1428 if (TYPE_LENGTH (type) > 16)
1429 return -1;
1430
1431 if (*fundamental_type == nullptr)
1432 *fundamental_type = type;
1433 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
78134374 1434 || type->code () != (*fundamental_type)->code ())
ea92689a
AH		 1435 return -1;
1436
1437 return 1;
1438
1439 case TYPE_CODE_COMPLEX:
1440 {
1441 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1442 if (TYPE_LENGTH (target_type) > 16)
1443 return -1;
1444
1445 if (*fundamental_type == nullptr)
1446 *fundamental_type = target_type;
1447 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
78134374 1448 || target_type->code () != (*fundamental_type)->code ())
ea92689a
AH		 1449 return -1;
1450
1451 return 2;
1452 }
1453
1454 case TYPE_CODE_ARRAY:
1455 {
1456 if (TYPE_VECTOR (type))
1457 {
1458 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1459 return -1;
1460
1461 if (*fundamental_type == nullptr)
1462 *fundamental_type = type;
1463 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
78134374 1464 || type->code () != (*fundamental_type)->code ())
ea92689a
AH		 1465 return -1;
1466
1467 return 1;
1468 }
1469 else
1470 {
1471 struct type *target_type = TYPE_TARGET_TYPE (type);
1472 int count = aapcs_is_vfp_call_or_return_candidate_1
1473 (target_type, fundamental_type);
1474
1475 if (count == -1)
1476 return count;
1477
d4718d5c 1478 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1479 return count;
1480 }
1481 }
1482
1483 case TYPE_CODE_STRUCT:
1484 case TYPE_CODE_UNION:
1485 {
1486 int count = 0;
1487
1f704f76 1488 for (int i = 0; i < type->num_fields (); i++)
ea92689a 1489 {
353229bf 1490 /* Ignore any static fields. */
ceacbf6e 1491 if (field_is_static (&type->field (i)))
353229bf
AH		 1492 continue;
1493
940da03e 1494 struct type *member = check_typedef (type->field (i).type ());
ea92689a
AH		 1495
1496 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1497 (member, fundamental_type);
1498 if (sub_count == -1)
1499 return -1;
1500 count += sub_count;
1501 }
73021deb
AH		 1502
1503 /* Ensure there is no padding between the fields (allowing for empty
1504 zero length structs) */
1505 int ftype_length = (*fundamental_type == nullptr)
1506 ? 0 : TYPE_LENGTH (*fundamental_type);
1507 if (count * ftype_length != TYPE_LENGTH (type))
1508 return -1;
1509
ea92689a
AH		 1510 return count;
1511 }
1512
1513 default:
1514 break;
1515 }
1516
1517 return -1;
1518}
1519
1520/* Return true if an argument, whose type is described by TYPE, can be passed or
1521 returned in simd/fp registers, providing enough parameter passing registers
1522 are available. This is as described in the AAPCS64.
1523
1524 Upon successful return, *COUNT returns the number of needed registers,
1525 *FUNDAMENTAL_TYPE contains the type of those registers.
1526
1527 Candidate as per the AAPCS64 5.4.2.C is either a:
1528 - float.
1529 - short-vector.
1530 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1531 all the members are floats and has at most 4 members.
1532 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1533 all the members are short vectors and has at most 4 members.
1534 - Complex (7.1.1)
1535
1536 Note that HFAs and HVAs can include nested structures and arrays. */
1537
0e745c60 1538static bool
ea92689a
AH		 1539aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1540 struct type **fundamental_type)
1541{
1542 if (type == nullptr)
1543 return false;
1544
1545 *fundamental_type = nullptr;
1546
1547 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1548 fundamental_type);
1549
1550 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1551 {
1552 *count = ag_count;
1553 return true;
1554 }
1555 else
1556 return false;
1557}
1558
07b287a0
MS		 1559/* AArch64 function call information structure. */
1560struct aarch64_call_info
1561{
1562 /* the current argument number. */
89055eaa 1563 unsigned argnum = 0;
07b287a0
MS		 1564
1565 /* The next general purpose register number, equivalent to NGRN as
1566 described in the AArch64 Procedure Call Standard. */
89055eaa 1567 unsigned ngrn = 0;
07b287a0
MS		 1568
1569 /* The next SIMD and floating point register number, equivalent to
1570 NSRN as described in the AArch64 Procedure Call Standard. */
89055eaa 1571 unsigned nsrn = 0;
07b287a0
MS		 1572
1573 /* The next stacked argument address, equivalent to NSAA as
1574 described in the AArch64 Procedure Call Standard. */
89055eaa 1575 unsigned nsaa = 0;
07b287a0
MS		 1576
1577 /* Stack item vector. */
89055eaa 1578 std::vector<stack_item_t> si;
07b287a0
MS		 1579};
1580
1581/* Pass a value in a sequence of consecutive X registers. The caller
30baf67b 1582 is responsible for ensuring sufficient registers are available. */
07b287a0
MS		 1583
1584static void
1585pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1586 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1587 struct value *arg)
07b287a0
MS		 1588{
1589 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1590 int len = TYPE_LENGTH (type);
78134374 1591 enum type_code typecode = type->code ();
07b287a0 1592 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1593 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1594
1595 info->argnum++;
1596
1597 while (len > 0)
1598 {
1599 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1600 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1601 byte_order);
1602
1603
1604 /* Adjust sub-word struct/union args when big-endian. */
1605 if (byte_order == BFD_ENDIAN_BIG
1606 && partial_len < X_REGISTER_SIZE
1607 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1608 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1609
1610 if (aarch64_debug)
b277c936
PL		 1611 {
1612 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1613 gdbarch_register_name (gdbarch, regnum),
1614 phex (regval, X_REGISTER_SIZE));
1615 }
07b287a0
MS		 1616 regcache_cooked_write_unsigned (regcache, regnum, regval);
1617 len -= partial_len;
1618 buf += partial_len;
1619 regnum++;
1620 }
1621}
1622
1623/* Attempt to marshall a value in a V register. Return 1 if
1624 successful, or 0 if insufficient registers are available. This
1625 function, unlike the equivalent pass_in_x() function does not
1626 handle arguments spread across multiple registers. */
1627
1628static int
1629pass_in_v (struct gdbarch *gdbarch,
1630 struct regcache *regcache,
1631 struct aarch64_call_info *info,
0735fddd 1632 int len, const bfd_byte *buf)
07b287a0
MS		 1633{
1634 if (info->nsrn < 8)
1635 {
07b287a0 1636 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1637 /* Enough space for a full vector register. */
1638 gdb_byte reg[register_size (gdbarch, regnum)];
1639 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1640
1641 info->argnum++;
1642 info->nsrn++;
1643
0735fddd
YQ		 1644 memset (reg, 0, sizeof (reg));
1645 /* PCS C.1, the argument is allocated to the least significant
1646 bits of V register. */
1647 memcpy (reg, buf, len);
b66f5587 1648 regcache->cooked_write (regnum, reg);
0735fddd 1649
07b287a0 1650 if (aarch64_debug)
b277c936
PL		 1651 {
1652 debug_printf ("arg %d in %s\n", info->argnum,
1653 gdbarch_register_name (gdbarch, regnum));
1654 }
07b287a0
MS		 1655 return 1;
1656 }
1657 info->nsrn = 8;
1658 return 0;
1659}
1660
1661/* Marshall an argument onto the stack. */
1662
1663static void
1664pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1665 struct value *arg)
07b287a0 1666{
8e80f9d1 1667 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1668 int len = TYPE_LENGTH (type);
1669 int align;
1670 stack_item_t item;
1671
1672 info->argnum++;
1673
b907456c 1674 align = type_align (type);
07b287a0
MS		 1675
1676 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1677 Natural alignment of the argument's type. */
1678 align = align_up (align, 8);
1679
1680 /* The AArch64 PCS requires at most doubleword alignment. */
1681 if (align > 16)
1682 align = 16;
1683
1684 if (aarch64_debug)
b277c936
PL		 1685 {
1686 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1687 info->nsaa);
1688 }
07b287a0
MS		 1689
1690 item.len = len;
1691 item.data = buf;
89055eaa 1692 info->si.push_back (item);
07b287a0
MS		 1693
1694 info->nsaa += len;
1695 if (info->nsaa & (align - 1))
1696 {
1697 /* Push stack alignment padding. */
1698 int pad = align - (info->nsaa & (align - 1));
1699
1700 item.len = pad;
c3c87445 1701 item.data = NULL;
07b287a0 1702
89055eaa 1703 info->si.push_back (item);
07b287a0
MS		 1704 info->nsaa += pad;
1705 }
1706}
1707
1708/* Marshall an argument into a sequence of one or more consecutive X
1709 registers or, if insufficient X registers are available then onto
1710 the stack. */
1711
1712static void
1713pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1714 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1715 struct value *arg)
07b287a0
MS		 1716{
1717 int len = TYPE_LENGTH (type);
1718 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1719
1720 /* PCS C.13 - Pass in registers if we have enough spare */
1721 if (info->ngrn + nregs <= 8)
1722 {
8e80f9d1 1723 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1724 info->ngrn += nregs;
1725 }
1726 else
1727 {
1728 info->ngrn = 8;
8e80f9d1 1729 pass_on_stack (info, type, arg);
07b287a0
MS		 1730 }
1731}
1732
0e745c60
AH		 1733/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1734 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1735 registers. A return value of false is an error state as the value will have
1736 been partially passed to the stack. */
1737static bool
1738pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1739 struct aarch64_call_info *info, struct type *arg_type,
1740 struct value *arg)
07b287a0 1741{
78134374 1742 switch (arg_type->code ())
0e745c60
AH		 1743 {
1744 case TYPE_CODE_FLT:
1745 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1746 value_contents (arg));
1747 break;
1748
1749 case TYPE_CODE_COMPLEX:
1750 {
1751 const bfd_byte *buf = value_contents (arg);
1752 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1753
1754 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1755 buf))
1756 return false;
1757
1758 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1759 buf + TYPE_LENGTH (target_type));
1760 }
1761
1762 case TYPE_CODE_ARRAY:
1763 if (TYPE_VECTOR (arg_type))
1764 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1765 value_contents (arg));
1766 /* fall through. */
1767
1768 case TYPE_CODE_STRUCT:
1769 case TYPE_CODE_UNION:
1f704f76 1770 for (int i = 0; i < arg_type->num_fields (); i++)
0e745c60 1771 {
353229bf 1772 /* Don't include static fields. */
ceacbf6e 1773 if (field_is_static (&arg_type->field (i)))
353229bf
AH		 1774 continue;
1775
0e745c60
AH		 1776 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1777 struct type *field_type = check_typedef (value_type (field));
1778
1779 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1780 field))
1781 return false;
1782 }
1783 return true;
1784
1785 default:
1786 return false;
1787 }
07b287a0
MS		 1788}
1789
1790/* Implement the "push_dummy_call" gdbarch method. */
1791
1792static CORE_ADDR
1793aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1794 struct regcache *regcache, CORE_ADDR bp_addr,
1795 int nargs,
cf84fa6b
AH		 1796 struct value **args, CORE_ADDR sp,
1797 function_call_return_method return_method,
07b287a0
MS		 1798 CORE_ADDR struct_addr)
1799{
07b287a0 1800 int argnum;
07b287a0 1801 struct aarch64_call_info info;
07b287a0 1802
07b287a0
MS		 1803 /* We need to know what the type of the called function is in order
1804 to determine the number of named/anonymous arguments for the
1805 actual argument placement, and the return type in order to handle
1806 return value correctly.
1807
1808 The generic code above us views the decision of return in memory
1809 or return in registers as a two stage processes. The language
1810 handler is consulted first and may decide to return in memory (eg
1811 class with copy constructor returned by value), this will cause
1812 the generic code to allocate space AND insert an initial leading
1813 argument.
1814
1815 If the language code does not decide to pass in memory then the
1816 target code is consulted.
1817
1818 If the language code decides to pass in memory we want to move
1819 the pointer inserted as the initial argument from the argument
1820 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1821 register. */
07b287a0
MS		 1822
1823 /* Set the return address. For the AArch64, the return breakpoint
1824 is always at BP_ADDR. */
1825 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1826
38a72da0
AH		 1827 /* If we were given an initial argument for the return slot, lose it. */
1828 if (return_method == return_method_hidden_param)
07b287a0
MS		 1829 {
1830 args++;
1831 nargs--;
1832 }
1833
1834 /* The struct_return pointer occupies X8. */
38a72da0 1835 if (return_method != return_method_normal)
07b287a0
MS		 1836 {
1837 if (aarch64_debug)
b277c936
PL		 1838 {
1839 debug_printf ("struct return in %s = 0x%s\n",
1840 gdbarch_register_name (gdbarch,
1841 AARCH64_STRUCT_RETURN_REGNUM),
1842 paddress (gdbarch, struct_addr));
1843 }
07b287a0
MS		 1844 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1845 struct_addr);
1846 }
1847
1848 for (argnum = 0; argnum < nargs; argnum++)
1849 {
1850 struct value *arg = args[argnum];
0e745c60
AH		 1851 struct type *arg_type, *fundamental_type;
1852 int len, elements;
07b287a0
MS		 1853
1854 arg_type = check_typedef (value_type (arg));
1855 len = TYPE_LENGTH (arg_type);
1856
0e745c60
AH		 1857 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1858 if there are enough spare registers. */
1859 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1860 &fundamental_type))
1861 {
1862 if (info.nsrn + elements <= 8)
1863 {
1864 /* We know that we have sufficient registers available therefore
1865 this will never need to fallback to the stack. */
1866 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1867 arg))
1868 gdb_assert_not_reached ("Failed to push args");
1869 }
1870 else
1871 {
1872 info.nsrn = 8;
1873 pass_on_stack (&info, arg_type, arg);
1874 }
1875 continue;
1876 }
1877
78134374 1878 switch (arg_type->code ())
07b287a0
MS		 1879 {
1880 case TYPE_CODE_INT:
1881 case TYPE_CODE_BOOL:
1882 case TYPE_CODE_CHAR:
1883 case TYPE_CODE_RANGE:
1884 case TYPE_CODE_ENUM:
1885 if (len < 4)
1886 {
1887 /* Promote to 32 bit integer. */
1888 if (TYPE_UNSIGNED (arg_type))
1889 arg_type = builtin_type (gdbarch)->builtin_uint32;
1890 else
1891 arg_type = builtin_type (gdbarch)->builtin_int32;
1892 arg = value_cast (arg_type, arg);
1893 }
8e80f9d1 1894 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1895 break;
1896
07b287a0
MS		 1897 case TYPE_CODE_STRUCT:
1898 case TYPE_CODE_ARRAY:
1899 case TYPE_CODE_UNION:
0e745c60 1900 if (len > 16)
07b287a0
MS		 1901 {
1902 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1903 invisible reference. */
1904
1905 /* Allocate aligned storage. */
1906 sp = align_down (sp - len, 16);
1907
1908 /* Write the real data into the stack. */
1909 write_memory (sp, value_contents (arg), len);
1910
1911 /* Construct the indirection. */
1912 arg_type = lookup_pointer_type (arg_type);
1913 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1914 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1915 }
1916 else
1917 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1918 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1919 break;
1920
1921 default:
8e80f9d1 1922 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1923 break;
1924 }
1925 }
1926
1927 /* Make sure stack retains 16 byte alignment. */
1928 if (info.nsaa & 15)
1929 sp -= 16 - (info.nsaa & 15);
1930
89055eaa 1931 while (!info.si.empty ())
07b287a0 1932 {
89055eaa 1933 const stack_item_t &si = info.si.back ();
07b287a0 1934
89055eaa
TT		 1935 sp -= si.len;
1936 if (si.data != NULL)
1937 write_memory (sp, si.data, si.len);
1938 info.si.pop_back ();
07b287a0
MS		 1939 }
1940
07b287a0
MS		 1941 /* Finally, update the SP register. */
1942 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1943
1944 return sp;
1945}
1946
1947/* Implement the "frame_align" gdbarch method. */
1948
1949static CORE_ADDR
1950aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1951{
1952 /* Align the stack to sixteen bytes. */
1953 return sp & ~(CORE_ADDR) 15;
1954}
1955
1956/* Return the type for an AdvSISD Q register. */
1957
1958static struct type *
1959aarch64_vnq_type (struct gdbarch *gdbarch)
1960{
1961 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1962
1963 if (tdep->vnq_type == NULL)
1964 {
1965 struct type *t;
1966 struct type *elem;
1967
1968 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1969 TYPE_CODE_UNION);
1970
1971 elem = builtin_type (gdbarch)->builtin_uint128;
1972 append_composite_type_field (t, "u", elem);
1973
1974 elem = builtin_type (gdbarch)->builtin_int128;
1975 append_composite_type_field (t, "s", elem);
1976
1977 tdep->vnq_type = t;
1978 }
1979
1980 return tdep->vnq_type;
1981}
1982
1983/* Return the type for an AdvSISD D register. */
1984
1985static struct type *
1986aarch64_vnd_type (struct gdbarch *gdbarch)
1987{
1988 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1989
1990 if (tdep->vnd_type == NULL)
1991 {
1992 struct type *t;
1993 struct type *elem;
1994
1995 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1996 TYPE_CODE_UNION);
1997
1998 elem = builtin_type (gdbarch)->builtin_double;
1999 append_composite_type_field (t, "f", elem);
2000
2001 elem = builtin_type (gdbarch)->builtin_uint64;
2002 append_composite_type_field (t, "u", elem);
2003
2004 elem = builtin_type (gdbarch)->builtin_int64;
2005 append_composite_type_field (t, "s", elem);
2006
2007 tdep->vnd_type = t;
2008 }
2009
2010 return tdep->vnd_type;
2011}
2012
2013/* Return the type for an AdvSISD S register. */
2014
2015static struct type *
2016aarch64_vns_type (struct gdbarch *gdbarch)
2017{
2018 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2019
2020 if (tdep->vns_type == NULL)
2021 {
2022 struct type *t;
2023 struct type *elem;
2024
2025 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
2026 TYPE_CODE_UNION);
2027
2028 elem = builtin_type (gdbarch)->builtin_float;
2029 append_composite_type_field (t, "f", elem);
2030
2031 elem = builtin_type (gdbarch)->builtin_uint32;
2032 append_composite_type_field (t, "u", elem);
2033
2034 elem = builtin_type (gdbarch)->builtin_int32;
2035 append_composite_type_field (t, "s", elem);
2036
2037 tdep->vns_type = t;
2038 }
2039
2040 return tdep->vns_type;
2041}
2042
2043/* Return the type for an AdvSISD H register. */
2044
2045static struct type *
2046aarch64_vnh_type (struct gdbarch *gdbarch)
2047{
2048 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2049
2050 if (tdep->vnh_type == NULL)
2051 {
2052 struct type *t;
2053 struct type *elem;
2054
2055 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
2056 TYPE_CODE_UNION);
2057
a6d0f249
AH		 2058 elem = builtin_type (gdbarch)->builtin_half;
2059 append_composite_type_field (t, "f", elem);
2060
07b287a0
MS		 2061 elem = builtin_type (gdbarch)->builtin_uint16;
2062 append_composite_type_field (t, "u", elem);
2063
2064 elem = builtin_type (gdbarch)->builtin_int16;
2065 append_composite_type_field (t, "s", elem);
2066
2067 tdep->vnh_type = t;
2068 }
2069
2070 return tdep->vnh_type;
2071}
2072
2073/* Return the type for an AdvSISD B register. */
2074
2075static struct type *
2076aarch64_vnb_type (struct gdbarch *gdbarch)
2077{
2078 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2079
2080 if (tdep->vnb_type == NULL)
2081 {
2082 struct type *t;
2083 struct type *elem;
2084
2085 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
2086 TYPE_CODE_UNION);
2087
2088 elem = builtin_type (gdbarch)->builtin_uint8;
2089 append_composite_type_field (t, "u", elem);
2090
2091 elem = builtin_type (gdbarch)->builtin_int8;
2092 append_composite_type_field (t, "s", elem);
2093
2094 tdep->vnb_type = t;
2095 }
2096
2097 return tdep->vnb_type;
2098}
2099
63bad7b6
AH		 2100/* Return the type for an AdvSISD V register. */
2101
2102static struct type *
2103aarch64_vnv_type (struct gdbarch *gdbarch)
2104{
2105 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2106
2107 if (tdep->vnv_type == NULL)
2108 {
09624f1f 2109 /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
bffa1015
AH		 2110 slice from the non-pseudo vector registers. However NEON V registers
2111 are always vector registers, and need constructing as such. */
2112 const struct builtin_type *bt = builtin_type (gdbarch);
2113
63bad7b6
AH		 2114 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
2115 TYPE_CODE_UNION);
2116
bffa1015
AH		 2117 struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
2118 TYPE_CODE_UNION);
2119 append_composite_type_field (sub, "f",
2120 init_vector_type (bt->builtin_double, 2));
2121 append_composite_type_field (sub, "u",
2122 init_vector_type (bt->builtin_uint64, 2));
2123 append_composite_type_field (sub, "s",
2124 init_vector_type (bt->builtin_int64, 2));
2125 append_composite_type_field (t, "d", sub);
2126
2127 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
2128 TYPE_CODE_UNION);
2129 append_composite_type_field (sub, "f",
2130 init_vector_type (bt->builtin_float, 4));
2131 append_composite_type_field (sub, "u",
2132 init_vector_type (bt->builtin_uint32, 4));
2133 append_composite_type_field (sub, "s",
2134 init_vector_type (bt->builtin_int32, 4));
2135 append_composite_type_field (t, "s", sub);
2136
2137 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
2138 TYPE_CODE_UNION);
a6d0f249
AH		 2139 append_composite_type_field (sub, "f",
2140 init_vector_type (bt->builtin_half, 8));
bffa1015
AH		 2141 append_composite_type_field (sub, "u",
2142 init_vector_type (bt->builtin_uint16, 8));
2143 append_composite_type_field (sub, "s",
2144 init_vector_type (bt->builtin_int16, 8));
2145 append_composite_type_field (t, "h", sub);
2146
2147 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
2148 TYPE_CODE_UNION);
2149 append_composite_type_field (sub, "u",
2150 init_vector_type (bt->builtin_uint8, 16));
2151 append_composite_type_field (sub, "s",
2152 init_vector_type (bt->builtin_int8, 16));
2153 append_composite_type_field (t, "b", sub);
2154
2155 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
2156 TYPE_CODE_UNION);
2157 append_composite_type_field (sub, "u",
2158 init_vector_type (bt->builtin_uint128, 1));
2159 append_composite_type_field (sub, "s",
2160 init_vector_type (bt->builtin_int128, 1));
2161 append_composite_type_field (t, "q", sub);
63bad7b6
AH		 2162
2163 tdep->vnv_type = t;
2164 }
2165
2166 return tdep->vnv_type;
2167}
2168
07b287a0
MS		 2169/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2170
2171static int
2172aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
2173{
34dcc7cf
AH		 2174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2175
07b287a0
MS		 2176 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
2177 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
2178
2179 if (reg == AARCH64_DWARF_SP)
2180 return AARCH64_SP_REGNUM;
2181
2182 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
2183 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
2184
65d4cada
AH		 2185 if (reg == AARCH64_DWARF_SVE_VG)
2186 return AARCH64_SVE_VG_REGNUM;
2187
2188 if (reg == AARCH64_DWARF_SVE_FFR)
2189 return AARCH64_SVE_FFR_REGNUM;
2190
2191 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
2192 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
2193
2194 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
2195 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
2196
34dcc7cf
AH		 2197 if (tdep->has_pauth ())
2198 {
2199 if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
2200 return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
2201
2202 if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
2203 return tdep->pauth_ra_state_regnum;
2204 }
2205
07b287a0
MS		 2206 return -1;
2207}
07b287a0
MS		 2208
2209/* Implement the "print_insn" gdbarch method. */
2210
2211static int
2212aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
2213{
2214 info->symbols = NULL;
6394c606 2215 return default_print_insn (memaddr, info);
07b287a0
MS		 2216}
2217
2218/* AArch64 BRK software debug mode instruction.
2219 Note that AArch64 code is always little-endian.
2220 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 2221constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 2222
04180708 2223typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 2224
2225/* Extract from an array REGS containing the (raw) register state a
2226 function return value of type TYPE, and copy that, in virtual
2227 format, into VALBUF. */
2228
2229static void
2230aarch64_extract_return_value (struct type *type, struct regcache *regs,
2231 gdb_byte *valbuf)
2232{
ac7936df 2233 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2234 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2235 int elements;
2236 struct type *fundamental_type;
07b287a0 2237
4f4aedeb
AH		 2238 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2239 &fundamental_type))
07b287a0 2240 {
4f4aedeb
AH		 2241 int len = TYPE_LENGTH (fundamental_type);
2242
2243 for (int i = 0; i < elements; i++)
2244 {
2245 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2246 /* Enough space for a full vector register. */
2247 gdb_byte buf[register_size (gdbarch, regno)];
2248 gdb_assert (len <= sizeof (buf));
4f4aedeb
AH		 2249
2250 if (aarch64_debug)
2251 {
2252 debug_printf ("read HFA or HVA return value element %d from %s\n",
2253 i + 1,
2254 gdbarch_register_name (gdbarch, regno));
2255 }
2256 regs->cooked_read (regno, buf);
07b287a0 2257
4f4aedeb
AH		 2258 memcpy (valbuf, buf, len);
2259 valbuf += len;
2260 }
07b287a0 2261 }
78134374
SM		 2262 else if (type->code () == TYPE_CODE_INT
2263 || type->code () == TYPE_CODE_CHAR
2264 || type->code () == TYPE_CODE_BOOL
2265 || type->code () == TYPE_CODE_PTR
aa006118 2266 || TYPE_IS_REFERENCE (type)
78134374 2267 || type->code () == TYPE_CODE_ENUM)
07b287a0 2268 {
6471e7d2 2269 /* If the type is a plain integer, then the access is
07b287a0
MS		 2270 straight-forward. Otherwise we have to play around a bit
2271 more. */
2272 int len = TYPE_LENGTH (type);
2273 int regno = AARCH64_X0_REGNUM;
2274 ULONGEST tmp;
2275
2276 while (len > 0)
2277 {
2278 /* By using store_unsigned_integer we avoid having to do
2279 anything special for small big-endian values. */
2280 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2281 store_unsigned_integer (valbuf,
2282 (len > X_REGISTER_SIZE
2283 ? X_REGISTER_SIZE : len), byte_order, tmp);
2284 len -= X_REGISTER_SIZE;
2285 valbuf += X_REGISTER_SIZE;
2286 }
2287 }
07b287a0
MS		 2288 else
2289 {
2290 /* For a structure or union the behaviour is as if the value had
2291 been stored to word-aligned memory and then loaded into
2292 registers with 64-bit load instruction(s). */
2293 int len = TYPE_LENGTH (type);
2294 int regno = AARCH64_X0_REGNUM;
2295 bfd_byte buf[X_REGISTER_SIZE];
2296
2297 while (len > 0)
2298 {
dca08e1f 2299 regs->cooked_read (regno++, buf);
07b287a0
MS		 2300 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2301 len -= X_REGISTER_SIZE;
2302 valbuf += X_REGISTER_SIZE;
2303 }
2304 }
2305}
2306
2307
2308/* Will a function return an aggregate type in memory or in a
2309 register? Return 0 if an aggregate type can be returned in a
2310 register, 1 if it must be returned in memory. */
2311
2312static int
2313aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2314{
f168693b 2315 type = check_typedef (type);
4f4aedeb
AH		 2316 int elements;
2317 struct type *fundamental_type;
07b287a0 2318
4f4aedeb
AH		 2319 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2320 &fundamental_type))
07b287a0 2321 {
cd635f74
YQ		 2322 /* v0-v7 are used to return values and one register is allocated
2323 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 2324 return 0;
2325 }
2326
2327 if (TYPE_LENGTH (type) > 16)
2328 {
2329 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2330 invisible reference. */
2331
2332 return 1;
2333 }
2334
2335 return 0;
2336}
2337
2338/* Write into appropriate registers a function return value of type
2339 TYPE, given in virtual format. */
2340
2341static void
2342aarch64_store_return_value (struct type *type, struct regcache *regs,
2343 const gdb_byte *valbuf)
2344{
ac7936df 2345 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2346 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2347 int elements;
2348 struct type *fundamental_type;
07b287a0 2349
4f4aedeb
AH		 2350 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2351 &fundamental_type))
07b287a0 2352 {
4f4aedeb
AH		 2353 int len = TYPE_LENGTH (fundamental_type);
2354
2355 for (int i = 0; i < elements; i++)
2356 {
2357 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2358 /* Enough space for a full vector register. */
2359 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2360 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb
AH		 2361
2362 if (aarch64_debug)
2363 {
2364 debug_printf ("write HFA or HVA return value element %d to %s\n",
2365 i + 1,
2366 gdbarch_register_name (gdbarch, regno));
2367 }
07b287a0 2368
4f4aedeb
AH		 2369 memcpy (tmpbuf, valbuf,
2370 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2371 regs->cooked_write (regno, tmpbuf);
2372 valbuf += len;
2373 }
07b287a0 2374 }
78134374
SM		 2375 else if (type->code () == TYPE_CODE_INT
2376 || type->code () == TYPE_CODE_CHAR
2377 || type->code () == TYPE_CODE_BOOL
2378 || type->code () == TYPE_CODE_PTR
aa006118 2379 || TYPE_IS_REFERENCE (type)
78134374 2380 || type->code () == TYPE_CODE_ENUM)
07b287a0
MS		 2381 {
2382 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2383 {
2384 /* Values of one word or less are zero/sign-extended and
2385 returned in r0. */
2386 bfd_byte tmpbuf[X_REGISTER_SIZE];
2387 LONGEST val = unpack_long (type, valbuf);
2388
2389 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2390 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2391 }
2392 else
2393 {
2394 /* Integral values greater than one word are stored in
2395 consecutive registers starting with r0. This will always
2396 be a multiple of the regiser size. */
2397 int len = TYPE_LENGTH (type);
2398 int regno = AARCH64_X0_REGNUM;
2399
2400 while (len > 0)
2401 {
b66f5587 2402 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2403 len -= X_REGISTER_SIZE;
2404 valbuf += X_REGISTER_SIZE;
2405 }
2406 }
2407 }
07b287a0
MS		 2408 else
2409 {
2410 /* For a structure or union the behaviour is as if the value had
2411 been stored to word-aligned memory and then loaded into
2412 registers with 64-bit load instruction(s). */
2413 int len = TYPE_LENGTH (type);
2414 int regno = AARCH64_X0_REGNUM;
2415 bfd_byte tmpbuf[X_REGISTER_SIZE];
2416
2417 while (len > 0)
2418 {
2419 memcpy (tmpbuf, valbuf,
2420 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2421 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2422 len -= X_REGISTER_SIZE;
2423 valbuf += X_REGISTER_SIZE;
2424 }
2425 }
2426}
2427
2428/* Implement the "return_value" gdbarch method. */
2429
2430static enum return_value_convention
2431aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2432 struct type *valtype, struct regcache *regcache,
2433 gdb_byte *readbuf, const gdb_byte *writebuf)
2434{
07b287a0 2435
78134374
SM		 2436 if (valtype->code () == TYPE_CODE_STRUCT
2437 || valtype->code () == TYPE_CODE_UNION
2438 || valtype->code () == TYPE_CODE_ARRAY)
07b287a0
MS		 2439 {
2440 if (aarch64_return_in_memory (gdbarch, valtype))
2441 {
2442 if (aarch64_debug)
b277c936 2443 debug_printf ("return value in memory\n");
07b287a0
MS		 2444 return RETURN_VALUE_STRUCT_CONVENTION;
2445 }
2446 }
2447
2448 if (writebuf)
2449 aarch64_store_return_value (valtype, regcache, writebuf);
2450
2451 if (readbuf)
2452 aarch64_extract_return_value (valtype, regcache, readbuf);
2453
2454 if (aarch64_debug)
b277c936 2455 debug_printf ("return value in registers\n");
07b287a0
MS		 2456
2457 return RETURN_VALUE_REGISTER_CONVENTION;
2458}
2459
2460/* Implement the "get_longjmp_target" gdbarch method. */
2461
2462static int
2463aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2464{
2465 CORE_ADDR jb_addr;
2466 gdb_byte buf[X_REGISTER_SIZE];
2467 struct gdbarch *gdbarch = get_frame_arch (frame);
2468 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2469 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2470
2471 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2472
2473 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2474 X_REGISTER_SIZE))
2475 return 0;
2476
2477 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2478 return 1;
2479}
ea873d8e
PL		 2480
2481/* Implement the "gen_return_address" gdbarch method. */
2482
2483static void
2484aarch64_gen_return_address (struct gdbarch *gdbarch,
2485 struct agent_expr *ax, struct axs_value *value,
2486 CORE_ADDR scope)
2487{
2488 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2489 value->kind = axs_lvalue_register;
2490 value->u.reg = AARCH64_LR_REGNUM;
2491}
07b287a0
MS		 2492\f
2493
2494/* Return the pseudo register name corresponding to register regnum. */
2495
2496static const char *
2497aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2498{
63bad7b6
AH		 2499 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2500
07b287a0
MS		 2501 static const char *const q_name[] =
2502 {
2503 "q0", "q1", "q2", "q3",
2504 "q4", "q5", "q6", "q7",
2505 "q8", "q9", "q10", "q11",
2506 "q12", "q13", "q14", "q15",
2507 "q16", "q17", "q18", "q19",
2508 "q20", "q21", "q22", "q23",
2509 "q24", "q25", "q26", "q27",
2510 "q28", "q29", "q30", "q31",
2511 };
2512
2513 static const char *const d_name[] =
2514 {
2515 "d0", "d1", "d2", "d3",
2516 "d4", "d5", "d6", "d7",
2517 "d8", "d9", "d10", "d11",
2518 "d12", "d13", "d14", "d15",
2519 "d16", "d17", "d18", "d19",
2520 "d20", "d21", "d22", "d23",
2521 "d24", "d25", "d26", "d27",
2522 "d28", "d29", "d30", "d31",
2523 };
2524
2525 static const char *const s_name[] =
2526 {
2527 "s0", "s1", "s2", "s3",
2528 "s4", "s5", "s6", "s7",
2529 "s8", "s9", "s10", "s11",
2530 "s12", "s13", "s14", "s15",
2531 "s16", "s17", "s18", "s19",
2532 "s20", "s21", "s22", "s23",
2533 "s24", "s25", "s26", "s27",
2534 "s28", "s29", "s30", "s31",
2535 };
2536
2537 static const char *const h_name[] =
2538 {
2539 "h0", "h1", "h2", "h3",
2540 "h4", "h5", "h6", "h7",
2541 "h8", "h9", "h10", "h11",
2542 "h12", "h13", "h14", "h15",
2543 "h16", "h17", "h18", "h19",
2544 "h20", "h21", "h22", "h23",
2545 "h24", "h25", "h26", "h27",
2546 "h28", "h29", "h30", "h31",
2547 };
2548
2549 static const char *const b_name[] =
2550 {
2551 "b0", "b1", "b2", "b3",
2552 "b4", "b5", "b6", "b7",
2553 "b8", "b9", "b10", "b11",
2554 "b12", "b13", "b14", "b15",
2555 "b16", "b17", "b18", "b19",
2556 "b20", "b21", "b22", "b23",
2557 "b24", "b25", "b26", "b27",
2558 "b28", "b29", "b30", "b31",
2559 };
2560
34dcc7cf 2561 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2562
34dcc7cf
AH		 2563 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2564 return q_name[p_regnum - AARCH64_Q0_REGNUM];
07b287a0 2565
34dcc7cf
AH		 2566 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2567 return d_name[p_regnum - AARCH64_D0_REGNUM];
07b287a0 2568
34dcc7cf
AH		 2569 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2570 return s_name[p_regnum - AARCH64_S0_REGNUM];
07b287a0 2571
34dcc7cf
AH		 2572 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2573 return h_name[p_regnum - AARCH64_H0_REGNUM];
07b287a0 2574
34dcc7cf
AH		 2575 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2576 return b_name[p_regnum - AARCH64_B0_REGNUM];
07b287a0 2577
63bad7b6
AH		 2578 if (tdep->has_sve ())
2579 {
2580 static const char *const sve_v_name[] =
2581 {
2582 "v0", "v1", "v2", "v3",
2583 "v4", "v5", "v6", "v7",
2584 "v8", "v9", "v10", "v11",
2585 "v12", "v13", "v14", "v15",
2586 "v16", "v17", "v18", "v19",
2587 "v20", "v21", "v22", "v23",
2588 "v24", "v25", "v26", "v27",
2589 "v28", "v29", "v30", "v31",
2590 };
2591
34dcc7cf
AH		 2592 if (p_regnum >= AARCH64_SVE_V0_REGNUM
2593 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2594 return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
63bad7b6
AH		 2595 }
2596
34dcc7cf
AH		 2597 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2598 prevents it from being read by methods such as
2599 mi_cmd_trace_frame_collected. */
2600 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2601 return "";
2602
07b287a0
MS		 2603 internal_error (__FILE__, __LINE__,
2604 _("aarch64_pseudo_register_name: bad register number %d"),
34dcc7cf 2605 p_regnum);
07b287a0
MS		 2606}
2607
2608/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2609
2610static struct type *
2611aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2612{
63bad7b6
AH		 2613 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2614
34dcc7cf 2615 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2616
34dcc7cf 2617 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0
MS		 2618 return aarch64_vnq_type (gdbarch);
2619
34dcc7cf 2620 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2621 return aarch64_vnd_type (gdbarch);
2622
34dcc7cf 2623 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2624 return aarch64_vns_type (gdbarch);
2625
34dcc7cf 2626 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0
MS		 2627 return aarch64_vnh_type (gdbarch);
2628
34dcc7cf 2629 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0
MS		 2630 return aarch64_vnb_type (gdbarch);
2631
34dcc7cf
AH		 2632 if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2633 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6
AH		 2634 return aarch64_vnv_type (gdbarch);
2635
34dcc7cf
AH		 2636 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2637 return builtin_type (gdbarch)->builtin_uint64;
2638
07b287a0
MS		 2639 internal_error (__FILE__, __LINE__,
2640 _("aarch64_pseudo_register_type: bad register number %d"),
34dcc7cf 2641 p_regnum);
07b287a0
MS		 2642}
2643
2644/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2645
2646static int
2647aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2648 struct reggroup *group)
2649{
63bad7b6
AH		 2650 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2651
34dcc7cf 2652 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2653
34dcc7cf 2654 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0 2655 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2656 else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2657 return (group == all_reggroup || group == vector_reggroup
2658 || group == float_reggroup);
34dcc7cf 2659 else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2660 return (group == all_reggroup || group == vector_reggroup
2661 || group == float_reggroup);
34dcc7cf 2662 else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0 2663 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2664 else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0 2665 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2666 else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2667 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6 2668 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2669 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2670 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2671 return 0;
07b287a0
MS		 2672
2673 return group == all_reggroup;
2674}
2675
3c5cd5c3
AH		 2676/* Helper for aarch64_pseudo_read_value. */
2677
2678static struct value *
63bad7b6
AH		 2679aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2680 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2681 int regsize, struct value *result_value)
2682{
3c5cd5c3
AH		 2683 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2684
63bad7b6
AH		 2685 /* Enough space for a full vector register. */
2686 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2687 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2688
3c5cd5c3
AH		 2689 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2690 mark_value_bytes_unavailable (result_value, 0,
2691 TYPE_LENGTH (value_type (result_value)));
2692 else
2693 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2694
3c5cd5c3
AH		 2695 return result_value;
2696 }
2697
07b287a0
MS		 2698/* Implement the "pseudo_register_read_value" gdbarch method. */
2699
2700static struct value *
3c5cd5c3 2701aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2702 int regnum)
2703{
63bad7b6 2704 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2705 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2706
07b287a0
MS		 2707 VALUE_LVAL (result_value) = lval_register;
2708 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2709
2710 regnum -= gdbarch_num_regs (gdbarch);
2711
2712 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2713 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2714 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2715 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2716
2717 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2718 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2719 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2720 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2721
2722 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2723 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2724 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2725 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2726
2727 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2728 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2729 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2730 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2731
2732 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2733 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2734 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2735 B_REGISTER_SIZE, result_value);
07b287a0 2736
63bad7b6
AH		 2737 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2738 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2739 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2740 regnum - AARCH64_SVE_V0_REGNUM,
2741 V_REGISTER_SIZE, result_value);
2742
07b287a0
MS		 2743 gdb_assert_not_reached ("regnum out of bound");
2744}
2745
3c5cd5c3 2746/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2747
2748static void
63bad7b6
AH		 2749aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2750 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2751{
3c5cd5c3 2752 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2753
63bad7b6
AH		 2754 /* Enough space for a full vector register. */
2755 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2756 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2757
07b287a0
MS		 2758 /* Ensure the register buffer is zero, we want gdb writes of the
2759 various 'scalar' pseudo registers to behavior like architectural
2760 writes, register width bytes are written the remainder are set to
2761 zero. */
63bad7b6 2762 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2763
3c5cd5c3
AH		 2764 memcpy (reg_buf, buf, regsize);
2765 regcache->raw_write (v_regnum, reg_buf);
2766}
2767
2768/* Implement the "pseudo_register_write" gdbarch method. */
2769
2770static void
2771aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2772 int regnum, const gdb_byte *buf)
2773{
63bad7b6 2774 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2775 regnum -= gdbarch_num_regs (gdbarch);
2776
2777 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2778 return aarch64_pseudo_write_1 (gdbarch, regcache,
2779 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2780 buf);
07b287a0
MS		 2781
2782 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2783 return aarch64_pseudo_write_1 (gdbarch, regcache,
2784 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2785 buf);
07b287a0
MS		 2786
2787 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2788 return aarch64_pseudo_write_1 (gdbarch, regcache,
2789 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2790 buf);
07b287a0
MS		 2791
2792 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2793 return aarch64_pseudo_write_1 (gdbarch, regcache,
2794 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2795 buf);
07b287a0
MS		 2796
2797 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2798 return aarch64_pseudo_write_1 (gdbarch, regcache,
2799 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2800 buf);
2801
2802 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2803 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2804 return aarch64_pseudo_write_1 (gdbarch, regcache,
2805 regnum - AARCH64_SVE_V0_REGNUM,
2806 V_REGISTER_SIZE, buf);
07b287a0
MS		 2807
2808 gdb_assert_not_reached ("regnum out of bound");
2809}
2810
07b287a0
MS		 2811/* Callback function for user_reg_add. */
2812
2813static struct value *
2814value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2815{
9a3c8263 2816 const int *reg_p = (const int *) baton;
07b287a0
MS		 2817
2818 return value_of_register (*reg_p, frame);
2819}
2820\f
2821
9404b58f
KM		 2822/* Implement the "software_single_step" gdbarch method, needed to
2823 single step through atomic sequences on AArch64. */
2824
a0ff9e1a 2825static std::vector<CORE_ADDR>
f5ea389a 2826aarch64_software_single_step (struct regcache *regcache)
9404b58f 2827{
ac7936df 2828 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2829 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2830 const int insn_size = 4;
2831 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2832 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2833 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2834 CORE_ADDR loc = pc;
2835 CORE_ADDR closing_insn = 0;
2836 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2837 byte_order_for_code);
2838 int index;
2839 int insn_count;
2840 int bc_insn_count = 0; /* Conditional branch instruction count. */
2841 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2842 aarch64_inst inst;
2843
561a72d4 2844 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2845 return {};
9404b58f
KM		 2846
2847 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2848 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2849 return {};
9404b58f
KM		 2850
2851 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2852 {
9404b58f
KM		 2853 loc += insn_size;
2854 insn = read_memory_unsigned_integer (loc, insn_size,
2855 byte_order_for_code);
2856
561a72d4 2857 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2858 return {};
9404b58f 2859 /* Check if the instruction is a conditional branch. */
f77ee802 2860 if (inst.opcode->iclass == condbranch)
9404b58f 2861 {
f77ee802
YQ		 2862 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2863
9404b58f 2864 if (bc_insn_count >= 1)
a0ff9e1a 2865 return {};
9404b58f
KM		 2866
2867 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2868 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2869
2870 bc_insn_count++;
2871 last_breakpoint++;
2872 }
2873
2874 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2875 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2876 {
2877 closing_insn = loc;
2878 break;
2879 }
2880 }
2881
2882 /* We didn't find a closing Store Exclusive instruction, fall back. */
2883 if (!closing_insn)
a0ff9e1a 2884 return {};
9404b58f
KM		 2885
2886 /* Insert breakpoint after the end of the atomic sequence. */
2887 breaks[0] = loc + insn_size;
2888
2889 /* Check for duplicated breakpoints, and also check that the second
2890 breakpoint is not within the atomic sequence. */
2891 if (last_breakpoint
2892 && (breaks[1] == breaks[0]
2893 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2894 last_breakpoint = 0;
2895
a0ff9e1a
SM		 2896 std::vector<CORE_ADDR> next_pcs;
2897
9404b58f
KM		 2898 /* Insert the breakpoint at the end of the sequence, and one at the
2899 destination of the conditional branch, if it exists. */
2900 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2901 next_pcs.push_back (breaks[index]);
9404b58f 2902
93f9a11f 2903 return next_pcs;
9404b58f
KM		 2904}
2905
cfba9872 2906struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2907{
2908 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2909 is being displaced stepping. */
f0c702d4 2910 bool cond = false;
b6542f81 2911
0c271889
LM		 2912 /* PC adjustment offset after displaced stepping. If 0, then we don't
2913 write the PC back, assuming the PC is already the right address. */
cfba9872 2914 int32_t pc_adjust = 0;
b6542f81
YQ		 2915};
2916
2917/* Data when visiting instructions for displaced stepping. */
2918
2919struct aarch64_displaced_step_data
2920{
2921 struct aarch64_insn_data base;
2922
2923 /* The address where the instruction will be executed at. */
2924 CORE_ADDR new_addr;
2925 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
e935475c 2926 uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
b6542f81
YQ		 2927 /* Number of instructions in INSN_BUF. */
2928 unsigned insn_count;
2929 /* Registers when doing displaced stepping. */
2930 struct regcache *regs;
2931
cfba9872 2932 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2933};
2934
2935/* Implementation of aarch64_insn_visitor method "b". */
2936
2937static void
2938aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2939 struct aarch64_insn_data *data)
2940{
2941 struct aarch64_displaced_step_data *dsd
2942 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2943 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2944
2945 if (can_encode_int32 (new_offset, 28))
2946 {
2947 /* Emit B rather than BL, because executing BL on a new address
2948 will get the wrong address into LR. In order to avoid this,
2949 we emit B, and update LR if the instruction is BL. */
2950 emit_b (dsd->insn_buf, 0, new_offset);
2951 dsd->insn_count++;
2952 }
2953 else
2954 {
2955 /* Write NOP. */
2956 emit_nop (dsd->insn_buf);
2957 dsd->insn_count++;
2958 dsd->dsc->pc_adjust = offset;
2959 }
2960
2961 if (is_bl)
2962 {
2963 /* Update LR. */
2964 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2965 data->insn_addr + 4);
2966 }
2967}
2968
2969/* Implementation of aarch64_insn_visitor method "b_cond". */
2970
2971static void
2972aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2973 struct aarch64_insn_data *data)
2974{
2975 struct aarch64_displaced_step_data *dsd
2976 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2977
2978 /* GDB has to fix up PC after displaced step this instruction
2979 differently according to the condition is true or false. Instead
2980 of checking COND against conditional flags, we can use
2981 the following instructions, and GDB can tell how to fix up PC
2982 according to the PC value.
2983
2984 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2985 INSN1 ;
2986 TAKEN:
2987 INSN2
2988 */
2989
2990 emit_bcond (dsd->insn_buf, cond, 8);
f0c702d4 2991 dsd->dsc->cond = true;
b6542f81
YQ		 2992 dsd->dsc->pc_adjust = offset;
2993 dsd->insn_count = 1;
2994}
2995
2996/* Dynamically allocate a new register. If we know the register
2997 statically, we should make it a global as above instead of using this
2998 helper function. */
2999
3000static struct aarch64_register
3001aarch64_register (unsigned num, int is64)
3002{
3003 return (struct aarch64_register) { num, is64 };
3004}
3005
3006/* Implementation of aarch64_insn_visitor method "cb". */
3007
3008static void
3009aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
3010 const unsigned rn, int is64,
3011 struct aarch64_insn_data *data)
3012{
3013 struct aarch64_displaced_step_data *dsd
3014 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 3015
3016 /* The offset is out of range for a compare and branch
3017 instruction. We can use the following instructions instead:
3018
3019 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
3020 INSN1 ;
3021 TAKEN:
3022 INSN2
3023 */
3024 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
3025 dsd->insn_count = 1;
f0c702d4 3026 dsd->dsc->cond = true;
b6542f81
YQ		 3027 dsd->dsc->pc_adjust = offset;
3028}
3029
3030/* Implementation of aarch64_insn_visitor method "tb". */
3031
3032static void
3033aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
3034 const unsigned rt, unsigned bit,
3035 struct aarch64_insn_data *data)
3036{
3037 struct aarch64_displaced_step_data *dsd
3038 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 3039
3040 /* The offset is out of range for a test bit and branch
3041 instruction We can use the following instructions instead:
3042
3043 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
3044 INSN1 ;
3045 TAKEN:
3046 INSN2
3047
3048 */
3049 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
3050 dsd->insn_count = 1;
f0c702d4 3051 dsd->dsc->cond = true;
b6542f81
YQ		 3052 dsd->dsc->pc_adjust = offset;
3053}
3054
3055/* Implementation of aarch64_insn_visitor method "adr". */
3056
3057static void
3058aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
3059 const int is_adrp, struct aarch64_insn_data *data)
3060{
3061 struct aarch64_displaced_step_data *dsd
3062 = (struct aarch64_displaced_step_data *) data;
3063 /* We know exactly the address the ADR{P,} instruction will compute.
3064 We can just write it to the destination register. */
3065 CORE_ADDR address = data->insn_addr + offset;
3066
3067 if (is_adrp)
3068 {
3069 /* Clear the lower 12 bits of the offset to get the 4K page. */
3070 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
3071 address & ~0xfff);
3072 }
3073 else
3074 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
3075 address);
3076
3077 dsd->dsc->pc_adjust = 4;
3078 emit_nop (dsd->insn_buf);
3079 dsd->insn_count = 1;
3080}
3081
3082/* Implementation of aarch64_insn_visitor method "ldr_literal". */
3083
3084static void
3085aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
3086 const unsigned rt, const int is64,
3087 struct aarch64_insn_data *data)
3088{
3089 struct aarch64_displaced_step_data *dsd
3090 = (struct aarch64_displaced_step_data *) data;
3091 CORE_ADDR address = data->insn_addr + offset;
3092 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
3093
3094 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
3095 address);
3096
3097 if (is_sw)
3098 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
3099 aarch64_register (rt, 1), zero);
3100 else
3101 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
3102 aarch64_register (rt, 1), zero);
3103
3104 dsd->dsc->pc_adjust = 4;
3105}
3106
3107/* Implementation of aarch64_insn_visitor method "others". */
3108
3109static void
3110aarch64_displaced_step_others (const uint32_t insn,
3111 struct aarch64_insn_data *data)
3112{
3113 struct aarch64_displaced_step_data *dsd
3114 = (struct aarch64_displaced_step_data *) data;
3115
e1c587c3 3116 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 3117 dsd->insn_count = 1;
3118
3119 if ((insn & 0xfffffc1f) == 0xd65f0000)
3120 {
3121 /* RET */
3122 dsd->dsc->pc_adjust = 0;
3123 }
3124 else
3125 dsd->dsc->pc_adjust = 4;
3126}
3127
3128static const struct aarch64_insn_visitor visitor =
3129{
3130 aarch64_displaced_step_b,
3131 aarch64_displaced_step_b_cond,
3132 aarch64_displaced_step_cb,
3133 aarch64_displaced_step_tb,
3134 aarch64_displaced_step_adr,
3135 aarch64_displaced_step_ldr_literal,
3136 aarch64_displaced_step_others,
3137};
3138
3139/* Implement the "displaced_step_copy_insn" gdbarch method. */
3140
fdb61c6c 3141displaced_step_closure_up
b6542f81
YQ		 3142aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
3143 CORE_ADDR from, CORE_ADDR to,
3144 struct regcache *regs)
3145{
b6542f81
YQ		 3146 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3147 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
3148 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 3149 aarch64_inst inst;
3150
561a72d4 3151 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 3152 return NULL;
b6542f81
YQ		 3153
3154 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 3155 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 3156 {
3157 /* We can't displaced step atomic sequences. */
3158 return NULL;
3159 }
3160
cfba9872
SM		 3161 std::unique_ptr<aarch64_displaced_step_closure> dsc
3162 (new aarch64_displaced_step_closure);
b6542f81
YQ		 3163 dsd.base.insn_addr = from;
3164 dsd.new_addr = to;
3165 dsd.regs = regs;
cfba9872 3166 dsd.dsc = dsc.get ();
034f1a81 3167 dsd.insn_count = 0;
b6542f81
YQ		 3168 aarch64_relocate_instruction (insn, &visitor,
3169 (struct aarch64_insn_data *) &dsd);
e935475c 3170 gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS);
b6542f81
YQ		 3171
3172 if (dsd.insn_count != 0)
3173 {
3174 int i;
3175
3176 /* Instruction can be relocated to scratch pad. Copy
3177 relocated instruction(s) there. */
3178 for (i = 0; i < dsd.insn_count; i++)
3179 {
3180 if (debug_displaced)
3181 {
3182 debug_printf ("displaced: writing insn ");
3183 debug_printf ("%.8x", dsd.insn_buf[i]);
3184 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
3185 }
3186 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
3187 (ULONGEST) dsd.insn_buf[i]);
3188 }
3189 }
3190 else
3191 {
b6542f81
YQ		 3192 dsc = NULL;
3193 }
3194
6d0cf446
BE		 3195 /* This is a work around for a problem with g++ 4.8. */
3196 return displaced_step_closure_up (dsc.release ());
b6542f81
YQ		 3197}
3198
3199/* Implement the "displaced_step_fixup" gdbarch method. */
3200
3201void
3202aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 3203 struct displaced_step_closure *dsc_,
b6542f81
YQ		 3204 CORE_ADDR from, CORE_ADDR to,
3205 struct regcache *regs)
3206{
cfba9872
SM		 3207 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
3208
0c271889
LM		 3209 ULONGEST pc;
3210
3211 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
3212
1ab139e5
LM		 3213 if (debug_displaced)
3214 debug_printf ("Displaced: PC after stepping: %s (was %s).\n",
3215 paddress (gdbarch, pc), paddress (gdbarch, to));
3216
b6542f81
YQ		 3217 if (dsc->cond)
3218 {
1ab139e5
LM		 3219 if (debug_displaced)
3220 debug_printf ("Displaced: [Conditional] pc_adjust before: %d\n",
3221 dsc->pc_adjust);
3222
b6542f81
YQ		 3223 if (pc - to == 8)
3224 {
3225 /* Condition is true. */
3226 }
3227 else if (pc - to == 4)
3228 {
3229 /* Condition is false. */
3230 dsc->pc_adjust = 4;
3231 }
3232 else
3233 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
1ab139e5
LM		 3234
3235 if (debug_displaced)
3236 debug_printf ("Displaced: [Conditional] pc_adjust after: %d\n",
3237 dsc->pc_adjust);
b6542f81
YQ		 3238 }
3239
1ab139e5
LM		 3240 if (debug_displaced)
3241 debug_printf ("Displaced: %s PC by %d\n",
3242 dsc->pc_adjust? "adjusting" : "not adjusting",
3243 dsc->pc_adjust);
3244
3245
b6542f81
YQ		 3246 if (dsc->pc_adjust != 0)
3247 {
0c271889
LM		 3248 /* Make sure the previous instruction was executed (that is, the PC
3249 has changed). If the PC didn't change, then discard the adjustment
3250 offset. Otherwise we may skip an instruction before its execution
3251 took place. */
3252 if ((pc - to) == 0)
1ab139e5
LM		 3253 {
3254 if (debug_displaced)
3255 debug_printf ("Displaced: PC did not move. Discarding PC "
3256 "adjustment.\n");
3257 dsc->pc_adjust = 0;
3258 }
0c271889 3259
b6542f81
YQ		 3260 if (debug_displaced)
3261 {
1ab139e5 3262 debug_printf ("Displaced: fixup: set PC to %s:%d\n",
b6542f81
YQ		 3263 paddress (gdbarch, from), dsc->pc_adjust);
3264 }
3265 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
3266 from + dsc->pc_adjust);
3267 }
3268}
3269
3270/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3271
3272int
3273aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
3274 struct displaced_step_closure *closure)
3275{
3276 return 1;
3277}
3278
95228a0d
AH		 3279/* Get the correct target description for the given VQ value.
3280 If VQ is zero then it is assumed SVE is not supported.
3281 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 3282
3283const target_desc *
6dc0ebde 3284aarch64_read_description (uint64_t vq, bool pauth_p)
da434ccb 3285{
95228a0d 3286 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 3287 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 3288 AARCH64_MAX_SVE_VQ);
3289
6dc0ebde 3290 struct target_desc *tdesc = tdesc_aarch64_list[vq][pauth_p];
da434ccb 3291
95228a0d
AH		 3292 if (tdesc == NULL)
3293 {
6dc0ebde
AH		 3294 tdesc = aarch64_create_target_description (vq, pauth_p);
3295 tdesc_aarch64_list[vq][pauth_p] = tdesc;
95228a0d 3296 }
da434ccb 3297
95228a0d 3298 return tdesc;
da434ccb
AH		 3299}
3300
ba2d2bb2
AH		 3301/* Return the VQ used when creating the target description TDESC. */
3302
1332a140 3303static uint64_t
ba2d2bb2
AH		 3304aarch64_get_tdesc_vq (const struct target_desc *tdesc)
3305{
3306 const struct tdesc_feature *feature_sve;
3307
3308 if (!tdesc_has_registers (tdesc))
3309 return 0;
3310
3311 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3312
3313 if (feature_sve == nullptr)
3314 return 0;
3315
12863263
AH		 3316 uint64_t vl = tdesc_register_bitsize (feature_sve,
3317 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 3318 return sve_vq_from_vl (vl);
3319}
3320
0ef8a082
AH		 3321/* Add all the expected register sets into GDBARCH. */
3322
3323static void
3324aarch64_add_reggroups (struct gdbarch *gdbarch)
3325{
3326 reggroup_add (gdbarch, general_reggroup);
3327 reggroup_add (gdbarch, float_reggroup);
3328 reggroup_add (gdbarch, system_reggroup);
3329 reggroup_add (gdbarch, vector_reggroup);
3330 reggroup_add (gdbarch, all_reggroup);
3331 reggroup_add (gdbarch, save_reggroup);
3332 reggroup_add (gdbarch, restore_reggroup);
3333}
ba2d2bb2 3334
76bed0fd
AH		 3335/* Implement the "cannot_store_register" gdbarch method. */
3336
3337static int
3338aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum)
3339{
3340 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3341
3342 if (!tdep->has_pauth ())
3343 return 0;
3344
3345 /* Pointer authentication registers are read-only. */
3346 return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
3347 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base));
3348}
3349
07b287a0
MS		 3350/* Initialize the current architecture based on INFO. If possible,
3351 re-use an architecture from ARCHES, which is a list of
3352 architectures already created during this debugging session.
3353
3354 Called e.g. at program startup, when reading a core file, and when
3355 reading a binary file. */
3356
3357static struct gdbarch *
3358aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3359{
ccb8d7e8 3360 const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve;
76bed0fd 3361 const struct tdesc_feature *feature_pauth;
ccb8d7e8
AH		 3362 bool valid_p = true;
3363 int i, num_regs = 0, num_pseudo_regs = 0;
3364 int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
3365
4da037ef
AH		 3366 /* Use the vector length passed via the target info. Here -1 is used for no
3367 SVE, and 0 is unset. If unset then use the vector length from the existing
3368 tdesc. */
3369 uint64_t vq = 0;
3370 if (info.id == (int *) -1)
3371 vq = 0;
3372 else if (info.id != 0)
3373 vq = (uint64_t) info.id;
3374 else
3375 vq = aarch64_get_tdesc_vq (info.target_desc);
3376
3377 if (vq > AARCH64_MAX_SVE_VQ)
596179f7
SDJ		 3378 internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"),
3379 pulongest (vq), AARCH64_MAX_SVE_VQ);
4da037ef 3380
ccb8d7e8
AH		 3381 /* If there is already a candidate, use it. */
3382 for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
3383 best_arch != nullptr;
3384 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3385 {
3386 struct gdbarch_tdep *tdep = gdbarch_tdep (best_arch->gdbarch);
4da037ef 3387 if (tdep && tdep->vq == vq)
ccb8d7e8
AH		 3388 return best_arch->gdbarch;
3389 }
07b287a0 3390
4da037ef
AH		 3391 /* Ensure we always have a target descriptor, and that it is for the given VQ
3392 value. */
ccb8d7e8 3393 const struct target_desc *tdesc = info.target_desc;
4da037ef
AH		 3394 if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc))
3395 tdesc = aarch64_read_description (vq, false);
07b287a0
MS		 3396 gdb_assert (tdesc);
3397
ccb8d7e8 3398 feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
ba2d2bb2
AH		 3399 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
3400 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
76bed0fd 3401 feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
07b287a0 3402
ccb8d7e8
AH		 3403 if (feature_core == nullptr)
3404 return nullptr;
07b287a0 3405
ccb8d7e8 3406 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
07b287a0 3407
ba2d2bb2 3408 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 3409 and allocate their numbers. */
3410 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 3411 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
3412 AARCH64_X0_REGNUM + i,
3413 aarch64_r_register_names[i]);
07b287a0
MS		 3414
3415 num_regs = AARCH64_X0_REGNUM + i;
3416
ba2d2bb2 3417 /* Add the V registers. */
ccb8d7e8 3418 if (feature_fpu != nullptr)
07b287a0 3419 {
ccb8d7e8 3420 if (feature_sve != nullptr)
ba2d2bb2
AH		 3421 error (_("Program contains both fpu and SVE features."));
3422
3423 /* Validate the description provides the mandatory V registers
3424 and allocate their numbers. */
07b287a0 3425 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 3426 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
3427 AARCH64_V0_REGNUM + i,
3428 aarch64_v_register_names[i]);
07b287a0
MS		 3429
3430 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 3431 }
07b287a0 3432
ba2d2bb2 3433 /* Add the SVE registers. */
ccb8d7e8 3434 if (feature_sve != nullptr)
ba2d2bb2
AH		 3435 {
3436 /* Validate the description provides the mandatory SVE registers
3437 and allocate their numbers. */
3438 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3439 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3440 AARCH64_SVE_Z0_REGNUM + i,
3441 aarch64_sve_register_names[i]);
3442
3443 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3444 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3445 }
3446
ccb8d7e8 3447 if (feature_fpu != nullptr || feature_sve != nullptr)
ba2d2bb2 3448 {
07b287a0
MS		 3449 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3450 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3451 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3452 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3453 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3454 }
3455
76bed0fd
AH		 3456 /* Add the pauth registers. */
3457 if (feature_pauth != NULL)
3458 {
3459 first_pauth_regnum = num_regs;
34dcc7cf 3460 pauth_ra_state_offset = num_pseudo_regs;
76bed0fd
AH		 3461 /* Validate the descriptor provides the mandatory PAUTH registers and
3462 allocate their numbers. */
3463 for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
3464 valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data,
3465 first_pauth_regnum + i,
3466 aarch64_pauth_register_names[i]);
3467
3468 num_regs += i;
34dcc7cf 3469 num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
76bed0fd
AH		 3470 }
3471
07b287a0
MS		 3472 if (!valid_p)
3473 {
3474 tdesc_data_cleanup (tdesc_data);
ccb8d7e8 3475 return nullptr;
07b287a0
MS		 3476 }
3477
3478 /* AArch64 code is always little-endian. */
3479 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3480
ccb8d7e8
AH		 3481 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
3482 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
07b287a0
MS		 3483
3484 /* This should be low enough for everything. */
3485 tdep->lowest_pc = 0x20;
3486 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3487 tdep->jb_elt_size = 8;
4da037ef 3488 tdep->vq = vq;
76bed0fd 3489 tdep->pauth_reg_base = first_pauth_regnum;
34dcc7cf
AH		 3490 tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
3491 : pauth_ra_state_offset + num_regs;
3492
07b287a0
MS		 3493 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3494 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3495
07b287a0
MS		 3496 /* Advance PC across function entry code. */
3497 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3498
3499 /* The stack grows downward. */
3500 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3501
3502 /* Breakpoint manipulation. */
04180708
YQ		 3503 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3504 aarch64_breakpoint::kind_from_pc);
3505 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3506 aarch64_breakpoint::bp_from_kind);
07b287a0 3507 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3508 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3509
3510 /* Information about registers, etc. */
3511 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3512 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3513 set_gdbarch_num_regs (gdbarch, num_regs);
3514
3515 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3516 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3517 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3518 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3519 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3520 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3521 aarch64_pseudo_register_reggroup_p);
76bed0fd 3522 set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register);
07b287a0
MS		 3523
3524 /* ABI */
3525 set_gdbarch_short_bit (gdbarch, 16);
3526 set_gdbarch_int_bit (gdbarch, 32);
3527 set_gdbarch_float_bit (gdbarch, 32);
3528 set_gdbarch_double_bit (gdbarch, 64);
3529 set_gdbarch_long_double_bit (gdbarch, 128);
3530 set_gdbarch_long_bit (gdbarch, 64);
3531 set_gdbarch_long_long_bit (gdbarch, 64);
3532 set_gdbarch_ptr_bit (gdbarch, 64);
3533 set_gdbarch_char_signed (gdbarch, 0);
53375380 3534 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3535 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3536 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3537 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
b907456c 3538 set_gdbarch_type_align (gdbarch, aarch64_type_align);
07b287a0
MS		 3539
3540 /* Internal <-> external register number maps. */
3541 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3542
3543 /* Returning results. */
3544 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3545
3546 /* Disassembly. */
3547 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3548
3549 /* Virtual tables. */
3550 set_gdbarch_vbit_in_delta (gdbarch, 1);
3551
0ef8a082
AH		 3552 /* Register architecture. */
3553 aarch64_add_reggroups (gdbarch);
3554
07b287a0
MS		 3555 /* Hook in the ABI-specific overrides, if they have been registered. */
3556 info.target_desc = tdesc;
0dba2a6c 3557 info.tdesc_data = tdesc_data;
07b287a0
MS		 3558 gdbarch_init_osabi (info, gdbarch);
3559
3560 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
11e1b75f
AH		 3561 /* Register DWARF CFA vendor handler. */
3562 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
3563 aarch64_execute_dwarf_cfa_vendor_op);
07b287a0 3564
5133a315
LM		 3565 /* Permanent/Program breakpoint handling. */
3566 set_gdbarch_program_breakpoint_here_p (gdbarch,
3567 aarch64_program_breakpoint_here_p);
3568
07b287a0
MS		 3569 /* Add some default predicates. */
3570 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3571 dwarf2_append_unwinders (gdbarch);
3572 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3573
3574 frame_base_set_default (gdbarch, &aarch64_normal_base);
3575
3576 /* Now we have tuned the configuration, set a few final things,
3577 based on what the OS ABI has told us. */
3578
3579 if (tdep->jb_pc >= 0)
3580 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3581
ea873d8e
PL		 3582 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3583
aa7ca1bb
AH		 3584 set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags);
3585
07b287a0
MS		 3586 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3587
3588 /* Add standard register aliases. */
3589 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3590 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3591 value_of_aarch64_user_reg,
3592 &aarch64_register_aliases[i].regnum);
3593
e8bf1ce4
JB		 3594 register_aarch64_ravenscar_ops (gdbarch);
3595
07b287a0
MS		 3596 return gdbarch;
3597}
3598
3599static void
3600aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3601{
3602 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3603
3604 if (tdep == NULL)
3605 return;
3606
3607 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3608 paddress (gdbarch, tdep->lowest_pc));
3609}
3610
0d4c07af 3611#if GDB_SELF_TEST
1e2b521d
YQ		 3612namespace selftests
3613{
3614static void aarch64_process_record_test (void);
3615}
0d4c07af 3616#endif
1e2b521d 3617
6c265988 3618void _initialize_aarch64_tdep ();
07b287a0 3619void
6c265988 3620_initialize_aarch64_tdep ()
07b287a0
MS		 3621{
3622 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3623 aarch64_dump_tdep);
3624
07b287a0
MS		 3625 /* Debug this file's internals. */
3626 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3627Set AArch64 debugging."), _("\
3628Show AArch64 debugging."), _("\
3629When on, AArch64 specific debugging is enabled."),
3630 NULL,
3631 show_aarch64_debug,
3632 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3633
3634#if GDB_SELF_TEST
1526853e
SM		 3635 selftests::register_test ("aarch64-analyze-prologue",
3636 selftests::aarch64_analyze_prologue_test);
3637 selftests::register_test ("aarch64-process-record",
3638 selftests::aarch64_process_record_test);
4d9a9006 3639#endif
07b287a0 3640}
99afc88b
OJ		 3641
3642/* AArch64 process record-replay related structures, defines etc. */
3643
99afc88b
OJ		 3644#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3645 do \
3646 { \
3647 unsigned int reg_len = LENGTH; \
3648 if (reg_len) \
3649 { \
3650 REGS = XNEWVEC (uint32_t, reg_len); \
3651 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3652 } \
3653 } \
3654 while (0)
3655
3656#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3657 do \
3658 { \
3659 unsigned int mem_len = LENGTH; \
3660 if (mem_len) \
3661 { \
3662 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3663 memcpy(&MEMS->len, &RECORD_BUF[0], \
3664 sizeof(struct aarch64_mem_r) * LENGTH); \
3665 } \
3666 } \
3667 while (0)
3668
3669/* AArch64 record/replay structures and enumerations. */
3670
3671struct aarch64_mem_r
3672{
3673 uint64_t len; /* Record length. */
3674 uint64_t addr; /* Memory address. */
3675};
3676
3677enum aarch64_record_result
3678{
3679 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3680 AARCH64_RECORD_UNSUPPORTED,
3681 AARCH64_RECORD_UNKNOWN
3682};
3683
3684typedef struct insn_decode_record_t
3685{
3686 struct gdbarch *gdbarch;
3687 struct regcache *regcache;
3688 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3689 uint32_t aarch64_insn; /* Insn to be recorded. */
3690 uint32_t mem_rec_count; /* Count of memory records. */
3691 uint32_t reg_rec_count; /* Count of register records. */
3692 uint32_t *aarch64_regs; /* Registers to be recorded. */
3693 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3694} insn_decode_record;
3695
3696/* Record handler for data processing - register instructions. */
3697
3698static unsigned int
3699aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3700{
3701 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3702 uint32_t record_buf[4];
3703
3704 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3705 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3706 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3707
3708 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3709 {
3710 uint8_t setflags;
3711
3712 /* Logical (shifted register). */
3713 if (insn_bits24_27 == 0x0a)
3714 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3715 /* Add/subtract. */
3716 else if (insn_bits24_27 == 0x0b)
3717 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3718 else
3719 return AARCH64_RECORD_UNKNOWN;
3720
3721 record_buf[0] = reg_rd;
3722 aarch64_insn_r->reg_rec_count = 1;
3723 if (setflags)
3724 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3725 }
3726 else
3727 {
3728 if (insn_bits24_27 == 0x0b)
3729 {
3730 /* Data-processing (3 source). */
3731 record_buf[0] = reg_rd;
3732 aarch64_insn_r->reg_rec_count = 1;
3733 }
3734 else if (insn_bits24_27 == 0x0a)
3735 {
3736 if (insn_bits21_23 == 0x00)
3737 {
3738 /* Add/subtract (with carry). */
3739 record_buf[0] = reg_rd;
3740 aarch64_insn_r->reg_rec_count = 1;
3741 if (bit (aarch64_insn_r->aarch64_insn, 29))
3742 {
3743 record_buf[1] = AARCH64_CPSR_REGNUM;
3744 aarch64_insn_r->reg_rec_count = 2;
3745 }
3746 }
3747 else if (insn_bits21_23 == 0x02)
3748 {
3749 /* Conditional compare (register) and conditional compare
3750 (immediate) instructions. */
3751 record_buf[0] = AARCH64_CPSR_REGNUM;
3752 aarch64_insn_r->reg_rec_count = 1;
3753 }
3754 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3755 {
85102364 3756 /* Conditional select. */
99afc88b
OJ		 3757 /* Data-processing (2 source). */
3758 /* Data-processing (1 source). */
3759 record_buf[0] = reg_rd;
3760 aarch64_insn_r->reg_rec_count = 1;
3761 }
3762 else
3763 return AARCH64_RECORD_UNKNOWN;
3764 }
3765 }
3766
3767 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3768 record_buf);
3769 return AARCH64_RECORD_SUCCESS;
3770}
3771
3772/* Record handler for data processing - immediate instructions. */
3773
3774static unsigned int
3775aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3776{
78cc6c2d 3777 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3778 uint32_t record_buf[4];
3779
3780 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3781 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3782 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3783
3784 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3785 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3786 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3787 {
3788 record_buf[0] = reg_rd;
3789 aarch64_insn_r->reg_rec_count = 1;
3790 }
3791 else if (insn_bits24_27 == 0x01)
3792 {
3793 /* Add/Subtract (immediate). */
3794 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3795 record_buf[0] = reg_rd;
3796 aarch64_insn_r->reg_rec_count = 1;
3797 if (setflags)
3798 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3799 }
3800 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3801 {
3802 /* Logical (immediate). */
3803 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3804 record_buf[0] = reg_rd;
3805 aarch64_insn_r->reg_rec_count = 1;
3806 if (setflags)
3807 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3808 }
3809 else
3810 return AARCH64_RECORD_UNKNOWN;
3811
3812 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3813 record_buf);
3814 return AARCH64_RECORD_SUCCESS;
3815}
3816
3817/* Record handler for branch, exception generation and system instructions. */
3818
3819static unsigned int
3820aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3821{
3822 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3823 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3824 uint32_t record_buf[4];
3825
3826 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3827 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3828 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3829
3830 if (insn_bits28_31 == 0x0d)
3831 {
3832 /* Exception generation instructions. */
3833 if (insn_bits24_27 == 0x04)
3834 {
5d98d3cd
YQ		 3835 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3836 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3837 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3838 {
3839 ULONGEST svc_number;
3840
3841 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3842 &svc_number);
3843 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3844 svc_number);
3845 }
3846 else
3847 return AARCH64_RECORD_UNSUPPORTED;
3848 }
3849 /* System instructions. */
3850 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3851 {
3852 uint32_t reg_rt, reg_crn;
3853
3854 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3855 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3856
3857 /* Record rt in case of sysl and mrs instructions. */
3858 if (bit (aarch64_insn_r->aarch64_insn, 21))
3859 {
3860 record_buf[0] = reg_rt;
3861 aarch64_insn_r->reg_rec_count = 1;
3862 }
3863 /* Record cpsr for hint and msr(immediate) instructions. */
3864 else if (reg_crn == 0x02 || reg_crn == 0x04)
3865 {
3866 record_buf[0] = AARCH64_CPSR_REGNUM;
3867 aarch64_insn_r->reg_rec_count = 1;
3868 }
3869 }
3870 /* Unconditional branch (register). */
3871 else if((insn_bits24_27 & 0x0e) == 0x06)
3872 {
3873 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3874 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3875 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3876 }
3877 else
3878 return AARCH64_RECORD_UNKNOWN;
3879 }
3880 /* Unconditional branch (immediate). */
3881 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3882 {
3883 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3884 if (bit (aarch64_insn_r->aarch64_insn, 31))
3885 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3886 }
3887 else
3888 /* Compare & branch (immediate), Test & branch (immediate) and
3889 Conditional branch (immediate). */
3890 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3891
3892 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3893 record_buf);
3894 return AARCH64_RECORD_SUCCESS;
3895}
3896
3897/* Record handler for advanced SIMD load and store instructions. */
3898
3899static unsigned int
3900aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3901{
3902 CORE_ADDR address;
3903 uint64_t addr_offset = 0;
3904 uint32_t record_buf[24];
3905 uint64_t record_buf_mem[24];
3906 uint32_t reg_rn, reg_rt;
3907 uint32_t reg_index = 0, mem_index = 0;
3908 uint8_t opcode_bits, size_bits;
3909
3910 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3911 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3912 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3913 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3914 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3915
3916 if (record_debug)
b277c936 3917 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3918
3919 /* Load/store single structure. */
3920 if (bit (aarch64_insn_r->aarch64_insn, 24))
3921 {
3922 uint8_t sindex, scale, selem, esize, replicate = 0;
3923 scale = opcode_bits >> 2;
3924 selem = ((opcode_bits & 0x02) |
3925 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3926 switch (scale)
3927 {
3928 case 1:
3929 if (size_bits & 0x01)
3930 return AARCH64_RECORD_UNKNOWN;
3931 break;
3932 case 2:
3933 if ((size_bits >> 1) & 0x01)
3934 return AARCH64_RECORD_UNKNOWN;
3935 if (size_bits & 0x01)
3936 {
3937 if (!((opcode_bits >> 1) & 0x01))
3938 scale = 3;
3939 else
3940 return AARCH64_RECORD_UNKNOWN;
3941 }
3942 break;
3943 case 3:
3944 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3945 {
3946 scale = size_bits;
3947 replicate = 1;
3948 break;
3949 }
3950 else
3951 return AARCH64_RECORD_UNKNOWN;
3952 default:
3953 break;
3954 }
3955 esize = 8 << scale;
3956 if (replicate)
3957 for (sindex = 0; sindex < selem; sindex++)
3958 {
3959 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3960 reg_rt = (reg_rt + 1) % 32;
3961 }
3962 else
3963 {
3964 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3965 {
3966 if (bit (aarch64_insn_r->aarch64_insn, 22))
3967 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3968 else
3969 {
3970 record_buf_mem[mem_index++] = esize / 8;
3971 record_buf_mem[mem_index++] = address + addr_offset;
3972 }
3973 addr_offset = addr_offset + (esize / 8);
3974 reg_rt = (reg_rt + 1) % 32;
3975 }
99afc88b
OJ		 3976 }
3977 }
3978 /* Load/store multiple structure. */
3979 else
3980 {
3981 uint8_t selem, esize, rpt, elements;
3982 uint8_t eindex, rindex;
3983
3984 esize = 8 << size_bits;
3985 if (bit (aarch64_insn_r->aarch64_insn, 30))
3986 elements = 128 / esize;
3987 else
3988 elements = 64 / esize;
3989
3990 switch (opcode_bits)
3991 {
3992 /*LD/ST4 (4 Registers). */
3993 case 0:
3994 rpt = 1;
3995 selem = 4;
3996 break;
3997 /*LD/ST1 (4 Registers). */
3998 case 2:
3999 rpt = 4;
4000 selem = 1;
4001 break;
4002 /*LD/ST3 (3 Registers). */
4003 case 4:
4004 rpt = 1;
4005 selem = 3;
4006 break;
4007 /*LD/ST1 (3 Registers). */
4008 case 6:
4009 rpt = 3;
4010 selem = 1;
4011 break;
4012 /*LD/ST1 (1 Register). */
4013 case 7:
4014 rpt = 1;
4015 selem = 1;
4016 break;
4017 /*LD/ST2 (2 Registers). */
4018 case 8:
4019 rpt = 1;
4020 selem = 2;
4021 break;
4022 /*LD/ST1 (2 Registers). */
4023 case 10:
4024 rpt = 2;
4025 selem = 1;
4026 break;
4027 default:
4028 return AARCH64_RECORD_UNSUPPORTED;
4029 break;
4030 }
4031 for (rindex = 0; rindex < rpt; rindex++)
4032 for (eindex = 0; eindex < elements; eindex++)
4033 {
4034 uint8_t reg_tt, sindex;
4035 reg_tt = (reg_rt + rindex) % 32;
4036 for (sindex = 0; sindex < selem; sindex++)
4037 {
4038 if (bit (aarch64_insn_r->aarch64_insn, 22))
4039 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
4040 else
4041 {
4042 record_buf_mem[mem_index++] = esize / 8;
4043 record_buf_mem[mem_index++] = address + addr_offset;
4044 }
4045 addr_offset = addr_offset + (esize / 8);
4046 reg_tt = (reg_tt + 1) % 32;
4047 }
4048 }
4049 }
4050
4051 if (bit (aarch64_insn_r->aarch64_insn, 23))
4052 record_buf[reg_index++] = reg_rn;
4053
4054 aarch64_insn_r->reg_rec_count = reg_index;
4055 aarch64_insn_r->mem_rec_count = mem_index / 2;
4056 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
4057 record_buf_mem);
4058 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4059 record_buf);
4060 return AARCH64_RECORD_SUCCESS;
4061}
4062
4063/* Record handler for load and store instructions. */
4064
4065static unsigned int
4066aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
4067{
4068 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
4069 uint8_t insn_bit23, insn_bit21;
4070 uint8_t opc, size_bits, ld_flag, vector_flag;
4071 uint32_t reg_rn, reg_rt, reg_rt2;
4072 uint64_t datasize, offset;
4073 uint32_t record_buf[8];
4074 uint64_t record_buf_mem[8];
4075 CORE_ADDR address;
4076
4077 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4078 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4079 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
4080 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4081 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
4082 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
4083 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
4084 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4085 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
4086 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
4087 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
4088
4089 /* Load/store exclusive. */
4090 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
4091 {
4092 if (record_debug)
b277c936 4093 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 4094
4095 if (ld_flag)
4096 {
4097 record_buf[0] = reg_rt;
4098 aarch64_insn_r->reg_rec_count = 1;
4099 if (insn_bit21)
4100 {
4101 record_buf[1] = reg_rt2;
4102 aarch64_insn_r->reg_rec_count = 2;
4103 }
4104 }
4105 else
4106 {
4107 if (insn_bit21)
4108 datasize = (8 << size_bits) * 2;
4109 else
4110 datasize = (8 << size_bits);
4111 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4112 &address);
4113 record_buf_mem[0] = datasize / 8;
4114 record_buf_mem[1] = address;
4115 aarch64_insn_r->mem_rec_count = 1;
4116 if (!insn_bit23)
4117 {
4118 /* Save register rs. */
4119 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
4120 aarch64_insn_r->reg_rec_count = 1;
4121 }
4122 }
4123 }
4124 /* Load register (literal) instructions decoding. */
4125 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
4126 {
4127 if (record_debug)
b277c936 4128 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 4129 if (vector_flag)
4130 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4131 else
4132 record_buf[0] = reg_rt;
4133 aarch64_insn_r->reg_rec_count = 1;
4134 }
4135 /* All types of load/store pair instructions decoding. */
4136 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
4137 {
4138 if (record_debug)
b277c936 4139 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 4140
4141 if (ld_flag)
4142 {
4143 if (vector_flag)
4144 {
4145 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4146 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
4147 }
4148 else
4149 {
4150 record_buf[0] = reg_rt;
4151 record_buf[1] = reg_rt2;
4152 }
4153 aarch64_insn_r->reg_rec_count = 2;
4154 }
4155 else
4156 {
4157 uint16_t imm7_off;
4158 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
4159 if (!vector_flag)
4160 size_bits = size_bits >> 1;
4161 datasize = 8 << (2 + size_bits);
4162 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
4163 offset = offset << (2 + size_bits);
4164 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4165 &address);
4166 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
4167 {
4168 if (imm7_off & 0x40)
4169 address = address - offset;
4170 else
4171 address = address + offset;
4172 }
4173
4174 record_buf_mem[0] = datasize / 8;
4175 record_buf_mem[1] = address;
4176 record_buf_mem[2] = datasize / 8;
4177 record_buf_mem[3] = address + (datasize / 8);
4178 aarch64_insn_r->mem_rec_count = 2;
4179 }
4180 if (bit (aarch64_insn_r->aarch64_insn, 23))
4181 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4182 }
4183 /* Load/store register (unsigned immediate) instructions. */
4184 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
4185 {
4186 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4187 if (!(opc >> 1))
33877125
YQ		 4188 {
4189 if (opc & 0x01)
4190 ld_flag = 0x01;
4191 else
4192 ld_flag = 0x0;
4193 }
99afc88b 4194 else
33877125 4195 {
1e2b521d
YQ		 4196 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
4197 {
4198 /* PRFM (immediate) */
4199 return AARCH64_RECORD_SUCCESS;
4200 }
4201 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
4202 {
4203 /* LDRSW (immediate) */
4204 ld_flag = 0x1;
4205 }
33877125 4206 else
1e2b521d
YQ		 4207 {
4208 if (opc & 0x01)
4209 ld_flag = 0x01;
4210 else
4211 ld_flag = 0x0;
4212 }
33877125 4213 }
99afc88b
OJ		 4214
4215 if (record_debug)
4216 {
b277c936
PL		 4217 debug_printf ("Process record: load/store (unsigned immediate):"
4218 " size %x V %d opc %x\n", size_bits, vector_flag,
4219 opc);
99afc88b
OJ		 4220 }
4221
4222 if (!ld_flag)
4223 {
4224 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
4225 datasize = 8 << size_bits;
4226 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4227 &address);
4228 offset = offset << size_bits;
4229 address = address + offset;
4230
4231 record_buf_mem[0] = datasize >> 3;
4232 record_buf_mem[1] = address;
4233 aarch64_insn_r->mem_rec_count = 1;
4234 }
4235 else
4236 {
4237 if (vector_flag)
4238 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4239 else
4240 record_buf[0] = reg_rt;
4241 aarch64_insn_r->reg_rec_count = 1;
4242 }
4243 }
4244 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 4245 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4246 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 4247 {
4248 if (record_debug)
b277c936 4249 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 4250 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4251 if (!(opc >> 1))
4252 if (opc & 0x01)
4253 ld_flag = 0x01;
4254 else
4255 ld_flag = 0x0;
4256 else
4257 if (size_bits != 0x03)
4258 ld_flag = 0x01;
4259 else
4260 return AARCH64_RECORD_UNKNOWN;
4261
4262 if (!ld_flag)
4263 {
d9436c7c
PA		 4264 ULONGEST reg_rm_val;
4265
99afc88b
OJ		 4266 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
4267 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
4268 if (bit (aarch64_insn_r->aarch64_insn, 12))
4269 offset = reg_rm_val << size_bits;
4270 else
4271 offset = reg_rm_val;
4272 datasize = 8 << size_bits;
4273 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4274 &address);
4275 address = address + offset;
4276 record_buf_mem[0] = datasize >> 3;
4277 record_buf_mem[1] = address;
4278 aarch64_insn_r->mem_rec_count = 1;
4279 }
4280 else
4281 {
4282 if (vector_flag)
4283 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4284 else
4285 record_buf[0] = reg_rt;
4286 aarch64_insn_r->reg_rec_count = 1;
4287 }
4288 }
4289 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 4290 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4291 && !insn_bit21)
99afc88b
OJ		 4292 {
4293 if (record_debug)
4294 {
b277c936
PL		 4295 debug_printf ("Process record: load/store "
4296 "(immediate and unprivileged)\n");
99afc88b
OJ		 4297 }
4298 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4299 if (!(opc >> 1))
4300 if (opc & 0x01)
4301 ld_flag = 0x01;
4302 else
4303 ld_flag = 0x0;
4304 else
4305 if (size_bits != 0x03)
4306 ld_flag = 0x01;
4307 else
4308 return AARCH64_RECORD_UNKNOWN;
4309
4310 if (!ld_flag)
4311 {
4312 uint16_t imm9_off;
4313 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
4314 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
4315 datasize = 8 << size_bits;
4316 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4317 &address);
4318 if (insn_bits10_11 != 0x01)
4319 {
4320 if (imm9_off & 0x0100)
4321 address = address - offset;
4322 else
4323 address = address + offset;
4324 }
4325 record_buf_mem[0] = datasize >> 3;
4326 record_buf_mem[1] = address;
4327 aarch64_insn_r->mem_rec_count = 1;
4328 }
4329 else
4330 {
4331 if (vector_flag)
4332 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4333 else
4334 record_buf[0] = reg_rt;
4335 aarch64_insn_r->reg_rec_count = 1;
4336 }
4337 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
4338 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4339 }
4340 /* Advanced SIMD load/store instructions. */
4341 else
4342 return aarch64_record_asimd_load_store (aarch64_insn_r);
4343
4344 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
4345 record_buf_mem);
4346 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4347 record_buf);
4348 return AARCH64_RECORD_SUCCESS;
4349}
4350
4351/* Record handler for data processing SIMD and floating point instructions. */
4352
4353static unsigned int
4354aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
4355{
4356 uint8_t insn_bit21, opcode, rmode, reg_rd;
4357 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
4358 uint8_t insn_bits11_14;
4359 uint32_t record_buf[2];
4360
4361 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4362 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
4363 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4364 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
4365 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
4366 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
4367 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
4368 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4369 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4370
4371 if (record_debug)
b277c936 4372 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 4373
4374 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
4375 {
4376 /* Floating point - fixed point conversion instructions. */
4377 if (!insn_bit21)
4378 {
4379 if (record_debug)
b277c936 4380 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 4381
4382 if ((opcode >> 1) == 0x0 && rmode == 0x03)
4383 record_buf[0] = reg_rd;
4384 else
4385 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4386 }
4387 /* Floating point - conditional compare instructions. */
4388 else if (insn_bits10_11 == 0x01)
4389 {
4390 if (record_debug)
b277c936 4391 debug_printf ("FP - conditional compare");
99afc88b
OJ		 4392
4393 record_buf[0] = AARCH64_CPSR_REGNUM;
4394 }
4395 /* Floating point - data processing (2-source) and
4396 conditional select instructions. */
4397 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
4398 {
4399 if (record_debug)
b277c936 4400 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 4401
4402 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4403 }
4404 else if (insn_bits10_11 == 0x00)
4405 {
4406 /* Floating point - immediate instructions. */
4407 if ((insn_bits12_15 & 0x01) == 0x01
4408 || (insn_bits12_15 & 0x07) == 0x04)
4409 {
4410 if (record_debug)
b277c936 4411 debug_printf ("FP - immediate");
99afc88b
OJ		 4412 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4413 }
4414 /* Floating point - compare instructions. */
4415 else if ((insn_bits12_15 & 0x03) == 0x02)
4416 {
4417 if (record_debug)
b277c936 4418 debug_printf ("FP - immediate");
99afc88b
OJ		 4419 record_buf[0] = AARCH64_CPSR_REGNUM;
4420 }
4421 /* Floating point - integer conversions instructions. */
f62fce35 4422 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 4423 {
4424 /* Convert float to integer instruction. */
4425 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4426 {
4427 if (record_debug)
b277c936 4428 debug_printf ("float to int conversion");
99afc88b
OJ		 4429
4430 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4431 }
4432 /* Convert integer to float instruction. */
4433 else if ((opcode >> 1) == 0x01 && !rmode)
4434 {
4435 if (record_debug)
b277c936 4436 debug_printf ("int to float conversion");
99afc88b
OJ		 4437
4438 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4439 }
4440 /* Move float to integer instruction. */
4441 else if ((opcode >> 1) == 0x03)
4442 {
4443 if (record_debug)
b277c936 4444 debug_printf ("move float to int");
99afc88b
OJ		 4445
4446 if (!(opcode & 0x01))
4447 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4448 else
4449 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4450 }
f62fce35
YQ		 4451 else
4452 return AARCH64_RECORD_UNKNOWN;
99afc88b 4453 }
f62fce35
YQ		 4454 else
4455 return AARCH64_RECORD_UNKNOWN;
99afc88b 4456 }
f62fce35
YQ		 4457 else
4458 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4459 }
4460 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4461 {
4462 if (record_debug)
b277c936 4463 debug_printf ("SIMD copy");
99afc88b
OJ		 4464
4465 /* Advanced SIMD copy instructions. */
4466 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4467 && !bit (aarch64_insn_r->aarch64_insn, 15)
4468 && bit (aarch64_insn_r->aarch64_insn, 10))
4469 {
4470 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4471 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4472 else
4473 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4474 }
4475 else
4476 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4477 }
4478 /* All remaining floating point or advanced SIMD instructions. */
4479 else
4480 {
4481 if (record_debug)
b277c936 4482 debug_printf ("all remain");
99afc88b
OJ		 4483
4484 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4485 }
4486
4487 if (record_debug)
b277c936 4488 debug_printf ("\n");
99afc88b
OJ		 4489
4490 aarch64_insn_r->reg_rec_count++;
4491 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4492 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4493 record_buf);
4494 return AARCH64_RECORD_SUCCESS;
4495}
4496
4497/* Decodes insns type and invokes its record handler. */
4498
4499static unsigned int
4500aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4501{
4502 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4503
4504 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4505 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4506 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4507 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4508
4509 /* Data processing - immediate instructions. */
4510 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4511 return aarch64_record_data_proc_imm (aarch64_insn_r);
4512
4513 /* Branch, exception generation and system instructions. */
4514 if (ins_bit26 && !ins_bit27 && ins_bit28)
4515 return aarch64_record_branch_except_sys (aarch64_insn_r);
4516
4517 /* Load and store instructions. */
4518 if (!ins_bit25 && ins_bit27)
4519 return aarch64_record_load_store (aarch64_insn_r);
4520
4521 /* Data processing - register instructions. */
4522 if (ins_bit25 && !ins_bit26 && ins_bit27)
4523 return aarch64_record_data_proc_reg (aarch64_insn_r);
4524
4525 /* Data processing - SIMD and floating point instructions. */
4526 if (ins_bit25 && ins_bit26 && ins_bit27)
4527 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4528
4529 return AARCH64_RECORD_UNSUPPORTED;
4530}
4531
4532/* Cleans up local record registers and memory allocations. */
4533
4534static void
4535deallocate_reg_mem (insn_decode_record *record)
4536{
4537 xfree (record->aarch64_regs);
4538 xfree (record->aarch64_mems);
4539}
4540
1e2b521d
YQ		 4541#if GDB_SELF_TEST
4542namespace selftests {
4543
4544static void
4545aarch64_process_record_test (void)
4546{
4547 struct gdbarch_info info;
4548 uint32_t ret;
4549
4550 gdbarch_info_init (&info);
4551 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4552
4553 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4554 SELF_CHECK (gdbarch != NULL);
4555
4556 insn_decode_record aarch64_record;
4557
4558 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4559 aarch64_record.regcache = NULL;
4560 aarch64_record.this_addr = 0;
4561 aarch64_record.gdbarch = gdbarch;
4562
4563 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4564 aarch64_record.aarch64_insn = 0xf9800020;
4565 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4566 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4567 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4568 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4569
4570 deallocate_reg_mem (&aarch64_record);
4571}
4572
4573} // namespace selftests
4574#endif /* GDB_SELF_TEST */
4575
99afc88b
OJ		 4576/* Parse the current instruction and record the values of the registers and
4577 memory that will be changed in current instruction to record_arch_list
4578 return -1 if something is wrong. */
4579
4580int
4581aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4582 CORE_ADDR insn_addr)
4583{
4584 uint32_t rec_no = 0;
4585 uint8_t insn_size = 4;
4586 uint32_t ret = 0;
99afc88b
OJ		 4587 gdb_byte buf[insn_size];
4588 insn_decode_record aarch64_record;
4589
4590 memset (&buf[0], 0, insn_size);
4591 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4592 target_read_memory (insn_addr, &buf[0], insn_size);
4593 aarch64_record.aarch64_insn
4594 = (uint32_t) extract_unsigned_integer (&buf[0],
4595 insn_size,
4596 gdbarch_byte_order (gdbarch));
4597 aarch64_record.regcache = regcache;
4598 aarch64_record.this_addr = insn_addr;
4599 aarch64_record.gdbarch = gdbarch;
4600
4601 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4602 if (ret == AARCH64_RECORD_UNSUPPORTED)
4603 {
4604 printf_unfiltered (_("Process record does not support instruction "
4605 "0x%0x at address %s.\n"),
4606 aarch64_record.aarch64_insn,
4607 paddress (gdbarch, insn_addr));
4608 ret = -1;
4609 }
4610
4611 if (0 == ret)
4612 {
4613 /* Record registers. */
4614 record_full_arch_list_add_reg (aarch64_record.regcache,
4615 AARCH64_PC_REGNUM);
4616 /* Always record register CPSR. */
4617 record_full_arch_list_add_reg (aarch64_record.regcache,
4618 AARCH64_CPSR_REGNUM);
4619 if (aarch64_record.aarch64_regs)
4620 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4621 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4622 aarch64_record.aarch64_regs[rec_no]))
4623 ret = -1;
4624
4625 /* Record memories. */
4626 if (aarch64_record.aarch64_mems)
4627 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4628 if (record_full_arch_list_add_mem
4629 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4630 aarch64_record.aarch64_mems[rec_no].len))
4631 ret = -1;
4632
4633 if (record_full_arch_list_add_end ())
4634 ret = -1;
4635 }
4636
4637 deallocate_reg_mem (&aarch64_record);
4638 return ret;
4639}
GDB Binutils - Deliverables
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