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Testsuite: Ensure pie is disabled on some tests
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
42a4f53d 3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
24#include "inferior.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
07b287a0
MS		 27#include "dis-asm.h"
28#include "regcache.h"
29#include "reggroups.h"
07b287a0
MS		 30#include "value.h"
31#include "arch-utils.h"
32#include "osabi.h"
33#include "frame-unwind.h"
34#include "frame-base.h"
35#include "trad-frame.h"
36#include "objfiles.h"
37#include "dwarf2-frame.h"
38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
41#include "user-regs.h"
42#include "language.h"
43#include "infcall.h"
ea873d8e
PL		 44#include "ax.h"
45#include "ax-gdb.h"
0747795c 46#include "common/selftest.h"
07b287a0
MS		 47
48#include "aarch64-tdep.h"
e8bf1ce4 49#include "aarch64-ravenscar-thread.h"
07b287a0
MS		 50
51#include "elf-bfd.h"
52#include "elf/aarch64.h"
53
0747795c 54#include "common/vec.h"
07b287a0 55
99afc88b
OJ		 56#include "record.h"
57#include "record-full.h"
787749ea
PL		 58#include "arch/aarch64-insn.h"
59
f77ee802 60#include "opcode/aarch64.h"
325fac50 61#include <algorithm>
f77ee802
YQ		 62
63#define submask(x) ((1L << ((x) + 1)) - 1)
64#define bit(obj,st) (((obj) >> (st)) & 1)
65#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
66
ea92689a
AH		 67/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
68 four members. */
69#define HA_MAX_NUM_FLDS 4
70
95228a0d
AH		 71/* All possible aarch64 target descriptors. */
72struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1];
73
07b287a0
MS		 74/* The standard register names, and all the valid aliases for them. */
75static const struct
76{
77 const char *const name;
78 int regnum;
79} aarch64_register_aliases[] =
80{
81 /* 64-bit register names. */
82 {"fp", AARCH64_FP_REGNUM},
83 {"lr", AARCH64_LR_REGNUM},
84 {"sp", AARCH64_SP_REGNUM},
85
86 /* 32-bit register names. */
87 {"w0", AARCH64_X0_REGNUM + 0},
88 {"w1", AARCH64_X0_REGNUM + 1},
89 {"w2", AARCH64_X0_REGNUM + 2},
90 {"w3", AARCH64_X0_REGNUM + 3},
91 {"w4", AARCH64_X0_REGNUM + 4},
92 {"w5", AARCH64_X0_REGNUM + 5},
93 {"w6", AARCH64_X0_REGNUM + 6},
94 {"w7", AARCH64_X0_REGNUM + 7},
95 {"w8", AARCH64_X0_REGNUM + 8},
96 {"w9", AARCH64_X0_REGNUM + 9},
97 {"w10", AARCH64_X0_REGNUM + 10},
98 {"w11", AARCH64_X0_REGNUM + 11},
99 {"w12", AARCH64_X0_REGNUM + 12},
100 {"w13", AARCH64_X0_REGNUM + 13},
101 {"w14", AARCH64_X0_REGNUM + 14},
102 {"w15", AARCH64_X0_REGNUM + 15},
103 {"w16", AARCH64_X0_REGNUM + 16},
104 {"w17", AARCH64_X0_REGNUM + 17},
105 {"w18", AARCH64_X0_REGNUM + 18},
106 {"w19", AARCH64_X0_REGNUM + 19},
107 {"w20", AARCH64_X0_REGNUM + 20},
108 {"w21", AARCH64_X0_REGNUM + 21},
109 {"w22", AARCH64_X0_REGNUM + 22},
110 {"w23", AARCH64_X0_REGNUM + 23},
111 {"w24", AARCH64_X0_REGNUM + 24},
112 {"w25", AARCH64_X0_REGNUM + 25},
113 {"w26", AARCH64_X0_REGNUM + 26},
114 {"w27", AARCH64_X0_REGNUM + 27},
115 {"w28", AARCH64_X0_REGNUM + 28},
116 {"w29", AARCH64_X0_REGNUM + 29},
117 {"w30", AARCH64_X0_REGNUM + 30},
118
119 /* specials */
120 {"ip0", AARCH64_X0_REGNUM + 16},
121 {"ip1", AARCH64_X0_REGNUM + 17}
122};
123
124/* The required core 'R' registers. */
125static const char *const aarch64_r_register_names[] =
126{
127 /* These registers must appear in consecutive RAW register number
128 order and they must begin with AARCH64_X0_REGNUM! */
129 "x0", "x1", "x2", "x3",
130 "x4", "x5", "x6", "x7",
131 "x8", "x9", "x10", "x11",
132 "x12", "x13", "x14", "x15",
133 "x16", "x17", "x18", "x19",
134 "x20", "x21", "x22", "x23",
135 "x24", "x25", "x26", "x27",
136 "x28", "x29", "x30", "sp",
137 "pc", "cpsr"
138};
139
140/* The FP/SIMD 'V' registers. */
141static const char *const aarch64_v_register_names[] =
142{
143 /* These registers must appear in consecutive RAW register number
144 order and they must begin with AARCH64_V0_REGNUM! */
145 "v0", "v1", "v2", "v3",
146 "v4", "v5", "v6", "v7",
147 "v8", "v9", "v10", "v11",
148 "v12", "v13", "v14", "v15",
149 "v16", "v17", "v18", "v19",
150 "v20", "v21", "v22", "v23",
151 "v24", "v25", "v26", "v27",
152 "v28", "v29", "v30", "v31",
153 "fpsr",
154 "fpcr"
155};
156
739e8682
AH		 157/* The SVE 'Z' and 'P' registers. */
158static const char *const aarch64_sve_register_names[] =
159{
160 /* These registers must appear in consecutive RAW register number
161 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
162 "z0", "z1", "z2", "z3",
163 "z4", "z5", "z6", "z7",
164 "z8", "z9", "z10", "z11",
165 "z12", "z13", "z14", "z15",
166 "z16", "z17", "z18", "z19",
167 "z20", "z21", "z22", "z23",
168 "z24", "z25", "z26", "z27",
169 "z28", "z29", "z30", "z31",
170 "fpsr", "fpcr",
171 "p0", "p1", "p2", "p3",
172 "p4", "p5", "p6", "p7",
173 "p8", "p9", "p10", "p11",
174 "p12", "p13", "p14", "p15",
175 "ffr", "vg"
176};
177
07b287a0
MS		 178/* AArch64 prologue cache structure. */
179struct aarch64_prologue_cache
180{
db634143
PL		 181 /* The program counter at the start of the function. It is used to
182 identify this frame as a prologue frame. */
183 CORE_ADDR func;
184
185 /* The program counter at the time this frame was created; i.e. where
186 this function was called from. It is used to identify this frame as a
187 stub frame. */
188 CORE_ADDR prev_pc;
189
07b287a0
MS		 190 /* The stack pointer at the time this frame was created; i.e. the
191 caller's stack pointer when this function was called. It is used
192 to identify this frame. */
193 CORE_ADDR prev_sp;
194
7dfa3edc
PL		 195 /* Is the target available to read from? */
196 int available_p;
197
07b287a0
MS		 198 /* The frame base for this frame is just prev_sp - frame size.
199 FRAMESIZE is the distance from the frame pointer to the
200 initial stack pointer. */
201 int framesize;
202
203 /* The register used to hold the frame pointer for this frame. */
204 int framereg;
205
206 /* Saved register offsets. */
207 struct trad_frame_saved_reg *saved_regs;
208};
209
07b287a0
MS		 210static void
211show_aarch64_debug (struct ui_file *file, int from_tty,
212 struct cmd_list_element *c, const char *value)
213{
214 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
215}
216
ffdbe864
YQ		 217namespace {
218
4d9a9006
YQ		 219/* Abstract instruction reader. */
220
221class abstract_instruction_reader
222{
223public:
224 /* Read in one instruction. */
225 virtual ULONGEST read (CORE_ADDR memaddr, int len,
226 enum bfd_endian byte_order) = 0;
227};
228
229/* Instruction reader from real target. */
230
231class instruction_reader : public abstract_instruction_reader
232{
233 public:
234 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 235 override
4d9a9006 236 {
fc2f703e 237 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 238 }
239};
240
ffdbe864
YQ		 241} // namespace
242
07b287a0
MS		 243/* Analyze a prologue, looking for a recognizable stack frame
244 and frame pointer. Scan until we encounter a store that could
245 clobber the stack frame unexpectedly, or an unknown instruction. */
246
247static CORE_ADDR
248aarch64_analyze_prologue (struct gdbarch *gdbarch,
249 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 250 struct aarch64_prologue_cache *cache,
251 abstract_instruction_reader& reader)
07b287a0
MS		 252{
253 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
254 int i;
187f5d00
YQ		 255 /* Track X registers and D registers in prologue. */
256 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 257
187f5d00 258 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 259 regs[i] = pv_register (i, 0);
f7b7ed97 260 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 261
262 for (; start < limit; start += 4)
263 {
264 uint32_t insn;
d9ebcbce 265 aarch64_inst inst;
07b287a0 266
4d9a9006 267 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 268
561a72d4 269 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 270 break;
271
272 if (inst.opcode->iclass == addsub_imm
273 && (inst.opcode->op == OP_ADD
274 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 275 {
d9ebcbce
YQ		 276 unsigned rd = inst.operands[0].reg.regno;
277 unsigned rn = inst.operands[1].reg.regno;
278
279 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
280 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
281 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
282 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
283
284 if (inst.opcode->op == OP_ADD)
285 {
286 regs[rd] = pv_add_constant (regs[rn],
287 inst.operands[2].imm.value);
288 }
289 else
290 {
291 regs[rd] = pv_add_constant (regs[rn],
292 -inst.operands[2].imm.value);
293 }
294 }
295 else if (inst.opcode->iclass == pcreladdr
296 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
297 {
298 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
299 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
300
301 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 302 }
d9ebcbce 303 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 304 {
305 /* Stop analysis on branch. */
306 break;
307 }
d9ebcbce 308 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 309 {
310 /* Stop analysis on branch. */
311 break;
312 }
d9ebcbce 313 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 314 {
315 /* Stop analysis on branch. */
316 break;
317 }
d9ebcbce 318 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 319 {
320 /* Stop analysis on branch. */
321 break;
322 }
d9ebcbce
YQ		 323 else if (inst.opcode->op == OP_MOVZ)
324 {
325 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
326 regs[inst.operands[0].reg.regno] = pv_unknown ();
327 }
328 else if (inst.opcode->iclass == log_shift
329 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 330 {
d9ebcbce
YQ		 331 unsigned rd = inst.operands[0].reg.regno;
332 unsigned rn = inst.operands[1].reg.regno;
333 unsigned rm = inst.operands[2].reg.regno;
334
335 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
336 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
337 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
338
339 if (inst.operands[2].shifter.amount == 0
340 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 341 regs[rd] = regs[rm];
342 else
343 {
344 if (aarch64_debug)
b277c936
PL		 345 {
346 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 347 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 348 core_addr_to_string_nz (start), insn);
349 }
07b287a0
MS		 350 break;
351 }
352 }
d9ebcbce 353 else if (inst.opcode->op == OP_STUR)
07b287a0 354 {
d9ebcbce
YQ		 355 unsigned rt = inst.operands[0].reg.regno;
356 unsigned rn = inst.operands[1].addr.base_regno;
357 int is64
358 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
359
360 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
361 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
362 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
363 gdb_assert (!inst.operands[1].addr.offset.is_reg);
364
f7b7ed97
TT		 365 stack.store (pv_add_constant (regs[rn],
366 inst.operands[1].addr.offset.imm),
367 is64 ? 8 : 4, regs[rt]);
07b287a0 368 }
d9ebcbce 369 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 370 || (inst.opcode->iclass == ldstpair_indexed
371 && inst.operands[2].addr.preind))
d9ebcbce 372 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 373 {
03bcd739 374 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 375 unsigned rt1;
376 unsigned rt2;
d9ebcbce
YQ		 377 unsigned rn = inst.operands[2].addr.base_regno;
378 int32_t imm = inst.operands[2].addr.offset.imm;
379
187f5d00
YQ		 380 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
381 || inst.operands[0].type == AARCH64_OPND_Ft);
382 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
383 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 384 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
385 gdb_assert (!inst.operands[2].addr.offset.is_reg);
386
07b287a0
MS		 387 /* If recording this store would invalidate the store area
388 (perhaps because rn is not known) then we should abandon
389 further prologue analysis. */
f7b7ed97 390 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 391 break;
392
f7b7ed97 393 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 394 break;
395
187f5d00
YQ		 396 rt1 = inst.operands[0].reg.regno;
397 rt2 = inst.operands[1].reg.regno;
398 if (inst.operands[0].type == AARCH64_OPND_Ft)
399 {
400 /* Only bottom 64-bit of each V register (D register) need
401 to be preserved. */
402 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
403 rt1 += AARCH64_X_REGISTER_COUNT;
404 rt2 += AARCH64_X_REGISTER_COUNT;
405 }
406
f7b7ed97
TT		 407 stack.store (pv_add_constant (regs[rn], imm), 8,
408 regs[rt1]);
409 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
410 regs[rt2]);
14ac654f 411
d9ebcbce 412 if (inst.operands[2].addr.writeback)
93d96012 413 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 414
07b287a0 415 }
432ec081
YQ		 416 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
417 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
418 && (inst.opcode->op == OP_STR_POS
419 || inst.opcode->op == OP_STRF_POS)))
420 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
421 && strcmp ("str", inst.opcode->name) == 0)
422 {
423 /* STR (immediate) */
424 unsigned int rt = inst.operands[0].reg.regno;
425 int32_t imm = inst.operands[1].addr.offset.imm;
426 unsigned int rn = inst.operands[1].addr.base_regno;
427 bool is64
428 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
429 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
430 || inst.operands[0].type == AARCH64_OPND_Ft);
431
432 if (inst.operands[0].type == AARCH64_OPND_Ft)
433 {
434 /* Only bottom 64-bit of each V register (D register) need
435 to be preserved. */
436 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
437 rt += AARCH64_X_REGISTER_COUNT;
438 }
439
f7b7ed97
TT		 440 stack.store (pv_add_constant (regs[rn], imm),
441 is64 ? 8 : 4, regs[rt]);
432ec081
YQ		 442 if (inst.operands[1].addr.writeback)
443 regs[rn] = pv_add_constant (regs[rn], imm);
444 }
d9ebcbce 445 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 446 {
447 /* Stop analysis on branch. */
448 break;
449 }
450 else
451 {
452 if (aarch64_debug)
b277c936 453 {
0a0da556 454 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 455 " opcode=0x%x\n",
456 core_addr_to_string_nz (start), insn);
457 }
07b287a0
MS		 458 break;
459 }
460 }
461
462 if (cache == NULL)
f7b7ed97 463 return start;
07b287a0
MS		 464
465 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
466 {
467 /* Frame pointer is fp. Frame size is constant. */
468 cache->framereg = AARCH64_FP_REGNUM;
469 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
470 }
471 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
472 {
473 /* Try the stack pointer. */
474 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
475 cache->framereg = AARCH64_SP_REGNUM;
476 }
477 else
478 {
479 /* We're just out of luck. We don't know where the frame is. */
480 cache->framereg = -1;
481 cache->framesize = 0;
482 }
483
484 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
485 {
486 CORE_ADDR offset;
487
f7b7ed97 488 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 489 cache->saved_regs[i].addr = offset;
490 }
491
187f5d00
YQ		 492 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
493 {
494 int regnum = gdbarch_num_regs (gdbarch);
495 CORE_ADDR offset;
496
f7b7ed97
TT		 497 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
498 &offset))
187f5d00
YQ		 499 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
500 }
501
07b287a0
MS		 502 return start;
503}
504
4d9a9006
YQ		 505static CORE_ADDR
506aarch64_analyze_prologue (struct gdbarch *gdbarch,
507 CORE_ADDR start, CORE_ADDR limit,
508 struct aarch64_prologue_cache *cache)
509{
510 instruction_reader reader;
511
512 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
513 reader);
514}
515
516#if GDB_SELF_TEST
517
518namespace selftests {
519
520/* Instruction reader from manually cooked instruction sequences. */
521
522class instruction_reader_test : public abstract_instruction_reader
523{
524public:
525 template<size_t SIZE>
526 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
527 : m_insns (insns), m_insns_size (SIZE)
528 {}
529
530 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 531 override
4d9a9006
YQ		 532 {
533 SELF_CHECK (len == 4);
534 SELF_CHECK (memaddr % 4 == 0);
535 SELF_CHECK (memaddr / 4 < m_insns_size);
536
537 return m_insns[memaddr / 4];
538 }
539
540private:
541 const uint32_t *m_insns;
542 size_t m_insns_size;
543};
544
545static void
546aarch64_analyze_prologue_test (void)
547{
548 struct gdbarch_info info;
549
550 gdbarch_info_init (&info);
551 info.bfd_arch_info = bfd_scan_arch ("aarch64");
552
553 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
554 SELF_CHECK (gdbarch != NULL);
555
556 /* Test the simple prologue in which frame pointer is used. */
557 {
558 struct aarch64_prologue_cache cache;
559 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
560
561 static const uint32_t insns[] = {
562 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
563 0x910003fd, /* mov x29, sp */
564 0x97ffffe6, /* bl 0x400580 */
565 };
566 instruction_reader_test reader (insns);
567
568 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
569 SELF_CHECK (end == 4 * 2);
570
571 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
572 SELF_CHECK (cache.framesize == 272);
573
574 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
575 {
576 if (i == AARCH64_FP_REGNUM)
577 SELF_CHECK (cache.saved_regs[i].addr == -272);
578 else if (i == AARCH64_LR_REGNUM)
579 SELF_CHECK (cache.saved_regs[i].addr == -264);
580 else
581 SELF_CHECK (cache.saved_regs[i].addr == -1);
582 }
583
584 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
585 {
586 int regnum = gdbarch_num_regs (gdbarch);
587
588 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
589 == -1);
590 }
591 }
432ec081
YQ		 592
593 /* Test a prologue in which STR is used and frame pointer is not
594 used. */
595 {
596 struct aarch64_prologue_cache cache;
597 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
598
599 static const uint32_t insns[] = {
600 0xf81d0ff3, /* str x19, [sp, #-48]! */
601 0xb9002fe0, /* str w0, [sp, #44] */
602 0xf90013e1, /* str x1, [sp, #32]*/
603 0xfd000fe0, /* str d0, [sp, #24] */
604 0xaa0203f3, /* mov x19, x2 */
605 0xf94013e0, /* ldr x0, [sp, #32] */
606 };
607 instruction_reader_test reader (insns);
608
609 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
610
611 SELF_CHECK (end == 4 * 5);
612
613 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
614 SELF_CHECK (cache.framesize == 48);
615
616 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
617 {
618 if (i == 1)
619 SELF_CHECK (cache.saved_regs[i].addr == -16);
620 else if (i == 19)
621 SELF_CHECK (cache.saved_regs[i].addr == -48);
622 else
623 SELF_CHECK (cache.saved_regs[i].addr == -1);
624 }
625
626 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
627 {
628 int regnum = gdbarch_num_regs (gdbarch);
629
630 if (i == 0)
631 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
632 == -24);
633 else
634 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
635 == -1);
636 }
637 }
4d9a9006
YQ		 638}
639} // namespace selftests
640#endif /* GDB_SELF_TEST */
641
07b287a0
MS		 642/* Implement the "skip_prologue" gdbarch method. */
643
644static CORE_ADDR
645aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
646{
07b287a0 647 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 648
649 /* See if we can determine the end of the prologue via the symbol
650 table. If so, then return either PC, or the PC after the
651 prologue, whichever is greater. */
652 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
653 {
654 CORE_ADDR post_prologue_pc
655 = skip_prologue_using_sal (gdbarch, func_addr);
656
657 if (post_prologue_pc != 0)
325fac50 658 return std::max (pc, post_prologue_pc);
07b287a0
MS		 659 }
660
661 /* Can't determine prologue from the symbol table, need to examine
662 instructions. */
663
664 /* Find an upper limit on the function prologue using the debug
665 information. If the debug information could not be used to
666 provide that bound, then use an arbitrary large number as the
667 upper bound. */
668 limit_pc = skip_prologue_using_sal (gdbarch, pc);
669 if (limit_pc == 0)
670 limit_pc = pc + 128; /* Magic. */
671
672 /* Try disassembling prologue. */
673 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
674}
675
676/* Scan the function prologue for THIS_FRAME and populate the prologue
677 cache CACHE. */
678
679static void
680aarch64_scan_prologue (struct frame_info *this_frame,
681 struct aarch64_prologue_cache *cache)
682{
683 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
684 CORE_ADDR prologue_start;
685 CORE_ADDR prologue_end;
686 CORE_ADDR prev_pc = get_frame_pc (this_frame);
687 struct gdbarch *gdbarch = get_frame_arch (this_frame);
688
db634143
PL		 689 cache->prev_pc = prev_pc;
690
07b287a0
MS		 691 /* Assume we do not find a frame. */
692 cache->framereg = -1;
693 cache->framesize = 0;
694
695 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
696 &prologue_end))
697 {
698 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
699
700 if (sal.line == 0)
701 {
702 /* No line info so use the current PC. */
703 prologue_end = prev_pc;
704 }
705 else if (sal.end < prologue_end)
706 {
707 /* The next line begins after the function end. */
708 prologue_end = sal.end;
709 }
710
325fac50 711 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 712 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
713 }
714 else
715 {
716 CORE_ADDR frame_loc;
07b287a0
MS		 717
718 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
719 if (frame_loc == 0)
720 return;
721
722 cache->framereg = AARCH64_FP_REGNUM;
723 cache->framesize = 16;
724 cache->saved_regs[29].addr = 0;
725 cache->saved_regs[30].addr = 8;
726 }
727}
728
7dfa3edc
PL		 729/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
730 function may throw an exception if the inferior's registers or memory is
731 not available. */
07b287a0 732
7dfa3edc
PL		 733static void
734aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
735 struct aarch64_prologue_cache *cache)
07b287a0 736{
07b287a0
MS		 737 CORE_ADDR unwound_fp;
738 int reg;
739
07b287a0
MS		 740 aarch64_scan_prologue (this_frame, cache);
741
742 if (cache->framereg == -1)
7dfa3edc 743 return;
07b287a0
MS		 744
745 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
746 if (unwound_fp == 0)
7dfa3edc 747 return;
07b287a0
MS		 748
749 cache->prev_sp = unwound_fp + cache->framesize;
750
751 /* Calculate actual addresses of saved registers using offsets
752 determined by aarch64_analyze_prologue. */
753 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
754 if (trad_frame_addr_p (cache->saved_regs, reg))
755 cache->saved_regs[reg].addr += cache->prev_sp;
756
db634143
PL		 757 cache->func = get_frame_func (this_frame);
758
7dfa3edc
PL		 759 cache->available_p = 1;
760}
761
762/* Allocate and fill in *THIS_CACHE with information about the prologue of
763 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
764 Return a pointer to the current aarch64_prologue_cache in
765 *THIS_CACHE. */
766
767static struct aarch64_prologue_cache *
768aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
769{
770 struct aarch64_prologue_cache *cache;
771
772 if (*this_cache != NULL)
9a3c8263 773 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 774
775 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
776 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
777 *this_cache = cache;
778
779 TRY
780 {
781 aarch64_make_prologue_cache_1 (this_frame, cache);
782 }
783 CATCH (ex, RETURN_MASK_ERROR)
784 {
785 if (ex.error != NOT_AVAILABLE_ERROR)
786 throw_exception (ex);
787 }
788 END_CATCH
789
07b287a0
MS		 790 return cache;
791}
792
7dfa3edc
PL		 793/* Implement the "stop_reason" frame_unwind method. */
794
795static enum unwind_stop_reason
796aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
797 void **this_cache)
798{
799 struct aarch64_prologue_cache *cache
800 = aarch64_make_prologue_cache (this_frame, this_cache);
801
802 if (!cache->available_p)
803 return UNWIND_UNAVAILABLE;
804
805 /* Halt the backtrace at "_start". */
806 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
807 return UNWIND_OUTERMOST;
808
809 /* We've hit a wall, stop. */
810 if (cache->prev_sp == 0)
811 return UNWIND_OUTERMOST;
812
813 return UNWIND_NO_REASON;
814}
815
07b287a0
MS		 816/* Our frame ID for a normal frame is the current function's starting
817 PC and the caller's SP when we were called. */
818
819static void
820aarch64_prologue_this_id (struct frame_info *this_frame,
821 void **this_cache, struct frame_id *this_id)
822{
7c8edfae
PL		 823 struct aarch64_prologue_cache *cache
824 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 825
7dfa3edc
PL		 826 if (!cache->available_p)
827 *this_id = frame_id_build_unavailable_stack (cache->func);
828 else
829 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 830}
831
832/* Implement the "prev_register" frame_unwind method. */
833
834static struct value *
835aarch64_prologue_prev_register (struct frame_info *this_frame,
836 void **this_cache, int prev_regnum)
837{
7c8edfae
PL		 838 struct aarch64_prologue_cache *cache
839 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 840
841 /* If we are asked to unwind the PC, then we need to return the LR
842 instead. The prologue may save PC, but it will point into this
843 frame's prologue, not the next frame's resume location. */
844 if (prev_regnum == AARCH64_PC_REGNUM)
845 {
846 CORE_ADDR lr;
847
848 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
849 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
850 }
851
852 /* SP is generally not saved to the stack, but this frame is
853 identified by the next frame's stack pointer at the time of the
854 call. The value was already reconstructed into PREV_SP. */
855 /*
856 +----------+ ^
857 | saved lr | |
858 +->| saved fp |--+
859 | | |
860 | | | <- Previous SP
861 | +----------+
862 | | saved lr |
863 +--| saved fp |<- FP
864 | |
865 | |<- SP
866 +----------+ */
867 if (prev_regnum == AARCH64_SP_REGNUM)
868 return frame_unwind_got_constant (this_frame, prev_regnum,
869 cache->prev_sp);
870
871 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
872 prev_regnum);
873}
874
875/* AArch64 prologue unwinder. */
876struct frame_unwind aarch64_prologue_unwind =
877{
878 NORMAL_FRAME,
7dfa3edc 879 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 880 aarch64_prologue_this_id,
881 aarch64_prologue_prev_register,
882 NULL,
883 default_frame_sniffer
884};
885
8b61f75d
PL		 886/* Allocate and fill in *THIS_CACHE with information about the prologue of
887 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
888 Return a pointer to the current aarch64_prologue_cache in
889 *THIS_CACHE. */
07b287a0
MS		 890
891static struct aarch64_prologue_cache *
8b61f75d 892aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 893{
07b287a0 894 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 895
896 if (*this_cache != NULL)
9a3c8263 897 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 898
899 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
900 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 901 *this_cache = cache;
07b287a0 902
02a2a705
PL		 903 TRY
904 {
905 cache->prev_sp = get_frame_register_unsigned (this_frame,
906 AARCH64_SP_REGNUM);
907 cache->prev_pc = get_frame_pc (this_frame);
908 cache->available_p = 1;
909 }
910 CATCH (ex, RETURN_MASK_ERROR)
911 {
912 if (ex.error != NOT_AVAILABLE_ERROR)
913 throw_exception (ex);
914 }
915 END_CATCH
07b287a0
MS		 916
917 return cache;
918}
919
02a2a705
PL		 920/* Implement the "stop_reason" frame_unwind method. */
921
922static enum unwind_stop_reason
923aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
924 void **this_cache)
925{
926 struct aarch64_prologue_cache *cache
927 = aarch64_make_stub_cache (this_frame, this_cache);
928
929 if (!cache->available_p)
930 return UNWIND_UNAVAILABLE;
931
932 return UNWIND_NO_REASON;
933}
934
07b287a0
MS		 935/* Our frame ID for a stub frame is the current SP and LR. */
936
937static void
938aarch64_stub_this_id (struct frame_info *this_frame,
939 void **this_cache, struct frame_id *this_id)
940{
8b61f75d
PL		 941 struct aarch64_prologue_cache *cache
942 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 943
02a2a705
PL		 944 if (cache->available_p)
945 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
946 else
947 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 948}
949
950/* Implement the "sniffer" frame_unwind method. */
951
952static int
953aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
954 struct frame_info *this_frame,
955 void **this_prologue_cache)
956{
957 CORE_ADDR addr_in_block;
958 gdb_byte dummy[4];
959
960 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 961 if (in_plt_section (addr_in_block)
07b287a0
MS		 962 /* We also use the stub winder if the target memory is unreadable
963 to avoid having the prologue unwinder trying to read it. */
964 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
965 return 1;
966
967 return 0;
968}
969
970/* AArch64 stub unwinder. */
971struct frame_unwind aarch64_stub_unwind =
972{
973 NORMAL_FRAME,
02a2a705 974 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 975 aarch64_stub_this_id,
976 aarch64_prologue_prev_register,
977 NULL,
978 aarch64_stub_unwind_sniffer
979};
980
981/* Return the frame base address of *THIS_FRAME. */
982
983static CORE_ADDR
984aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
985{
7c8edfae
PL		 986 struct aarch64_prologue_cache *cache
987 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 988
989 return cache->prev_sp - cache->framesize;
990}
991
992/* AArch64 default frame base information. */
993struct frame_base aarch64_normal_base =
994{
995 &aarch64_prologue_unwind,
996 aarch64_normal_frame_base,
997 aarch64_normal_frame_base,
998 aarch64_normal_frame_base
999};
1000
07b287a0
MS		 1001/* Return the value of the REGNUM register in the previous frame of
1002 *THIS_FRAME. */
1003
1004static struct value *
1005aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1006 void **this_cache, int regnum)
1007{
07b287a0
MS		 1008 CORE_ADDR lr;
1009
1010 switch (regnum)
1011 {
1012 case AARCH64_PC_REGNUM:
1013 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
1014 return frame_unwind_got_constant (this_frame, regnum, lr);
1015
1016 default:
1017 internal_error (__FILE__, __LINE__,
1018 _("Unexpected register %d"), regnum);
1019 }
1020}
1021
1022/* Implement the "init_reg" dwarf2_frame_ops method. */
1023
1024static void
1025aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1026 struct dwarf2_frame_state_reg *reg,
1027 struct frame_info *this_frame)
1028{
1029 switch (regnum)
1030 {
1031 case AARCH64_PC_REGNUM:
1032 reg->how = DWARF2_FRAME_REG_FN;
1033 reg->loc.fn = aarch64_dwarf2_prev_register;
1034 break;
1035 case AARCH64_SP_REGNUM:
1036 reg->how = DWARF2_FRAME_REG_CFA;
1037 break;
1038 }
1039}
1040
1041/* When arguments must be pushed onto the stack, they go on in reverse
1042 order. The code below implements a FILO (stack) to do this. */
1043
1044typedef struct
1045{
c3c87445
YQ		 1046 /* Value to pass on stack. It can be NULL if this item is for stack
1047 padding. */
7c543f7b 1048 const gdb_byte *data;
07b287a0
MS		 1049
1050 /* Size in bytes of value to pass on stack. */
1051 int len;
1052} stack_item_t;
1053
1054DEF_VEC_O (stack_item_t);
1055
1056/* Return the alignment (in bytes) of the given type. */
1057
1058static int
1059aarch64_type_align (struct type *t)
1060{
1061 int n;
1062 int align;
1063 int falign;
1064
1065 t = check_typedef (t);
1066 switch (TYPE_CODE (t))
1067 {
1068 default:
1069 /* Should never happen. */
1070 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1071 return 4;
1072
1073 case TYPE_CODE_PTR:
1074 case TYPE_CODE_ENUM:
1075 case TYPE_CODE_INT:
1076 case TYPE_CODE_FLT:
1077 case TYPE_CODE_SET:
1078 case TYPE_CODE_RANGE:
1079 case TYPE_CODE_BITSTRING:
1080 case TYPE_CODE_REF:
aa006118 1081 case TYPE_CODE_RVALUE_REF:
07b287a0
MS		 1082 case TYPE_CODE_CHAR:
1083 case TYPE_CODE_BOOL:
1084 return TYPE_LENGTH (t);
1085
1086 case TYPE_CODE_ARRAY:
238f2452
YQ		 1087 if (TYPE_VECTOR (t))
1088 {
1089 /* Use the natural alignment for vector types (the same for
1090 scalar type), but the maximum alignment is 128-bit. */
1091 if (TYPE_LENGTH (t) > 16)
1092 return 16;
1093 else
1094 return TYPE_LENGTH (t);
1095 }
1096 else
1097 return aarch64_type_align (TYPE_TARGET_TYPE (t));
07b287a0
MS		 1098 case TYPE_CODE_COMPLEX:
1099 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1100
1101 case TYPE_CODE_STRUCT:
1102 case TYPE_CODE_UNION:
1103 align = 1;
1104 for (n = 0; n < TYPE_NFIELDS (t); n++)
1105 {
1106 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
1107 if (falign > align)
1108 align = falign;
1109 }
1110 return align;
1111 }
1112}
1113
ea92689a
AH		 1114/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1115
1116 Return the number of register required, or -1 on failure.
1117
1118 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1119 to the element, else fail if the type of this element does not match the
1120 existing value. */
1121
1122static int
1123aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1124 struct type **fundamental_type)
1125{
1126 if (type == nullptr)
1127 return -1;
1128
1129 switch (TYPE_CODE (type))
1130 {
1131 case TYPE_CODE_FLT:
1132 if (TYPE_LENGTH (type) > 16)
1133 return -1;
1134
1135 if (*fundamental_type == nullptr)
1136 *fundamental_type = type;
1137 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1138 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1139 return -1;
1140
1141 return 1;
1142
1143 case TYPE_CODE_COMPLEX:
1144 {
1145 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1146 if (TYPE_LENGTH (target_type) > 16)
1147 return -1;
1148
1149 if (*fundamental_type == nullptr)
1150 *fundamental_type = target_type;
1151 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1152 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1153 return -1;
1154
1155 return 2;
1156 }
1157
1158 case TYPE_CODE_ARRAY:
1159 {
1160 if (TYPE_VECTOR (type))
1161 {
1162 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1163 return -1;
1164
1165 if (*fundamental_type == nullptr)
1166 *fundamental_type = type;
1167 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1168 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1169 return -1;
1170
1171 return 1;
1172 }
1173 else
1174 {
1175 struct type *target_type = TYPE_TARGET_TYPE (type);
1176 int count = aapcs_is_vfp_call_or_return_candidate_1
1177 (target_type, fundamental_type);
1178
1179 if (count == -1)
1180 return count;
1181
d4718d5c 1182 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1183 return count;
1184 }
1185 }
1186
1187 case TYPE_CODE_STRUCT:
1188 case TYPE_CODE_UNION:
1189 {
1190 int count = 0;
1191
1192 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1193 {
353229bf
AH		 1194 /* Ignore any static fields. */
1195 if (field_is_static (&TYPE_FIELD (type, i)))
1196 continue;
1197
ea92689a
AH		 1198 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1199
1200 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1201 (member, fundamental_type);
1202 if (sub_count == -1)
1203 return -1;
1204 count += sub_count;
1205 }
73021deb
AH		 1206
1207 /* Ensure there is no padding between the fields (allowing for empty
1208 zero length structs) */
1209 int ftype_length = (*fundamental_type == nullptr)
1210 ? 0 : TYPE_LENGTH (*fundamental_type);
1211 if (count * ftype_length != TYPE_LENGTH (type))
1212 return -1;
1213
ea92689a
AH		 1214 return count;
1215 }
1216
1217 default:
1218 break;
1219 }
1220
1221 return -1;
1222}
1223
1224/* Return true if an argument, whose type is described by TYPE, can be passed or
1225 returned in simd/fp registers, providing enough parameter passing registers
1226 are available. This is as described in the AAPCS64.
1227
1228 Upon successful return, *COUNT returns the number of needed registers,
1229 *FUNDAMENTAL_TYPE contains the type of those registers.
1230
1231 Candidate as per the AAPCS64 5.4.2.C is either a:
1232 - float.
1233 - short-vector.
1234 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1235 all the members are floats and has at most 4 members.
1236 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1237 all the members are short vectors and has at most 4 members.
1238 - Complex (7.1.1)
1239
1240 Note that HFAs and HVAs can include nested structures and arrays. */
1241
0e745c60 1242static bool
ea92689a
AH		 1243aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1244 struct type **fundamental_type)
1245{
1246 if (type == nullptr)
1247 return false;
1248
1249 *fundamental_type = nullptr;
1250
1251 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1252 fundamental_type);
1253
1254 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1255 {
1256 *count = ag_count;
1257 return true;
1258 }
1259 else
1260 return false;
1261}
1262
07b287a0
MS		 1263/* AArch64 function call information structure. */
1264struct aarch64_call_info
1265{
1266 /* the current argument number. */
1267 unsigned argnum;
1268
1269 /* The next general purpose register number, equivalent to NGRN as
1270 described in the AArch64 Procedure Call Standard. */
1271 unsigned ngrn;
1272
1273 /* The next SIMD and floating point register number, equivalent to
1274 NSRN as described in the AArch64 Procedure Call Standard. */
1275 unsigned nsrn;
1276
1277 /* The next stacked argument address, equivalent to NSAA as
1278 described in the AArch64 Procedure Call Standard. */
1279 unsigned nsaa;
1280
1281 /* Stack item vector. */
1282 VEC(stack_item_t) *si;
1283};
1284
1285/* Pass a value in a sequence of consecutive X registers. The caller
1286 is responsbile for ensuring sufficient registers are available. */
1287
1288static void
1289pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1290 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1291 struct value *arg)
07b287a0
MS		 1292{
1293 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1294 int len = TYPE_LENGTH (type);
1295 enum type_code typecode = TYPE_CODE (type);
1296 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1297 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1298
1299 info->argnum++;
1300
1301 while (len > 0)
1302 {
1303 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1304 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1305 byte_order);
1306
1307
1308 /* Adjust sub-word struct/union args when big-endian. */
1309 if (byte_order == BFD_ENDIAN_BIG
1310 && partial_len < X_REGISTER_SIZE
1311 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1312 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1313
1314 if (aarch64_debug)
b277c936
PL		 1315 {
1316 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1317 gdbarch_register_name (gdbarch, regnum),
1318 phex (regval, X_REGISTER_SIZE));
1319 }
07b287a0
MS		 1320 regcache_cooked_write_unsigned (regcache, regnum, regval);
1321 len -= partial_len;
1322 buf += partial_len;
1323 regnum++;
1324 }
1325}
1326
1327/* Attempt to marshall a value in a V register. Return 1 if
1328 successful, or 0 if insufficient registers are available. This
1329 function, unlike the equivalent pass_in_x() function does not
1330 handle arguments spread across multiple registers. */
1331
1332static int
1333pass_in_v (struct gdbarch *gdbarch,
1334 struct regcache *regcache,
1335 struct aarch64_call_info *info,
0735fddd 1336 int len, const bfd_byte *buf)
07b287a0
MS		 1337{
1338 if (info->nsrn < 8)
1339 {
07b287a0 1340 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1341 /* Enough space for a full vector register. */
1342 gdb_byte reg[register_size (gdbarch, regnum)];
1343 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1344
1345 info->argnum++;
1346 info->nsrn++;
1347
0735fddd
YQ		 1348 memset (reg, 0, sizeof (reg));
1349 /* PCS C.1, the argument is allocated to the least significant
1350 bits of V register. */
1351 memcpy (reg, buf, len);
b66f5587 1352 regcache->cooked_write (regnum, reg);
0735fddd 1353
07b287a0 1354 if (aarch64_debug)
b277c936
PL		 1355 {
1356 debug_printf ("arg %d in %s\n", info->argnum,
1357 gdbarch_register_name (gdbarch, regnum));
1358 }
07b287a0
MS		 1359 return 1;
1360 }
1361 info->nsrn = 8;
1362 return 0;
1363}
1364
1365/* Marshall an argument onto the stack. */
1366
1367static void
1368pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1369 struct value *arg)
07b287a0 1370{
8e80f9d1 1371 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1372 int len = TYPE_LENGTH (type);
1373 int align;
1374 stack_item_t item;
1375
1376 info->argnum++;
1377
1378 align = aarch64_type_align (type);
1379
1380 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1381 Natural alignment of the argument's type. */
1382 align = align_up (align, 8);
1383
1384 /* The AArch64 PCS requires at most doubleword alignment. */
1385 if (align > 16)
1386 align = 16;
1387
1388 if (aarch64_debug)
b277c936
PL		 1389 {
1390 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1391 info->nsaa);
1392 }
07b287a0
MS		 1393
1394 item.len = len;
1395 item.data = buf;
1396 VEC_safe_push (stack_item_t, info->si, &item);
1397
1398 info->nsaa += len;
1399 if (info->nsaa & (align - 1))
1400 {
1401 /* Push stack alignment padding. */
1402 int pad = align - (info->nsaa & (align - 1));
1403
1404 item.len = pad;
c3c87445 1405 item.data = NULL;
07b287a0
MS		 1406
1407 VEC_safe_push (stack_item_t, info->si, &item);
1408 info->nsaa += pad;
1409 }
1410}
1411
1412/* Marshall an argument into a sequence of one or more consecutive X
1413 registers or, if insufficient X registers are available then onto
1414 the stack. */
1415
1416static void
1417pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1418 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1419 struct value *arg)
07b287a0
MS		 1420{
1421 int len = TYPE_LENGTH (type);
1422 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1423
1424 /* PCS C.13 - Pass in registers if we have enough spare */
1425 if (info->ngrn + nregs <= 8)
1426 {
8e80f9d1 1427 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1428 info->ngrn += nregs;
1429 }
1430 else
1431 {
1432 info->ngrn = 8;
8e80f9d1 1433 pass_on_stack (info, type, arg);
07b287a0
MS		 1434 }
1435}
1436
0e745c60
AH		 1437/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1438 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1439 registers. A return value of false is an error state as the value will have
1440 been partially passed to the stack. */
1441static bool
1442pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1443 struct aarch64_call_info *info, struct type *arg_type,
1444 struct value *arg)
07b287a0 1445{
0e745c60
AH		 1446 switch (TYPE_CODE (arg_type))
1447 {
1448 case TYPE_CODE_FLT:
1449 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1450 value_contents (arg));
1451 break;
1452
1453 case TYPE_CODE_COMPLEX:
1454 {
1455 const bfd_byte *buf = value_contents (arg);
1456 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1457
1458 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1459 buf))
1460 return false;
1461
1462 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1463 buf + TYPE_LENGTH (target_type));
1464 }
1465
1466 case TYPE_CODE_ARRAY:
1467 if (TYPE_VECTOR (arg_type))
1468 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1469 value_contents (arg));
1470 /* fall through. */
1471
1472 case TYPE_CODE_STRUCT:
1473 case TYPE_CODE_UNION:
1474 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1475 {
353229bf
AH		 1476 /* Don't include static fields. */
1477 if (field_is_static (&TYPE_FIELD (arg_type, i)))
1478 continue;
1479
0e745c60
AH		 1480 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1481 struct type *field_type = check_typedef (value_type (field));
1482
1483 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1484 field))
1485 return false;
1486 }
1487 return true;
1488
1489 default:
1490 return false;
1491 }
07b287a0
MS		 1492}
1493
1494/* Implement the "push_dummy_call" gdbarch method. */
1495
1496static CORE_ADDR
1497aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1498 struct regcache *regcache, CORE_ADDR bp_addr,
1499 int nargs,
cf84fa6b
AH		 1500 struct value **args, CORE_ADDR sp,
1501 function_call_return_method return_method,
07b287a0
MS		 1502 CORE_ADDR struct_addr)
1503{
07b287a0 1504 int argnum;
07b287a0 1505 struct aarch64_call_info info;
07b287a0
MS		 1506
1507 memset (&info, 0, sizeof (info));
1508
1509 /* We need to know what the type of the called function is in order
1510 to determine the number of named/anonymous arguments for the
1511 actual argument placement, and the return type in order to handle
1512 return value correctly.
1513
1514 The generic code above us views the decision of return in memory
1515 or return in registers as a two stage processes. The language
1516 handler is consulted first and may decide to return in memory (eg
1517 class with copy constructor returned by value), this will cause
1518 the generic code to allocate space AND insert an initial leading
1519 argument.
1520
1521 If the language code does not decide to pass in memory then the
1522 target code is consulted.
1523
1524 If the language code decides to pass in memory we want to move
1525 the pointer inserted as the initial argument from the argument
1526 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1527 register. */
07b287a0
MS		 1528
1529 /* Set the return address. For the AArch64, the return breakpoint
1530 is always at BP_ADDR. */
1531 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1532
38a72da0
AH		 1533 /* If we were given an initial argument for the return slot, lose it. */
1534 if (return_method == return_method_hidden_param)
07b287a0
MS		 1535 {
1536 args++;
1537 nargs--;
1538 }
1539
1540 /* The struct_return pointer occupies X8. */
38a72da0 1541 if (return_method != return_method_normal)
07b287a0
MS		 1542 {
1543 if (aarch64_debug)
b277c936
PL		 1544 {
1545 debug_printf ("struct return in %s = 0x%s\n",
1546 gdbarch_register_name (gdbarch,
1547 AARCH64_STRUCT_RETURN_REGNUM),
1548 paddress (gdbarch, struct_addr));
1549 }
07b287a0
MS		 1550 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1551 struct_addr);
1552 }
1553
1554 for (argnum = 0; argnum < nargs; argnum++)
1555 {
1556 struct value *arg = args[argnum];
0e745c60
AH		 1557 struct type *arg_type, *fundamental_type;
1558 int len, elements;
07b287a0
MS		 1559
1560 arg_type = check_typedef (value_type (arg));
1561 len = TYPE_LENGTH (arg_type);
1562
0e745c60
AH		 1563 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1564 if there are enough spare registers. */
1565 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1566 &fundamental_type))
1567 {
1568 if (info.nsrn + elements <= 8)
1569 {
1570 /* We know that we have sufficient registers available therefore
1571 this will never need to fallback to the stack. */
1572 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1573 arg))
1574 gdb_assert_not_reached ("Failed to push args");
1575 }
1576 else
1577 {
1578 info.nsrn = 8;
1579 pass_on_stack (&info, arg_type, arg);
1580 }
1581 continue;
1582 }
1583
07b287a0
MS		 1584 switch (TYPE_CODE (arg_type))
1585 {
1586 case TYPE_CODE_INT:
1587 case TYPE_CODE_BOOL:
1588 case TYPE_CODE_CHAR:
1589 case TYPE_CODE_RANGE:
1590 case TYPE_CODE_ENUM:
1591 if (len < 4)
1592 {
1593 /* Promote to 32 bit integer. */
1594 if (TYPE_UNSIGNED (arg_type))
1595 arg_type = builtin_type (gdbarch)->builtin_uint32;
1596 else
1597 arg_type = builtin_type (gdbarch)->builtin_int32;
1598 arg = value_cast (arg_type, arg);
1599 }
8e80f9d1 1600 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1601 break;
1602
07b287a0
MS		 1603 case TYPE_CODE_STRUCT:
1604 case TYPE_CODE_ARRAY:
1605 case TYPE_CODE_UNION:
0e745c60 1606 if (len > 16)
07b287a0
MS		 1607 {
1608 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1609 invisible reference. */
1610
1611 /* Allocate aligned storage. */
1612 sp = align_down (sp - len, 16);
1613
1614 /* Write the real data into the stack. */
1615 write_memory (sp, value_contents (arg), len);
1616
1617 /* Construct the indirection. */
1618 arg_type = lookup_pointer_type (arg_type);
1619 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1620 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1621 }
1622 else
1623 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1624 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1625 break;
1626
1627 default:
8e80f9d1 1628 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1629 break;
1630 }
1631 }
1632
1633 /* Make sure stack retains 16 byte alignment. */
1634 if (info.nsaa & 15)
1635 sp -= 16 - (info.nsaa & 15);
1636
1637 while (!VEC_empty (stack_item_t, info.si))
1638 {
1639 stack_item_t *si = VEC_last (stack_item_t, info.si);
1640
1641 sp -= si->len;
c3c87445
YQ		 1642 if (si->data != NULL)
1643 write_memory (sp, si->data, si->len);
07b287a0
MS		 1644 VEC_pop (stack_item_t, info.si);
1645 }
1646
1647 VEC_free (stack_item_t, info.si);
1648
1649 /* Finally, update the SP register. */
1650 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1651
1652 return sp;
1653}
1654
1655/* Implement the "frame_align" gdbarch method. */
1656
1657static CORE_ADDR
1658aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1659{
1660 /* Align the stack to sixteen bytes. */
1661 return sp & ~(CORE_ADDR) 15;
1662}
1663
1664/* Return the type for an AdvSISD Q register. */
1665
1666static struct type *
1667aarch64_vnq_type (struct gdbarch *gdbarch)
1668{
1669 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1670
1671 if (tdep->vnq_type == NULL)
1672 {
1673 struct type *t;
1674 struct type *elem;
1675
1676 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1677 TYPE_CODE_UNION);
1678
1679 elem = builtin_type (gdbarch)->builtin_uint128;
1680 append_composite_type_field (t, "u", elem);
1681
1682 elem = builtin_type (gdbarch)->builtin_int128;
1683 append_composite_type_field (t, "s", elem);
1684
1685 tdep->vnq_type = t;
1686 }
1687
1688 return tdep->vnq_type;
1689}
1690
1691/* Return the type for an AdvSISD D register. */
1692
1693static struct type *
1694aarch64_vnd_type (struct gdbarch *gdbarch)
1695{
1696 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1697
1698 if (tdep->vnd_type == NULL)
1699 {
1700 struct type *t;
1701 struct type *elem;
1702
1703 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1704 TYPE_CODE_UNION);
1705
1706 elem = builtin_type (gdbarch)->builtin_double;
1707 append_composite_type_field (t, "f", elem);
1708
1709 elem = builtin_type (gdbarch)->builtin_uint64;
1710 append_composite_type_field (t, "u", elem);
1711
1712 elem = builtin_type (gdbarch)->builtin_int64;
1713 append_composite_type_field (t, "s", elem);
1714
1715 tdep->vnd_type = t;
1716 }
1717
1718 return tdep->vnd_type;
1719}
1720
1721/* Return the type for an AdvSISD S register. */
1722
1723static struct type *
1724aarch64_vns_type (struct gdbarch *gdbarch)
1725{
1726 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1727
1728 if (tdep->vns_type == NULL)
1729 {
1730 struct type *t;
1731 struct type *elem;
1732
1733 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1734 TYPE_CODE_UNION);
1735
1736 elem = builtin_type (gdbarch)->builtin_float;
1737 append_composite_type_field (t, "f", elem);
1738
1739 elem = builtin_type (gdbarch)->builtin_uint32;
1740 append_composite_type_field (t, "u", elem);
1741
1742 elem = builtin_type (gdbarch)->builtin_int32;
1743 append_composite_type_field (t, "s", elem);
1744
1745 tdep->vns_type = t;
1746 }
1747
1748 return tdep->vns_type;
1749}
1750
1751/* Return the type for an AdvSISD H register. */
1752
1753static struct type *
1754aarch64_vnh_type (struct gdbarch *gdbarch)
1755{
1756 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1757
1758 if (tdep->vnh_type == NULL)
1759 {
1760 struct type *t;
1761 struct type *elem;
1762
1763 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1764 TYPE_CODE_UNION);
1765
1766 elem = builtin_type (gdbarch)->builtin_uint16;
1767 append_composite_type_field (t, "u", elem);
1768
1769 elem = builtin_type (gdbarch)->builtin_int16;
1770 append_composite_type_field (t, "s", elem);
1771
1772 tdep->vnh_type = t;
1773 }
1774
1775 return tdep->vnh_type;
1776}
1777
1778/* Return the type for an AdvSISD B register. */
1779
1780static struct type *
1781aarch64_vnb_type (struct gdbarch *gdbarch)
1782{
1783 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1784
1785 if (tdep->vnb_type == NULL)
1786 {
1787 struct type *t;
1788 struct type *elem;
1789
1790 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1791 TYPE_CODE_UNION);
1792
1793 elem = builtin_type (gdbarch)->builtin_uint8;
1794 append_composite_type_field (t, "u", elem);
1795
1796 elem = builtin_type (gdbarch)->builtin_int8;
1797 append_composite_type_field (t, "s", elem);
1798
1799 tdep->vnb_type = t;
1800 }
1801
1802 return tdep->vnb_type;
1803}
1804
63bad7b6
AH		 1805/* Return the type for an AdvSISD V register. */
1806
1807static struct type *
1808aarch64_vnv_type (struct gdbarch *gdbarch)
1809{
1810 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1811
1812 if (tdep->vnv_type == NULL)
1813 {
1814 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1815 TYPE_CODE_UNION);
1816
1817 append_composite_type_field (t, "d", aarch64_vnd_type (gdbarch));
1818 append_composite_type_field (t, "s", aarch64_vns_type (gdbarch));
1819 append_composite_type_field (t, "h", aarch64_vnh_type (gdbarch));
1820 append_composite_type_field (t, "b", aarch64_vnb_type (gdbarch));
1821 append_composite_type_field (t, "q", aarch64_vnq_type (gdbarch));
1822
1823 tdep->vnv_type = t;
1824 }
1825
1826 return tdep->vnv_type;
1827}
1828
07b287a0
MS		 1829/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1830
1831static int
1832aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1833{
1834 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1835 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1836
1837 if (reg == AARCH64_DWARF_SP)
1838 return AARCH64_SP_REGNUM;
1839
1840 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1841 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1842
65d4cada
AH		 1843 if (reg == AARCH64_DWARF_SVE_VG)
1844 return AARCH64_SVE_VG_REGNUM;
1845
1846 if (reg == AARCH64_DWARF_SVE_FFR)
1847 return AARCH64_SVE_FFR_REGNUM;
1848
1849 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
1850 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
1851
1852 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
1853 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
1854
07b287a0
MS		 1855 return -1;
1856}
07b287a0
MS		 1857
1858/* Implement the "print_insn" gdbarch method. */
1859
1860static int
1861aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1862{
1863 info->symbols = NULL;
6394c606 1864 return default_print_insn (memaddr, info);
07b287a0
MS		 1865}
1866
1867/* AArch64 BRK software debug mode instruction.
1868 Note that AArch64 code is always little-endian.
1869 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 1870constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 1871
04180708 1872typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 1873
1874/* Extract from an array REGS containing the (raw) register state a
1875 function return value of type TYPE, and copy that, in virtual
1876 format, into VALBUF. */
1877
1878static void
1879aarch64_extract_return_value (struct type *type, struct regcache *regs,
1880 gdb_byte *valbuf)
1881{
ac7936df 1882 struct gdbarch *gdbarch = regs->arch ();
07b287a0 1883 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 1884 int elements;
1885 struct type *fundamental_type;
07b287a0 1886
4f4aedeb
AH		 1887 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
1888 &fundamental_type))
07b287a0 1889 {
4f4aedeb
AH		 1890 int len = TYPE_LENGTH (fundamental_type);
1891
1892 for (int i = 0; i < elements; i++)
1893 {
1894 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 1895 /* Enough space for a full vector register. */
1896 gdb_byte buf[register_size (gdbarch, regno)];
1897 gdb_assert (len <= sizeof (buf));
4f4aedeb
AH		 1898
1899 if (aarch64_debug)
1900 {
1901 debug_printf ("read HFA or HVA return value element %d from %s\n",
1902 i + 1,
1903 gdbarch_register_name (gdbarch, regno));
1904 }
1905 regs->cooked_read (regno, buf);
07b287a0 1906
4f4aedeb
AH		 1907 memcpy (valbuf, buf, len);
1908 valbuf += len;
1909 }
07b287a0
MS		 1910 }
1911 else if (TYPE_CODE (type) == TYPE_CODE_INT
1912 || TYPE_CODE (type) == TYPE_CODE_CHAR
1913 || TYPE_CODE (type) == TYPE_CODE_BOOL
1914 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 1915 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 1916 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1917 {
6471e7d2 1918 /* If the type is a plain integer, then the access is
07b287a0
MS		 1919 straight-forward. Otherwise we have to play around a bit
1920 more. */
1921 int len = TYPE_LENGTH (type);
1922 int regno = AARCH64_X0_REGNUM;
1923 ULONGEST tmp;
1924
1925 while (len > 0)
1926 {
1927 /* By using store_unsigned_integer we avoid having to do
1928 anything special for small big-endian values. */
1929 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1930 store_unsigned_integer (valbuf,
1931 (len > X_REGISTER_SIZE
1932 ? X_REGISTER_SIZE : len), byte_order, tmp);
1933 len -= X_REGISTER_SIZE;
1934 valbuf += X_REGISTER_SIZE;
1935 }
1936 }
07b287a0
MS		 1937 else
1938 {
1939 /* For a structure or union the behaviour is as if the value had
1940 been stored to word-aligned memory and then loaded into
1941 registers with 64-bit load instruction(s). */
1942 int len = TYPE_LENGTH (type);
1943 int regno = AARCH64_X0_REGNUM;
1944 bfd_byte buf[X_REGISTER_SIZE];
1945
1946 while (len > 0)
1947 {
dca08e1f 1948 regs->cooked_read (regno++, buf);
07b287a0
MS		 1949 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1950 len -= X_REGISTER_SIZE;
1951 valbuf += X_REGISTER_SIZE;
1952 }
1953 }
1954}
1955
1956
1957/* Will a function return an aggregate type in memory or in a
1958 register? Return 0 if an aggregate type can be returned in a
1959 register, 1 if it must be returned in memory. */
1960
1961static int
1962aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1963{
f168693b 1964 type = check_typedef (type);
4f4aedeb
AH		 1965 int elements;
1966 struct type *fundamental_type;
07b287a0 1967
4f4aedeb
AH		 1968 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
1969 &fundamental_type))
07b287a0 1970 {
cd635f74
YQ		 1971 /* v0-v7 are used to return values and one register is allocated
1972 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 1973 return 0;
1974 }
1975
1976 if (TYPE_LENGTH (type) > 16)
1977 {
1978 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1979 invisible reference. */
1980
1981 return 1;
1982 }
1983
1984 return 0;
1985}
1986
1987/* Write into appropriate registers a function return value of type
1988 TYPE, given in virtual format. */
1989
1990static void
1991aarch64_store_return_value (struct type *type, struct regcache *regs,
1992 const gdb_byte *valbuf)
1993{
ac7936df 1994 struct gdbarch *gdbarch = regs->arch ();
07b287a0 1995 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 1996 int elements;
1997 struct type *fundamental_type;
07b287a0 1998
4f4aedeb
AH		 1999 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2000 &fundamental_type))
07b287a0 2001 {
4f4aedeb
AH		 2002 int len = TYPE_LENGTH (fundamental_type);
2003
2004 for (int i = 0; i < elements; i++)
2005 {
2006 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2007 /* Enough space for a full vector register. */
2008 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2009 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb
AH		 2010
2011 if (aarch64_debug)
2012 {
2013 debug_printf ("write HFA or HVA return value element %d to %s\n",
2014 i + 1,
2015 gdbarch_register_name (gdbarch, regno));
2016 }
07b287a0 2017
4f4aedeb
AH		 2018 memcpy (tmpbuf, valbuf,
2019 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2020 regs->cooked_write (regno, tmpbuf);
2021 valbuf += len;
2022 }
07b287a0
MS		 2023 }
2024 else if (TYPE_CODE (type) == TYPE_CODE_INT
2025 || TYPE_CODE (type) == TYPE_CODE_CHAR
2026 || TYPE_CODE (type) == TYPE_CODE_BOOL
2027 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2028 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2029 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2030 {
2031 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2032 {
2033 /* Values of one word or less are zero/sign-extended and
2034 returned in r0. */
2035 bfd_byte tmpbuf[X_REGISTER_SIZE];
2036 LONGEST val = unpack_long (type, valbuf);
2037
2038 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2039 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2040 }
2041 else
2042 {
2043 /* Integral values greater than one word are stored in
2044 consecutive registers starting with r0. This will always
2045 be a multiple of the regiser size. */
2046 int len = TYPE_LENGTH (type);
2047 int regno = AARCH64_X0_REGNUM;
2048
2049 while (len > 0)
2050 {
b66f5587 2051 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2052 len -= X_REGISTER_SIZE;
2053 valbuf += X_REGISTER_SIZE;
2054 }
2055 }
2056 }
07b287a0
MS		 2057 else
2058 {
2059 /* For a structure or union the behaviour is as if the value had
2060 been stored to word-aligned memory and then loaded into
2061 registers with 64-bit load instruction(s). */
2062 int len = TYPE_LENGTH (type);
2063 int regno = AARCH64_X0_REGNUM;
2064 bfd_byte tmpbuf[X_REGISTER_SIZE];
2065
2066 while (len > 0)
2067 {
2068 memcpy (tmpbuf, valbuf,
2069 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2070 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2071 len -= X_REGISTER_SIZE;
2072 valbuf += X_REGISTER_SIZE;
2073 }
2074 }
2075}
2076
2077/* Implement the "return_value" gdbarch method. */
2078
2079static enum return_value_convention
2080aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2081 struct type *valtype, struct regcache *regcache,
2082 gdb_byte *readbuf, const gdb_byte *writebuf)
2083{
07b287a0
MS		 2084
2085 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2086 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2087 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2088 {
2089 if (aarch64_return_in_memory (gdbarch, valtype))
2090 {
2091 if (aarch64_debug)
b277c936 2092 debug_printf ("return value in memory\n");
07b287a0
MS		 2093 return RETURN_VALUE_STRUCT_CONVENTION;
2094 }
2095 }
2096
2097 if (writebuf)
2098 aarch64_store_return_value (valtype, regcache, writebuf);
2099
2100 if (readbuf)
2101 aarch64_extract_return_value (valtype, regcache, readbuf);
2102
2103 if (aarch64_debug)
b277c936 2104 debug_printf ("return value in registers\n");
07b287a0
MS		 2105
2106 return RETURN_VALUE_REGISTER_CONVENTION;
2107}
2108
2109/* Implement the "get_longjmp_target" gdbarch method. */
2110
2111static int
2112aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2113{
2114 CORE_ADDR jb_addr;
2115 gdb_byte buf[X_REGISTER_SIZE];
2116 struct gdbarch *gdbarch = get_frame_arch (frame);
2117 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2118 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2119
2120 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2121
2122 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2123 X_REGISTER_SIZE))
2124 return 0;
2125
2126 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2127 return 1;
2128}
ea873d8e
PL		 2129
2130/* Implement the "gen_return_address" gdbarch method. */
2131
2132static void
2133aarch64_gen_return_address (struct gdbarch *gdbarch,
2134 struct agent_expr *ax, struct axs_value *value,
2135 CORE_ADDR scope)
2136{
2137 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2138 value->kind = axs_lvalue_register;
2139 value->u.reg = AARCH64_LR_REGNUM;
2140}
07b287a0
MS		 2141\f
2142
2143/* Return the pseudo register name corresponding to register regnum. */
2144
2145static const char *
2146aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2147{
63bad7b6
AH		 2148 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2149
07b287a0
MS		 2150 static const char *const q_name[] =
2151 {
2152 "q0", "q1", "q2", "q3",
2153 "q4", "q5", "q6", "q7",
2154 "q8", "q9", "q10", "q11",
2155 "q12", "q13", "q14", "q15",
2156 "q16", "q17", "q18", "q19",
2157 "q20", "q21", "q22", "q23",
2158 "q24", "q25", "q26", "q27",
2159 "q28", "q29", "q30", "q31",
2160 };
2161
2162 static const char *const d_name[] =
2163 {
2164 "d0", "d1", "d2", "d3",
2165 "d4", "d5", "d6", "d7",
2166 "d8", "d9", "d10", "d11",
2167 "d12", "d13", "d14", "d15",
2168 "d16", "d17", "d18", "d19",
2169 "d20", "d21", "d22", "d23",
2170 "d24", "d25", "d26", "d27",
2171 "d28", "d29", "d30", "d31",
2172 };
2173
2174 static const char *const s_name[] =
2175 {
2176 "s0", "s1", "s2", "s3",
2177 "s4", "s5", "s6", "s7",
2178 "s8", "s9", "s10", "s11",
2179 "s12", "s13", "s14", "s15",
2180 "s16", "s17", "s18", "s19",
2181 "s20", "s21", "s22", "s23",
2182 "s24", "s25", "s26", "s27",
2183 "s28", "s29", "s30", "s31",
2184 };
2185
2186 static const char *const h_name[] =
2187 {
2188 "h0", "h1", "h2", "h3",
2189 "h4", "h5", "h6", "h7",
2190 "h8", "h9", "h10", "h11",
2191 "h12", "h13", "h14", "h15",
2192 "h16", "h17", "h18", "h19",
2193 "h20", "h21", "h22", "h23",
2194 "h24", "h25", "h26", "h27",
2195 "h28", "h29", "h30", "h31",
2196 };
2197
2198 static const char *const b_name[] =
2199 {
2200 "b0", "b1", "b2", "b3",
2201 "b4", "b5", "b6", "b7",
2202 "b8", "b9", "b10", "b11",
2203 "b12", "b13", "b14", "b15",
2204 "b16", "b17", "b18", "b19",
2205 "b20", "b21", "b22", "b23",
2206 "b24", "b25", "b26", "b27",
2207 "b28", "b29", "b30", "b31",
2208 };
2209
2210 regnum -= gdbarch_num_regs (gdbarch);
2211
2212 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2213 return q_name[regnum - AARCH64_Q0_REGNUM];
2214
2215 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2216 return d_name[regnum - AARCH64_D0_REGNUM];
2217
2218 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2219 return s_name[regnum - AARCH64_S0_REGNUM];
2220
2221 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2222 return h_name[regnum - AARCH64_H0_REGNUM];
2223
2224 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2225 return b_name[regnum - AARCH64_B0_REGNUM];
2226
63bad7b6
AH		 2227 if (tdep->has_sve ())
2228 {
2229 static const char *const sve_v_name[] =
2230 {
2231 "v0", "v1", "v2", "v3",
2232 "v4", "v5", "v6", "v7",
2233 "v8", "v9", "v10", "v11",
2234 "v12", "v13", "v14", "v15",
2235 "v16", "v17", "v18", "v19",
2236 "v20", "v21", "v22", "v23",
2237 "v24", "v25", "v26", "v27",
2238 "v28", "v29", "v30", "v31",
2239 };
2240
2241 if (regnum >= AARCH64_SVE_V0_REGNUM
2242 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2243 return sve_v_name[regnum - AARCH64_SVE_V0_REGNUM];
2244 }
2245
07b287a0
MS		 2246 internal_error (__FILE__, __LINE__,
2247 _("aarch64_pseudo_register_name: bad register number %d"),
2248 regnum);
2249}
2250
2251/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2252
2253static struct type *
2254aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2255{
63bad7b6
AH		 2256 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2257
07b287a0
MS		 2258 regnum -= gdbarch_num_regs (gdbarch);
2259
2260 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2261 return aarch64_vnq_type (gdbarch);
2262
2263 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2264 return aarch64_vnd_type (gdbarch);
2265
2266 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2267 return aarch64_vns_type (gdbarch);
2268
2269 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2270 return aarch64_vnh_type (gdbarch);
2271
2272 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2273 return aarch64_vnb_type (gdbarch);
2274
63bad7b6
AH		 2275 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2276 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2277 return aarch64_vnv_type (gdbarch);
2278
07b287a0
MS		 2279 internal_error (__FILE__, __LINE__,
2280 _("aarch64_pseudo_register_type: bad register number %d"),
2281 regnum);
2282}
2283
2284/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2285
2286static int
2287aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2288 struct reggroup *group)
2289{
63bad7b6
AH		 2290 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2291
07b287a0
MS		 2292 regnum -= gdbarch_num_regs (gdbarch);
2293
2294 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2295 return group == all_reggroup || group == vector_reggroup;
2296 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2297 return (group == all_reggroup || group == vector_reggroup
2298 || group == float_reggroup);
2299 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2300 return (group == all_reggroup || group == vector_reggroup
2301 || group == float_reggroup);
2302 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2303 return group == all_reggroup || group == vector_reggroup;
2304 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2305 return group == all_reggroup || group == vector_reggroup;
63bad7b6
AH		 2306 else if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2307 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2308 return group == all_reggroup || group == vector_reggroup;
07b287a0
MS		 2309
2310 return group == all_reggroup;
2311}
2312
3c5cd5c3
AH		 2313/* Helper for aarch64_pseudo_read_value. */
2314
2315static struct value *
63bad7b6
AH		 2316aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2317 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2318 int regsize, struct value *result_value)
2319{
3c5cd5c3
AH		 2320 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2321
63bad7b6
AH		 2322 /* Enough space for a full vector register. */
2323 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2324 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2325
3c5cd5c3
AH		 2326 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2327 mark_value_bytes_unavailable (result_value, 0,
2328 TYPE_LENGTH (value_type (result_value)));
2329 else
2330 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2331
3c5cd5c3
AH		 2332 return result_value;
2333 }
2334
07b287a0
MS		 2335/* Implement the "pseudo_register_read_value" gdbarch method. */
2336
2337static struct value *
3c5cd5c3 2338aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2339 int regnum)
2340{
63bad7b6 2341 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2342 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2343
07b287a0
MS		 2344 VALUE_LVAL (result_value) = lval_register;
2345 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2346
2347 regnum -= gdbarch_num_regs (gdbarch);
2348
2349 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2350 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2351 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2352 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2353
2354 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2355 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2356 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2357 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2358
2359 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2360 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2361 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2362 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2363
2364 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2365 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2366 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2367 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2368
2369 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2370 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2371 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2372 B_REGISTER_SIZE, result_value);
07b287a0 2373
63bad7b6
AH		 2374 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2375 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2376 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2377 regnum - AARCH64_SVE_V0_REGNUM,
2378 V_REGISTER_SIZE, result_value);
2379
07b287a0
MS		 2380 gdb_assert_not_reached ("regnum out of bound");
2381}
2382
3c5cd5c3 2383/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2384
2385static void
63bad7b6
AH		 2386aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2387 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2388{
3c5cd5c3 2389 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2390
63bad7b6
AH		 2391 /* Enough space for a full vector register. */
2392 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2393 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2394
07b287a0
MS		 2395 /* Ensure the register buffer is zero, we want gdb writes of the
2396 various 'scalar' pseudo registers to behavior like architectural
2397 writes, register width bytes are written the remainder are set to
2398 zero. */
63bad7b6 2399 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2400
3c5cd5c3
AH		 2401 memcpy (reg_buf, buf, regsize);
2402 regcache->raw_write (v_regnum, reg_buf);
2403}
2404
2405/* Implement the "pseudo_register_write" gdbarch method. */
2406
2407static void
2408aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2409 int regnum, const gdb_byte *buf)
2410{
63bad7b6 2411 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2412 regnum -= gdbarch_num_regs (gdbarch);
2413
2414 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2415 return aarch64_pseudo_write_1 (gdbarch, regcache,
2416 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2417 buf);
07b287a0
MS		 2418
2419 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2420 return aarch64_pseudo_write_1 (gdbarch, regcache,
2421 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2422 buf);
07b287a0
MS		 2423
2424 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2425 return aarch64_pseudo_write_1 (gdbarch, regcache,
2426 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2427 buf);
07b287a0
MS		 2428
2429 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2430 return aarch64_pseudo_write_1 (gdbarch, regcache,
2431 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2432 buf);
07b287a0
MS		 2433
2434 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2435 return aarch64_pseudo_write_1 (gdbarch, regcache,
2436 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2437 buf);
2438
2439 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2440 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2441 return aarch64_pseudo_write_1 (gdbarch, regcache,
2442 regnum - AARCH64_SVE_V0_REGNUM,
2443 V_REGISTER_SIZE, buf);
07b287a0
MS		 2444
2445 gdb_assert_not_reached ("regnum out of bound");
2446}
2447
07b287a0
MS		 2448/* Callback function for user_reg_add. */
2449
2450static struct value *
2451value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2452{
9a3c8263 2453 const int *reg_p = (const int *) baton;
07b287a0
MS		 2454
2455 return value_of_register (*reg_p, frame);
2456}
2457\f
2458
9404b58f
KM		 2459/* Implement the "software_single_step" gdbarch method, needed to
2460 single step through atomic sequences on AArch64. */
2461
a0ff9e1a 2462static std::vector<CORE_ADDR>
f5ea389a 2463aarch64_software_single_step (struct regcache *regcache)
9404b58f 2464{
ac7936df 2465 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2466 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2467 const int insn_size = 4;
2468 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2469 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2470 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2471 CORE_ADDR loc = pc;
2472 CORE_ADDR closing_insn = 0;
2473 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2474 byte_order_for_code);
2475 int index;
2476 int insn_count;
2477 int bc_insn_count = 0; /* Conditional branch instruction count. */
2478 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2479 aarch64_inst inst;
2480
561a72d4 2481 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2482 return {};
9404b58f
KM		 2483
2484 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2485 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2486 return {};
9404b58f
KM		 2487
2488 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2489 {
9404b58f
KM		 2490 loc += insn_size;
2491 insn = read_memory_unsigned_integer (loc, insn_size,
2492 byte_order_for_code);
2493
561a72d4 2494 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2495 return {};
9404b58f 2496 /* Check if the instruction is a conditional branch. */
f77ee802 2497 if (inst.opcode->iclass == condbranch)
9404b58f 2498 {
f77ee802
YQ		 2499 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2500
9404b58f 2501 if (bc_insn_count >= 1)
a0ff9e1a 2502 return {};
9404b58f
KM		 2503
2504 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2505 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2506
2507 bc_insn_count++;
2508 last_breakpoint++;
2509 }
2510
2511 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2512 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2513 {
2514 closing_insn = loc;
2515 break;
2516 }
2517 }
2518
2519 /* We didn't find a closing Store Exclusive instruction, fall back. */
2520 if (!closing_insn)
a0ff9e1a 2521 return {};
9404b58f
KM		 2522
2523 /* Insert breakpoint after the end of the atomic sequence. */
2524 breaks[0] = loc + insn_size;
2525
2526 /* Check for duplicated breakpoints, and also check that the second
2527 breakpoint is not within the atomic sequence. */
2528 if (last_breakpoint
2529 && (breaks[1] == breaks[0]
2530 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2531 last_breakpoint = 0;
2532
a0ff9e1a
SM		 2533 std::vector<CORE_ADDR> next_pcs;
2534
9404b58f
KM		 2535 /* Insert the breakpoint at the end of the sequence, and one at the
2536 destination of the conditional branch, if it exists. */
2537 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2538 next_pcs.push_back (breaks[index]);
9404b58f 2539
93f9a11f 2540 return next_pcs;
9404b58f
KM		 2541}
2542
cfba9872 2543struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2544{
2545 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2546 is being displaced stepping. */
cfba9872 2547 int cond = 0;
b6542f81
YQ		 2548
2549 /* PC adjustment offset after displaced stepping. */
cfba9872 2550 int32_t pc_adjust = 0;
b6542f81
YQ		 2551};
2552
2553/* Data when visiting instructions for displaced stepping. */
2554
2555struct aarch64_displaced_step_data
2556{
2557 struct aarch64_insn_data base;
2558
2559 /* The address where the instruction will be executed at. */
2560 CORE_ADDR new_addr;
2561 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2562 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2563 /* Number of instructions in INSN_BUF. */
2564 unsigned insn_count;
2565 /* Registers when doing displaced stepping. */
2566 struct regcache *regs;
2567
cfba9872 2568 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2569};
2570
2571/* Implementation of aarch64_insn_visitor method "b". */
2572
2573static void
2574aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2575 struct aarch64_insn_data *data)
2576{
2577 struct aarch64_displaced_step_data *dsd
2578 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2579 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2580
2581 if (can_encode_int32 (new_offset, 28))
2582 {
2583 /* Emit B rather than BL, because executing BL on a new address
2584 will get the wrong address into LR. In order to avoid this,
2585 we emit B, and update LR if the instruction is BL. */
2586 emit_b (dsd->insn_buf, 0, new_offset);
2587 dsd->insn_count++;
2588 }
2589 else
2590 {
2591 /* Write NOP. */
2592 emit_nop (dsd->insn_buf);
2593 dsd->insn_count++;
2594 dsd->dsc->pc_adjust = offset;
2595 }
2596
2597 if (is_bl)
2598 {
2599 /* Update LR. */
2600 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2601 data->insn_addr + 4);
2602 }
2603}
2604
2605/* Implementation of aarch64_insn_visitor method "b_cond". */
2606
2607static void
2608aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2609 struct aarch64_insn_data *data)
2610{
2611 struct aarch64_displaced_step_data *dsd
2612 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2613
2614 /* GDB has to fix up PC after displaced step this instruction
2615 differently according to the condition is true or false. Instead
2616 of checking COND against conditional flags, we can use
2617 the following instructions, and GDB can tell how to fix up PC
2618 according to the PC value.
2619
2620 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2621 INSN1 ;
2622 TAKEN:
2623 INSN2
2624 */
2625
2626 emit_bcond (dsd->insn_buf, cond, 8);
2627 dsd->dsc->cond = 1;
2628 dsd->dsc->pc_adjust = offset;
2629 dsd->insn_count = 1;
2630}
2631
2632/* Dynamically allocate a new register. If we know the register
2633 statically, we should make it a global as above instead of using this
2634 helper function. */
2635
2636static struct aarch64_register
2637aarch64_register (unsigned num, int is64)
2638{
2639 return (struct aarch64_register) { num, is64 };
2640}
2641
2642/* Implementation of aarch64_insn_visitor method "cb". */
2643
2644static void
2645aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2646 const unsigned rn, int is64,
2647 struct aarch64_insn_data *data)
2648{
2649 struct aarch64_displaced_step_data *dsd
2650 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2651
2652 /* The offset is out of range for a compare and branch
2653 instruction. We can use the following instructions instead:
2654
2655 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2656 INSN1 ;
2657 TAKEN:
2658 INSN2
2659 */
2660 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2661 dsd->insn_count = 1;
2662 dsd->dsc->cond = 1;
2663 dsd->dsc->pc_adjust = offset;
2664}
2665
2666/* Implementation of aarch64_insn_visitor method "tb". */
2667
2668static void
2669aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2670 const unsigned rt, unsigned bit,
2671 struct aarch64_insn_data *data)
2672{
2673 struct aarch64_displaced_step_data *dsd
2674 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2675
2676 /* The offset is out of range for a test bit and branch
2677 instruction We can use the following instructions instead:
2678
2679 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2680 INSN1 ;
2681 TAKEN:
2682 INSN2
2683
2684 */
2685 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2686 dsd->insn_count = 1;
2687 dsd->dsc->cond = 1;
2688 dsd->dsc->pc_adjust = offset;
2689}
2690
2691/* Implementation of aarch64_insn_visitor method "adr". */
2692
2693static void
2694aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2695 const int is_adrp, struct aarch64_insn_data *data)
2696{
2697 struct aarch64_displaced_step_data *dsd
2698 = (struct aarch64_displaced_step_data *) data;
2699 /* We know exactly the address the ADR{P,} instruction will compute.
2700 We can just write it to the destination register. */
2701 CORE_ADDR address = data->insn_addr + offset;
2702
2703 if (is_adrp)
2704 {
2705 /* Clear the lower 12 bits of the offset to get the 4K page. */
2706 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2707 address & ~0xfff);
2708 }
2709 else
2710 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2711 address);
2712
2713 dsd->dsc->pc_adjust = 4;
2714 emit_nop (dsd->insn_buf);
2715 dsd->insn_count = 1;
2716}
2717
2718/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2719
2720static void
2721aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2722 const unsigned rt, const int is64,
2723 struct aarch64_insn_data *data)
2724{
2725 struct aarch64_displaced_step_data *dsd
2726 = (struct aarch64_displaced_step_data *) data;
2727 CORE_ADDR address = data->insn_addr + offset;
2728 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2729
2730 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2731 address);
2732
2733 if (is_sw)
2734 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2735 aarch64_register (rt, 1), zero);
2736 else
2737 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2738 aarch64_register (rt, 1), zero);
2739
2740 dsd->dsc->pc_adjust = 4;
2741}
2742
2743/* Implementation of aarch64_insn_visitor method "others". */
2744
2745static void
2746aarch64_displaced_step_others (const uint32_t insn,
2747 struct aarch64_insn_data *data)
2748{
2749 struct aarch64_displaced_step_data *dsd
2750 = (struct aarch64_displaced_step_data *) data;
2751
e1c587c3 2752 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2753 dsd->insn_count = 1;
2754
2755 if ((insn & 0xfffffc1f) == 0xd65f0000)
2756 {
2757 /* RET */
2758 dsd->dsc->pc_adjust = 0;
2759 }
2760 else
2761 dsd->dsc->pc_adjust = 4;
2762}
2763
2764static const struct aarch64_insn_visitor visitor =
2765{
2766 aarch64_displaced_step_b,
2767 aarch64_displaced_step_b_cond,
2768 aarch64_displaced_step_cb,
2769 aarch64_displaced_step_tb,
2770 aarch64_displaced_step_adr,
2771 aarch64_displaced_step_ldr_literal,
2772 aarch64_displaced_step_others,
2773};
2774
2775/* Implement the "displaced_step_copy_insn" gdbarch method. */
2776
2777struct displaced_step_closure *
2778aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2779 CORE_ADDR from, CORE_ADDR to,
2780 struct regcache *regs)
2781{
b6542f81
YQ		 2782 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2783 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2784 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 2785 aarch64_inst inst;
2786
561a72d4 2787 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 2788 return NULL;
b6542f81
YQ		 2789
2790 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 2791 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 2792 {
2793 /* We can't displaced step atomic sequences. */
2794 return NULL;
2795 }
2796
cfba9872
SM		 2797 std::unique_ptr<aarch64_displaced_step_closure> dsc
2798 (new aarch64_displaced_step_closure);
b6542f81
YQ		 2799 dsd.base.insn_addr = from;
2800 dsd.new_addr = to;
2801 dsd.regs = regs;
cfba9872 2802 dsd.dsc = dsc.get ();
034f1a81 2803 dsd.insn_count = 0;
b6542f81
YQ		 2804 aarch64_relocate_instruction (insn, &visitor,
2805 (struct aarch64_insn_data *) &dsd);
2806 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2807
2808 if (dsd.insn_count != 0)
2809 {
2810 int i;
2811
2812 /* Instruction can be relocated to scratch pad. Copy
2813 relocated instruction(s) there. */
2814 for (i = 0; i < dsd.insn_count; i++)
2815 {
2816 if (debug_displaced)
2817 {
2818 debug_printf ("displaced: writing insn ");
2819 debug_printf ("%.8x", dsd.insn_buf[i]);
2820 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2821 }
2822 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2823 (ULONGEST) dsd.insn_buf[i]);
2824 }
2825 }
2826 else
2827 {
b6542f81
YQ		 2828 dsc = NULL;
2829 }
2830
cfba9872 2831 return dsc.release ();
b6542f81
YQ		 2832}
2833
2834/* Implement the "displaced_step_fixup" gdbarch method. */
2835
2836void
2837aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 2838 struct displaced_step_closure *dsc_,
b6542f81
YQ		 2839 CORE_ADDR from, CORE_ADDR to,
2840 struct regcache *regs)
2841{
cfba9872
SM		 2842 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
2843
b6542f81
YQ		 2844 if (dsc->cond)
2845 {
2846 ULONGEST pc;
2847
2848 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2849 if (pc - to == 8)
2850 {
2851 /* Condition is true. */
2852 }
2853 else if (pc - to == 4)
2854 {
2855 /* Condition is false. */
2856 dsc->pc_adjust = 4;
2857 }
2858 else
2859 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2860 }
2861
2862 if (dsc->pc_adjust != 0)
2863 {
2864 if (debug_displaced)
2865 {
2866 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2867 paddress (gdbarch, from), dsc->pc_adjust);
2868 }
2869 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2870 from + dsc->pc_adjust);
2871 }
2872}
2873
2874/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2875
2876int
2877aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2878 struct displaced_step_closure *closure)
2879{
2880 return 1;
2881}
2882
95228a0d
AH		 2883/* Get the correct target description for the given VQ value.
2884 If VQ is zero then it is assumed SVE is not supported.
2885 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 2886
2887const target_desc *
39bfb937 2888aarch64_read_description (uint64_t vq)
da434ccb 2889{
95228a0d 2890 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 2891 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 2892 AARCH64_MAX_SVE_VQ);
2893
2894 struct target_desc *tdesc = tdesc_aarch64_list[vq];
da434ccb 2895
95228a0d
AH		 2896 if (tdesc == NULL)
2897 {
2898 tdesc = aarch64_create_target_description (vq);
2899 tdesc_aarch64_list[vq] = tdesc;
2900 }
da434ccb 2901
95228a0d 2902 return tdesc;
da434ccb
AH		 2903}
2904
ba2d2bb2
AH		 2905/* Return the VQ used when creating the target description TDESC. */
2906
1332a140 2907static uint64_t
ba2d2bb2
AH		 2908aarch64_get_tdesc_vq (const struct target_desc *tdesc)
2909{
2910 const struct tdesc_feature *feature_sve;
2911
2912 if (!tdesc_has_registers (tdesc))
2913 return 0;
2914
2915 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
2916
2917 if (feature_sve == nullptr)
2918 return 0;
2919
12863263
AH		 2920 uint64_t vl = tdesc_register_bitsize (feature_sve,
2921 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 2922 return sve_vq_from_vl (vl);
2923}
2924
0ef8a082
AH		 2925/* Add all the expected register sets into GDBARCH. */
2926
2927static void
2928aarch64_add_reggroups (struct gdbarch *gdbarch)
2929{
2930 reggroup_add (gdbarch, general_reggroup);
2931 reggroup_add (gdbarch, float_reggroup);
2932 reggroup_add (gdbarch, system_reggroup);
2933 reggroup_add (gdbarch, vector_reggroup);
2934 reggroup_add (gdbarch, all_reggroup);
2935 reggroup_add (gdbarch, save_reggroup);
2936 reggroup_add (gdbarch, restore_reggroup);
2937}
ba2d2bb2 2938
07b287a0
MS		 2939/* Initialize the current architecture based on INFO. If possible,
2940 re-use an architecture from ARCHES, which is a list of
2941 architectures already created during this debugging session.
2942
2943 Called e.g. at program startup, when reading a core file, and when
2944 reading a binary file. */
2945
2946static struct gdbarch *
2947aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2948{
2949 struct gdbarch_tdep *tdep;
2950 struct gdbarch *gdbarch;
2951 struct gdbarch_list *best_arch;
2952 struct tdesc_arch_data *tdesc_data = NULL;
2953 const struct target_desc *tdesc = info.target_desc;
2954 int i;
07b287a0 2955 int valid_p = 1;
ba2d2bb2
AH		 2956 const struct tdesc_feature *feature_core;
2957 const struct tdesc_feature *feature_fpu;
2958 const struct tdesc_feature *feature_sve;
07b287a0
MS		 2959 int num_regs = 0;
2960 int num_pseudo_regs = 0;
2961
ba2d2bb2 2962 /* Ensure we always have a target description. */
07b287a0 2963 if (!tdesc_has_registers (tdesc))
ba2d2bb2 2964 tdesc = aarch64_read_description (0);
07b287a0
MS		 2965 gdb_assert (tdesc);
2966
ba2d2bb2
AH		 2967 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2968 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2969 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
07b287a0 2970
ba2d2bb2 2971 if (feature_core == NULL)
07b287a0
MS		 2972 return NULL;
2973
2974 tdesc_data = tdesc_data_alloc ();
2975
ba2d2bb2 2976 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 2977 and allocate their numbers. */
2978 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 2979 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
2980 AARCH64_X0_REGNUM + i,
2981 aarch64_r_register_names[i]);
07b287a0
MS		 2982
2983 num_regs = AARCH64_X0_REGNUM + i;
2984
ba2d2bb2
AH		 2985 /* Add the V registers. */
2986 if (feature_fpu != NULL)
07b287a0 2987 {
ba2d2bb2
AH		 2988 if (feature_sve != NULL)
2989 error (_("Program contains both fpu and SVE features."));
2990
2991 /* Validate the description provides the mandatory V registers
2992 and allocate their numbers. */
07b287a0 2993 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 2994 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
2995 AARCH64_V0_REGNUM + i,
2996 aarch64_v_register_names[i]);
07b287a0
MS		 2997
2998 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 2999 }
07b287a0 3000
ba2d2bb2
AH		 3001 /* Add the SVE registers. */
3002 if (feature_sve != NULL)
3003 {
3004 /* Validate the description provides the mandatory SVE registers
3005 and allocate their numbers. */
3006 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3007 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3008 AARCH64_SVE_Z0_REGNUM + i,
3009 aarch64_sve_register_names[i]);
3010
3011 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3012 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3013 }
3014
3015 if (feature_fpu != NULL || feature_sve != NULL)
3016 {
07b287a0
MS		 3017 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3018 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3019 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3020 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3021 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3022 }
3023
3024 if (!valid_p)
3025 {
3026 tdesc_data_cleanup (tdesc_data);
3027 return NULL;
3028 }
3029
3030 /* AArch64 code is always little-endian. */
3031 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3032
3033 /* If there is already a candidate, use it. */
3034 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3035 best_arch != NULL;
3036 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3037 {
3038 /* Found a match. */
3039 break;
3040 }
3041
3042 if (best_arch != NULL)
3043 {
3044 if (tdesc_data != NULL)
3045 tdesc_data_cleanup (tdesc_data);
3046 return best_arch->gdbarch;
3047 }
3048
8d749320 3049 tdep = XCNEW (struct gdbarch_tdep);
07b287a0
MS		 3050 gdbarch = gdbarch_alloc (&info, tdep);
3051
3052 /* This should be low enough for everything. */
3053 tdep->lowest_pc = 0x20;
3054 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3055 tdep->jb_elt_size = 8;
ba2d2bb2 3056 tdep->vq = aarch64_get_tdesc_vq (tdesc);
07b287a0
MS		 3057
3058 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3059 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3060
07b287a0
MS		 3061 /* Advance PC across function entry code. */
3062 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3063
3064 /* The stack grows downward. */
3065 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3066
3067 /* Breakpoint manipulation. */
04180708
YQ		 3068 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3069 aarch64_breakpoint::kind_from_pc);
3070 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3071 aarch64_breakpoint::bp_from_kind);
07b287a0 3072 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3073 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3074
3075 /* Information about registers, etc. */
3076 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3077 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3078 set_gdbarch_num_regs (gdbarch, num_regs);
3079
3080 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3081 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3082 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3083 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3084 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3085 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3086 aarch64_pseudo_register_reggroup_p);
3087
3088 /* ABI */
3089 set_gdbarch_short_bit (gdbarch, 16);
3090 set_gdbarch_int_bit (gdbarch, 32);
3091 set_gdbarch_float_bit (gdbarch, 32);
3092 set_gdbarch_double_bit (gdbarch, 64);
3093 set_gdbarch_long_double_bit (gdbarch, 128);
3094 set_gdbarch_long_bit (gdbarch, 64);
3095 set_gdbarch_long_long_bit (gdbarch, 64);
3096 set_gdbarch_ptr_bit (gdbarch, 64);
3097 set_gdbarch_char_signed (gdbarch, 0);
53375380 3098 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3099 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3100 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3101 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3102
3103 /* Internal <-> external register number maps. */
3104 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3105
3106 /* Returning results. */
3107 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3108
3109 /* Disassembly. */
3110 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3111
3112 /* Virtual tables. */
3113 set_gdbarch_vbit_in_delta (gdbarch, 1);
3114
0ef8a082
AH		 3115 /* Register architecture. */
3116 aarch64_add_reggroups (gdbarch);
3117
07b287a0
MS		 3118 /* Hook in the ABI-specific overrides, if they have been registered. */
3119 info.target_desc = tdesc;
0dba2a6c 3120 info.tdesc_data = tdesc_data;
07b287a0
MS		 3121 gdbarch_init_osabi (info, gdbarch);
3122
3123 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
3124
3125 /* Add some default predicates. */
3126 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3127 dwarf2_append_unwinders (gdbarch);
3128 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3129
3130 frame_base_set_default (gdbarch, &aarch64_normal_base);
3131
3132 /* Now we have tuned the configuration, set a few final things,
3133 based on what the OS ABI has told us. */
3134
3135 if (tdep->jb_pc >= 0)
3136 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3137
ea873d8e
PL		 3138 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3139
07b287a0
MS		 3140 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3141
3142 /* Add standard register aliases. */
3143 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3144 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3145 value_of_aarch64_user_reg,
3146 &aarch64_register_aliases[i].regnum);
3147
e8bf1ce4
JB		 3148 register_aarch64_ravenscar_ops (gdbarch);
3149
07b287a0
MS		 3150 return gdbarch;
3151}
3152
3153static void
3154aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3155{
3156 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3157
3158 if (tdep == NULL)
3159 return;
3160
3161 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3162 paddress (gdbarch, tdep->lowest_pc));
3163}
3164
0d4c07af 3165#if GDB_SELF_TEST
1e2b521d
YQ		 3166namespace selftests
3167{
3168static void aarch64_process_record_test (void);
3169}
0d4c07af 3170#endif
1e2b521d 3171
07b287a0
MS		 3172void
3173_initialize_aarch64_tdep (void)
3174{
3175 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3176 aarch64_dump_tdep);
3177
07b287a0
MS		 3178 /* Debug this file's internals. */
3179 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3180Set AArch64 debugging."), _("\
3181Show AArch64 debugging."), _("\
3182When on, AArch64 specific debugging is enabled."),
3183 NULL,
3184 show_aarch64_debug,
3185 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3186
3187#if GDB_SELF_TEST
1526853e
SM		 3188 selftests::register_test ("aarch64-analyze-prologue",
3189 selftests::aarch64_analyze_prologue_test);
3190 selftests::register_test ("aarch64-process-record",
3191 selftests::aarch64_process_record_test);
6654d750 3192 selftests::record_xml_tdesc ("aarch64.xml",
95228a0d 3193 aarch64_create_target_description (0));
4d9a9006 3194#endif
07b287a0 3195}
99afc88b
OJ		 3196
3197/* AArch64 process record-replay related structures, defines etc. */
3198
99afc88b
OJ		 3199#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3200 do \
3201 { \
3202 unsigned int reg_len = LENGTH; \
3203 if (reg_len) \
3204 { \
3205 REGS = XNEWVEC (uint32_t, reg_len); \
3206 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3207 } \
3208 } \
3209 while (0)
3210
3211#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3212 do \
3213 { \
3214 unsigned int mem_len = LENGTH; \
3215 if (mem_len) \
3216 { \
3217 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3218 memcpy(&MEMS->len, &RECORD_BUF[0], \
3219 sizeof(struct aarch64_mem_r) * LENGTH); \
3220 } \
3221 } \
3222 while (0)
3223
3224/* AArch64 record/replay structures and enumerations. */
3225
3226struct aarch64_mem_r
3227{
3228 uint64_t len; /* Record length. */
3229 uint64_t addr; /* Memory address. */
3230};
3231
3232enum aarch64_record_result
3233{
3234 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3235 AARCH64_RECORD_UNSUPPORTED,
3236 AARCH64_RECORD_UNKNOWN
3237};
3238
3239typedef struct insn_decode_record_t
3240{
3241 struct gdbarch *gdbarch;
3242 struct regcache *regcache;
3243 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3244 uint32_t aarch64_insn; /* Insn to be recorded. */
3245 uint32_t mem_rec_count; /* Count of memory records. */
3246 uint32_t reg_rec_count; /* Count of register records. */
3247 uint32_t *aarch64_regs; /* Registers to be recorded. */
3248 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3249} insn_decode_record;
3250
3251/* Record handler for data processing - register instructions. */
3252
3253static unsigned int
3254aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3255{
3256 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3257 uint32_t record_buf[4];
3258
3259 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3260 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3261 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3262
3263 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3264 {
3265 uint8_t setflags;
3266
3267 /* Logical (shifted register). */
3268 if (insn_bits24_27 == 0x0a)
3269 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3270 /* Add/subtract. */
3271 else if (insn_bits24_27 == 0x0b)
3272 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3273 else
3274 return AARCH64_RECORD_UNKNOWN;
3275
3276 record_buf[0] = reg_rd;
3277 aarch64_insn_r->reg_rec_count = 1;
3278 if (setflags)
3279 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3280 }
3281 else
3282 {
3283 if (insn_bits24_27 == 0x0b)
3284 {
3285 /* Data-processing (3 source). */
3286 record_buf[0] = reg_rd;
3287 aarch64_insn_r->reg_rec_count = 1;
3288 }
3289 else if (insn_bits24_27 == 0x0a)
3290 {
3291 if (insn_bits21_23 == 0x00)
3292 {
3293 /* Add/subtract (with carry). */
3294 record_buf[0] = reg_rd;
3295 aarch64_insn_r->reg_rec_count = 1;
3296 if (bit (aarch64_insn_r->aarch64_insn, 29))
3297 {
3298 record_buf[1] = AARCH64_CPSR_REGNUM;
3299 aarch64_insn_r->reg_rec_count = 2;
3300 }
3301 }
3302 else if (insn_bits21_23 == 0x02)
3303 {
3304 /* Conditional compare (register) and conditional compare
3305 (immediate) instructions. */
3306 record_buf[0] = AARCH64_CPSR_REGNUM;
3307 aarch64_insn_r->reg_rec_count = 1;
3308 }
3309 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3310 {
3311 /* CConditional select. */
3312 /* Data-processing (2 source). */
3313 /* Data-processing (1 source). */
3314 record_buf[0] = reg_rd;
3315 aarch64_insn_r->reg_rec_count = 1;
3316 }
3317 else
3318 return AARCH64_RECORD_UNKNOWN;
3319 }
3320 }
3321
3322 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3323 record_buf);
3324 return AARCH64_RECORD_SUCCESS;
3325}
3326
3327/* Record handler for data processing - immediate instructions. */
3328
3329static unsigned int
3330aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3331{
78cc6c2d 3332 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3333 uint32_t record_buf[4];
3334
3335 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3336 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3337 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3338
3339 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3340 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3341 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3342 {
3343 record_buf[0] = reg_rd;
3344 aarch64_insn_r->reg_rec_count = 1;
3345 }
3346 else if (insn_bits24_27 == 0x01)
3347 {
3348 /* Add/Subtract (immediate). */
3349 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3350 record_buf[0] = reg_rd;
3351 aarch64_insn_r->reg_rec_count = 1;
3352 if (setflags)
3353 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3354 }
3355 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3356 {
3357 /* Logical (immediate). */
3358 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3359 record_buf[0] = reg_rd;
3360 aarch64_insn_r->reg_rec_count = 1;
3361 if (setflags)
3362 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3363 }
3364 else
3365 return AARCH64_RECORD_UNKNOWN;
3366
3367 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3368 record_buf);
3369 return AARCH64_RECORD_SUCCESS;
3370}
3371
3372/* Record handler for branch, exception generation and system instructions. */
3373
3374static unsigned int
3375aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3376{
3377 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3378 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3379 uint32_t record_buf[4];
3380
3381 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3382 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3383 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3384
3385 if (insn_bits28_31 == 0x0d)
3386 {
3387 /* Exception generation instructions. */
3388 if (insn_bits24_27 == 0x04)
3389 {
5d98d3cd
YQ		 3390 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3391 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3392 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3393 {
3394 ULONGEST svc_number;
3395
3396 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3397 &svc_number);
3398 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3399 svc_number);
3400 }
3401 else
3402 return AARCH64_RECORD_UNSUPPORTED;
3403 }
3404 /* System instructions. */
3405 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3406 {
3407 uint32_t reg_rt, reg_crn;
3408
3409 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3410 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3411
3412 /* Record rt in case of sysl and mrs instructions. */
3413 if (bit (aarch64_insn_r->aarch64_insn, 21))
3414 {
3415 record_buf[0] = reg_rt;
3416 aarch64_insn_r->reg_rec_count = 1;
3417 }
3418 /* Record cpsr for hint and msr(immediate) instructions. */
3419 else if (reg_crn == 0x02 || reg_crn == 0x04)
3420 {
3421 record_buf[0] = AARCH64_CPSR_REGNUM;
3422 aarch64_insn_r->reg_rec_count = 1;
3423 }
3424 }
3425 /* Unconditional branch (register). */
3426 else if((insn_bits24_27 & 0x0e) == 0x06)
3427 {
3428 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3429 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3430 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3431 }
3432 else
3433 return AARCH64_RECORD_UNKNOWN;
3434 }
3435 /* Unconditional branch (immediate). */
3436 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3437 {
3438 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3439 if (bit (aarch64_insn_r->aarch64_insn, 31))
3440 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3441 }
3442 else
3443 /* Compare & branch (immediate), Test & branch (immediate) and
3444 Conditional branch (immediate). */
3445 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3446
3447 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3448 record_buf);
3449 return AARCH64_RECORD_SUCCESS;
3450}
3451
3452/* Record handler for advanced SIMD load and store instructions. */
3453
3454static unsigned int
3455aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3456{
3457 CORE_ADDR address;
3458 uint64_t addr_offset = 0;
3459 uint32_t record_buf[24];
3460 uint64_t record_buf_mem[24];
3461 uint32_t reg_rn, reg_rt;
3462 uint32_t reg_index = 0, mem_index = 0;
3463 uint8_t opcode_bits, size_bits;
3464
3465 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3466 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3467 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3468 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3469 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3470
3471 if (record_debug)
b277c936 3472 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3473
3474 /* Load/store single structure. */
3475 if (bit (aarch64_insn_r->aarch64_insn, 24))
3476 {
3477 uint8_t sindex, scale, selem, esize, replicate = 0;
3478 scale = opcode_bits >> 2;
3479 selem = ((opcode_bits & 0x02) |
3480 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3481 switch (scale)
3482 {
3483 case 1:
3484 if (size_bits & 0x01)
3485 return AARCH64_RECORD_UNKNOWN;
3486 break;
3487 case 2:
3488 if ((size_bits >> 1) & 0x01)
3489 return AARCH64_RECORD_UNKNOWN;
3490 if (size_bits & 0x01)
3491 {
3492 if (!((opcode_bits >> 1) & 0x01))
3493 scale = 3;
3494 else
3495 return AARCH64_RECORD_UNKNOWN;
3496 }
3497 break;
3498 case 3:
3499 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3500 {
3501 scale = size_bits;
3502 replicate = 1;
3503 break;
3504 }
3505 else
3506 return AARCH64_RECORD_UNKNOWN;
3507 default:
3508 break;
3509 }
3510 esize = 8 << scale;
3511 if (replicate)
3512 for (sindex = 0; sindex < selem; sindex++)
3513 {
3514 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3515 reg_rt = (reg_rt + 1) % 32;
3516 }
3517 else
3518 {
3519 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3520 {
3521 if (bit (aarch64_insn_r->aarch64_insn, 22))
3522 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3523 else
3524 {
3525 record_buf_mem[mem_index++] = esize / 8;
3526 record_buf_mem[mem_index++] = address + addr_offset;
3527 }
3528 addr_offset = addr_offset + (esize / 8);
3529 reg_rt = (reg_rt + 1) % 32;
3530 }
99afc88b
OJ		 3531 }
3532 }
3533 /* Load/store multiple structure. */
3534 else
3535 {
3536 uint8_t selem, esize, rpt, elements;
3537 uint8_t eindex, rindex;
3538
3539 esize = 8 << size_bits;
3540 if (bit (aarch64_insn_r->aarch64_insn, 30))
3541 elements = 128 / esize;
3542 else
3543 elements = 64 / esize;
3544
3545 switch (opcode_bits)
3546 {
3547 /*LD/ST4 (4 Registers). */
3548 case 0:
3549 rpt = 1;
3550 selem = 4;
3551 break;
3552 /*LD/ST1 (4 Registers). */
3553 case 2:
3554 rpt = 4;
3555 selem = 1;
3556 break;
3557 /*LD/ST3 (3 Registers). */
3558 case 4:
3559 rpt = 1;
3560 selem = 3;
3561 break;
3562 /*LD/ST1 (3 Registers). */
3563 case 6:
3564 rpt = 3;
3565 selem = 1;
3566 break;
3567 /*LD/ST1 (1 Register). */
3568 case 7:
3569 rpt = 1;
3570 selem = 1;
3571 break;
3572 /*LD/ST2 (2 Registers). */
3573 case 8:
3574 rpt = 1;
3575 selem = 2;
3576 break;
3577 /*LD/ST1 (2 Registers). */
3578 case 10:
3579 rpt = 2;
3580 selem = 1;
3581 break;
3582 default:
3583 return AARCH64_RECORD_UNSUPPORTED;
3584 break;
3585 }
3586 for (rindex = 0; rindex < rpt; rindex++)
3587 for (eindex = 0; eindex < elements; eindex++)
3588 {
3589 uint8_t reg_tt, sindex;
3590 reg_tt = (reg_rt + rindex) % 32;
3591 for (sindex = 0; sindex < selem; sindex++)
3592 {
3593 if (bit (aarch64_insn_r->aarch64_insn, 22))
3594 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3595 else
3596 {
3597 record_buf_mem[mem_index++] = esize / 8;
3598 record_buf_mem[mem_index++] = address + addr_offset;
3599 }
3600 addr_offset = addr_offset + (esize / 8);
3601 reg_tt = (reg_tt + 1) % 32;
3602 }
3603 }
3604 }
3605
3606 if (bit (aarch64_insn_r->aarch64_insn, 23))
3607 record_buf[reg_index++] = reg_rn;
3608
3609 aarch64_insn_r->reg_rec_count = reg_index;
3610 aarch64_insn_r->mem_rec_count = mem_index / 2;
3611 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3612 record_buf_mem);
3613 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3614 record_buf);
3615 return AARCH64_RECORD_SUCCESS;
3616}
3617
3618/* Record handler for load and store instructions. */
3619
3620static unsigned int
3621aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3622{
3623 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3624 uint8_t insn_bit23, insn_bit21;
3625 uint8_t opc, size_bits, ld_flag, vector_flag;
3626 uint32_t reg_rn, reg_rt, reg_rt2;
3627 uint64_t datasize, offset;
3628 uint32_t record_buf[8];
3629 uint64_t record_buf_mem[8];
3630 CORE_ADDR address;
3631
3632 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3633 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3634 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3635 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3636 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3637 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3638 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3639 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3640 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3641 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3642 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3643
3644 /* Load/store exclusive. */
3645 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3646 {
3647 if (record_debug)
b277c936 3648 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3649
3650 if (ld_flag)
3651 {
3652 record_buf[0] = reg_rt;
3653 aarch64_insn_r->reg_rec_count = 1;
3654 if (insn_bit21)
3655 {
3656 record_buf[1] = reg_rt2;
3657 aarch64_insn_r->reg_rec_count = 2;
3658 }
3659 }
3660 else
3661 {
3662 if (insn_bit21)
3663 datasize = (8 << size_bits) * 2;
3664 else
3665 datasize = (8 << size_bits);
3666 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3667 &address);
3668 record_buf_mem[0] = datasize / 8;
3669 record_buf_mem[1] = address;
3670 aarch64_insn_r->mem_rec_count = 1;
3671 if (!insn_bit23)
3672 {
3673 /* Save register rs. */
3674 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3675 aarch64_insn_r->reg_rec_count = 1;
3676 }
3677 }
3678 }
3679 /* Load register (literal) instructions decoding. */
3680 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3681 {
3682 if (record_debug)
b277c936 3683 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3684 if (vector_flag)
3685 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3686 else
3687 record_buf[0] = reg_rt;
3688 aarch64_insn_r->reg_rec_count = 1;
3689 }
3690 /* All types of load/store pair instructions decoding. */
3691 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3692 {
3693 if (record_debug)
b277c936 3694 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 3695
3696 if (ld_flag)
3697 {
3698 if (vector_flag)
3699 {
3700 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3701 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3702 }
3703 else
3704 {
3705 record_buf[0] = reg_rt;
3706 record_buf[1] = reg_rt2;
3707 }
3708 aarch64_insn_r->reg_rec_count = 2;
3709 }
3710 else
3711 {
3712 uint16_t imm7_off;
3713 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3714 if (!vector_flag)
3715 size_bits = size_bits >> 1;
3716 datasize = 8 << (2 + size_bits);
3717 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3718 offset = offset << (2 + size_bits);
3719 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3720 &address);
3721 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3722 {
3723 if (imm7_off & 0x40)
3724 address = address - offset;
3725 else
3726 address = address + offset;
3727 }
3728
3729 record_buf_mem[0] = datasize / 8;
3730 record_buf_mem[1] = address;
3731 record_buf_mem[2] = datasize / 8;
3732 record_buf_mem[3] = address + (datasize / 8);
3733 aarch64_insn_r->mem_rec_count = 2;
3734 }
3735 if (bit (aarch64_insn_r->aarch64_insn, 23))
3736 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3737 }
3738 /* Load/store register (unsigned immediate) instructions. */
3739 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3740 {
3741 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3742 if (!(opc >> 1))
33877125
YQ		 3743 {
3744 if (opc & 0x01)
3745 ld_flag = 0x01;
3746 else
3747 ld_flag = 0x0;
3748 }
99afc88b 3749 else
33877125 3750 {
1e2b521d
YQ		 3751 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3752 {
3753 /* PRFM (immediate) */
3754 return AARCH64_RECORD_SUCCESS;
3755 }
3756 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3757 {
3758 /* LDRSW (immediate) */
3759 ld_flag = 0x1;
3760 }
33877125 3761 else
1e2b521d
YQ		 3762 {
3763 if (opc & 0x01)
3764 ld_flag = 0x01;
3765 else
3766 ld_flag = 0x0;
3767 }
33877125 3768 }
99afc88b
OJ		 3769
3770 if (record_debug)
3771 {
b277c936
PL		 3772 debug_printf ("Process record: load/store (unsigned immediate):"
3773 " size %x V %d opc %x\n", size_bits, vector_flag,
3774 opc);
99afc88b
OJ		 3775 }
3776
3777 if (!ld_flag)
3778 {
3779 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3780 datasize = 8 << size_bits;
3781 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3782 &address);
3783 offset = offset << size_bits;
3784 address = address + offset;
3785
3786 record_buf_mem[0] = datasize >> 3;
3787 record_buf_mem[1] = address;
3788 aarch64_insn_r->mem_rec_count = 1;
3789 }
3790 else
3791 {
3792 if (vector_flag)
3793 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3794 else
3795 record_buf[0] = reg_rt;
3796 aarch64_insn_r->reg_rec_count = 1;
3797 }
3798 }
3799 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 3800 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3801 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 3802 {
3803 if (record_debug)
b277c936 3804 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 3805 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3806 if (!(opc >> 1))
3807 if (opc & 0x01)
3808 ld_flag = 0x01;
3809 else
3810 ld_flag = 0x0;
3811 else
3812 if (size_bits != 0x03)
3813 ld_flag = 0x01;
3814 else
3815 return AARCH64_RECORD_UNKNOWN;
3816
3817 if (!ld_flag)
3818 {
d9436c7c
PA		 3819 ULONGEST reg_rm_val;
3820
99afc88b
OJ		 3821 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3822 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
3823 if (bit (aarch64_insn_r->aarch64_insn, 12))
3824 offset = reg_rm_val << size_bits;
3825 else
3826 offset = reg_rm_val;
3827 datasize = 8 << size_bits;
3828 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3829 &address);
3830 address = address + offset;
3831 record_buf_mem[0] = datasize >> 3;
3832 record_buf_mem[1] = address;
3833 aarch64_insn_r->mem_rec_count = 1;
3834 }
3835 else
3836 {
3837 if (vector_flag)
3838 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3839 else
3840 record_buf[0] = reg_rt;
3841 aarch64_insn_r->reg_rec_count = 1;
3842 }
3843 }
3844 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 3845 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3846 && !insn_bit21)
99afc88b
OJ		 3847 {
3848 if (record_debug)
3849 {
b277c936
PL		 3850 debug_printf ("Process record: load/store "
3851 "(immediate and unprivileged)\n");
99afc88b
OJ		 3852 }
3853 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3854 if (!(opc >> 1))
3855 if (opc & 0x01)
3856 ld_flag = 0x01;
3857 else
3858 ld_flag = 0x0;
3859 else
3860 if (size_bits != 0x03)
3861 ld_flag = 0x01;
3862 else
3863 return AARCH64_RECORD_UNKNOWN;
3864
3865 if (!ld_flag)
3866 {
3867 uint16_t imm9_off;
3868 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3869 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3870 datasize = 8 << size_bits;
3871 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3872 &address);
3873 if (insn_bits10_11 != 0x01)
3874 {
3875 if (imm9_off & 0x0100)
3876 address = address - offset;
3877 else
3878 address = address + offset;
3879 }
3880 record_buf_mem[0] = datasize >> 3;
3881 record_buf_mem[1] = address;
3882 aarch64_insn_r->mem_rec_count = 1;
3883 }
3884 else
3885 {
3886 if (vector_flag)
3887 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3888 else
3889 record_buf[0] = reg_rt;
3890 aarch64_insn_r->reg_rec_count = 1;
3891 }
3892 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3893 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3894 }
3895 /* Advanced SIMD load/store instructions. */
3896 else
3897 return aarch64_record_asimd_load_store (aarch64_insn_r);
3898
3899 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3900 record_buf_mem);
3901 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3902 record_buf);
3903 return AARCH64_RECORD_SUCCESS;
3904}
3905
3906/* Record handler for data processing SIMD and floating point instructions. */
3907
3908static unsigned int
3909aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3910{
3911 uint8_t insn_bit21, opcode, rmode, reg_rd;
3912 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3913 uint8_t insn_bits11_14;
3914 uint32_t record_buf[2];
3915
3916 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3917 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3918 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3919 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3920 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3921 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3922 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3923 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3924 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3925
3926 if (record_debug)
b277c936 3927 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 3928
3929 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3930 {
3931 /* Floating point - fixed point conversion instructions. */
3932 if (!insn_bit21)
3933 {
3934 if (record_debug)
b277c936 3935 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 3936
3937 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3938 record_buf[0] = reg_rd;
3939 else
3940 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3941 }
3942 /* Floating point - conditional compare instructions. */
3943 else if (insn_bits10_11 == 0x01)
3944 {
3945 if (record_debug)
b277c936 3946 debug_printf ("FP - conditional compare");
99afc88b
OJ		 3947
3948 record_buf[0] = AARCH64_CPSR_REGNUM;
3949 }
3950 /* Floating point - data processing (2-source) and
3951 conditional select instructions. */
3952 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3953 {
3954 if (record_debug)
b277c936 3955 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 3956
3957 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3958 }
3959 else if (insn_bits10_11 == 0x00)
3960 {
3961 /* Floating point - immediate instructions. */
3962 if ((insn_bits12_15 & 0x01) == 0x01
3963 || (insn_bits12_15 & 0x07) == 0x04)
3964 {
3965 if (record_debug)
b277c936 3966 debug_printf ("FP - immediate");
99afc88b
OJ		 3967 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3968 }
3969 /* Floating point - compare instructions. */
3970 else if ((insn_bits12_15 & 0x03) == 0x02)
3971 {
3972 if (record_debug)
b277c936 3973 debug_printf ("FP - immediate");
99afc88b
OJ		 3974 record_buf[0] = AARCH64_CPSR_REGNUM;
3975 }
3976 /* Floating point - integer conversions instructions. */
f62fce35 3977 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 3978 {
3979 /* Convert float to integer instruction. */
3980 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3981 {
3982 if (record_debug)
b277c936 3983 debug_printf ("float to int conversion");
99afc88b
OJ		 3984
3985 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3986 }
3987 /* Convert integer to float instruction. */
3988 else if ((opcode >> 1) == 0x01 && !rmode)
3989 {
3990 if (record_debug)
b277c936 3991 debug_printf ("int to float conversion");
99afc88b
OJ		 3992
3993 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3994 }
3995 /* Move float to integer instruction. */
3996 else if ((opcode >> 1) == 0x03)
3997 {
3998 if (record_debug)
b277c936 3999 debug_printf ("move float to int");
99afc88b
OJ		 4000
4001 if (!(opcode & 0x01))
4002 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4003 else
4004 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4005 }
f62fce35
YQ		 4006 else
4007 return AARCH64_RECORD_UNKNOWN;
99afc88b 4008 }
f62fce35
YQ		 4009 else
4010 return AARCH64_RECORD_UNKNOWN;
99afc88b 4011 }
f62fce35
YQ		 4012 else
4013 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4014 }
4015 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4016 {
4017 if (record_debug)
b277c936 4018 debug_printf ("SIMD copy");
99afc88b
OJ		 4019
4020 /* Advanced SIMD copy instructions. */
4021 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4022 && !bit (aarch64_insn_r->aarch64_insn, 15)
4023 && bit (aarch64_insn_r->aarch64_insn, 10))
4024 {
4025 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4026 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4027 else
4028 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4029 }
4030 else
4031 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4032 }
4033 /* All remaining floating point or advanced SIMD instructions. */
4034 else
4035 {
4036 if (record_debug)
b277c936 4037 debug_printf ("all remain");
99afc88b
OJ		 4038
4039 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4040 }
4041
4042 if (record_debug)
b277c936 4043 debug_printf ("\n");
99afc88b
OJ		 4044
4045 aarch64_insn_r->reg_rec_count++;
4046 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4047 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4048 record_buf);
4049 return AARCH64_RECORD_SUCCESS;
4050}
4051
4052/* Decodes insns type and invokes its record handler. */
4053
4054static unsigned int
4055aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4056{
4057 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4058
4059 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4060 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4061 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4062 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4063
4064 /* Data processing - immediate instructions. */
4065 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4066 return aarch64_record_data_proc_imm (aarch64_insn_r);
4067
4068 /* Branch, exception generation and system instructions. */
4069 if (ins_bit26 && !ins_bit27 && ins_bit28)
4070 return aarch64_record_branch_except_sys (aarch64_insn_r);
4071
4072 /* Load and store instructions. */
4073 if (!ins_bit25 && ins_bit27)
4074 return aarch64_record_load_store (aarch64_insn_r);
4075
4076 /* Data processing - register instructions. */
4077 if (ins_bit25 && !ins_bit26 && ins_bit27)
4078 return aarch64_record_data_proc_reg (aarch64_insn_r);
4079
4080 /* Data processing - SIMD and floating point instructions. */
4081 if (ins_bit25 && ins_bit26 && ins_bit27)
4082 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4083
4084 return AARCH64_RECORD_UNSUPPORTED;
4085}
4086
4087/* Cleans up local record registers and memory allocations. */
4088
4089static void
4090deallocate_reg_mem (insn_decode_record *record)
4091{
4092 xfree (record->aarch64_regs);
4093 xfree (record->aarch64_mems);
4094}
4095
1e2b521d
YQ		 4096#if GDB_SELF_TEST
4097namespace selftests {
4098
4099static void
4100aarch64_process_record_test (void)
4101{
4102 struct gdbarch_info info;
4103 uint32_t ret;
4104
4105 gdbarch_info_init (&info);
4106 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4107
4108 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4109 SELF_CHECK (gdbarch != NULL);
4110
4111 insn_decode_record aarch64_record;
4112
4113 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4114 aarch64_record.regcache = NULL;
4115 aarch64_record.this_addr = 0;
4116 aarch64_record.gdbarch = gdbarch;
4117
4118 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4119 aarch64_record.aarch64_insn = 0xf9800020;
4120 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4121 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4122 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4123 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4124
4125 deallocate_reg_mem (&aarch64_record);
4126}
4127
4128} // namespace selftests
4129#endif /* GDB_SELF_TEST */
4130
99afc88b
OJ		 4131/* Parse the current instruction and record the values of the registers and
4132 memory that will be changed in current instruction to record_arch_list
4133 return -1 if something is wrong. */
4134
4135int
4136aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4137 CORE_ADDR insn_addr)
4138{
4139 uint32_t rec_no = 0;
4140 uint8_t insn_size = 4;
4141 uint32_t ret = 0;
99afc88b
OJ		 4142 gdb_byte buf[insn_size];
4143 insn_decode_record aarch64_record;
4144
4145 memset (&buf[0], 0, insn_size);
4146 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4147 target_read_memory (insn_addr, &buf[0], insn_size);
4148 aarch64_record.aarch64_insn
4149 = (uint32_t) extract_unsigned_integer (&buf[0],
4150 insn_size,
4151 gdbarch_byte_order (gdbarch));
4152 aarch64_record.regcache = regcache;
4153 aarch64_record.this_addr = insn_addr;
4154 aarch64_record.gdbarch = gdbarch;
4155
4156 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4157 if (ret == AARCH64_RECORD_UNSUPPORTED)
4158 {
4159 printf_unfiltered (_("Process record does not support instruction "
4160 "0x%0x at address %s.\n"),
4161 aarch64_record.aarch64_insn,
4162 paddress (gdbarch, insn_addr));
4163 ret = -1;
4164 }
4165
4166 if (0 == ret)
4167 {
4168 /* Record registers. */
4169 record_full_arch_list_add_reg (aarch64_record.regcache,
4170 AARCH64_PC_REGNUM);
4171 /* Always record register CPSR. */
4172 record_full_arch_list_add_reg (aarch64_record.regcache,
4173 AARCH64_CPSR_REGNUM);
4174 if (aarch64_record.aarch64_regs)
4175 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4176 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4177 aarch64_record.aarch64_regs[rec_no]))
4178 ret = -1;
4179
4180 /* Record memories. */
4181 if (aarch64_record.aarch64_mems)
4182 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4183 if (record_full_arch_list_add_mem
4184 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4185 aarch64_record.aarch64_mems[rec_no].len))
4186 ret = -1;
4187
4188 if (record_full_arch_list_add_end ())
4189 ret = -1;
4190 }
4191
4192 deallocate_reg_mem (&aarch64_record);
4193 return ret;
4194}
GDB Binutils - Deliverables
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