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Arm: Clean up PE GAS testsuite correct THUMB tests.
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
42a4f53d 3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
24#include "inferior.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
07b287a0
MS		 27#include "dis-asm.h"
28#include "regcache.h"
29#include "reggroups.h"
07b287a0
MS		 30#include "value.h"
31#include "arch-utils.h"
32#include "osabi.h"
33#include "frame-unwind.h"
34#include "frame-base.h"
35#include "trad-frame.h"
36#include "objfiles.h"
37#include "dwarf2-frame.h"
38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
41#include "user-regs.h"
42#include "language.h"
43#include "infcall.h"
ea873d8e
PL		 44#include "ax.h"
45#include "ax-gdb.h"
4d9a9006 46#include "selftest.h"
07b287a0
MS		 47
48#include "aarch64-tdep.h"
e8bf1ce4 49#include "aarch64-ravenscar-thread.h"
07b287a0
MS		 50
51#include "elf-bfd.h"
52#include "elf/aarch64.h"
53
07b287a0
MS		 54#include "vec.h"
55
99afc88b
OJ		 56#include "record.h"
57#include "record-full.h"
787749ea
PL		 58#include "arch/aarch64-insn.h"
59
f77ee802 60#include "opcode/aarch64.h"
325fac50 61#include <algorithm>
f77ee802
YQ		 62
63#define submask(x) ((1L << ((x) + 1)) - 1)
64#define bit(obj,st) (((obj) >> (st)) & 1)
65#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
66
ea92689a
AH		 67/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
68 four members. */
69#define HA_MAX_NUM_FLDS 4
70
95228a0d
AH		 71/* All possible aarch64 target descriptors. */
72struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1];
73
07b287a0
MS		 74/* The standard register names, and all the valid aliases for them. */
75static const struct
76{
77 const char *const name;
78 int regnum;
79} aarch64_register_aliases[] =
80{
81 /* 64-bit register names. */
82 {"fp", AARCH64_FP_REGNUM},
83 {"lr", AARCH64_LR_REGNUM},
84 {"sp", AARCH64_SP_REGNUM},
85
86 /* 32-bit register names. */
87 {"w0", AARCH64_X0_REGNUM + 0},
88 {"w1", AARCH64_X0_REGNUM + 1},
89 {"w2", AARCH64_X0_REGNUM + 2},
90 {"w3", AARCH64_X0_REGNUM + 3},
91 {"w4", AARCH64_X0_REGNUM + 4},
92 {"w5", AARCH64_X0_REGNUM + 5},
93 {"w6", AARCH64_X0_REGNUM + 6},
94 {"w7", AARCH64_X0_REGNUM + 7},
95 {"w8", AARCH64_X0_REGNUM + 8},
96 {"w9", AARCH64_X0_REGNUM + 9},
97 {"w10", AARCH64_X0_REGNUM + 10},
98 {"w11", AARCH64_X0_REGNUM + 11},
99 {"w12", AARCH64_X0_REGNUM + 12},
100 {"w13", AARCH64_X0_REGNUM + 13},
101 {"w14", AARCH64_X0_REGNUM + 14},
102 {"w15", AARCH64_X0_REGNUM + 15},
103 {"w16", AARCH64_X0_REGNUM + 16},
104 {"w17", AARCH64_X0_REGNUM + 17},
105 {"w18", AARCH64_X0_REGNUM + 18},
106 {"w19", AARCH64_X0_REGNUM + 19},
107 {"w20", AARCH64_X0_REGNUM + 20},
108 {"w21", AARCH64_X0_REGNUM + 21},
109 {"w22", AARCH64_X0_REGNUM + 22},
110 {"w23", AARCH64_X0_REGNUM + 23},
111 {"w24", AARCH64_X0_REGNUM + 24},
112 {"w25", AARCH64_X0_REGNUM + 25},
113 {"w26", AARCH64_X0_REGNUM + 26},
114 {"w27", AARCH64_X0_REGNUM + 27},
115 {"w28", AARCH64_X0_REGNUM + 28},
116 {"w29", AARCH64_X0_REGNUM + 29},
117 {"w30", AARCH64_X0_REGNUM + 30},
118
119 /* specials */
120 {"ip0", AARCH64_X0_REGNUM + 16},
121 {"ip1", AARCH64_X0_REGNUM + 17}
122};
123
124/* The required core 'R' registers. */
125static const char *const aarch64_r_register_names[] =
126{
127 /* These registers must appear in consecutive RAW register number
128 order and they must begin with AARCH64_X0_REGNUM! */
129 "x0", "x1", "x2", "x3",
130 "x4", "x5", "x6", "x7",
131 "x8", "x9", "x10", "x11",
132 "x12", "x13", "x14", "x15",
133 "x16", "x17", "x18", "x19",
134 "x20", "x21", "x22", "x23",
135 "x24", "x25", "x26", "x27",
136 "x28", "x29", "x30", "sp",
137 "pc", "cpsr"
138};
139
140/* The FP/SIMD 'V' registers. */
141static const char *const aarch64_v_register_names[] =
142{
143 /* These registers must appear in consecutive RAW register number
144 order and they must begin with AARCH64_V0_REGNUM! */
145 "v0", "v1", "v2", "v3",
146 "v4", "v5", "v6", "v7",
147 "v8", "v9", "v10", "v11",
148 "v12", "v13", "v14", "v15",
149 "v16", "v17", "v18", "v19",
150 "v20", "v21", "v22", "v23",
151 "v24", "v25", "v26", "v27",
152 "v28", "v29", "v30", "v31",
153 "fpsr",
154 "fpcr"
155};
156
739e8682
AH		 157/* The SVE 'Z' and 'P' registers. */
158static const char *const aarch64_sve_register_names[] =
159{
160 /* These registers must appear in consecutive RAW register number
161 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
162 "z0", "z1", "z2", "z3",
163 "z4", "z5", "z6", "z7",
164 "z8", "z9", "z10", "z11",
165 "z12", "z13", "z14", "z15",
166 "z16", "z17", "z18", "z19",
167 "z20", "z21", "z22", "z23",
168 "z24", "z25", "z26", "z27",
169 "z28", "z29", "z30", "z31",
170 "fpsr", "fpcr",
171 "p0", "p1", "p2", "p3",
172 "p4", "p5", "p6", "p7",
173 "p8", "p9", "p10", "p11",
174 "p12", "p13", "p14", "p15",
175 "ffr", "vg"
176};
177
07b287a0
MS		 178/* AArch64 prologue cache structure. */
179struct aarch64_prologue_cache
180{
db634143
PL		 181 /* The program counter at the start of the function. It is used to
182 identify this frame as a prologue frame. */
183 CORE_ADDR func;
184
185 /* The program counter at the time this frame was created; i.e. where
186 this function was called from. It is used to identify this frame as a
187 stub frame. */
188 CORE_ADDR prev_pc;
189
07b287a0
MS		 190 /* The stack pointer at the time this frame was created; i.e. the
191 caller's stack pointer when this function was called. It is used
192 to identify this frame. */
193 CORE_ADDR prev_sp;
194
7dfa3edc
PL		 195 /* Is the target available to read from? */
196 int available_p;
197
07b287a0
MS		 198 /* The frame base for this frame is just prev_sp - frame size.
199 FRAMESIZE is the distance from the frame pointer to the
200 initial stack pointer. */
201 int framesize;
202
203 /* The register used to hold the frame pointer for this frame. */
204 int framereg;
205
206 /* Saved register offsets. */
207 struct trad_frame_saved_reg *saved_regs;
208};
209
07b287a0
MS		 210static void
211show_aarch64_debug (struct ui_file *file, int from_tty,
212 struct cmd_list_element *c, const char *value)
213{
214 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
215}
216
ffdbe864
YQ		 217namespace {
218
4d9a9006
YQ		 219/* Abstract instruction reader. */
220
221class abstract_instruction_reader
222{
223public:
224 /* Read in one instruction. */
225 virtual ULONGEST read (CORE_ADDR memaddr, int len,
226 enum bfd_endian byte_order) = 0;
227};
228
229/* Instruction reader from real target. */
230
231class instruction_reader : public abstract_instruction_reader
232{
233 public:
234 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 235 override
4d9a9006 236 {
fc2f703e 237 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 238 }
239};
240
ffdbe864
YQ		 241} // namespace
242
07b287a0
MS		 243/* Analyze a prologue, looking for a recognizable stack frame
244 and frame pointer. Scan until we encounter a store that could
245 clobber the stack frame unexpectedly, or an unknown instruction. */
246
247static CORE_ADDR
248aarch64_analyze_prologue (struct gdbarch *gdbarch,
249 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 250 struct aarch64_prologue_cache *cache,
251 abstract_instruction_reader& reader)
07b287a0
MS		 252{
253 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
254 int i;
187f5d00
YQ		 255 /* Track X registers and D registers in prologue. */
256 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 257
187f5d00 258 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 259 regs[i] = pv_register (i, 0);
f7b7ed97 260 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 261
262 for (; start < limit; start += 4)
263 {
264 uint32_t insn;
d9ebcbce 265 aarch64_inst inst;
07b287a0 266
4d9a9006 267 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 268
561a72d4 269 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 270 break;
271
272 if (inst.opcode->iclass == addsub_imm
273 && (inst.opcode->op == OP_ADD
274 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 275 {
d9ebcbce
YQ		 276 unsigned rd = inst.operands[0].reg.regno;
277 unsigned rn = inst.operands[1].reg.regno;
278
279 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
280 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
281 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
282 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
283
284 if (inst.opcode->op == OP_ADD)
285 {
286 regs[rd] = pv_add_constant (regs[rn],
287 inst.operands[2].imm.value);
288 }
289 else
290 {
291 regs[rd] = pv_add_constant (regs[rn],
292 -inst.operands[2].imm.value);
293 }
294 }
295 else if (inst.opcode->iclass == pcreladdr
296 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
297 {
298 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
299 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
300
301 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 302 }
d9ebcbce 303 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 304 {
305 /* Stop analysis on branch. */
306 break;
307 }
d9ebcbce 308 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 309 {
310 /* Stop analysis on branch. */
311 break;
312 }
d9ebcbce 313 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 314 {
315 /* Stop analysis on branch. */
316 break;
317 }
d9ebcbce 318 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 319 {
320 /* Stop analysis on branch. */
321 break;
322 }
d9ebcbce
YQ		 323 else if (inst.opcode->op == OP_MOVZ)
324 {
325 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
326 regs[inst.operands[0].reg.regno] = pv_unknown ();
327 }
328 else if (inst.opcode->iclass == log_shift
329 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 330 {
d9ebcbce
YQ		 331 unsigned rd = inst.operands[0].reg.regno;
332 unsigned rn = inst.operands[1].reg.regno;
333 unsigned rm = inst.operands[2].reg.regno;
334
335 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
336 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
337 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
338
339 if (inst.operands[2].shifter.amount == 0
340 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 341 regs[rd] = regs[rm];
342 else
343 {
344 if (aarch64_debug)
b277c936
PL		 345 {
346 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 347 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 348 core_addr_to_string_nz (start), insn);
349 }
07b287a0
MS		 350 break;
351 }
352 }
d9ebcbce 353 else if (inst.opcode->op == OP_STUR)
07b287a0 354 {
d9ebcbce
YQ		 355 unsigned rt = inst.operands[0].reg.regno;
356 unsigned rn = inst.operands[1].addr.base_regno;
357 int is64
358 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
359
360 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
361 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
362 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
363 gdb_assert (!inst.operands[1].addr.offset.is_reg);
364
f7b7ed97
TT		 365 stack.store (pv_add_constant (regs[rn],
366 inst.operands[1].addr.offset.imm),
367 is64 ? 8 : 4, regs[rt]);
07b287a0 368 }
d9ebcbce 369 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 370 || (inst.opcode->iclass == ldstpair_indexed
371 && inst.operands[2].addr.preind))
d9ebcbce 372 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 373 {
03bcd739 374 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 375 unsigned rt1;
376 unsigned rt2;
d9ebcbce
YQ		 377 unsigned rn = inst.operands[2].addr.base_regno;
378 int32_t imm = inst.operands[2].addr.offset.imm;
379
187f5d00
YQ		 380 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
381 || inst.operands[0].type == AARCH64_OPND_Ft);
382 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
383 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 384 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
385 gdb_assert (!inst.operands[2].addr.offset.is_reg);
386
07b287a0
MS		 387 /* If recording this store would invalidate the store area
388 (perhaps because rn is not known) then we should abandon
389 further prologue analysis. */
f7b7ed97 390 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 391 break;
392
f7b7ed97 393 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 394 break;
395
187f5d00
YQ		 396 rt1 = inst.operands[0].reg.regno;
397 rt2 = inst.operands[1].reg.regno;
398 if (inst.operands[0].type == AARCH64_OPND_Ft)
399 {
400 /* Only bottom 64-bit of each V register (D register) need
401 to be preserved. */
402 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
403 rt1 += AARCH64_X_REGISTER_COUNT;
404 rt2 += AARCH64_X_REGISTER_COUNT;
405 }
406
f7b7ed97
TT		 407 stack.store (pv_add_constant (regs[rn], imm), 8,
408 regs[rt1]);
409 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
410 regs[rt2]);
14ac654f 411
d9ebcbce 412 if (inst.operands[2].addr.writeback)
93d96012 413 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 414
07b287a0 415 }
432ec081
YQ		 416 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
417 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
418 && (inst.opcode->op == OP_STR_POS
419 || inst.opcode->op == OP_STRF_POS)))
420 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
421 && strcmp ("str", inst.opcode->name) == 0)
422 {
423 /* STR (immediate) */
424 unsigned int rt = inst.operands[0].reg.regno;
425 int32_t imm = inst.operands[1].addr.offset.imm;
426 unsigned int rn = inst.operands[1].addr.base_regno;
427 bool is64
428 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
429 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
430 || inst.operands[0].type == AARCH64_OPND_Ft);
431
432 if (inst.operands[0].type == AARCH64_OPND_Ft)
433 {
434 /* Only bottom 64-bit of each V register (D register) need
435 to be preserved. */
436 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
437 rt += AARCH64_X_REGISTER_COUNT;
438 }
439
f7b7ed97
TT		 440 stack.store (pv_add_constant (regs[rn], imm),
441 is64 ? 8 : 4, regs[rt]);
432ec081
YQ		 442 if (inst.operands[1].addr.writeback)
443 regs[rn] = pv_add_constant (regs[rn], imm);
444 }
d9ebcbce 445 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 446 {
447 /* Stop analysis on branch. */
448 break;
449 }
450 else
451 {
452 if (aarch64_debug)
b277c936 453 {
0a0da556 454 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 455 " opcode=0x%x\n",
456 core_addr_to_string_nz (start), insn);
457 }
07b287a0
MS		 458 break;
459 }
460 }
461
462 if (cache == NULL)
f7b7ed97 463 return start;
07b287a0
MS		 464
465 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
466 {
467 /* Frame pointer is fp. Frame size is constant. */
468 cache->framereg = AARCH64_FP_REGNUM;
469 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
470 }
471 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
472 {
473 /* Try the stack pointer. */
474 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
475 cache->framereg = AARCH64_SP_REGNUM;
476 }
477 else
478 {
479 /* We're just out of luck. We don't know where the frame is. */
480 cache->framereg = -1;
481 cache->framesize = 0;
482 }
483
484 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
485 {
486 CORE_ADDR offset;
487
f7b7ed97 488 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 489 cache->saved_regs[i].addr = offset;
490 }
491
187f5d00
YQ		 492 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
493 {
494 int regnum = gdbarch_num_regs (gdbarch);
495 CORE_ADDR offset;
496
f7b7ed97
TT		 497 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
498 &offset))
187f5d00
YQ		 499 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
500 }
501
07b287a0
MS		 502 return start;
503}
504
4d9a9006
YQ		 505static CORE_ADDR
506aarch64_analyze_prologue (struct gdbarch *gdbarch,
507 CORE_ADDR start, CORE_ADDR limit,
508 struct aarch64_prologue_cache *cache)
509{
510 instruction_reader reader;
511
512 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
513 reader);
514}
515
516#if GDB_SELF_TEST
517
518namespace selftests {
519
520/* Instruction reader from manually cooked instruction sequences. */
521
522class instruction_reader_test : public abstract_instruction_reader
523{
524public:
525 template<size_t SIZE>
526 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
527 : m_insns (insns), m_insns_size (SIZE)
528 {}
529
530 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 531 override
4d9a9006
YQ		 532 {
533 SELF_CHECK (len == 4);
534 SELF_CHECK (memaddr % 4 == 0);
535 SELF_CHECK (memaddr / 4 < m_insns_size);
536
537 return m_insns[memaddr / 4];
538 }
539
540private:
541 const uint32_t *m_insns;
542 size_t m_insns_size;
543};
544
545static void
546aarch64_analyze_prologue_test (void)
547{
548 struct gdbarch_info info;
549
550 gdbarch_info_init (&info);
551 info.bfd_arch_info = bfd_scan_arch ("aarch64");
552
553 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
554 SELF_CHECK (gdbarch != NULL);
555
556 /* Test the simple prologue in which frame pointer is used. */
557 {
558 struct aarch64_prologue_cache cache;
559 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
560
561 static const uint32_t insns[] = {
562 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
563 0x910003fd, /* mov x29, sp */
564 0x97ffffe6, /* bl 0x400580 */
565 };
566 instruction_reader_test reader (insns);
567
568 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
569 SELF_CHECK (end == 4 * 2);
570
571 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
572 SELF_CHECK (cache.framesize == 272);
573
574 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
575 {
576 if (i == AARCH64_FP_REGNUM)
577 SELF_CHECK (cache.saved_regs[i].addr == -272);
578 else if (i == AARCH64_LR_REGNUM)
579 SELF_CHECK (cache.saved_regs[i].addr == -264);
580 else
581 SELF_CHECK (cache.saved_regs[i].addr == -1);
582 }
583
584 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
585 {
586 int regnum = gdbarch_num_regs (gdbarch);
587
588 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
589 == -1);
590 }
591 }
432ec081
YQ		 592
593 /* Test a prologue in which STR is used and frame pointer is not
594 used. */
595 {
596 struct aarch64_prologue_cache cache;
597 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
598
599 static const uint32_t insns[] = {
600 0xf81d0ff3, /* str x19, [sp, #-48]! */
601 0xb9002fe0, /* str w0, [sp, #44] */
602 0xf90013e1, /* str x1, [sp, #32]*/
603 0xfd000fe0, /* str d0, [sp, #24] */
604 0xaa0203f3, /* mov x19, x2 */
605 0xf94013e0, /* ldr x0, [sp, #32] */
606 };
607 instruction_reader_test reader (insns);
608
609 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
610
611 SELF_CHECK (end == 4 * 5);
612
613 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
614 SELF_CHECK (cache.framesize == 48);
615
616 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
617 {
618 if (i == 1)
619 SELF_CHECK (cache.saved_regs[i].addr == -16);
620 else if (i == 19)
621 SELF_CHECK (cache.saved_regs[i].addr == -48);
622 else
623 SELF_CHECK (cache.saved_regs[i].addr == -1);
624 }
625
626 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
627 {
628 int regnum = gdbarch_num_regs (gdbarch);
629
630 if (i == 0)
631 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
632 == -24);
633 else
634 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
635 == -1);
636 }
637 }
4d9a9006
YQ		 638}
639} // namespace selftests
640#endif /* GDB_SELF_TEST */
641
07b287a0
MS		 642/* Implement the "skip_prologue" gdbarch method. */
643
644static CORE_ADDR
645aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
646{
07b287a0 647 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 648
649 /* See if we can determine the end of the prologue via the symbol
650 table. If so, then return either PC, or the PC after the
651 prologue, whichever is greater. */
652 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
653 {
654 CORE_ADDR post_prologue_pc
655 = skip_prologue_using_sal (gdbarch, func_addr);
656
657 if (post_prologue_pc != 0)
325fac50 658 return std::max (pc, post_prologue_pc);
07b287a0
MS		 659 }
660
661 /* Can't determine prologue from the symbol table, need to examine
662 instructions. */
663
664 /* Find an upper limit on the function prologue using the debug
665 information. If the debug information could not be used to
666 provide that bound, then use an arbitrary large number as the
667 upper bound. */
668 limit_pc = skip_prologue_using_sal (gdbarch, pc);
669 if (limit_pc == 0)
670 limit_pc = pc + 128; /* Magic. */
671
672 /* Try disassembling prologue. */
673 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
674}
675
676/* Scan the function prologue for THIS_FRAME and populate the prologue
677 cache CACHE. */
678
679static void
680aarch64_scan_prologue (struct frame_info *this_frame,
681 struct aarch64_prologue_cache *cache)
682{
683 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
684 CORE_ADDR prologue_start;
685 CORE_ADDR prologue_end;
686 CORE_ADDR prev_pc = get_frame_pc (this_frame);
687 struct gdbarch *gdbarch = get_frame_arch (this_frame);
688
db634143
PL		 689 cache->prev_pc = prev_pc;
690
07b287a0
MS		 691 /* Assume we do not find a frame. */
692 cache->framereg = -1;
693 cache->framesize = 0;
694
695 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
696 &prologue_end))
697 {
698 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
699
700 if (sal.line == 0)
701 {
702 /* No line info so use the current PC. */
703 prologue_end = prev_pc;
704 }
705 else if (sal.end < prologue_end)
706 {
707 /* The next line begins after the function end. */
708 prologue_end = sal.end;
709 }
710
325fac50 711 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 712 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
713 }
714 else
715 {
716 CORE_ADDR frame_loc;
07b287a0
MS		 717
718 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
719 if (frame_loc == 0)
720 return;
721
722 cache->framereg = AARCH64_FP_REGNUM;
723 cache->framesize = 16;
724 cache->saved_regs[29].addr = 0;
725 cache->saved_regs[30].addr = 8;
726 }
727}
728
7dfa3edc
PL		 729/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
730 function may throw an exception if the inferior's registers or memory is
731 not available. */
07b287a0 732
7dfa3edc
PL		 733static void
734aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
735 struct aarch64_prologue_cache *cache)
07b287a0 736{
07b287a0
MS		 737 CORE_ADDR unwound_fp;
738 int reg;
739
07b287a0
MS		 740 aarch64_scan_prologue (this_frame, cache);
741
742 if (cache->framereg == -1)
7dfa3edc 743 return;
07b287a0
MS		 744
745 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
746 if (unwound_fp == 0)
7dfa3edc 747 return;
07b287a0
MS		 748
749 cache->prev_sp = unwound_fp + cache->framesize;
750
751 /* Calculate actual addresses of saved registers using offsets
752 determined by aarch64_analyze_prologue. */
753 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
754 if (trad_frame_addr_p (cache->saved_regs, reg))
755 cache->saved_regs[reg].addr += cache->prev_sp;
756
db634143
PL		 757 cache->func = get_frame_func (this_frame);
758
7dfa3edc
PL		 759 cache->available_p = 1;
760}
761
762/* Allocate and fill in *THIS_CACHE with information about the prologue of
763 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
764 Return a pointer to the current aarch64_prologue_cache in
765 *THIS_CACHE. */
766
767static struct aarch64_prologue_cache *
768aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
769{
770 struct aarch64_prologue_cache *cache;
771
772 if (*this_cache != NULL)
9a3c8263 773 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 774
775 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
776 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
777 *this_cache = cache;
778
779 TRY
780 {
781 aarch64_make_prologue_cache_1 (this_frame, cache);
782 }
783 CATCH (ex, RETURN_MASK_ERROR)
784 {
785 if (ex.error != NOT_AVAILABLE_ERROR)
786 throw_exception (ex);
787 }
788 END_CATCH
789
07b287a0
MS		 790 return cache;
791}
792
7dfa3edc
PL		 793/* Implement the "stop_reason" frame_unwind method. */
794
795static enum unwind_stop_reason
796aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
797 void **this_cache)
798{
799 struct aarch64_prologue_cache *cache
800 = aarch64_make_prologue_cache (this_frame, this_cache);
801
802 if (!cache->available_p)
803 return UNWIND_UNAVAILABLE;
804
805 /* Halt the backtrace at "_start". */
806 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
807 return UNWIND_OUTERMOST;
808
809 /* We've hit a wall, stop. */
810 if (cache->prev_sp == 0)
811 return UNWIND_OUTERMOST;
812
813 return UNWIND_NO_REASON;
814}
815
07b287a0
MS		 816/* Our frame ID for a normal frame is the current function's starting
817 PC and the caller's SP when we were called. */
818
819static void
820aarch64_prologue_this_id (struct frame_info *this_frame,
821 void **this_cache, struct frame_id *this_id)
822{
7c8edfae
PL		 823 struct aarch64_prologue_cache *cache
824 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 825
7dfa3edc
PL		 826 if (!cache->available_p)
827 *this_id = frame_id_build_unavailable_stack (cache->func);
828 else
829 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 830}
831
832/* Implement the "prev_register" frame_unwind method. */
833
834static struct value *
835aarch64_prologue_prev_register (struct frame_info *this_frame,
836 void **this_cache, int prev_regnum)
837{
7c8edfae
PL		 838 struct aarch64_prologue_cache *cache
839 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 840
841 /* If we are asked to unwind the PC, then we need to return the LR
842 instead. The prologue may save PC, but it will point into this
843 frame's prologue, not the next frame's resume location. */
844 if (prev_regnum == AARCH64_PC_REGNUM)
845 {
846 CORE_ADDR lr;
847
848 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
849 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
850 }
851
852 /* SP is generally not saved to the stack, but this frame is
853 identified by the next frame's stack pointer at the time of the
854 call. The value was already reconstructed into PREV_SP. */
855 /*
856 +----------+ ^
857 | saved lr | |
858 +->| saved fp |--+
859 | | |
860 | | | <- Previous SP
861 | +----------+
862 | | saved lr |
863 +--| saved fp |<- FP
864 | |
865 | |<- SP
866 +----------+ */
867 if (prev_regnum == AARCH64_SP_REGNUM)
868 return frame_unwind_got_constant (this_frame, prev_regnum,
869 cache->prev_sp);
870
871 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
872 prev_regnum);
873}
874
875/* AArch64 prologue unwinder. */
876struct frame_unwind aarch64_prologue_unwind =
877{
878 NORMAL_FRAME,
7dfa3edc 879 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 880 aarch64_prologue_this_id,
881 aarch64_prologue_prev_register,
882 NULL,
883 default_frame_sniffer
884};
885
8b61f75d
PL		 886/* Allocate and fill in *THIS_CACHE with information about the prologue of
887 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
888 Return a pointer to the current aarch64_prologue_cache in
889 *THIS_CACHE. */
07b287a0
MS		 890
891static struct aarch64_prologue_cache *
8b61f75d 892aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 893{
07b287a0 894 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 895
896 if (*this_cache != NULL)
9a3c8263 897 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 898
899 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
900 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 901 *this_cache = cache;
07b287a0 902
02a2a705
PL		 903 TRY
904 {
905 cache->prev_sp = get_frame_register_unsigned (this_frame,
906 AARCH64_SP_REGNUM);
907 cache->prev_pc = get_frame_pc (this_frame);
908 cache->available_p = 1;
909 }
910 CATCH (ex, RETURN_MASK_ERROR)
911 {
912 if (ex.error != NOT_AVAILABLE_ERROR)
913 throw_exception (ex);
914 }
915 END_CATCH
07b287a0
MS		 916
917 return cache;
918}
919
02a2a705
PL		 920/* Implement the "stop_reason" frame_unwind method. */
921
922static enum unwind_stop_reason
923aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
924 void **this_cache)
925{
926 struct aarch64_prologue_cache *cache
927 = aarch64_make_stub_cache (this_frame, this_cache);
928
929 if (!cache->available_p)
930 return UNWIND_UNAVAILABLE;
931
932 return UNWIND_NO_REASON;
933}
934
07b287a0
MS		 935/* Our frame ID for a stub frame is the current SP and LR. */
936
937static void
938aarch64_stub_this_id (struct frame_info *this_frame,
939 void **this_cache, struct frame_id *this_id)
940{
8b61f75d
PL		 941 struct aarch64_prologue_cache *cache
942 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 943
02a2a705
PL		 944 if (cache->available_p)
945 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
946 else
947 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 948}
949
950/* Implement the "sniffer" frame_unwind method. */
951
952static int
953aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
954 struct frame_info *this_frame,
955 void **this_prologue_cache)
956{
957 CORE_ADDR addr_in_block;
958 gdb_byte dummy[4];
959
960 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 961 if (in_plt_section (addr_in_block)
07b287a0
MS		 962 /* We also use the stub winder if the target memory is unreadable
963 to avoid having the prologue unwinder trying to read it. */
964 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
965 return 1;
966
967 return 0;
968}
969
970/* AArch64 stub unwinder. */
971struct frame_unwind aarch64_stub_unwind =
972{
973 NORMAL_FRAME,
02a2a705 974 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 975 aarch64_stub_this_id,
976 aarch64_prologue_prev_register,
977 NULL,
978 aarch64_stub_unwind_sniffer
979};
980
981/* Return the frame base address of *THIS_FRAME. */
982
983static CORE_ADDR
984aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
985{
7c8edfae
PL		 986 struct aarch64_prologue_cache *cache
987 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 988
989 return cache->prev_sp - cache->framesize;
990}
991
992/* AArch64 default frame base information. */
993struct frame_base aarch64_normal_base =
994{
995 &aarch64_prologue_unwind,
996 aarch64_normal_frame_base,
997 aarch64_normal_frame_base,
998 aarch64_normal_frame_base
999};
1000
1001/* Assuming THIS_FRAME is a dummy, return the frame ID of that
1002 dummy frame. The frame ID's base needs to match the TOS value
1003 saved by save_dummy_frame_tos () and returned from
1004 aarch64_push_dummy_call, and the PC needs to match the dummy
1005 frame's breakpoint. */
1006
1007static struct frame_id
1008aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1009{
1010 return frame_id_build (get_frame_register_unsigned (this_frame,
1011 AARCH64_SP_REGNUM),
1012 get_frame_pc (this_frame));
1013}
1014
1015/* Implement the "unwind_pc" gdbarch method. */
1016
1017static CORE_ADDR
1018aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1019{
1020 CORE_ADDR pc
1021 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
1022
1023 return pc;
1024}
1025
1026/* Implement the "unwind_sp" gdbarch method. */
1027
1028static CORE_ADDR
1029aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1030{
1031 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
1032}
1033
1034/* Return the value of the REGNUM register in the previous frame of
1035 *THIS_FRAME. */
1036
1037static struct value *
1038aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1039 void **this_cache, int regnum)
1040{
07b287a0
MS		 1041 CORE_ADDR lr;
1042
1043 switch (regnum)
1044 {
1045 case AARCH64_PC_REGNUM:
1046 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
1047 return frame_unwind_got_constant (this_frame, regnum, lr);
1048
1049 default:
1050 internal_error (__FILE__, __LINE__,
1051 _("Unexpected register %d"), regnum);
1052 }
1053}
1054
1055/* Implement the "init_reg" dwarf2_frame_ops method. */
1056
1057static void
1058aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1059 struct dwarf2_frame_state_reg *reg,
1060 struct frame_info *this_frame)
1061{
1062 switch (regnum)
1063 {
1064 case AARCH64_PC_REGNUM:
1065 reg->how = DWARF2_FRAME_REG_FN;
1066 reg->loc.fn = aarch64_dwarf2_prev_register;
1067 break;
1068 case AARCH64_SP_REGNUM:
1069 reg->how = DWARF2_FRAME_REG_CFA;
1070 break;
1071 }
1072}
1073
1074/* When arguments must be pushed onto the stack, they go on in reverse
1075 order. The code below implements a FILO (stack) to do this. */
1076
1077typedef struct
1078{
c3c87445
YQ		 1079 /* Value to pass on stack. It can be NULL if this item is for stack
1080 padding. */
7c543f7b 1081 const gdb_byte *data;
07b287a0
MS		 1082
1083 /* Size in bytes of value to pass on stack. */
1084 int len;
1085} stack_item_t;
1086
1087DEF_VEC_O (stack_item_t);
1088
1089/* Return the alignment (in bytes) of the given type. */
1090
1091static int
1092aarch64_type_align (struct type *t)
1093{
1094 int n;
1095 int align;
1096 int falign;
1097
1098 t = check_typedef (t);
1099 switch (TYPE_CODE (t))
1100 {
1101 default:
1102 /* Should never happen. */
1103 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1104 return 4;
1105
1106 case TYPE_CODE_PTR:
1107 case TYPE_CODE_ENUM:
1108 case TYPE_CODE_INT:
1109 case TYPE_CODE_FLT:
1110 case TYPE_CODE_SET:
1111 case TYPE_CODE_RANGE:
1112 case TYPE_CODE_BITSTRING:
1113 case TYPE_CODE_REF:
aa006118 1114 case TYPE_CODE_RVALUE_REF:
07b287a0
MS		 1115 case TYPE_CODE_CHAR:
1116 case TYPE_CODE_BOOL:
1117 return TYPE_LENGTH (t);
1118
1119 case TYPE_CODE_ARRAY:
238f2452
YQ		 1120 if (TYPE_VECTOR (t))
1121 {
1122 /* Use the natural alignment for vector types (the same for
1123 scalar type), but the maximum alignment is 128-bit. */
1124 if (TYPE_LENGTH (t) > 16)
1125 return 16;
1126 else
1127 return TYPE_LENGTH (t);
1128 }
1129 else
1130 return aarch64_type_align (TYPE_TARGET_TYPE (t));
07b287a0
MS		 1131 case TYPE_CODE_COMPLEX:
1132 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1133
1134 case TYPE_CODE_STRUCT:
1135 case TYPE_CODE_UNION:
1136 align = 1;
1137 for (n = 0; n < TYPE_NFIELDS (t); n++)
1138 {
1139 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
1140 if (falign > align)
1141 align = falign;
1142 }
1143 return align;
1144 }
1145}
1146
ea92689a
AH		 1147/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1148
1149 Return the number of register required, or -1 on failure.
1150
1151 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1152 to the element, else fail if the type of this element does not match the
1153 existing value. */
1154
1155static int
1156aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1157 struct type **fundamental_type)
1158{
1159 if (type == nullptr)
1160 return -1;
1161
1162 switch (TYPE_CODE (type))
1163 {
1164 case TYPE_CODE_FLT:
1165 if (TYPE_LENGTH (type) > 16)
1166 return -1;
1167
1168 if (*fundamental_type == nullptr)
1169 *fundamental_type = type;
1170 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1171 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1172 return -1;
1173
1174 return 1;
1175
1176 case TYPE_CODE_COMPLEX:
1177 {
1178 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1179 if (TYPE_LENGTH (target_type) > 16)
1180 return -1;
1181
1182 if (*fundamental_type == nullptr)
1183 *fundamental_type = target_type;
1184 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1185 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1186 return -1;
1187
1188 return 2;
1189 }
1190
1191 case TYPE_CODE_ARRAY:
1192 {
1193 if (TYPE_VECTOR (type))
1194 {
1195 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1196 return -1;
1197
1198 if (*fundamental_type == nullptr)
1199 *fundamental_type = type;
1200 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1201 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1202 return -1;
1203
1204 return 1;
1205 }
1206 else
1207 {
1208 struct type *target_type = TYPE_TARGET_TYPE (type);
1209 int count = aapcs_is_vfp_call_or_return_candidate_1
1210 (target_type, fundamental_type);
1211
1212 if (count == -1)
1213 return count;
1214
d4718d5c 1215 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1216 return count;
1217 }
1218 }
1219
1220 case TYPE_CODE_STRUCT:
1221 case TYPE_CODE_UNION:
1222 {
1223 int count = 0;
1224
1225 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1226 {
1227 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1228
1229 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1230 (member, fundamental_type);
1231 if (sub_count == -1)
1232 return -1;
1233 count += sub_count;
1234 }
1235 return count;
1236 }
1237
1238 default:
1239 break;
1240 }
1241
1242 return -1;
1243}
1244
1245/* Return true if an argument, whose type is described by TYPE, can be passed or
1246 returned in simd/fp registers, providing enough parameter passing registers
1247 are available. This is as described in the AAPCS64.
1248
1249 Upon successful return, *COUNT returns the number of needed registers,
1250 *FUNDAMENTAL_TYPE contains the type of those registers.
1251
1252 Candidate as per the AAPCS64 5.4.2.C is either a:
1253 - float.
1254 - short-vector.
1255 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1256 all the members are floats and has at most 4 members.
1257 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1258 all the members are short vectors and has at most 4 members.
1259 - Complex (7.1.1)
1260
1261 Note that HFAs and HVAs can include nested structures and arrays. */
1262
0e745c60 1263static bool
ea92689a
AH		 1264aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1265 struct type **fundamental_type)
1266{
1267 if (type == nullptr)
1268 return false;
1269
1270 *fundamental_type = nullptr;
1271
1272 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1273 fundamental_type);
1274
1275 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1276 {
1277 *count = ag_count;
1278 return true;
1279 }
1280 else
1281 return false;
1282}
1283
07b287a0
MS		 1284/* AArch64 function call information structure. */
1285struct aarch64_call_info
1286{
1287 /* the current argument number. */
1288 unsigned argnum;
1289
1290 /* The next general purpose register number, equivalent to NGRN as
1291 described in the AArch64 Procedure Call Standard. */
1292 unsigned ngrn;
1293
1294 /* The next SIMD and floating point register number, equivalent to
1295 NSRN as described in the AArch64 Procedure Call Standard. */
1296 unsigned nsrn;
1297
1298 /* The next stacked argument address, equivalent to NSAA as
1299 described in the AArch64 Procedure Call Standard. */
1300 unsigned nsaa;
1301
1302 /* Stack item vector. */
1303 VEC(stack_item_t) *si;
1304};
1305
1306/* Pass a value in a sequence of consecutive X registers. The caller
1307 is responsbile for ensuring sufficient registers are available. */
1308
1309static void
1310pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1311 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1312 struct value *arg)
07b287a0
MS		 1313{
1314 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1315 int len = TYPE_LENGTH (type);
1316 enum type_code typecode = TYPE_CODE (type);
1317 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1318 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1319
1320 info->argnum++;
1321
1322 while (len > 0)
1323 {
1324 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1325 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1326 byte_order);
1327
1328
1329 /* Adjust sub-word struct/union args when big-endian. */
1330 if (byte_order == BFD_ENDIAN_BIG
1331 && partial_len < X_REGISTER_SIZE
1332 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1333 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1334
1335 if (aarch64_debug)
b277c936
PL		 1336 {
1337 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1338 gdbarch_register_name (gdbarch, regnum),
1339 phex (regval, X_REGISTER_SIZE));
1340 }
07b287a0
MS		 1341 regcache_cooked_write_unsigned (regcache, regnum, regval);
1342 len -= partial_len;
1343 buf += partial_len;
1344 regnum++;
1345 }
1346}
1347
1348/* Attempt to marshall a value in a V register. Return 1 if
1349 successful, or 0 if insufficient registers are available. This
1350 function, unlike the equivalent pass_in_x() function does not
1351 handle arguments spread across multiple registers. */
1352
1353static int
1354pass_in_v (struct gdbarch *gdbarch,
1355 struct regcache *regcache,
1356 struct aarch64_call_info *info,
0735fddd 1357 int len, const bfd_byte *buf)
07b287a0
MS		 1358{
1359 if (info->nsrn < 8)
1360 {
07b287a0 1361 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1362 /* Enough space for a full vector register. */
1363 gdb_byte reg[register_size (gdbarch, regnum)];
1364 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1365
1366 info->argnum++;
1367 info->nsrn++;
1368
0735fddd
YQ		 1369 memset (reg, 0, sizeof (reg));
1370 /* PCS C.1, the argument is allocated to the least significant
1371 bits of V register. */
1372 memcpy (reg, buf, len);
b66f5587 1373 regcache->cooked_write (regnum, reg);
0735fddd 1374
07b287a0 1375 if (aarch64_debug)
b277c936
PL		 1376 {
1377 debug_printf ("arg %d in %s\n", info->argnum,
1378 gdbarch_register_name (gdbarch, regnum));
1379 }
07b287a0
MS		 1380 return 1;
1381 }
1382 info->nsrn = 8;
1383 return 0;
1384}
1385
1386/* Marshall an argument onto the stack. */
1387
1388static void
1389pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1390 struct value *arg)
07b287a0 1391{
8e80f9d1 1392 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1393 int len = TYPE_LENGTH (type);
1394 int align;
1395 stack_item_t item;
1396
1397 info->argnum++;
1398
1399 align = aarch64_type_align (type);
1400
1401 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1402 Natural alignment of the argument's type. */
1403 align = align_up (align, 8);
1404
1405 /* The AArch64 PCS requires at most doubleword alignment. */
1406 if (align > 16)
1407 align = 16;
1408
1409 if (aarch64_debug)
b277c936
PL		 1410 {
1411 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1412 info->nsaa);
1413 }
07b287a0
MS		 1414
1415 item.len = len;
1416 item.data = buf;
1417 VEC_safe_push (stack_item_t, info->si, &item);
1418
1419 info->nsaa += len;
1420 if (info->nsaa & (align - 1))
1421 {
1422 /* Push stack alignment padding. */
1423 int pad = align - (info->nsaa & (align - 1));
1424
1425 item.len = pad;
c3c87445 1426 item.data = NULL;
07b287a0
MS		 1427
1428 VEC_safe_push (stack_item_t, info->si, &item);
1429 info->nsaa += pad;
1430 }
1431}
1432
1433/* Marshall an argument into a sequence of one or more consecutive X
1434 registers or, if insufficient X registers are available then onto
1435 the stack. */
1436
1437static void
1438pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1439 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1440 struct value *arg)
07b287a0
MS		 1441{
1442 int len = TYPE_LENGTH (type);
1443 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1444
1445 /* PCS C.13 - Pass in registers if we have enough spare */
1446 if (info->ngrn + nregs <= 8)
1447 {
8e80f9d1 1448 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1449 info->ngrn += nregs;
1450 }
1451 else
1452 {
1453 info->ngrn = 8;
8e80f9d1 1454 pass_on_stack (info, type, arg);
07b287a0
MS		 1455 }
1456}
1457
0e745c60
AH		 1458/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1459 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1460 registers. A return value of false is an error state as the value will have
1461 been partially passed to the stack. */
1462static bool
1463pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1464 struct aarch64_call_info *info, struct type *arg_type,
1465 struct value *arg)
07b287a0 1466{
0e745c60
AH		 1467 switch (TYPE_CODE (arg_type))
1468 {
1469 case TYPE_CODE_FLT:
1470 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1471 value_contents (arg));
1472 break;
1473
1474 case TYPE_CODE_COMPLEX:
1475 {
1476 const bfd_byte *buf = value_contents (arg);
1477 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1478
1479 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1480 buf))
1481 return false;
1482
1483 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1484 buf + TYPE_LENGTH (target_type));
1485 }
1486
1487 case TYPE_CODE_ARRAY:
1488 if (TYPE_VECTOR (arg_type))
1489 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1490 value_contents (arg));
1491 /* fall through. */
1492
1493 case TYPE_CODE_STRUCT:
1494 case TYPE_CODE_UNION:
1495 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1496 {
1497 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1498 struct type *field_type = check_typedef (value_type (field));
1499
1500 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1501 field))
1502 return false;
1503 }
1504 return true;
1505
1506 default:
1507 return false;
1508 }
07b287a0
MS		 1509}
1510
1511/* Implement the "push_dummy_call" gdbarch method. */
1512
1513static CORE_ADDR
1514aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1515 struct regcache *regcache, CORE_ADDR bp_addr,
1516 int nargs,
cf84fa6b
AH		 1517 struct value **args, CORE_ADDR sp,
1518 function_call_return_method return_method,
07b287a0
MS		 1519 CORE_ADDR struct_addr)
1520{
07b287a0 1521 int argnum;
07b287a0 1522 struct aarch64_call_info info;
07b287a0
MS		 1523
1524 memset (&info, 0, sizeof (info));
1525
1526 /* We need to know what the type of the called function is in order
1527 to determine the number of named/anonymous arguments for the
1528 actual argument placement, and the return type in order to handle
1529 return value correctly.
1530
1531 The generic code above us views the decision of return in memory
1532 or return in registers as a two stage processes. The language
1533 handler is consulted first and may decide to return in memory (eg
1534 class with copy constructor returned by value), this will cause
1535 the generic code to allocate space AND insert an initial leading
1536 argument.
1537
1538 If the language code does not decide to pass in memory then the
1539 target code is consulted.
1540
1541 If the language code decides to pass in memory we want to move
1542 the pointer inserted as the initial argument from the argument
1543 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1544 register. */
07b287a0
MS		 1545
1546 /* Set the return address. For the AArch64, the return breakpoint
1547 is always at BP_ADDR. */
1548 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1549
38a72da0
AH		 1550 /* If we were given an initial argument for the return slot, lose it. */
1551 if (return_method == return_method_hidden_param)
07b287a0
MS		 1552 {
1553 args++;
1554 nargs--;
1555 }
1556
1557 /* The struct_return pointer occupies X8. */
38a72da0 1558 if (return_method != return_method_normal)
07b287a0
MS		 1559 {
1560 if (aarch64_debug)
b277c936
PL		 1561 {
1562 debug_printf ("struct return in %s = 0x%s\n",
1563 gdbarch_register_name (gdbarch,
1564 AARCH64_STRUCT_RETURN_REGNUM),
1565 paddress (gdbarch, struct_addr));
1566 }
07b287a0
MS		 1567 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1568 struct_addr);
1569 }
1570
1571 for (argnum = 0; argnum < nargs; argnum++)
1572 {
1573 struct value *arg = args[argnum];
0e745c60
AH		 1574 struct type *arg_type, *fundamental_type;
1575 int len, elements;
07b287a0
MS		 1576
1577 arg_type = check_typedef (value_type (arg));
1578 len = TYPE_LENGTH (arg_type);
1579
0e745c60
AH		 1580 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1581 if there are enough spare registers. */
1582 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1583 &fundamental_type))
1584 {
1585 if (info.nsrn + elements <= 8)
1586 {
1587 /* We know that we have sufficient registers available therefore
1588 this will never need to fallback to the stack. */
1589 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1590 arg))
1591 gdb_assert_not_reached ("Failed to push args");
1592 }
1593 else
1594 {
1595 info.nsrn = 8;
1596 pass_on_stack (&info, arg_type, arg);
1597 }
1598 continue;
1599 }
1600
07b287a0
MS		 1601 switch (TYPE_CODE (arg_type))
1602 {
1603 case TYPE_CODE_INT:
1604 case TYPE_CODE_BOOL:
1605 case TYPE_CODE_CHAR:
1606 case TYPE_CODE_RANGE:
1607 case TYPE_CODE_ENUM:
1608 if (len < 4)
1609 {
1610 /* Promote to 32 bit integer. */
1611 if (TYPE_UNSIGNED (arg_type))
1612 arg_type = builtin_type (gdbarch)->builtin_uint32;
1613 else
1614 arg_type = builtin_type (gdbarch)->builtin_int32;
1615 arg = value_cast (arg_type, arg);
1616 }
8e80f9d1 1617 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1618 break;
1619
07b287a0
MS		 1620 case TYPE_CODE_STRUCT:
1621 case TYPE_CODE_ARRAY:
1622 case TYPE_CODE_UNION:
0e745c60 1623 if (len > 16)
07b287a0
MS		 1624 {
1625 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1626 invisible reference. */
1627
1628 /* Allocate aligned storage. */
1629 sp = align_down (sp - len, 16);
1630
1631 /* Write the real data into the stack. */
1632 write_memory (sp, value_contents (arg), len);
1633
1634 /* Construct the indirection. */
1635 arg_type = lookup_pointer_type (arg_type);
1636 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1637 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1638 }
1639 else
1640 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1641 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1642 break;
1643
1644 default:
8e80f9d1 1645 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1646 break;
1647 }
1648 }
1649
1650 /* Make sure stack retains 16 byte alignment. */
1651 if (info.nsaa & 15)
1652 sp -= 16 - (info.nsaa & 15);
1653
1654 while (!VEC_empty (stack_item_t, info.si))
1655 {
1656 stack_item_t *si = VEC_last (stack_item_t, info.si);
1657
1658 sp -= si->len;
c3c87445
YQ		 1659 if (si->data != NULL)
1660 write_memory (sp, si->data, si->len);
07b287a0
MS		 1661 VEC_pop (stack_item_t, info.si);
1662 }
1663
1664 VEC_free (stack_item_t, info.si);
1665
1666 /* Finally, update the SP register. */
1667 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1668
1669 return sp;
1670}
1671
1672/* Implement the "frame_align" gdbarch method. */
1673
1674static CORE_ADDR
1675aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1676{
1677 /* Align the stack to sixteen bytes. */
1678 return sp & ~(CORE_ADDR) 15;
1679}
1680
1681/* Return the type for an AdvSISD Q register. */
1682
1683static struct type *
1684aarch64_vnq_type (struct gdbarch *gdbarch)
1685{
1686 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1687
1688 if (tdep->vnq_type == NULL)
1689 {
1690 struct type *t;
1691 struct type *elem;
1692
1693 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1694 TYPE_CODE_UNION);
1695
1696 elem = builtin_type (gdbarch)->builtin_uint128;
1697 append_composite_type_field (t, "u", elem);
1698
1699 elem = builtin_type (gdbarch)->builtin_int128;
1700 append_composite_type_field (t, "s", elem);
1701
1702 tdep->vnq_type = t;
1703 }
1704
1705 return tdep->vnq_type;
1706}
1707
1708/* Return the type for an AdvSISD D register. */
1709
1710static struct type *
1711aarch64_vnd_type (struct gdbarch *gdbarch)
1712{
1713 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1714
1715 if (tdep->vnd_type == NULL)
1716 {
1717 struct type *t;
1718 struct type *elem;
1719
1720 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1721 TYPE_CODE_UNION);
1722
1723 elem = builtin_type (gdbarch)->builtin_double;
1724 append_composite_type_field (t, "f", elem);
1725
1726 elem = builtin_type (gdbarch)->builtin_uint64;
1727 append_composite_type_field (t, "u", elem);
1728
1729 elem = builtin_type (gdbarch)->builtin_int64;
1730 append_composite_type_field (t, "s", elem);
1731
1732 tdep->vnd_type = t;
1733 }
1734
1735 return tdep->vnd_type;
1736}
1737
1738/* Return the type for an AdvSISD S register. */
1739
1740static struct type *
1741aarch64_vns_type (struct gdbarch *gdbarch)
1742{
1743 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1744
1745 if (tdep->vns_type == NULL)
1746 {
1747 struct type *t;
1748 struct type *elem;
1749
1750 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1751 TYPE_CODE_UNION);
1752
1753 elem = builtin_type (gdbarch)->builtin_float;
1754 append_composite_type_field (t, "f", elem);
1755
1756 elem = builtin_type (gdbarch)->builtin_uint32;
1757 append_composite_type_field (t, "u", elem);
1758
1759 elem = builtin_type (gdbarch)->builtin_int32;
1760 append_composite_type_field (t, "s", elem);
1761
1762 tdep->vns_type = t;
1763 }
1764
1765 return tdep->vns_type;
1766}
1767
1768/* Return the type for an AdvSISD H register. */
1769
1770static struct type *
1771aarch64_vnh_type (struct gdbarch *gdbarch)
1772{
1773 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1774
1775 if (tdep->vnh_type == NULL)
1776 {
1777 struct type *t;
1778 struct type *elem;
1779
1780 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1781 TYPE_CODE_UNION);
1782
1783 elem = builtin_type (gdbarch)->builtin_uint16;
1784 append_composite_type_field (t, "u", elem);
1785
1786 elem = builtin_type (gdbarch)->builtin_int16;
1787 append_composite_type_field (t, "s", elem);
1788
1789 tdep->vnh_type = t;
1790 }
1791
1792 return tdep->vnh_type;
1793}
1794
1795/* Return the type for an AdvSISD B register. */
1796
1797static struct type *
1798aarch64_vnb_type (struct gdbarch *gdbarch)
1799{
1800 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1801
1802 if (tdep->vnb_type == NULL)
1803 {
1804 struct type *t;
1805 struct type *elem;
1806
1807 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1808 TYPE_CODE_UNION);
1809
1810 elem = builtin_type (gdbarch)->builtin_uint8;
1811 append_composite_type_field (t, "u", elem);
1812
1813 elem = builtin_type (gdbarch)->builtin_int8;
1814 append_composite_type_field (t, "s", elem);
1815
1816 tdep->vnb_type = t;
1817 }
1818
1819 return tdep->vnb_type;
1820}
1821
63bad7b6
AH		 1822/* Return the type for an AdvSISD V register. */
1823
1824static struct type *
1825aarch64_vnv_type (struct gdbarch *gdbarch)
1826{
1827 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1828
1829 if (tdep->vnv_type == NULL)
1830 {
1831 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1832 TYPE_CODE_UNION);
1833
1834 append_composite_type_field (t, "d", aarch64_vnd_type (gdbarch));
1835 append_composite_type_field (t, "s", aarch64_vns_type (gdbarch));
1836 append_composite_type_field (t, "h", aarch64_vnh_type (gdbarch));
1837 append_composite_type_field (t, "b", aarch64_vnb_type (gdbarch));
1838 append_composite_type_field (t, "q", aarch64_vnq_type (gdbarch));
1839
1840 tdep->vnv_type = t;
1841 }
1842
1843 return tdep->vnv_type;
1844}
1845
07b287a0
MS		 1846/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1847
1848static int
1849aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1850{
1851 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1852 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1853
1854 if (reg == AARCH64_DWARF_SP)
1855 return AARCH64_SP_REGNUM;
1856
1857 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1858 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1859
65d4cada
AH		 1860 if (reg == AARCH64_DWARF_SVE_VG)
1861 return AARCH64_SVE_VG_REGNUM;
1862
1863 if (reg == AARCH64_DWARF_SVE_FFR)
1864 return AARCH64_SVE_FFR_REGNUM;
1865
1866 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
1867 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
1868
1869 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
1870 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
1871
07b287a0
MS		 1872 return -1;
1873}
07b287a0
MS		 1874
1875/* Implement the "print_insn" gdbarch method. */
1876
1877static int
1878aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1879{
1880 info->symbols = NULL;
6394c606 1881 return default_print_insn (memaddr, info);
07b287a0
MS		 1882}
1883
1884/* AArch64 BRK software debug mode instruction.
1885 Note that AArch64 code is always little-endian.
1886 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 1887constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 1888
04180708 1889typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 1890
1891/* Extract from an array REGS containing the (raw) register state a
1892 function return value of type TYPE, and copy that, in virtual
1893 format, into VALBUF. */
1894
1895static void
1896aarch64_extract_return_value (struct type *type, struct regcache *regs,
1897 gdb_byte *valbuf)
1898{
ac7936df 1899 struct gdbarch *gdbarch = regs->arch ();
07b287a0 1900 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 1901 int elements;
1902 struct type *fundamental_type;
07b287a0 1903
4f4aedeb
AH		 1904 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
1905 &fundamental_type))
07b287a0 1906 {
4f4aedeb
AH		 1907 int len = TYPE_LENGTH (fundamental_type);
1908
1909 for (int i = 0; i < elements; i++)
1910 {
1911 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 1912 /* Enough space for a full vector register. */
1913 gdb_byte buf[register_size (gdbarch, regno)];
1914 gdb_assert (len <= sizeof (buf));
4f4aedeb
AH		 1915
1916 if (aarch64_debug)
1917 {
1918 debug_printf ("read HFA or HVA return value element %d from %s\n",
1919 i + 1,
1920 gdbarch_register_name (gdbarch, regno));
1921 }
1922 regs->cooked_read (regno, buf);
07b287a0 1923
4f4aedeb
AH		 1924 memcpy (valbuf, buf, len);
1925 valbuf += len;
1926 }
07b287a0
MS		 1927 }
1928 else if (TYPE_CODE (type) == TYPE_CODE_INT
1929 || TYPE_CODE (type) == TYPE_CODE_CHAR
1930 || TYPE_CODE (type) == TYPE_CODE_BOOL
1931 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 1932 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 1933 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1934 {
1935 /* If the the type is a plain integer, then the access is
1936 straight-forward. Otherwise we have to play around a bit
1937 more. */
1938 int len = TYPE_LENGTH (type);
1939 int regno = AARCH64_X0_REGNUM;
1940 ULONGEST tmp;
1941
1942 while (len > 0)
1943 {
1944 /* By using store_unsigned_integer we avoid having to do
1945 anything special for small big-endian values. */
1946 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1947 store_unsigned_integer (valbuf,
1948 (len > X_REGISTER_SIZE
1949 ? X_REGISTER_SIZE : len), byte_order, tmp);
1950 len -= X_REGISTER_SIZE;
1951 valbuf += X_REGISTER_SIZE;
1952 }
1953 }
07b287a0
MS		 1954 else
1955 {
1956 /* For a structure or union the behaviour is as if the value had
1957 been stored to word-aligned memory and then loaded into
1958 registers with 64-bit load instruction(s). */
1959 int len = TYPE_LENGTH (type);
1960 int regno = AARCH64_X0_REGNUM;
1961 bfd_byte buf[X_REGISTER_SIZE];
1962
1963 while (len > 0)
1964 {
dca08e1f 1965 regs->cooked_read (regno++, buf);
07b287a0
MS		 1966 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1967 len -= X_REGISTER_SIZE;
1968 valbuf += X_REGISTER_SIZE;
1969 }
1970 }
1971}
1972
1973
1974/* Will a function return an aggregate type in memory or in a
1975 register? Return 0 if an aggregate type can be returned in a
1976 register, 1 if it must be returned in memory. */
1977
1978static int
1979aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1980{
f168693b 1981 type = check_typedef (type);
4f4aedeb
AH		 1982 int elements;
1983 struct type *fundamental_type;
07b287a0 1984
4f4aedeb
AH		 1985 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
1986 &fundamental_type))
07b287a0 1987 {
cd635f74
YQ		 1988 /* v0-v7 are used to return values and one register is allocated
1989 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 1990 return 0;
1991 }
1992
1993 if (TYPE_LENGTH (type) > 16)
1994 {
1995 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1996 invisible reference. */
1997
1998 return 1;
1999 }
2000
2001 return 0;
2002}
2003
2004/* Write into appropriate registers a function return value of type
2005 TYPE, given in virtual format. */
2006
2007static void
2008aarch64_store_return_value (struct type *type, struct regcache *regs,
2009 const gdb_byte *valbuf)
2010{
ac7936df 2011 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2012 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2013 int elements;
2014 struct type *fundamental_type;
07b287a0 2015
4f4aedeb
AH		 2016 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2017 &fundamental_type))
07b287a0 2018 {
4f4aedeb
AH		 2019 int len = TYPE_LENGTH (fundamental_type);
2020
2021 for (int i = 0; i < elements; i++)
2022 {
2023 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2024 /* Enough space for a full vector register. */
2025 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2026 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb
AH		 2027
2028 if (aarch64_debug)
2029 {
2030 debug_printf ("write HFA or HVA return value element %d to %s\n",
2031 i + 1,
2032 gdbarch_register_name (gdbarch, regno));
2033 }
07b287a0 2034
4f4aedeb
AH		 2035 memcpy (tmpbuf, valbuf,
2036 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2037 regs->cooked_write (regno, tmpbuf);
2038 valbuf += len;
2039 }
07b287a0
MS		 2040 }
2041 else if (TYPE_CODE (type) == TYPE_CODE_INT
2042 || TYPE_CODE (type) == TYPE_CODE_CHAR
2043 || TYPE_CODE (type) == TYPE_CODE_BOOL
2044 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2045 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2046 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2047 {
2048 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2049 {
2050 /* Values of one word or less are zero/sign-extended and
2051 returned in r0. */
2052 bfd_byte tmpbuf[X_REGISTER_SIZE];
2053 LONGEST val = unpack_long (type, valbuf);
2054
2055 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2056 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2057 }
2058 else
2059 {
2060 /* Integral values greater than one word are stored in
2061 consecutive registers starting with r0. This will always
2062 be a multiple of the regiser size. */
2063 int len = TYPE_LENGTH (type);
2064 int regno = AARCH64_X0_REGNUM;
2065
2066 while (len > 0)
2067 {
b66f5587 2068 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2069 len -= X_REGISTER_SIZE;
2070 valbuf += X_REGISTER_SIZE;
2071 }
2072 }
2073 }
07b287a0
MS		 2074 else
2075 {
2076 /* For a structure or union the behaviour is as if the value had
2077 been stored to word-aligned memory and then loaded into
2078 registers with 64-bit load instruction(s). */
2079 int len = TYPE_LENGTH (type);
2080 int regno = AARCH64_X0_REGNUM;
2081 bfd_byte tmpbuf[X_REGISTER_SIZE];
2082
2083 while (len > 0)
2084 {
2085 memcpy (tmpbuf, valbuf,
2086 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2087 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2088 len -= X_REGISTER_SIZE;
2089 valbuf += X_REGISTER_SIZE;
2090 }
2091 }
2092}
2093
2094/* Implement the "return_value" gdbarch method. */
2095
2096static enum return_value_convention
2097aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2098 struct type *valtype, struct regcache *regcache,
2099 gdb_byte *readbuf, const gdb_byte *writebuf)
2100{
07b287a0
MS		 2101
2102 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2103 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2104 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2105 {
2106 if (aarch64_return_in_memory (gdbarch, valtype))
2107 {
2108 if (aarch64_debug)
b277c936 2109 debug_printf ("return value in memory\n");
07b287a0
MS		 2110 return RETURN_VALUE_STRUCT_CONVENTION;
2111 }
2112 }
2113
2114 if (writebuf)
2115 aarch64_store_return_value (valtype, regcache, writebuf);
2116
2117 if (readbuf)
2118 aarch64_extract_return_value (valtype, regcache, readbuf);
2119
2120 if (aarch64_debug)
b277c936 2121 debug_printf ("return value in registers\n");
07b287a0
MS		 2122
2123 return RETURN_VALUE_REGISTER_CONVENTION;
2124}
2125
2126/* Implement the "get_longjmp_target" gdbarch method. */
2127
2128static int
2129aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2130{
2131 CORE_ADDR jb_addr;
2132 gdb_byte buf[X_REGISTER_SIZE];
2133 struct gdbarch *gdbarch = get_frame_arch (frame);
2134 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2135 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2136
2137 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2138
2139 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2140 X_REGISTER_SIZE))
2141 return 0;
2142
2143 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2144 return 1;
2145}
ea873d8e
PL		 2146
2147/* Implement the "gen_return_address" gdbarch method. */
2148
2149static void
2150aarch64_gen_return_address (struct gdbarch *gdbarch,
2151 struct agent_expr *ax, struct axs_value *value,
2152 CORE_ADDR scope)
2153{
2154 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2155 value->kind = axs_lvalue_register;
2156 value->u.reg = AARCH64_LR_REGNUM;
2157}
07b287a0
MS		 2158\f
2159
2160/* Return the pseudo register name corresponding to register regnum. */
2161
2162static const char *
2163aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2164{
63bad7b6
AH		 2165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2166
07b287a0
MS		 2167 static const char *const q_name[] =
2168 {
2169 "q0", "q1", "q2", "q3",
2170 "q4", "q5", "q6", "q7",
2171 "q8", "q9", "q10", "q11",
2172 "q12", "q13", "q14", "q15",
2173 "q16", "q17", "q18", "q19",
2174 "q20", "q21", "q22", "q23",
2175 "q24", "q25", "q26", "q27",
2176 "q28", "q29", "q30", "q31",
2177 };
2178
2179 static const char *const d_name[] =
2180 {
2181 "d0", "d1", "d2", "d3",
2182 "d4", "d5", "d6", "d7",
2183 "d8", "d9", "d10", "d11",
2184 "d12", "d13", "d14", "d15",
2185 "d16", "d17", "d18", "d19",
2186 "d20", "d21", "d22", "d23",
2187 "d24", "d25", "d26", "d27",
2188 "d28", "d29", "d30", "d31",
2189 };
2190
2191 static const char *const s_name[] =
2192 {
2193 "s0", "s1", "s2", "s3",
2194 "s4", "s5", "s6", "s7",
2195 "s8", "s9", "s10", "s11",
2196 "s12", "s13", "s14", "s15",
2197 "s16", "s17", "s18", "s19",
2198 "s20", "s21", "s22", "s23",
2199 "s24", "s25", "s26", "s27",
2200 "s28", "s29", "s30", "s31",
2201 };
2202
2203 static const char *const h_name[] =
2204 {
2205 "h0", "h1", "h2", "h3",
2206 "h4", "h5", "h6", "h7",
2207 "h8", "h9", "h10", "h11",
2208 "h12", "h13", "h14", "h15",
2209 "h16", "h17", "h18", "h19",
2210 "h20", "h21", "h22", "h23",
2211 "h24", "h25", "h26", "h27",
2212 "h28", "h29", "h30", "h31",
2213 };
2214
2215 static const char *const b_name[] =
2216 {
2217 "b0", "b1", "b2", "b3",
2218 "b4", "b5", "b6", "b7",
2219 "b8", "b9", "b10", "b11",
2220 "b12", "b13", "b14", "b15",
2221 "b16", "b17", "b18", "b19",
2222 "b20", "b21", "b22", "b23",
2223 "b24", "b25", "b26", "b27",
2224 "b28", "b29", "b30", "b31",
2225 };
2226
2227 regnum -= gdbarch_num_regs (gdbarch);
2228
2229 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2230 return q_name[regnum - AARCH64_Q0_REGNUM];
2231
2232 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2233 return d_name[regnum - AARCH64_D0_REGNUM];
2234
2235 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2236 return s_name[regnum - AARCH64_S0_REGNUM];
2237
2238 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2239 return h_name[regnum - AARCH64_H0_REGNUM];
2240
2241 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2242 return b_name[regnum - AARCH64_B0_REGNUM];
2243
63bad7b6
AH		 2244 if (tdep->has_sve ())
2245 {
2246 static const char *const sve_v_name[] =
2247 {
2248 "v0", "v1", "v2", "v3",
2249 "v4", "v5", "v6", "v7",
2250 "v8", "v9", "v10", "v11",
2251 "v12", "v13", "v14", "v15",
2252 "v16", "v17", "v18", "v19",
2253 "v20", "v21", "v22", "v23",
2254 "v24", "v25", "v26", "v27",
2255 "v28", "v29", "v30", "v31",
2256 };
2257
2258 if (regnum >= AARCH64_SVE_V0_REGNUM
2259 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2260 return sve_v_name[regnum - AARCH64_SVE_V0_REGNUM];
2261 }
2262
07b287a0
MS		 2263 internal_error (__FILE__, __LINE__,
2264 _("aarch64_pseudo_register_name: bad register number %d"),
2265 regnum);
2266}
2267
2268/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2269
2270static struct type *
2271aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2272{
63bad7b6
AH		 2273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2274
07b287a0
MS		 2275 regnum -= gdbarch_num_regs (gdbarch);
2276
2277 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2278 return aarch64_vnq_type (gdbarch);
2279
2280 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2281 return aarch64_vnd_type (gdbarch);
2282
2283 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2284 return aarch64_vns_type (gdbarch);
2285
2286 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2287 return aarch64_vnh_type (gdbarch);
2288
2289 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2290 return aarch64_vnb_type (gdbarch);
2291
63bad7b6
AH		 2292 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2293 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2294 return aarch64_vnv_type (gdbarch);
2295
07b287a0
MS		 2296 internal_error (__FILE__, __LINE__,
2297 _("aarch64_pseudo_register_type: bad register number %d"),
2298 regnum);
2299}
2300
2301/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2302
2303static int
2304aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2305 struct reggroup *group)
2306{
63bad7b6
AH		 2307 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2308
07b287a0
MS		 2309 regnum -= gdbarch_num_regs (gdbarch);
2310
2311 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2312 return group == all_reggroup || group == vector_reggroup;
2313 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2314 return (group == all_reggroup || group == vector_reggroup
2315 || group == float_reggroup);
2316 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2317 return (group == all_reggroup || group == vector_reggroup
2318 || group == float_reggroup);
2319 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2320 return group == all_reggroup || group == vector_reggroup;
2321 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2322 return group == all_reggroup || group == vector_reggroup;
63bad7b6
AH		 2323 else if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2324 && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2325 return group == all_reggroup || group == vector_reggroup;
07b287a0
MS		 2326
2327 return group == all_reggroup;
2328}
2329
3c5cd5c3
AH		 2330/* Helper for aarch64_pseudo_read_value. */
2331
2332static struct value *
63bad7b6
AH		 2333aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2334 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2335 int regsize, struct value *result_value)
2336{
3c5cd5c3
AH		 2337 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2338
63bad7b6
AH		 2339 /* Enough space for a full vector register. */
2340 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2341 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2342
3c5cd5c3
AH		 2343 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2344 mark_value_bytes_unavailable (result_value, 0,
2345 TYPE_LENGTH (value_type (result_value)));
2346 else
2347 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2348
3c5cd5c3
AH		 2349 return result_value;
2350 }
2351
07b287a0
MS		 2352/* Implement the "pseudo_register_read_value" gdbarch method. */
2353
2354static struct value *
3c5cd5c3 2355aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2356 int regnum)
2357{
63bad7b6 2358 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2359 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2360
07b287a0
MS		 2361 VALUE_LVAL (result_value) = lval_register;
2362 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2363
2364 regnum -= gdbarch_num_regs (gdbarch);
2365
2366 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2367 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2368 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2369 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2370
2371 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2372 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2373 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2374 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2375
2376 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2377 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2378 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2379 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2380
2381 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2382 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2383 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2384 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2385
2386 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2387 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2388 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2389 B_REGISTER_SIZE, result_value);
07b287a0 2390
63bad7b6
AH		 2391 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2392 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2393 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2394 regnum - AARCH64_SVE_V0_REGNUM,
2395 V_REGISTER_SIZE, result_value);
2396
07b287a0
MS		 2397 gdb_assert_not_reached ("regnum out of bound");
2398}
2399
3c5cd5c3 2400/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2401
2402static void
63bad7b6
AH		 2403aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2404 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2405{
3c5cd5c3 2406 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2407
63bad7b6
AH		 2408 /* Enough space for a full vector register. */
2409 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2410 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2411
07b287a0
MS		 2412 /* Ensure the register buffer is zero, we want gdb writes of the
2413 various 'scalar' pseudo registers to behavior like architectural
2414 writes, register width bytes are written the remainder are set to
2415 zero. */
63bad7b6 2416 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2417
3c5cd5c3
AH		 2418 memcpy (reg_buf, buf, regsize);
2419 regcache->raw_write (v_regnum, reg_buf);
2420}
2421
2422/* Implement the "pseudo_register_write" gdbarch method. */
2423
2424static void
2425aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2426 int regnum, const gdb_byte *buf)
2427{
63bad7b6 2428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2429 regnum -= gdbarch_num_regs (gdbarch);
2430
2431 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2432 return aarch64_pseudo_write_1 (gdbarch, regcache,
2433 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2434 buf);
07b287a0
MS		 2435
2436 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2437 return aarch64_pseudo_write_1 (gdbarch, regcache,
2438 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2439 buf);
07b287a0
MS		 2440
2441 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2442 return aarch64_pseudo_write_1 (gdbarch, regcache,
2443 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2444 buf);
07b287a0
MS		 2445
2446 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2447 return aarch64_pseudo_write_1 (gdbarch, regcache,
2448 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2449 buf);
07b287a0
MS		 2450
2451 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2452 return aarch64_pseudo_write_1 (gdbarch, regcache,
2453 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2454 buf);
2455
2456 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2457 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2458 return aarch64_pseudo_write_1 (gdbarch, regcache,
2459 regnum - AARCH64_SVE_V0_REGNUM,
2460 V_REGISTER_SIZE, buf);
07b287a0
MS		 2461
2462 gdb_assert_not_reached ("regnum out of bound");
2463}
2464
07b287a0
MS		 2465/* Callback function for user_reg_add. */
2466
2467static struct value *
2468value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2469{
9a3c8263 2470 const int *reg_p = (const int *) baton;
07b287a0
MS		 2471
2472 return value_of_register (*reg_p, frame);
2473}
2474\f
2475
9404b58f
KM		 2476/* Implement the "software_single_step" gdbarch method, needed to
2477 single step through atomic sequences on AArch64. */
2478
a0ff9e1a 2479static std::vector<CORE_ADDR>
f5ea389a 2480aarch64_software_single_step (struct regcache *regcache)
9404b58f 2481{
ac7936df 2482 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2483 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2484 const int insn_size = 4;
2485 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2486 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2487 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2488 CORE_ADDR loc = pc;
2489 CORE_ADDR closing_insn = 0;
2490 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2491 byte_order_for_code);
2492 int index;
2493 int insn_count;
2494 int bc_insn_count = 0; /* Conditional branch instruction count. */
2495 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2496 aarch64_inst inst;
2497
561a72d4 2498 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2499 return {};
9404b58f
KM		 2500
2501 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2502 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2503 return {};
9404b58f
KM		 2504
2505 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2506 {
9404b58f
KM		 2507 loc += insn_size;
2508 insn = read_memory_unsigned_integer (loc, insn_size,
2509 byte_order_for_code);
2510
561a72d4 2511 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2512 return {};
9404b58f 2513 /* Check if the instruction is a conditional branch. */
f77ee802 2514 if (inst.opcode->iclass == condbranch)
9404b58f 2515 {
f77ee802
YQ		 2516 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2517
9404b58f 2518 if (bc_insn_count >= 1)
a0ff9e1a 2519 return {};
9404b58f
KM		 2520
2521 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2522 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2523
2524 bc_insn_count++;
2525 last_breakpoint++;
2526 }
2527
2528 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2529 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2530 {
2531 closing_insn = loc;
2532 break;
2533 }
2534 }
2535
2536 /* We didn't find a closing Store Exclusive instruction, fall back. */
2537 if (!closing_insn)
a0ff9e1a 2538 return {};
9404b58f
KM		 2539
2540 /* Insert breakpoint after the end of the atomic sequence. */
2541 breaks[0] = loc + insn_size;
2542
2543 /* Check for duplicated breakpoints, and also check that the second
2544 breakpoint is not within the atomic sequence. */
2545 if (last_breakpoint
2546 && (breaks[1] == breaks[0]
2547 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2548 last_breakpoint = 0;
2549
a0ff9e1a
SM		 2550 std::vector<CORE_ADDR> next_pcs;
2551
9404b58f
KM		 2552 /* Insert the breakpoint at the end of the sequence, and one at the
2553 destination of the conditional branch, if it exists. */
2554 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2555 next_pcs.push_back (breaks[index]);
9404b58f 2556
93f9a11f 2557 return next_pcs;
9404b58f
KM		 2558}
2559
cfba9872 2560struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2561{
2562 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2563 is being displaced stepping. */
cfba9872 2564 int cond = 0;
b6542f81
YQ		 2565
2566 /* PC adjustment offset after displaced stepping. */
cfba9872 2567 int32_t pc_adjust = 0;
b6542f81
YQ		 2568};
2569
2570/* Data when visiting instructions for displaced stepping. */
2571
2572struct aarch64_displaced_step_data
2573{
2574 struct aarch64_insn_data base;
2575
2576 /* The address where the instruction will be executed at. */
2577 CORE_ADDR new_addr;
2578 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2579 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2580 /* Number of instructions in INSN_BUF. */
2581 unsigned insn_count;
2582 /* Registers when doing displaced stepping. */
2583 struct regcache *regs;
2584
cfba9872 2585 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2586};
2587
2588/* Implementation of aarch64_insn_visitor method "b". */
2589
2590static void
2591aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2592 struct aarch64_insn_data *data)
2593{
2594 struct aarch64_displaced_step_data *dsd
2595 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2596 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2597
2598 if (can_encode_int32 (new_offset, 28))
2599 {
2600 /* Emit B rather than BL, because executing BL on a new address
2601 will get the wrong address into LR. In order to avoid this,
2602 we emit B, and update LR if the instruction is BL. */
2603 emit_b (dsd->insn_buf, 0, new_offset);
2604 dsd->insn_count++;
2605 }
2606 else
2607 {
2608 /* Write NOP. */
2609 emit_nop (dsd->insn_buf);
2610 dsd->insn_count++;
2611 dsd->dsc->pc_adjust = offset;
2612 }
2613
2614 if (is_bl)
2615 {
2616 /* Update LR. */
2617 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2618 data->insn_addr + 4);
2619 }
2620}
2621
2622/* Implementation of aarch64_insn_visitor method "b_cond". */
2623
2624static void
2625aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2626 struct aarch64_insn_data *data)
2627{
2628 struct aarch64_displaced_step_data *dsd
2629 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2630
2631 /* GDB has to fix up PC after displaced step this instruction
2632 differently according to the condition is true or false. Instead
2633 of checking COND against conditional flags, we can use
2634 the following instructions, and GDB can tell how to fix up PC
2635 according to the PC value.
2636
2637 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2638 INSN1 ;
2639 TAKEN:
2640 INSN2
2641 */
2642
2643 emit_bcond (dsd->insn_buf, cond, 8);
2644 dsd->dsc->cond = 1;
2645 dsd->dsc->pc_adjust = offset;
2646 dsd->insn_count = 1;
2647}
2648
2649/* Dynamically allocate a new register. If we know the register
2650 statically, we should make it a global as above instead of using this
2651 helper function. */
2652
2653static struct aarch64_register
2654aarch64_register (unsigned num, int is64)
2655{
2656 return (struct aarch64_register) { num, is64 };
2657}
2658
2659/* Implementation of aarch64_insn_visitor method "cb". */
2660
2661static void
2662aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2663 const unsigned rn, int is64,
2664 struct aarch64_insn_data *data)
2665{
2666 struct aarch64_displaced_step_data *dsd
2667 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2668
2669 /* The offset is out of range for a compare and branch
2670 instruction. We can use the following instructions instead:
2671
2672 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2673 INSN1 ;
2674 TAKEN:
2675 INSN2
2676 */
2677 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2678 dsd->insn_count = 1;
2679 dsd->dsc->cond = 1;
2680 dsd->dsc->pc_adjust = offset;
2681}
2682
2683/* Implementation of aarch64_insn_visitor method "tb". */
2684
2685static void
2686aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2687 const unsigned rt, unsigned bit,
2688 struct aarch64_insn_data *data)
2689{
2690 struct aarch64_displaced_step_data *dsd
2691 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2692
2693 /* The offset is out of range for a test bit and branch
2694 instruction We can use the following instructions instead:
2695
2696 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2697 INSN1 ;
2698 TAKEN:
2699 INSN2
2700
2701 */
2702 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2703 dsd->insn_count = 1;
2704 dsd->dsc->cond = 1;
2705 dsd->dsc->pc_adjust = offset;
2706}
2707
2708/* Implementation of aarch64_insn_visitor method "adr". */
2709
2710static void
2711aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2712 const int is_adrp, struct aarch64_insn_data *data)
2713{
2714 struct aarch64_displaced_step_data *dsd
2715 = (struct aarch64_displaced_step_data *) data;
2716 /* We know exactly the address the ADR{P,} instruction will compute.
2717 We can just write it to the destination register. */
2718 CORE_ADDR address = data->insn_addr + offset;
2719
2720 if (is_adrp)
2721 {
2722 /* Clear the lower 12 bits of the offset to get the 4K page. */
2723 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2724 address & ~0xfff);
2725 }
2726 else
2727 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2728 address);
2729
2730 dsd->dsc->pc_adjust = 4;
2731 emit_nop (dsd->insn_buf);
2732 dsd->insn_count = 1;
2733}
2734
2735/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2736
2737static void
2738aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2739 const unsigned rt, const int is64,
2740 struct aarch64_insn_data *data)
2741{
2742 struct aarch64_displaced_step_data *dsd
2743 = (struct aarch64_displaced_step_data *) data;
2744 CORE_ADDR address = data->insn_addr + offset;
2745 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2746
2747 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2748 address);
2749
2750 if (is_sw)
2751 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2752 aarch64_register (rt, 1), zero);
2753 else
2754 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2755 aarch64_register (rt, 1), zero);
2756
2757 dsd->dsc->pc_adjust = 4;
2758}
2759
2760/* Implementation of aarch64_insn_visitor method "others". */
2761
2762static void
2763aarch64_displaced_step_others (const uint32_t insn,
2764 struct aarch64_insn_data *data)
2765{
2766 struct aarch64_displaced_step_data *dsd
2767 = (struct aarch64_displaced_step_data *) data;
2768
e1c587c3 2769 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2770 dsd->insn_count = 1;
2771
2772 if ((insn & 0xfffffc1f) == 0xd65f0000)
2773 {
2774 /* RET */
2775 dsd->dsc->pc_adjust = 0;
2776 }
2777 else
2778 dsd->dsc->pc_adjust = 4;
2779}
2780
2781static const struct aarch64_insn_visitor visitor =
2782{
2783 aarch64_displaced_step_b,
2784 aarch64_displaced_step_b_cond,
2785 aarch64_displaced_step_cb,
2786 aarch64_displaced_step_tb,
2787 aarch64_displaced_step_adr,
2788 aarch64_displaced_step_ldr_literal,
2789 aarch64_displaced_step_others,
2790};
2791
2792/* Implement the "displaced_step_copy_insn" gdbarch method. */
2793
2794struct displaced_step_closure *
2795aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2796 CORE_ADDR from, CORE_ADDR to,
2797 struct regcache *regs)
2798{
b6542f81
YQ		 2799 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2800 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2801 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 2802 aarch64_inst inst;
2803
561a72d4 2804 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 2805 return NULL;
b6542f81
YQ		 2806
2807 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 2808 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 2809 {
2810 /* We can't displaced step atomic sequences. */
2811 return NULL;
2812 }
2813
cfba9872
SM		 2814 std::unique_ptr<aarch64_displaced_step_closure> dsc
2815 (new aarch64_displaced_step_closure);
b6542f81
YQ		 2816 dsd.base.insn_addr = from;
2817 dsd.new_addr = to;
2818 dsd.regs = regs;
cfba9872 2819 dsd.dsc = dsc.get ();
034f1a81 2820 dsd.insn_count = 0;
b6542f81
YQ		 2821 aarch64_relocate_instruction (insn, &visitor,
2822 (struct aarch64_insn_data *) &dsd);
2823 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2824
2825 if (dsd.insn_count != 0)
2826 {
2827 int i;
2828
2829 /* Instruction can be relocated to scratch pad. Copy
2830 relocated instruction(s) there. */
2831 for (i = 0; i < dsd.insn_count; i++)
2832 {
2833 if (debug_displaced)
2834 {
2835 debug_printf ("displaced: writing insn ");
2836 debug_printf ("%.8x", dsd.insn_buf[i]);
2837 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2838 }
2839 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2840 (ULONGEST) dsd.insn_buf[i]);
2841 }
2842 }
2843 else
2844 {
b6542f81
YQ		 2845 dsc = NULL;
2846 }
2847
cfba9872 2848 return dsc.release ();
b6542f81
YQ		 2849}
2850
2851/* Implement the "displaced_step_fixup" gdbarch method. */
2852
2853void
2854aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 2855 struct displaced_step_closure *dsc_,
b6542f81
YQ		 2856 CORE_ADDR from, CORE_ADDR to,
2857 struct regcache *regs)
2858{
cfba9872
SM		 2859 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
2860
b6542f81
YQ		 2861 if (dsc->cond)
2862 {
2863 ULONGEST pc;
2864
2865 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2866 if (pc - to == 8)
2867 {
2868 /* Condition is true. */
2869 }
2870 else if (pc - to == 4)
2871 {
2872 /* Condition is false. */
2873 dsc->pc_adjust = 4;
2874 }
2875 else
2876 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2877 }
2878
2879 if (dsc->pc_adjust != 0)
2880 {
2881 if (debug_displaced)
2882 {
2883 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2884 paddress (gdbarch, from), dsc->pc_adjust);
2885 }
2886 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2887 from + dsc->pc_adjust);
2888 }
2889}
2890
2891/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2892
2893int
2894aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2895 struct displaced_step_closure *closure)
2896{
2897 return 1;
2898}
2899
95228a0d
AH		 2900/* Get the correct target description for the given VQ value.
2901 If VQ is zero then it is assumed SVE is not supported.
2902 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 2903
2904const target_desc *
39bfb937 2905aarch64_read_description (uint64_t vq)
da434ccb 2906{
95228a0d 2907 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 2908 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 2909 AARCH64_MAX_SVE_VQ);
2910
2911 struct target_desc *tdesc = tdesc_aarch64_list[vq];
da434ccb 2912
95228a0d
AH		 2913 if (tdesc == NULL)
2914 {
2915 tdesc = aarch64_create_target_description (vq);
2916 tdesc_aarch64_list[vq] = tdesc;
2917 }
da434ccb 2918
95228a0d 2919 return tdesc;
da434ccb
AH		 2920}
2921
ba2d2bb2
AH		 2922/* Return the VQ used when creating the target description TDESC. */
2923
1332a140 2924static uint64_t
ba2d2bb2
AH		 2925aarch64_get_tdesc_vq (const struct target_desc *tdesc)
2926{
2927 const struct tdesc_feature *feature_sve;
2928
2929 if (!tdesc_has_registers (tdesc))
2930 return 0;
2931
2932 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
2933
2934 if (feature_sve == nullptr)
2935 return 0;
2936
12863263
AH		 2937 uint64_t vl = tdesc_register_bitsize (feature_sve,
2938 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 2939 return sve_vq_from_vl (vl);
2940}
2941
2942
07b287a0
MS		 2943/* Initialize the current architecture based on INFO. If possible,
2944 re-use an architecture from ARCHES, which is a list of
2945 architectures already created during this debugging session.
2946
2947 Called e.g. at program startup, when reading a core file, and when
2948 reading a binary file. */
2949
2950static struct gdbarch *
2951aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2952{
2953 struct gdbarch_tdep *tdep;
2954 struct gdbarch *gdbarch;
2955 struct gdbarch_list *best_arch;
2956 struct tdesc_arch_data *tdesc_data = NULL;
2957 const struct target_desc *tdesc = info.target_desc;
2958 int i;
07b287a0 2959 int valid_p = 1;
ba2d2bb2
AH		 2960 const struct tdesc_feature *feature_core;
2961 const struct tdesc_feature *feature_fpu;
2962 const struct tdesc_feature *feature_sve;
07b287a0
MS		 2963 int num_regs = 0;
2964 int num_pseudo_regs = 0;
2965
ba2d2bb2 2966 /* Ensure we always have a target description. */
07b287a0 2967 if (!tdesc_has_registers (tdesc))
ba2d2bb2 2968 tdesc = aarch64_read_description (0);
07b287a0
MS		 2969 gdb_assert (tdesc);
2970
ba2d2bb2
AH		 2971 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2972 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2973 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
07b287a0 2974
ba2d2bb2 2975 if (feature_core == NULL)
07b287a0
MS		 2976 return NULL;
2977
2978 tdesc_data = tdesc_data_alloc ();
2979
ba2d2bb2 2980 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 2981 and allocate their numbers. */
2982 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 2983 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
2984 AARCH64_X0_REGNUM + i,
2985 aarch64_r_register_names[i]);
07b287a0
MS		 2986
2987 num_regs = AARCH64_X0_REGNUM + i;
2988
ba2d2bb2
AH		 2989 /* Add the V registers. */
2990 if (feature_fpu != NULL)
07b287a0 2991 {
ba2d2bb2
AH		 2992 if (feature_sve != NULL)
2993 error (_("Program contains both fpu and SVE features."));
2994
2995 /* Validate the description provides the mandatory V registers
2996 and allocate their numbers. */
07b287a0 2997 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 2998 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
2999 AARCH64_V0_REGNUM + i,
3000 aarch64_v_register_names[i]);
07b287a0
MS		 3001
3002 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 3003 }
07b287a0 3004
ba2d2bb2
AH		 3005 /* Add the SVE registers. */
3006 if (feature_sve != NULL)
3007 {
3008 /* Validate the description provides the mandatory SVE registers
3009 and allocate their numbers. */
3010 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3011 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3012 AARCH64_SVE_Z0_REGNUM + i,
3013 aarch64_sve_register_names[i]);
3014
3015 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3016 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3017 }
3018
3019 if (feature_fpu != NULL || feature_sve != NULL)
3020 {
07b287a0
MS		 3021 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3022 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3023 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3024 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3025 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3026 }
3027
3028 if (!valid_p)
3029 {
3030 tdesc_data_cleanup (tdesc_data);
3031 return NULL;
3032 }
3033
3034 /* AArch64 code is always little-endian. */
3035 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3036
3037 /* If there is already a candidate, use it. */
3038 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3039 best_arch != NULL;
3040 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3041 {
3042 /* Found a match. */
3043 break;
3044 }
3045
3046 if (best_arch != NULL)
3047 {
3048 if (tdesc_data != NULL)
3049 tdesc_data_cleanup (tdesc_data);
3050 return best_arch->gdbarch;
3051 }
3052
8d749320 3053 tdep = XCNEW (struct gdbarch_tdep);
07b287a0
MS		 3054 gdbarch = gdbarch_alloc (&info, tdep);
3055
3056 /* This should be low enough for everything. */
3057 tdep->lowest_pc = 0x20;
3058 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3059 tdep->jb_elt_size = 8;
ba2d2bb2 3060 tdep->vq = aarch64_get_tdesc_vq (tdesc);
07b287a0
MS		 3061
3062 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3063 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3064
07b287a0
MS		 3065 /* Frame handling. */
3066 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
3067 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
3068 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
3069
3070 /* Advance PC across function entry code. */
3071 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3072
3073 /* The stack grows downward. */
3074 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3075
3076 /* Breakpoint manipulation. */
04180708
YQ		 3077 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3078 aarch64_breakpoint::kind_from_pc);
3079 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3080 aarch64_breakpoint::bp_from_kind);
07b287a0 3081 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3082 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3083
3084 /* Information about registers, etc. */
3085 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3086 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3087 set_gdbarch_num_regs (gdbarch, num_regs);
3088
3089 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3090 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3091 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3092 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3093 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3094 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3095 aarch64_pseudo_register_reggroup_p);
3096
3097 /* ABI */
3098 set_gdbarch_short_bit (gdbarch, 16);
3099 set_gdbarch_int_bit (gdbarch, 32);
3100 set_gdbarch_float_bit (gdbarch, 32);
3101 set_gdbarch_double_bit (gdbarch, 64);
3102 set_gdbarch_long_double_bit (gdbarch, 128);
3103 set_gdbarch_long_bit (gdbarch, 64);
3104 set_gdbarch_long_long_bit (gdbarch, 64);
3105 set_gdbarch_ptr_bit (gdbarch, 64);
3106 set_gdbarch_char_signed (gdbarch, 0);
53375380 3107 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3108 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3109 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3110 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3111
3112 /* Internal <-> external register number maps. */
3113 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3114
3115 /* Returning results. */
3116 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3117
3118 /* Disassembly. */
3119 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3120
3121 /* Virtual tables. */
3122 set_gdbarch_vbit_in_delta (gdbarch, 1);
3123
3124 /* Hook in the ABI-specific overrides, if they have been registered. */
3125 info.target_desc = tdesc;
0dba2a6c 3126 info.tdesc_data = tdesc_data;
07b287a0
MS		 3127 gdbarch_init_osabi (info, gdbarch);
3128
3129 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
3130
3131 /* Add some default predicates. */
3132 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3133 dwarf2_append_unwinders (gdbarch);
3134 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3135
3136 frame_base_set_default (gdbarch, &aarch64_normal_base);
3137
3138 /* Now we have tuned the configuration, set a few final things,
3139 based on what the OS ABI has told us. */
3140
3141 if (tdep->jb_pc >= 0)
3142 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3143
ea873d8e
PL		 3144 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3145
07b287a0
MS		 3146 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3147
3148 /* Add standard register aliases. */
3149 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3150 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3151 value_of_aarch64_user_reg,
3152 &aarch64_register_aliases[i].regnum);
3153
e8bf1ce4
JB		 3154 register_aarch64_ravenscar_ops (gdbarch);
3155
07b287a0
MS		 3156 return gdbarch;
3157}
3158
3159static void
3160aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3161{
3162 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3163
3164 if (tdep == NULL)
3165 return;
3166
3167 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3168 paddress (gdbarch, tdep->lowest_pc));
3169}
3170
0d4c07af 3171#if GDB_SELF_TEST
1e2b521d
YQ		 3172namespace selftests
3173{
3174static void aarch64_process_record_test (void);
3175}
0d4c07af 3176#endif
1e2b521d 3177
07b287a0
MS		 3178void
3179_initialize_aarch64_tdep (void)
3180{
3181 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3182 aarch64_dump_tdep);
3183
07b287a0
MS		 3184 /* Debug this file's internals. */
3185 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3186Set AArch64 debugging."), _("\
3187Show AArch64 debugging."), _("\
3188When on, AArch64 specific debugging is enabled."),
3189 NULL,
3190 show_aarch64_debug,
3191 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3192
3193#if GDB_SELF_TEST
1526853e
SM		 3194 selftests::register_test ("aarch64-analyze-prologue",
3195 selftests::aarch64_analyze_prologue_test);
3196 selftests::register_test ("aarch64-process-record",
3197 selftests::aarch64_process_record_test);
6654d750 3198 selftests::record_xml_tdesc ("aarch64.xml",
95228a0d 3199 aarch64_create_target_description (0));
4d9a9006 3200#endif
07b287a0 3201}
99afc88b
OJ		 3202
3203/* AArch64 process record-replay related structures, defines etc. */
3204
99afc88b
OJ		 3205#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3206 do \
3207 { \
3208 unsigned int reg_len = LENGTH; \
3209 if (reg_len) \
3210 { \
3211 REGS = XNEWVEC (uint32_t, reg_len); \
3212 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3213 } \
3214 } \
3215 while (0)
3216
3217#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3218 do \
3219 { \
3220 unsigned int mem_len = LENGTH; \
3221 if (mem_len) \
3222 { \
3223 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3224 memcpy(&MEMS->len, &RECORD_BUF[0], \
3225 sizeof(struct aarch64_mem_r) * LENGTH); \
3226 } \
3227 } \
3228 while (0)
3229
3230/* AArch64 record/replay structures and enumerations. */
3231
3232struct aarch64_mem_r
3233{
3234 uint64_t len; /* Record length. */
3235 uint64_t addr; /* Memory address. */
3236};
3237
3238enum aarch64_record_result
3239{
3240 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3241 AARCH64_RECORD_UNSUPPORTED,
3242 AARCH64_RECORD_UNKNOWN
3243};
3244
3245typedef struct insn_decode_record_t
3246{
3247 struct gdbarch *gdbarch;
3248 struct regcache *regcache;
3249 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3250 uint32_t aarch64_insn; /* Insn to be recorded. */
3251 uint32_t mem_rec_count; /* Count of memory records. */
3252 uint32_t reg_rec_count; /* Count of register records. */
3253 uint32_t *aarch64_regs; /* Registers to be recorded. */
3254 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3255} insn_decode_record;
3256
3257/* Record handler for data processing - register instructions. */
3258
3259static unsigned int
3260aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3261{
3262 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3263 uint32_t record_buf[4];
3264
3265 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3266 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3267 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3268
3269 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3270 {
3271 uint8_t setflags;
3272
3273 /* Logical (shifted register). */
3274 if (insn_bits24_27 == 0x0a)
3275 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3276 /* Add/subtract. */
3277 else if (insn_bits24_27 == 0x0b)
3278 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3279 else
3280 return AARCH64_RECORD_UNKNOWN;
3281
3282 record_buf[0] = reg_rd;
3283 aarch64_insn_r->reg_rec_count = 1;
3284 if (setflags)
3285 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3286 }
3287 else
3288 {
3289 if (insn_bits24_27 == 0x0b)
3290 {
3291 /* Data-processing (3 source). */
3292 record_buf[0] = reg_rd;
3293 aarch64_insn_r->reg_rec_count = 1;
3294 }
3295 else if (insn_bits24_27 == 0x0a)
3296 {
3297 if (insn_bits21_23 == 0x00)
3298 {
3299 /* Add/subtract (with carry). */
3300 record_buf[0] = reg_rd;
3301 aarch64_insn_r->reg_rec_count = 1;
3302 if (bit (aarch64_insn_r->aarch64_insn, 29))
3303 {
3304 record_buf[1] = AARCH64_CPSR_REGNUM;
3305 aarch64_insn_r->reg_rec_count = 2;
3306 }
3307 }
3308 else if (insn_bits21_23 == 0x02)
3309 {
3310 /* Conditional compare (register) and conditional compare
3311 (immediate) instructions. */
3312 record_buf[0] = AARCH64_CPSR_REGNUM;
3313 aarch64_insn_r->reg_rec_count = 1;
3314 }
3315 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3316 {
3317 /* CConditional select. */
3318 /* Data-processing (2 source). */
3319 /* Data-processing (1 source). */
3320 record_buf[0] = reg_rd;
3321 aarch64_insn_r->reg_rec_count = 1;
3322 }
3323 else
3324 return AARCH64_RECORD_UNKNOWN;
3325 }
3326 }
3327
3328 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3329 record_buf);
3330 return AARCH64_RECORD_SUCCESS;
3331}
3332
3333/* Record handler for data processing - immediate instructions. */
3334
3335static unsigned int
3336aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3337{
78cc6c2d 3338 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3339 uint32_t record_buf[4];
3340
3341 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3342 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3343 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3344
3345 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3346 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3347 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3348 {
3349 record_buf[0] = reg_rd;
3350 aarch64_insn_r->reg_rec_count = 1;
3351 }
3352 else if (insn_bits24_27 == 0x01)
3353 {
3354 /* Add/Subtract (immediate). */
3355 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3356 record_buf[0] = reg_rd;
3357 aarch64_insn_r->reg_rec_count = 1;
3358 if (setflags)
3359 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3360 }
3361 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3362 {
3363 /* Logical (immediate). */
3364 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3365 record_buf[0] = reg_rd;
3366 aarch64_insn_r->reg_rec_count = 1;
3367 if (setflags)
3368 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3369 }
3370 else
3371 return AARCH64_RECORD_UNKNOWN;
3372
3373 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3374 record_buf);
3375 return AARCH64_RECORD_SUCCESS;
3376}
3377
3378/* Record handler for branch, exception generation and system instructions. */
3379
3380static unsigned int
3381aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3382{
3383 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3384 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3385 uint32_t record_buf[4];
3386
3387 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3388 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3389 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3390
3391 if (insn_bits28_31 == 0x0d)
3392 {
3393 /* Exception generation instructions. */
3394 if (insn_bits24_27 == 0x04)
3395 {
5d98d3cd
YQ		 3396 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3397 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3398 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3399 {
3400 ULONGEST svc_number;
3401
3402 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3403 &svc_number);
3404 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3405 svc_number);
3406 }
3407 else
3408 return AARCH64_RECORD_UNSUPPORTED;
3409 }
3410 /* System instructions. */
3411 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3412 {
3413 uint32_t reg_rt, reg_crn;
3414
3415 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3416 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3417
3418 /* Record rt in case of sysl and mrs instructions. */
3419 if (bit (aarch64_insn_r->aarch64_insn, 21))
3420 {
3421 record_buf[0] = reg_rt;
3422 aarch64_insn_r->reg_rec_count = 1;
3423 }
3424 /* Record cpsr for hint and msr(immediate) instructions. */
3425 else if (reg_crn == 0x02 || reg_crn == 0x04)
3426 {
3427 record_buf[0] = AARCH64_CPSR_REGNUM;
3428 aarch64_insn_r->reg_rec_count = 1;
3429 }
3430 }
3431 /* Unconditional branch (register). */
3432 else if((insn_bits24_27 & 0x0e) == 0x06)
3433 {
3434 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3435 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3436 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3437 }
3438 else
3439 return AARCH64_RECORD_UNKNOWN;
3440 }
3441 /* Unconditional branch (immediate). */
3442 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3443 {
3444 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3445 if (bit (aarch64_insn_r->aarch64_insn, 31))
3446 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3447 }
3448 else
3449 /* Compare & branch (immediate), Test & branch (immediate) and
3450 Conditional branch (immediate). */
3451 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3452
3453 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3454 record_buf);
3455 return AARCH64_RECORD_SUCCESS;
3456}
3457
3458/* Record handler for advanced SIMD load and store instructions. */
3459
3460static unsigned int
3461aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3462{
3463 CORE_ADDR address;
3464 uint64_t addr_offset = 0;
3465 uint32_t record_buf[24];
3466 uint64_t record_buf_mem[24];
3467 uint32_t reg_rn, reg_rt;
3468 uint32_t reg_index = 0, mem_index = 0;
3469 uint8_t opcode_bits, size_bits;
3470
3471 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3472 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3473 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3474 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3475 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3476
3477 if (record_debug)
b277c936 3478 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3479
3480 /* Load/store single structure. */
3481 if (bit (aarch64_insn_r->aarch64_insn, 24))
3482 {
3483 uint8_t sindex, scale, selem, esize, replicate = 0;
3484 scale = opcode_bits >> 2;
3485 selem = ((opcode_bits & 0x02) |
3486 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3487 switch (scale)
3488 {
3489 case 1:
3490 if (size_bits & 0x01)
3491 return AARCH64_RECORD_UNKNOWN;
3492 break;
3493 case 2:
3494 if ((size_bits >> 1) & 0x01)
3495 return AARCH64_RECORD_UNKNOWN;
3496 if (size_bits & 0x01)
3497 {
3498 if (!((opcode_bits >> 1) & 0x01))
3499 scale = 3;
3500 else
3501 return AARCH64_RECORD_UNKNOWN;
3502 }
3503 break;
3504 case 3:
3505 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3506 {
3507 scale = size_bits;
3508 replicate = 1;
3509 break;
3510 }
3511 else
3512 return AARCH64_RECORD_UNKNOWN;
3513 default:
3514 break;
3515 }
3516 esize = 8 << scale;
3517 if (replicate)
3518 for (sindex = 0; sindex < selem; sindex++)
3519 {
3520 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3521 reg_rt = (reg_rt + 1) % 32;
3522 }
3523 else
3524 {
3525 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3526 {
3527 if (bit (aarch64_insn_r->aarch64_insn, 22))
3528 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3529 else
3530 {
3531 record_buf_mem[mem_index++] = esize / 8;
3532 record_buf_mem[mem_index++] = address + addr_offset;
3533 }
3534 addr_offset = addr_offset + (esize / 8);
3535 reg_rt = (reg_rt + 1) % 32;
3536 }
99afc88b
OJ		 3537 }
3538 }
3539 /* Load/store multiple structure. */
3540 else
3541 {
3542 uint8_t selem, esize, rpt, elements;
3543 uint8_t eindex, rindex;
3544
3545 esize = 8 << size_bits;
3546 if (bit (aarch64_insn_r->aarch64_insn, 30))
3547 elements = 128 / esize;
3548 else
3549 elements = 64 / esize;
3550
3551 switch (opcode_bits)
3552 {
3553 /*LD/ST4 (4 Registers). */
3554 case 0:
3555 rpt = 1;
3556 selem = 4;
3557 break;
3558 /*LD/ST1 (4 Registers). */
3559 case 2:
3560 rpt = 4;
3561 selem = 1;
3562 break;
3563 /*LD/ST3 (3 Registers). */
3564 case 4:
3565 rpt = 1;
3566 selem = 3;
3567 break;
3568 /*LD/ST1 (3 Registers). */
3569 case 6:
3570 rpt = 3;
3571 selem = 1;
3572 break;
3573 /*LD/ST1 (1 Register). */
3574 case 7:
3575 rpt = 1;
3576 selem = 1;
3577 break;
3578 /*LD/ST2 (2 Registers). */
3579 case 8:
3580 rpt = 1;
3581 selem = 2;
3582 break;
3583 /*LD/ST1 (2 Registers). */
3584 case 10:
3585 rpt = 2;
3586 selem = 1;
3587 break;
3588 default:
3589 return AARCH64_RECORD_UNSUPPORTED;
3590 break;
3591 }
3592 for (rindex = 0; rindex < rpt; rindex++)
3593 for (eindex = 0; eindex < elements; eindex++)
3594 {
3595 uint8_t reg_tt, sindex;
3596 reg_tt = (reg_rt + rindex) % 32;
3597 for (sindex = 0; sindex < selem; sindex++)
3598 {
3599 if (bit (aarch64_insn_r->aarch64_insn, 22))
3600 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3601 else
3602 {
3603 record_buf_mem[mem_index++] = esize / 8;
3604 record_buf_mem[mem_index++] = address + addr_offset;
3605 }
3606 addr_offset = addr_offset + (esize / 8);
3607 reg_tt = (reg_tt + 1) % 32;
3608 }
3609 }
3610 }
3611
3612 if (bit (aarch64_insn_r->aarch64_insn, 23))
3613 record_buf[reg_index++] = reg_rn;
3614
3615 aarch64_insn_r->reg_rec_count = reg_index;
3616 aarch64_insn_r->mem_rec_count = mem_index / 2;
3617 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3618 record_buf_mem);
3619 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3620 record_buf);
3621 return AARCH64_RECORD_SUCCESS;
3622}
3623
3624/* Record handler for load and store instructions. */
3625
3626static unsigned int
3627aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3628{
3629 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3630 uint8_t insn_bit23, insn_bit21;
3631 uint8_t opc, size_bits, ld_flag, vector_flag;
3632 uint32_t reg_rn, reg_rt, reg_rt2;
3633 uint64_t datasize, offset;
3634 uint32_t record_buf[8];
3635 uint64_t record_buf_mem[8];
3636 CORE_ADDR address;
3637
3638 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3639 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3640 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3641 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3642 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3643 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3644 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3645 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3646 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3647 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3648 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3649
3650 /* Load/store exclusive. */
3651 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3652 {
3653 if (record_debug)
b277c936 3654 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3655
3656 if (ld_flag)
3657 {
3658 record_buf[0] = reg_rt;
3659 aarch64_insn_r->reg_rec_count = 1;
3660 if (insn_bit21)
3661 {
3662 record_buf[1] = reg_rt2;
3663 aarch64_insn_r->reg_rec_count = 2;
3664 }
3665 }
3666 else
3667 {
3668 if (insn_bit21)
3669 datasize = (8 << size_bits) * 2;
3670 else
3671 datasize = (8 << size_bits);
3672 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3673 &address);
3674 record_buf_mem[0] = datasize / 8;
3675 record_buf_mem[1] = address;
3676 aarch64_insn_r->mem_rec_count = 1;
3677 if (!insn_bit23)
3678 {
3679 /* Save register rs. */
3680 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3681 aarch64_insn_r->reg_rec_count = 1;
3682 }
3683 }
3684 }
3685 /* Load register (literal) instructions decoding. */
3686 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3687 {
3688 if (record_debug)
b277c936 3689 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3690 if (vector_flag)
3691 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3692 else
3693 record_buf[0] = reg_rt;
3694 aarch64_insn_r->reg_rec_count = 1;
3695 }
3696 /* All types of load/store pair instructions decoding. */
3697 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3698 {
3699 if (record_debug)
b277c936 3700 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 3701
3702 if (ld_flag)
3703 {
3704 if (vector_flag)
3705 {
3706 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3707 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3708 }
3709 else
3710 {
3711 record_buf[0] = reg_rt;
3712 record_buf[1] = reg_rt2;
3713 }
3714 aarch64_insn_r->reg_rec_count = 2;
3715 }
3716 else
3717 {
3718 uint16_t imm7_off;
3719 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3720 if (!vector_flag)
3721 size_bits = size_bits >> 1;
3722 datasize = 8 << (2 + size_bits);
3723 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3724 offset = offset << (2 + size_bits);
3725 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3726 &address);
3727 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3728 {
3729 if (imm7_off & 0x40)
3730 address = address - offset;
3731 else
3732 address = address + offset;
3733 }
3734
3735 record_buf_mem[0] = datasize / 8;
3736 record_buf_mem[1] = address;
3737 record_buf_mem[2] = datasize / 8;
3738 record_buf_mem[3] = address + (datasize / 8);
3739 aarch64_insn_r->mem_rec_count = 2;
3740 }
3741 if (bit (aarch64_insn_r->aarch64_insn, 23))
3742 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3743 }
3744 /* Load/store register (unsigned immediate) instructions. */
3745 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3746 {
3747 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3748 if (!(opc >> 1))
33877125
YQ		 3749 {
3750 if (opc & 0x01)
3751 ld_flag = 0x01;
3752 else
3753 ld_flag = 0x0;
3754 }
99afc88b 3755 else
33877125 3756 {
1e2b521d
YQ		 3757 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3758 {
3759 /* PRFM (immediate) */
3760 return AARCH64_RECORD_SUCCESS;
3761 }
3762 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3763 {
3764 /* LDRSW (immediate) */
3765 ld_flag = 0x1;
3766 }
33877125 3767 else
1e2b521d
YQ		 3768 {
3769 if (opc & 0x01)
3770 ld_flag = 0x01;
3771 else
3772 ld_flag = 0x0;
3773 }
33877125 3774 }
99afc88b
OJ		 3775
3776 if (record_debug)
3777 {
b277c936
PL		 3778 debug_printf ("Process record: load/store (unsigned immediate):"
3779 " size %x V %d opc %x\n", size_bits, vector_flag,
3780 opc);
99afc88b
OJ		 3781 }
3782
3783 if (!ld_flag)
3784 {
3785 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3786 datasize = 8 << size_bits;
3787 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3788 &address);
3789 offset = offset << size_bits;
3790 address = address + offset;
3791
3792 record_buf_mem[0] = datasize >> 3;
3793 record_buf_mem[1] = address;
3794 aarch64_insn_r->mem_rec_count = 1;
3795 }
3796 else
3797 {
3798 if (vector_flag)
3799 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3800 else
3801 record_buf[0] = reg_rt;
3802 aarch64_insn_r->reg_rec_count = 1;
3803 }
3804 }
3805 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 3806 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3807 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 3808 {
3809 if (record_debug)
b277c936 3810 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 3811 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3812 if (!(opc >> 1))
3813 if (opc & 0x01)
3814 ld_flag = 0x01;
3815 else
3816 ld_flag = 0x0;
3817 else
3818 if (size_bits != 0x03)
3819 ld_flag = 0x01;
3820 else
3821 return AARCH64_RECORD_UNKNOWN;
3822
3823 if (!ld_flag)
3824 {
d9436c7c
PA		 3825 ULONGEST reg_rm_val;
3826
99afc88b
OJ		 3827 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3828 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
3829 if (bit (aarch64_insn_r->aarch64_insn, 12))
3830 offset = reg_rm_val << size_bits;
3831 else
3832 offset = reg_rm_val;
3833 datasize = 8 << size_bits;
3834 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3835 &address);
3836 address = address + offset;
3837 record_buf_mem[0] = datasize >> 3;
3838 record_buf_mem[1] = address;
3839 aarch64_insn_r->mem_rec_count = 1;
3840 }
3841 else
3842 {
3843 if (vector_flag)
3844 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3845 else
3846 record_buf[0] = reg_rt;
3847 aarch64_insn_r->reg_rec_count = 1;
3848 }
3849 }
3850 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 3851 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3852 && !insn_bit21)
99afc88b
OJ		 3853 {
3854 if (record_debug)
3855 {
b277c936
PL		 3856 debug_printf ("Process record: load/store "
3857 "(immediate and unprivileged)\n");
99afc88b
OJ		 3858 }
3859 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3860 if (!(opc >> 1))
3861 if (opc & 0x01)
3862 ld_flag = 0x01;
3863 else
3864 ld_flag = 0x0;
3865 else
3866 if (size_bits != 0x03)
3867 ld_flag = 0x01;
3868 else
3869 return AARCH64_RECORD_UNKNOWN;
3870
3871 if (!ld_flag)
3872 {
3873 uint16_t imm9_off;
3874 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3875 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3876 datasize = 8 << size_bits;
3877 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3878 &address);
3879 if (insn_bits10_11 != 0x01)
3880 {
3881 if (imm9_off & 0x0100)
3882 address = address - offset;
3883 else
3884 address = address + offset;
3885 }
3886 record_buf_mem[0] = datasize >> 3;
3887 record_buf_mem[1] = address;
3888 aarch64_insn_r->mem_rec_count = 1;
3889 }
3890 else
3891 {
3892 if (vector_flag)
3893 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3894 else
3895 record_buf[0] = reg_rt;
3896 aarch64_insn_r->reg_rec_count = 1;
3897 }
3898 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3899 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3900 }
3901 /* Advanced SIMD load/store instructions. */
3902 else
3903 return aarch64_record_asimd_load_store (aarch64_insn_r);
3904
3905 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3906 record_buf_mem);
3907 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3908 record_buf);
3909 return AARCH64_RECORD_SUCCESS;
3910}
3911
3912/* Record handler for data processing SIMD and floating point instructions. */
3913
3914static unsigned int
3915aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3916{
3917 uint8_t insn_bit21, opcode, rmode, reg_rd;
3918 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3919 uint8_t insn_bits11_14;
3920 uint32_t record_buf[2];
3921
3922 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3923 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3924 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3925 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3926 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3927 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3928 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3929 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3930 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3931
3932 if (record_debug)
b277c936 3933 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 3934
3935 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3936 {
3937 /* Floating point - fixed point conversion instructions. */
3938 if (!insn_bit21)
3939 {
3940 if (record_debug)
b277c936 3941 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 3942
3943 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3944 record_buf[0] = reg_rd;
3945 else
3946 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3947 }
3948 /* Floating point - conditional compare instructions. */
3949 else if (insn_bits10_11 == 0x01)
3950 {
3951 if (record_debug)
b277c936 3952 debug_printf ("FP - conditional compare");
99afc88b
OJ		 3953
3954 record_buf[0] = AARCH64_CPSR_REGNUM;
3955 }
3956 /* Floating point - data processing (2-source) and
3957 conditional select instructions. */
3958 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3959 {
3960 if (record_debug)
b277c936 3961 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 3962
3963 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3964 }
3965 else if (insn_bits10_11 == 0x00)
3966 {
3967 /* Floating point - immediate instructions. */
3968 if ((insn_bits12_15 & 0x01) == 0x01
3969 || (insn_bits12_15 & 0x07) == 0x04)
3970 {
3971 if (record_debug)
b277c936 3972 debug_printf ("FP - immediate");
99afc88b
OJ		 3973 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3974 }
3975 /* Floating point - compare instructions. */
3976 else if ((insn_bits12_15 & 0x03) == 0x02)
3977 {
3978 if (record_debug)
b277c936 3979 debug_printf ("FP - immediate");
99afc88b
OJ		 3980 record_buf[0] = AARCH64_CPSR_REGNUM;
3981 }
3982 /* Floating point - integer conversions instructions. */
f62fce35 3983 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 3984 {
3985 /* Convert float to integer instruction. */
3986 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3987 {
3988 if (record_debug)
b277c936 3989 debug_printf ("float to int conversion");
99afc88b
OJ		 3990
3991 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3992 }
3993 /* Convert integer to float instruction. */
3994 else if ((opcode >> 1) == 0x01 && !rmode)
3995 {
3996 if (record_debug)
b277c936 3997 debug_printf ("int to float conversion");
99afc88b
OJ		 3998
3999 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4000 }
4001 /* Move float to integer instruction. */
4002 else if ((opcode >> 1) == 0x03)
4003 {
4004 if (record_debug)
b277c936 4005 debug_printf ("move float to int");
99afc88b
OJ		 4006
4007 if (!(opcode & 0x01))
4008 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4009 else
4010 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4011 }
f62fce35
YQ		 4012 else
4013 return AARCH64_RECORD_UNKNOWN;
99afc88b 4014 }
f62fce35
YQ		 4015 else
4016 return AARCH64_RECORD_UNKNOWN;
99afc88b 4017 }
f62fce35
YQ		 4018 else
4019 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4020 }
4021 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4022 {
4023 if (record_debug)
b277c936 4024 debug_printf ("SIMD copy");
99afc88b
OJ		 4025
4026 /* Advanced SIMD copy instructions. */
4027 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4028 && !bit (aarch64_insn_r->aarch64_insn, 15)
4029 && bit (aarch64_insn_r->aarch64_insn, 10))
4030 {
4031 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4032 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4033 else
4034 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4035 }
4036 else
4037 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4038 }
4039 /* All remaining floating point or advanced SIMD instructions. */
4040 else
4041 {
4042 if (record_debug)
b277c936 4043 debug_printf ("all remain");
99afc88b
OJ		 4044
4045 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4046 }
4047
4048 if (record_debug)
b277c936 4049 debug_printf ("\n");
99afc88b
OJ		 4050
4051 aarch64_insn_r->reg_rec_count++;
4052 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4053 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4054 record_buf);
4055 return AARCH64_RECORD_SUCCESS;
4056}
4057
4058/* Decodes insns type and invokes its record handler. */
4059
4060static unsigned int
4061aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4062{
4063 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4064
4065 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4066 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4067 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4068 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4069
4070 /* Data processing - immediate instructions. */
4071 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4072 return aarch64_record_data_proc_imm (aarch64_insn_r);
4073
4074 /* Branch, exception generation and system instructions. */
4075 if (ins_bit26 && !ins_bit27 && ins_bit28)
4076 return aarch64_record_branch_except_sys (aarch64_insn_r);
4077
4078 /* Load and store instructions. */
4079 if (!ins_bit25 && ins_bit27)
4080 return aarch64_record_load_store (aarch64_insn_r);
4081
4082 /* Data processing - register instructions. */
4083 if (ins_bit25 && !ins_bit26 && ins_bit27)
4084 return aarch64_record_data_proc_reg (aarch64_insn_r);
4085
4086 /* Data processing - SIMD and floating point instructions. */
4087 if (ins_bit25 && ins_bit26 && ins_bit27)
4088 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4089
4090 return AARCH64_RECORD_UNSUPPORTED;
4091}
4092
4093/* Cleans up local record registers and memory allocations. */
4094
4095static void
4096deallocate_reg_mem (insn_decode_record *record)
4097{
4098 xfree (record->aarch64_regs);
4099 xfree (record->aarch64_mems);
4100}
4101
1e2b521d
YQ		 4102#if GDB_SELF_TEST
4103namespace selftests {
4104
4105static void
4106aarch64_process_record_test (void)
4107{
4108 struct gdbarch_info info;
4109 uint32_t ret;
4110
4111 gdbarch_info_init (&info);
4112 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4113
4114 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4115 SELF_CHECK (gdbarch != NULL);
4116
4117 insn_decode_record aarch64_record;
4118
4119 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4120 aarch64_record.regcache = NULL;
4121 aarch64_record.this_addr = 0;
4122 aarch64_record.gdbarch = gdbarch;
4123
4124 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4125 aarch64_record.aarch64_insn = 0xf9800020;
4126 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4127 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4128 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4129 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4130
4131 deallocate_reg_mem (&aarch64_record);
4132}
4133
4134} // namespace selftests
4135#endif /* GDB_SELF_TEST */
4136
99afc88b
OJ		 4137/* Parse the current instruction and record the values of the registers and
4138 memory that will be changed in current instruction to record_arch_list
4139 return -1 if something is wrong. */
4140
4141int
4142aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4143 CORE_ADDR insn_addr)
4144{
4145 uint32_t rec_no = 0;
4146 uint8_t insn_size = 4;
4147 uint32_t ret = 0;
99afc88b
OJ		 4148 gdb_byte buf[insn_size];
4149 insn_decode_record aarch64_record;
4150
4151 memset (&buf[0], 0, insn_size);
4152 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4153 target_read_memory (insn_addr, &buf[0], insn_size);
4154 aarch64_record.aarch64_insn
4155 = (uint32_t) extract_unsigned_integer (&buf[0],
4156 insn_size,
4157 gdbarch_byte_order (gdbarch));
4158 aarch64_record.regcache = regcache;
4159 aarch64_record.this_addr = insn_addr;
4160 aarch64_record.gdbarch = gdbarch;
4161
4162 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4163 if (ret == AARCH64_RECORD_UNSUPPORTED)
4164 {
4165 printf_unfiltered (_("Process record does not support instruction "
4166 "0x%0x at address %s.\n"),
4167 aarch64_record.aarch64_insn,
4168 paddress (gdbarch, insn_addr));
4169 ret = -1;
4170 }
4171
4172 if (0 == ret)
4173 {
4174 /* Record registers. */
4175 record_full_arch_list_add_reg (aarch64_record.regcache,
4176 AARCH64_PC_REGNUM);
4177 /* Always record register CPSR. */
4178 record_full_arch_list_add_reg (aarch64_record.regcache,
4179 AARCH64_CPSR_REGNUM);
4180 if (aarch64_record.aarch64_regs)
4181 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4182 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4183 aarch64_record.aarch64_regs[rec_no]))
4184 ret = -1;
4185
4186 /* Record memories. */
4187 if (aarch64_record.aarch64_mems)
4188 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4189 if (record_full_arch_list_add_mem
4190 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4191 aarch64_record.aarch64_mems[rec_no].len))
4192 ret = -1;
4193
4194 if (record_full_arch_list_add_end ())
4195 ret = -1;
4196 }
4197
4198 deallocate_reg_mem (&aarch64_record);
4199 return ret;
4200}
GDB Binutils - Deliverables
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