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07b287a0 MS |
1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
3666a048 | 3 | Copyright (C) 2009-2021 Free Software Foundation, Inc. |
07b287a0 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | #ifndef AARCH64_TDEP_H | |
23 | #define AARCH64_TDEP_H | |
24 | ||
cc628f3d | 25 | #include "arch/aarch64.h" |
c7acb87b | 26 | #include "displaced-stepping.h" |
fdb61c6c | 27 | #include "infrun.h" |
cc628f3d | 28 | |
07b287a0 MS |
29 | /* Forward declarations. */ |
30 | struct gdbarch; | |
31 | struct regset; | |
32 | ||
33 | /* AArch64 Dwarf register numbering. */ | |
34 | #define AARCH64_DWARF_X0 0 | |
35 | #define AARCH64_DWARF_SP 31 | |
34dcc7cf AH |
36 | #define AARCH64_DWARF_PAUTH_RA_STATE 34 |
37 | #define AARCH64_DWARF_PAUTH_DMASK 35 | |
38 | #define AARCH64_DWARF_PAUTH_CMASK 36 | |
07b287a0 | 39 | #define AARCH64_DWARF_V0 64 |
65d4cada AH |
40 | #define AARCH64_DWARF_SVE_VG 46 |
41 | #define AARCH64_DWARF_SVE_FFR 47 | |
42 | #define AARCH64_DWARF_SVE_P0 48 | |
43 | #define AARCH64_DWARF_SVE_Z0 96 | |
07b287a0 | 44 | |
07b287a0 MS |
45 | /* Size of integer registers. */ |
46 | #define X_REGISTER_SIZE 8 | |
47 | #define B_REGISTER_SIZE 1 | |
48 | #define H_REGISTER_SIZE 2 | |
49 | #define S_REGISTER_SIZE 4 | |
50 | #define D_REGISTER_SIZE 8 | |
07b287a0 MS |
51 | #define Q_REGISTER_SIZE 16 |
52 | ||
53 | /* Total number of general (X) registers. */ | |
54 | #define AARCH64_X_REGISTER_COUNT 32 | |
187f5d00 YQ |
55 | /* Total number of D registers. */ |
56 | #define AARCH64_D_REGISTER_COUNT 32 | |
07b287a0 | 57 | |
b6542f81 YQ |
58 | /* The maximum number of modified instructions generated for one |
59 | single-stepped instruction. */ | |
e935475c | 60 | #define AARCH64_DISPLACED_MODIFIED_INSNS 1 |
b6542f81 | 61 | |
07b287a0 MS |
62 | /* Target-dependent structure in gdbarch. */ |
63 | struct gdbarch_tdep | |
64 | { | |
65 | /* Lowest address at which instructions will appear. */ | |
66 | CORE_ADDR lowest_pc; | |
67 | ||
68 | /* Offset to PC value in jump buffer. If this is negative, longjmp | |
69 | support will be disabled. */ | |
70 | int jb_pc; | |
71 | ||
72 | /* And the size of each entry in the buf. */ | |
73 | size_t jb_elt_size; | |
74 | ||
75 | /* Types for AdvSISD registers. */ | |
76 | struct type *vnq_type; | |
77 | struct type *vnd_type; | |
78 | struct type *vns_type; | |
79 | struct type *vnh_type; | |
80 | struct type *vnb_type; | |
63bad7b6 | 81 | struct type *vnv_type; |
99afc88b OJ |
82 | |
83 | /* syscall record. */ | |
84 | int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number); | |
ba2d2bb2 AH |
85 | |
86 | /* The VQ value for SVE targets, or zero if SVE is not supported. */ | |
1332a140 | 87 | uint64_t vq; |
ba2d2bb2 AH |
88 | |
89 | /* Returns true if the target supports SVE. */ | |
90 | bool has_sve () const | |
91 | { | |
92 | return vq != 0; | |
93 | } | |
76bed0fd AH |
94 | |
95 | int pauth_reg_base; | |
34dcc7cf | 96 | int pauth_ra_state_regnum; |
76bed0fd AH |
97 | |
98 | /* Returns true if the target supports pauth. */ | |
99 | bool has_pauth () const | |
100 | { | |
101 | return pauth_reg_base != -1; | |
102 | } | |
07b287a0 MS |
103 | }; |
104 | ||
6dc0ebde | 105 | const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p); |
9f2e0721 | 106 | |
99afc88b | 107 | extern int aarch64_process_record (struct gdbarch *gdbarch, |
dda83cd7 | 108 | struct regcache *regcache, CORE_ADDR addr); |
99afc88b | 109 | |
1152d984 | 110 | displaced_step_copy_insn_closure_up |
b6542f81 YQ |
111 | aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, |
112 | CORE_ADDR from, CORE_ADDR to, | |
113 | struct regcache *regs); | |
114 | ||
115 | void aarch64_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 116 | displaced_step_copy_insn_closure *dsc, |
b6542f81 YQ |
117 | CORE_ADDR from, CORE_ADDR to, |
118 | struct regcache *regs); | |
119 | ||
40a53766 | 120 | bool aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch); |
b6542f81 | 121 | |
07b287a0 | 122 | #endif /* aarch64-tdep.h */ |