[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.h

/* Common target dependent code for GDB on AArch64 systems.

   Copyright (C) 2009-2017 Free Software Foundation, Inc.
   Contributed by ARM Ltd.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */


#ifndef AARCH64_TDEP_H
#define AARCH64_TDEP_H

/* Forward declarations.  */
struct gdbarch;
struct regset;

/* AArch64 Dwarf register numbering.  */
#define AARCH64_DWARF_X0   0
#define AARCH64_DWARF_SP  31
#define AARCH64_DWARF_V0  64

/* Register numbers of various important registers.  */
enum aarch64_regnum
{
  AARCH64_X0_REGNUM,		/* First integer register */

  /* Frame register in AArch64 code, if used.  */
  AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29,
  AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30,	/* Return address */
  AARCH64_SP_REGNUM,		/* Stack pointer */
  AARCH64_PC_REGNUM,		/* Program counter */
  AARCH64_CPSR_REGNUM,		/* Contains status register */
  AARCH64_V0_REGNUM,		/* First floating point / vector register */

  /* Last floating point / vector register */
  AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31,
  AARCH64_FPSR_REGNUM,		/* Floating point status register */
  AARCH64_FPCR_REGNUM,		/* Floating point control register */

  /* Other useful registers.  */

  /* Last integer-like argument */
  AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7,
  AARCH64_STRUCT_RETURN_REGNUM = AARCH64_X0_REGNUM + 8,
  AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7
};

/* Size of integer registers.  */
#define X_REGISTER_SIZE  8
#define B_REGISTER_SIZE  1
#define H_REGISTER_SIZE  2
#define S_REGISTER_SIZE  4
#define D_REGISTER_SIZE  8
#define V_REGISTER_SIZE 16
#define Q_REGISTER_SIZE 16

/* Total number of general (X) registers.  */
#define AARCH64_X_REGISTER_COUNT 32
/* Total number of D registers.  */
#define AARCH64_D_REGISTER_COUNT 32

/* The maximum number of modified instructions generated for one
   single-stepped instruction.  */
#define DISPLACED_MODIFIED_INSNS 1

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* Lowest address at which instructions will appear.  */
  CORE_ADDR lowest_pc;

  /* Offset to PC value in jump buffer.  If this is negative, longjmp
     support will be disabled.  */
  int jb_pc;

  /* And the size of each entry in the buf.  */
  size_t jb_elt_size;

  /* Types for AdvSISD registers.  */
  struct type *vnq_type;
  struct type *vnd_type;
  struct type *vns_type;
  struct type *vnh_type;
  struct type *vnb_type;

  /* syscall record.  */
  int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};

extern struct target_desc *tdesc_aarch64;

extern int aarch64_process_record (struct gdbarch *gdbarch,
                               struct regcache *regcache, CORE_ADDR addr);

struct displaced_step_closure *
  aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
				    CORE_ADDR from, CORE_ADDR to,
				    struct regcache *regs);

void aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
				   struct displaced_step_closure *dsc,
				   CORE_ADDR from, CORE_ADDR to,
				   struct regcache *regs);

int aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
					  struct displaced_step_closure *closure);

#endif /* aarch64-tdep.h */
Commit	Line	Data
07b287a0 MS	1	/* Common target dependent code for GDB on AArch64 systems.
07b287a0 MS	2
61baf725	3	Copyright (C) 2009-2017 Free Software Foundation, Inc.
07b287a0 MS	4	Contributed by ARM Ltd.
	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
	21
	22	#ifndef AARCH64_TDEP_H
	23	#define AARCH64_TDEP_H
	24
	25	/* Forward declarations. */
	26	struct gdbarch;
	27	struct regset;
	28
	29	/* AArch64 Dwarf register numbering. */
	30	#define AARCH64_DWARF_X0 0
	31	#define AARCH64_DWARF_SP 31
	32	#define AARCH64_DWARF_V0 64
	33
	34	/* Register numbers of various important registers. */
	35	enum aarch64_regnum
	36	{
	37	AARCH64_X0_REGNUM, /* First integer register */
	38
	39	/* Frame register in AArch64 code, if used. */
	40	AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29,
	41	AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address */
	42	AARCH64_SP_REGNUM, /* Stack pointer */
	43	AARCH64_PC_REGNUM, /* Program counter */
	44	AARCH64_CPSR_REGNUM, /* Contains status register */
	45	AARCH64_V0_REGNUM, /* First floating point / vector register */
	46
	47	/* Last floating point / vector register */
	48	AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31,
	49	AARCH64_FPSR_REGNUM, /* Floating point status register */
	50	AARCH64_FPCR_REGNUM, /* Floating point control register */
	51
	52	/* Other useful registers. */
	53
	54	/* Last integer-like argument */
	55	AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7,
	56	AARCH64_STRUCT_RETURN_REGNUM = AARCH64_X0_REGNUM + 8,
	57	AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7
	58	};
	59
	60	/* Size of integer registers. */
	61	#define X_REGISTER_SIZE 8
	62	#define B_REGISTER_SIZE 1
	63	#define H_REGISTER_SIZE 2
	64	#define S_REGISTER_SIZE 4
	65	#define D_REGISTER_SIZE 8
	66	#define V_REGISTER_SIZE 16
	67	#define Q_REGISTER_SIZE 16
68
69	/* Total number of general (X) registers. */
70	#define AARCH64_X_REGISTER_COUNT 32
187f5d00 YQ	71	/* Total number of D registers. */
187f5d00 YQ	72	#define AARCH64_D_REGISTER_COUNT 32
07b287a0	73
b6542f81 YQ	74	/* The maximum number of modified instructions generated for one
	75	single-stepped instruction. */
	76	#define DISPLACED_MODIFIED_INSNS 1
	77
07b287a0 MS	78	/* Target-dependent structure in gdbarch. */
	79	struct gdbarch_tdep
	80	{
	81	/* Lowest address at which instructions will appear. */
	82	CORE_ADDR lowest_pc;
	83
	84	/* Offset to PC value in jump buffer. If this is negative, longjmp
	85	support will be disabled. */
	86	int jb_pc;
	87
	88	/* And the size of each entry in the buf. */
	89	size_t jb_elt_size;
	90
	91	/* Types for AdvSISD registers. */
	92	struct type *vnq_type;
	93	struct type *vnd_type;
	94	struct type *vns_type;
	95	struct type *vnh_type;
	96	struct type *vnb_type;
99afc88b OJ	97
	98	/* syscall record. */
	99	int (aarch64_syscall_record) (struct regcache regcache, unsigned long svc_number);
07b287a0 MS	100	};
07b287a0 MS	101
9f2e0721 MO	102	extern struct target_desc *tdesc_aarch64;
9f2e0721 MO	103
99afc88b OJ	104	extern int aarch64_process_record (struct gdbarch *gdbarch,
	105	struct regcache *regcache, CORE_ADDR addr);
	106
b6542f81 YQ	107	struct displaced_step_closure *
	108	aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
	109	CORE_ADDR from, CORE_ADDR to,
	110	struct regcache *regs);
	111
	112	void aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
	113	struct displaced_step_closure *dsc,
	114	CORE_ADDR from, CORE_ADDR to,
	115	struct regcache *regs);
	116
	117	int aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
	118	struct displaced_step_closure *closure);
	119
07b287a0	120	#endif /* aarch64-tdep.h */