Commit | Line | Data |
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a4b6fc86 | 1 | /* Native-dependent code for GNU/Linux x86-64. |
0a65a603 | 2 | |
b811d2c2 | 3 | Copyright (C) 2001-2020 Free Software Foundation, Inc. |
53e95fcf JS |
4 | Contributed by Jiri Smid, SuSE Labs. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf JS |
20 | |
21 | #include "defs.h" | |
4de283e4 TT |
22 | #include "inferior.h" |
23 | #include "regcache.h" | |
24 | #include "elf/common.h" | |
25 | #include <sys/uio.h> | |
26 | #include "nat/gdb_ptrace.h" | |
c43af07c | 27 | #include <asm/prctl.h> |
33a0a2ac | 28 | #include <sys/reg.h> |
4de283e4 TT |
29 | #include "gregset.h" |
30 | #include "gdb_proc_service.h" | |
c4f35dd8 | 31 | |
3116063b | 32 | #include "amd64-nat.h" |
9c1488cb | 33 | #include "amd64-tdep.h" |
4de283e4 | 34 | #include "amd64-linux-tdep.h" |
d55e5aa6 | 35 | #include "i386-linux-tdep.h" |
268a13a5 | 36 | #include "gdbsupport/x86-xstate.h" |
4de283e4 | 37 | |
d55e5aa6 | 38 | #include "x86-linux-nat.h" |
4de283e4 TT |
39 | #include "nat/linux-ptrace.h" |
40 | #include "nat/amd64-linux-siginfo.h" | |
60fac5b8 | 41 | |
2735833d WT |
42 | /* This definition comes from prctl.h. Kernels older than 2.5.64 |
43 | do not have it. */ | |
44 | #ifndef PTRACE_ARCH_PRCTL | |
45 | #define PTRACE_ARCH_PRCTL 30 | |
46 | #endif | |
47 | ||
f6ac5f3d PA |
48 | struct amd64_linux_nat_target final : public x86_linux_nat_target |
49 | { | |
50 | /* Add our register access methods. */ | |
51 | void fetch_registers (struct regcache *, int) override; | |
52 | void store_registers (struct regcache *, int) override; | |
135340af PA |
53 | |
54 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
55 | override; | |
f6ac5f3d PA |
56 | }; |
57 | ||
58 | static amd64_linux_nat_target the_amd64_linux_nat_target; | |
59 | ||
60fac5b8 MK |
60 | /* Mapping between the general-purpose registers in GNU/Linux x86-64 |
61 | `struct user' format and GDB's register cache layout for GNU/Linux | |
62 | i386. | |
63 | ||
64 | Note that most GNU/Linux x86-64 registers are 64-bit, while the | |
65 | GNU/Linux i386 registers are all 32-bit, but since we're | |
66 | little-endian we get away with that. */ | |
67 | ||
68 | /* From <sys/reg.h> on GNU/Linux i386. */ | |
430eaf2e | 69 | static int amd64_linux_gregset32_reg_offset[] = |
60fac5b8 | 70 | { |
f5859b4d MK |
71 | RAX * 8, RCX * 8, /* %eax, %ecx */ |
72 | RDX * 8, RBX * 8, /* %edx, %ebx */ | |
73 | RSP * 8, RBP * 8, /* %esp, %ebp */ | |
74 | RSI * 8, RDI * 8, /* %esi, %edi */ | |
75 | RIP * 8, EFLAGS * 8, /* %eip, %eflags */ | |
76 | CS * 8, SS * 8, /* %cs, %ss */ | |
77 | DS * 8, ES * 8, /* %ds, %es */ | |
78 | FS * 8, GS * 8, /* %fs, %gs */ | |
60fac5b8 MK |
79 | -1, -1, -1, -1, -1, -1, -1, -1, |
80 | -1, -1, -1, -1, -1, -1, -1, -1, | |
81 | -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
a055a187 | 82 | -1, -1, -1, -1, -1, -1, -1, -1, |
01f9f808 MS |
83 | -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */ |
84 | -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */ | |
85 | -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */ | |
86 | -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm7 (AVX512) */ | |
51547df6 | 87 | -1, /* PKEYS register PKRU */ |
01f9f808 | 88 | ORIG_RAX * 8 /* "orig_eax" */ |
60fac5b8 | 89 | }; |
53e95fcf JS |
90 | \f |
91 | ||
92 | /* Transfering the general-purpose registers between GDB, inferiors | |
93 | and core files. */ | |
94 | ||
3f52fdbc KB |
95 | /* See amd64_collect_native_gregset. This linux specific version handles |
96 | issues with negative EAX values not being restored correctly upon syscall | |
97 | return when debugging 32-bit targets. It has no effect on 64-bit | |
98 | targets. */ | |
99 | ||
100 | static void | |
101 | amd64_linux_collect_native_gregset (const struct regcache *regcache, | |
dda83cd7 | 102 | void *gregs, int regnum) |
3f52fdbc KB |
103 | { |
104 | amd64_collect_native_gregset (regcache, gregs, regnum); | |
105 | ||
106 | struct gdbarch *gdbarch = regcache->arch (); | |
107 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
108 | { | |
109 | /* Sign extend EAX value to avoid potential syscall restart | |
110 | problems. | |
111 | ||
112 | On Linux, when a syscall is interrupted by a signal, the | |
113 | (kernel function implementing the) syscall may return | |
114 | -ERESTARTSYS when a signal occurs. Doing so indicates that | |
115 | the syscall is restartable. Then, depending on settings | |
116 | associated with the signal handler, and after the signal | |
117 | handler is called, the kernel can then either return -EINTR | |
118 | or it can cause the syscall to be restarted. We are | |
119 | concerned with the latter case here. | |
120 | ||
121 | On (32-bit) i386, the status (-ERESTARTSYS) is placed in the | |
122 | EAX register. When debugging a 32-bit process from a 64-bit | |
123 | (amd64) GDB, the debugger fetches 64-bit registers even | |
124 | though the process being debugged is only 32-bit. The | |
125 | register cache is only 32 bits wide though; GDB discards the | |
126 | high 32 bits when placing 64-bit values in the 32-bit | |
127 | regcache. Normally, this is not a problem since the 32-bit | |
128 | process should only care about the lower 32-bit portions of | |
129 | these registers. That said, it can happen that the 64-bit | |
130 | value being restored will be different from the 64-bit value | |
131 | that was originally retrieved from the kernel. The one place | |
132 | (that we know of) where it does matter is in the kernel's | |
133 | syscall restart code. The kernel's code for restarting a | |
134 | syscall after a signal expects to see a negative value | |
135 | (specifically -ERESTARTSYS) in the 64-bit RAX register in | |
136 | order to correctly cause a syscall to be restarted. | |
137 | ||
138 | The call to amd64_collect_native_gregset, above, is setting | |
139 | the high 32 bits of RAX (and other registers too) to 0. For | |
140 | syscall restart, we need to sign extend EAX so that RAX will | |
141 | appear as a negative value when EAX is set to -ERESTARTSYS. | |
142 | This in turn will cause the signal handling code in the | |
143 | kernel to recognize -ERESTARTSYS which will in turn cause the | |
144 | syscall to be restarted. | |
145 | ||
146 | The test case gdb.base/interrupt.exp tests for this problem. | |
147 | Without this sign extension code in place, it'll show | |
148 | a number of failures when testing against unix/-m32. */ | |
149 | ||
150 | if (regnum == -1 || regnum == I386_EAX_REGNUM) | |
151 | { | |
152 | void *ptr = ((gdb_byte *) gregs | |
153 | + amd64_linux_gregset32_reg_offset[I386_EAX_REGNUM]); | |
154 | ||
155 | *(int64_t *) ptr = *(int32_t *) ptr; | |
156 | } | |
157 | } | |
158 | } | |
159 | ||
60fac5b8 | 160 | /* Fill GDB's register cache with the general-purpose register values |
53e95fcf JS |
161 | in *GREGSETP. */ |
162 | ||
163 | void | |
7f7fe91e | 164 | supply_gregset (struct regcache *regcache, const elf_gregset_t *gregsetp) |
53e95fcf | 165 | { |
7f7fe91e | 166 | amd64_supply_native_gregset (regcache, gregsetp, -1); |
53e95fcf JS |
167 | } |
168 | ||
60fac5b8 MK |
169 | /* Fill register REGNUM (if it is a general-purpose register) in |
170 | *GREGSETP with the value in GDB's register cache. If REGNUM is -1, | |
53e95fcf JS |
171 | do this for all registers. */ |
172 | ||
173 | void | |
7f7fe91e UW |
174 | fill_gregset (const struct regcache *regcache, |
175 | elf_gregset_t *gregsetp, int regnum) | |
53e95fcf | 176 | { |
3f52fdbc | 177 | amd64_linux_collect_native_gregset (regcache, gregsetp, regnum); |
53e95fcf JS |
178 | } |
179 | ||
53e95fcf JS |
180 | /* Transfering floating-point registers between GDB, inferiors and cores. */ |
181 | ||
60fac5b8 | 182 | /* Fill GDB's register cache with the floating-point and SSE register |
c4f35dd8 | 183 | values in *FPREGSETP. */ |
53e95fcf JS |
184 | |
185 | void | |
7f7fe91e | 186 | supply_fpregset (struct regcache *regcache, const elf_fpregset_t *fpregsetp) |
53e95fcf | 187 | { |
7f7fe91e | 188 | amd64_supply_fxsave (regcache, -1, fpregsetp); |
53e95fcf JS |
189 | } |
190 | ||
8dda9770 | 191 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
60fac5b8 | 192 | *FPREGSETP with the value in GDB's register cache. If REGNUM is |
c4f35dd8 | 193 | -1, do this for all registers. */ |
53e95fcf JS |
194 | |
195 | void | |
7f7fe91e UW |
196 | fill_fpregset (const struct regcache *regcache, |
197 | elf_fpregset_t *fpregsetp, int regnum) | |
53e95fcf | 198 | { |
7f7fe91e | 199 | amd64_collect_fxsave (regcache, regnum, fpregsetp); |
53e95fcf | 200 | } |
53e95fcf JS |
201 | \f |
202 | ||
203 | /* Transferring arbitrary registers between GDB and inferior. */ | |
204 | ||
60fac5b8 | 205 | /* Fetch register REGNUM from the child process. If REGNUM is -1, do |
53e95fcf JS |
206 | this for all registers (including the floating point and SSE |
207 | registers). */ | |
208 | ||
f6ac5f3d PA |
209 | void |
210 | amd64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) | |
53e95fcf | 211 | { |
ac7936df | 212 | struct gdbarch *gdbarch = regcache->arch (); |
53e95fcf JS |
213 | int tid; |
214 | ||
a4b6fc86 | 215 | /* GNU/Linux LWP ID's are process ID's. */ |
e38504b3 | 216 | tid = regcache->ptid ().lwp (); |
c4f35dd8 | 217 | if (tid == 0) |
e99b03dc | 218 | tid = regcache->ptid ().pid (); /* Not a threaded program. */ |
53e95fcf | 219 | |
f8028488 | 220 | if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 221 | { |
99679982 MK |
222 | elf_gregset_t regs; |
223 | ||
224 | if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 225 | perror_with_name (_("Couldn't get registers")); |
99679982 | 226 | |
56be3814 | 227 | amd64_supply_native_gregset (regcache, ®s, -1); |
60fac5b8 MK |
228 | if (regnum != -1) |
229 | return; | |
53e95fcf JS |
230 | } |
231 | ||
f8028488 | 232 | if (regnum == -1 || !amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 233 | { |
99679982 | 234 | elf_fpregset_t fpregs; |
53e95fcf | 235 | |
0bdb2f78 | 236 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
a055a187 | 237 | { |
df7e5265 | 238 | char xstateregs[X86_XSTATE_MAX_SIZE]; |
a055a187 L |
239 | struct iovec iov; |
240 | ||
3d435220 TV |
241 | /* Pre-4.14 kernels have a bug (fixed by commit 0852b374173b |
242 | "x86/fpu: Add FPU state copying quirk to handle XRSTOR failure on | |
243 | Intel Skylake CPUs") that sometimes causes the mxcsr location in | |
244 | xstateregs not to be copied by PTRACE_GETREGSET. Make sure that | |
245 | the location is at least initialized with a defined value. */ | |
246 | memset (xstateregs, 0, sizeof (xstateregs)); | |
a055a187 L |
247 | iov.iov_base = xstateregs; |
248 | iov.iov_len = sizeof (xstateregs); | |
249 | if (ptrace (PTRACE_GETREGSET, tid, | |
250 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
251 | perror_with_name (_("Couldn't get extended state status")); | |
99679982 | 252 | |
a055a187 L |
253 | amd64_supply_xsave (regcache, -1, xstateregs); |
254 | } | |
255 | else | |
256 | { | |
257 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (long) &fpregs) < 0) | |
258 | perror_with_name (_("Couldn't get floating point status")); | |
259 | ||
260 | amd64_supply_fxsave (regcache, -1, &fpregs); | |
261 | } | |
99679982 | 262 | } |
53e95fcf JS |
263 | } |
264 | ||
60fac5b8 MK |
265 | /* Store register REGNUM back into the child process. If REGNUM is |
266 | -1, do this for all registers (including the floating-point and SSE | |
53e95fcf | 267 | registers). */ |
c4f35dd8 | 268 | |
f6ac5f3d PA |
269 | void |
270 | amd64_linux_nat_target::store_registers (struct regcache *regcache, int regnum) | |
53e95fcf | 271 | { |
ac7936df | 272 | struct gdbarch *gdbarch = regcache->arch (); |
53e95fcf JS |
273 | int tid; |
274 | ||
a4b6fc86 | 275 | /* GNU/Linux LWP ID's are process ID's. */ |
e38504b3 | 276 | tid = regcache->ptid ().lwp (); |
c4f35dd8 | 277 | if (tid == 0) |
e99b03dc | 278 | tid = regcache->ptid ().pid (); /* Not a threaded program. */ |
53e95fcf | 279 | |
f8028488 | 280 | if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 281 | { |
99679982 MK |
282 | elf_gregset_t regs; |
283 | ||
284 | if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 285 | perror_with_name (_("Couldn't get registers")); |
99679982 | 286 | |
3f52fdbc | 287 | amd64_linux_collect_native_gregset (regcache, ®s, regnum); |
99679982 MK |
288 | |
289 | if (ptrace (PTRACE_SETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 290 | perror_with_name (_("Couldn't write registers")); |
99679982 | 291 | |
60fac5b8 MK |
292 | if (regnum != -1) |
293 | return; | |
53e95fcf JS |
294 | } |
295 | ||
f8028488 | 296 | if (regnum == -1 || !amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 297 | { |
99679982 MK |
298 | elf_fpregset_t fpregs; |
299 | ||
0bdb2f78 | 300 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
a055a187 | 301 | { |
df7e5265 | 302 | char xstateregs[X86_XSTATE_MAX_SIZE]; |
a055a187 L |
303 | struct iovec iov; |
304 | ||
305 | iov.iov_base = xstateregs; | |
306 | iov.iov_len = sizeof (xstateregs); | |
307 | if (ptrace (PTRACE_GETREGSET, tid, | |
308 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
309 | perror_with_name (_("Couldn't get extended state status")); | |
99679982 | 310 | |
a055a187 L |
311 | amd64_collect_xsave (regcache, regnum, xstateregs, 0); |
312 | ||
313 | if (ptrace (PTRACE_SETREGSET, tid, | |
314 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
315 | perror_with_name (_("Couldn't write extended state status")); | |
316 | } | |
317 | else | |
318 | { | |
319 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (long) &fpregs) < 0) | |
320 | perror_with_name (_("Couldn't get floating point status")); | |
99679982 | 321 | |
a055a187 | 322 | amd64_collect_fxsave (regcache, regnum, &fpregs); |
99679982 | 323 | |
a055a187 L |
324 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (long) &fpregs) < 0) |
325 | perror_with_name (_("Couldn't write floating point status")); | |
326 | } | |
53e95fcf | 327 | } |
53e95fcf JS |
328 | } |
329 | \f | |
1aa7e42c | 330 | |
50d71875 AC |
331 | /* This function is called by libthread_db as part of its handling of |
332 | a request for a thread's local storage address. */ | |
333 | ||
5bca7895 | 334 | ps_err_e |
754653a7 | 335 | ps_get_thread_area (struct ps_prochandle *ph, |
dda83cd7 | 336 | lwpid_t lwpid, int idx, void **base) |
c43af07c | 337 | { |
5b6d1e4f | 338 | if (gdbarch_bfd_arch_info (ph->thread->inf->gdbarch)->bits_per_word == 32) |
50d71875 | 339 | { |
8c420b8d GB |
340 | unsigned int base_addr; |
341 | ps_err_e result; | |
342 | ||
343 | result = x86_linux_get_thread_area (lwpid, (void *) (long) idx, | |
344 | &base_addr); | |
345 | if (result == PS_OK) | |
346 | { | |
347 | /* Extend the value to 64 bits. Here it's assumed that | |
348 | a "long" and a "void *" are the same. */ | |
349 | (*base) = (void *) (long) base_addr; | |
350 | } | |
351 | return result; | |
50d71875 AC |
352 | } |
353 | else | |
354 | { | |
2735833d | 355 | |
50d71875 AC |
356 | /* FIXME: ezannoni-2003-07-09 see comment above about include |
357 | file order. We could be getting bogus values for these two. */ | |
358 | gdb_assert (FS < ELF_NGREG); | |
359 | gdb_assert (GS < ELF_NGREG); | |
360 | switch (idx) | |
361 | { | |
362 | case FS: | |
6fea9e18 | 363 | { |
6fea9e18 L |
364 | unsigned long fs; |
365 | errno = 0; | |
366 | fs = ptrace (PTRACE_PEEKUSER, lwpid, | |
367 | offsetof (struct user_regs_struct, fs_base), 0); | |
368 | if (errno == 0) | |
369 | { | |
370 | *base = (void *) fs; | |
371 | return PS_OK; | |
372 | } | |
373 | } | |
1eb39914 | 374 | |
50d71875 | 375 | break; |
1eb39914 | 376 | |
50d71875 | 377 | case GS: |
6fea9e18 L |
378 | { |
379 | unsigned long gs; | |
380 | errno = 0; | |
381 | gs = ptrace (PTRACE_PEEKUSER, lwpid, | |
382 | offsetof (struct user_regs_struct, gs_base), 0); | |
383 | if (errno == 0) | |
384 | { | |
385 | *base = (void *) gs; | |
386 | return PS_OK; | |
387 | } | |
388 | } | |
50d71875 | 389 | break; |
1eb39914 | 390 | |
50d71875 AC |
391 | default: /* Should not happen. */ |
392 | return PS_BADADDR; | |
393 | } | |
c43af07c | 394 | } |
b6d42148 | 395 | return PS_ERR; /* ptrace failed. */ |
c43af07c | 396 | } |
5bca7895 | 397 | \f |
c43af07c | 398 | |
9cf12d57 | 399 | /* Convert a ptrace/host siginfo object, into/from the siginfo in the |
5b009018 PA |
400 | layout of the inferiors' architecture. Returns true if any |
401 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
9cf12d57 | 402 | from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to |
5b009018 PA |
403 | INF. */ |
404 | ||
135340af PA |
405 | bool |
406 | amd64_linux_nat_target::low_siginfo_fixup (siginfo_t *ptrace, | |
407 | gdb_byte *inf, | |
408 | int direction) | |
5b009018 | 409 | { |
ba224c70 L |
410 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); |
411 | ||
5b009018 PA |
412 | /* Is the inferior 32-bit? If so, then do fixup the siginfo |
413 | object. */ | |
ba224c70 | 414 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
135340af PA |
415 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
416 | FIXUP_32); | |
ba224c70 L |
417 | /* No fixup for native x32 GDB. */ |
418 | else if (gdbarch_addr_bit (gdbarch) == 32 && sizeof (void *) == 8) | |
135340af PA |
419 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
420 | FIXUP_X32); | |
5b009018 | 421 | else |
135340af | 422 | return false; |
5b009018 | 423 | } |
c1e246a0 | 424 | |
6c265988 | 425 | void _initialize_amd64_linux_nat (); |
c1e246a0 | 426 | void |
6c265988 | 427 | _initialize_amd64_linux_nat () |
c1e246a0 | 428 | { |
c1e246a0 GB |
429 | amd64_native_gregset32_reg_offset = amd64_linux_gregset32_reg_offset; |
430 | amd64_native_gregset32_num_regs = I386_LINUX_NUM_REGS; | |
431 | amd64_native_gregset64_reg_offset = amd64_linux_gregset_reg_offset; | |
432 | amd64_native_gregset64_num_regs = AMD64_LINUX_NUM_REGS; | |
433 | ||
434 | gdb_assert (ARRAY_SIZE (amd64_linux_gregset32_reg_offset) | |
435 | == amd64_native_gregset32_num_regs); | |
436 | ||
f6ac5f3d | 437 | linux_target = &the_amd64_linux_nat_target; |
c1e246a0 GB |
438 | |
439 | /* Add the target. */ | |
d9f719f1 | 440 | add_inf_child_target (linux_target); |
c1e246a0 | 441 | } |