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a4b6fc86 | 1 | /* Native-dependent code for GNU/Linux x86-64. |
0a65a603 | 2 | |
42a4f53d | 3 | Copyright (C) 2001-2019 Free Software Foundation, Inc. |
53e95fcf JS |
4 | Contributed by Jiri Smid, SuSE Labs. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf JS |
20 | |
21 | #include "defs.h" | |
d55e5aa6 TT |
22 | |
23 | /* Standard C includes. */ | |
c43af07c | 24 | #include <asm/prctl.h> |
33a0a2ac | 25 | #include <sys/reg.h> |
d55e5aa6 | 26 | #include <sys/uio.h> |
c4f35dd8 | 27 | |
d55e5aa6 TT |
28 | /* Local non-gdb includes. */ |
29 | #include "amd64-linux-tdep.h" | |
3116063b | 30 | #include "amd64-nat.h" |
9c1488cb | 31 | #include "amd64-tdep.h" |
0747795c | 32 | #include "common/x86-xstate.h" |
d55e5aa6 TT |
33 | #include "elf/common.h" |
34 | #include "gdb_proc_service.h" | |
35 | #include "gregset.h" | |
36 | #include "i386-linux-tdep.h" | |
37 | #include "inferior.h" | |
93813b37 | 38 | #include "nat/amd64-linux-siginfo.h" |
d55e5aa6 TT |
39 | #include "nat/gdb_ptrace.h" |
40 | #include "nat/linux-ptrace.h" | |
41 | #include "regcache.h" | |
42 | #include "x86-linux-nat.h" | |
60fac5b8 | 43 | |
2735833d WT |
44 | /* This definition comes from prctl.h. Kernels older than 2.5.64 |
45 | do not have it. */ | |
46 | #ifndef PTRACE_ARCH_PRCTL | |
47 | #define PTRACE_ARCH_PRCTL 30 | |
48 | #endif | |
49 | ||
f6ac5f3d PA |
50 | struct amd64_linux_nat_target final : public x86_linux_nat_target |
51 | { | |
52 | /* Add our register access methods. */ | |
53 | void fetch_registers (struct regcache *, int) override; | |
54 | void store_registers (struct regcache *, int) override; | |
135340af PA |
55 | |
56 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
57 | override; | |
f6ac5f3d PA |
58 | }; |
59 | ||
60 | static amd64_linux_nat_target the_amd64_linux_nat_target; | |
61 | ||
60fac5b8 MK |
62 | /* Mapping between the general-purpose registers in GNU/Linux x86-64 |
63 | `struct user' format and GDB's register cache layout for GNU/Linux | |
64 | i386. | |
65 | ||
66 | Note that most GNU/Linux x86-64 registers are 64-bit, while the | |
67 | GNU/Linux i386 registers are all 32-bit, but since we're | |
68 | little-endian we get away with that. */ | |
69 | ||
70 | /* From <sys/reg.h> on GNU/Linux i386. */ | |
430eaf2e | 71 | static int amd64_linux_gregset32_reg_offset[] = |
60fac5b8 | 72 | { |
f5859b4d MK |
73 | RAX * 8, RCX * 8, /* %eax, %ecx */ |
74 | RDX * 8, RBX * 8, /* %edx, %ebx */ | |
75 | RSP * 8, RBP * 8, /* %esp, %ebp */ | |
76 | RSI * 8, RDI * 8, /* %esi, %edi */ | |
77 | RIP * 8, EFLAGS * 8, /* %eip, %eflags */ | |
78 | CS * 8, SS * 8, /* %cs, %ss */ | |
79 | DS * 8, ES * 8, /* %ds, %es */ | |
80 | FS * 8, GS * 8, /* %fs, %gs */ | |
60fac5b8 MK |
81 | -1, -1, -1, -1, -1, -1, -1, -1, |
82 | -1, -1, -1, -1, -1, -1, -1, -1, | |
83 | -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
a055a187 | 84 | -1, -1, -1, -1, -1, -1, -1, -1, |
01f9f808 MS |
85 | -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */ |
86 | -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */ | |
87 | -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */ | |
88 | -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm7 (AVX512) */ | |
51547df6 | 89 | -1, /* PKEYS register PKRU */ |
01f9f808 | 90 | ORIG_RAX * 8 /* "orig_eax" */ |
60fac5b8 | 91 | }; |
53e95fcf JS |
92 | \f |
93 | ||
94 | /* Transfering the general-purpose registers between GDB, inferiors | |
95 | and core files. */ | |
96 | ||
60fac5b8 | 97 | /* Fill GDB's register cache with the general-purpose register values |
53e95fcf JS |
98 | in *GREGSETP. */ |
99 | ||
100 | void | |
7f7fe91e | 101 | supply_gregset (struct regcache *regcache, const elf_gregset_t *gregsetp) |
53e95fcf | 102 | { |
7f7fe91e | 103 | amd64_supply_native_gregset (regcache, gregsetp, -1); |
53e95fcf JS |
104 | } |
105 | ||
60fac5b8 MK |
106 | /* Fill register REGNUM (if it is a general-purpose register) in |
107 | *GREGSETP with the value in GDB's register cache. If REGNUM is -1, | |
53e95fcf JS |
108 | do this for all registers. */ |
109 | ||
110 | void | |
7f7fe91e UW |
111 | fill_gregset (const struct regcache *regcache, |
112 | elf_gregset_t *gregsetp, int regnum) | |
53e95fcf | 113 | { |
7f7fe91e | 114 | amd64_collect_native_gregset (regcache, gregsetp, regnum); |
53e95fcf JS |
115 | } |
116 | ||
53e95fcf JS |
117 | /* Transfering floating-point registers between GDB, inferiors and cores. */ |
118 | ||
60fac5b8 | 119 | /* Fill GDB's register cache with the floating-point and SSE register |
c4f35dd8 | 120 | values in *FPREGSETP. */ |
53e95fcf JS |
121 | |
122 | void | |
7f7fe91e | 123 | supply_fpregset (struct regcache *regcache, const elf_fpregset_t *fpregsetp) |
53e95fcf | 124 | { |
7f7fe91e | 125 | amd64_supply_fxsave (regcache, -1, fpregsetp); |
53e95fcf JS |
126 | } |
127 | ||
8dda9770 | 128 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
60fac5b8 | 129 | *FPREGSETP with the value in GDB's register cache. If REGNUM is |
c4f35dd8 | 130 | -1, do this for all registers. */ |
53e95fcf JS |
131 | |
132 | void | |
7f7fe91e UW |
133 | fill_fpregset (const struct regcache *regcache, |
134 | elf_fpregset_t *fpregsetp, int regnum) | |
53e95fcf | 135 | { |
7f7fe91e | 136 | amd64_collect_fxsave (regcache, regnum, fpregsetp); |
53e95fcf | 137 | } |
53e95fcf JS |
138 | \f |
139 | ||
140 | /* Transferring arbitrary registers between GDB and inferior. */ | |
141 | ||
60fac5b8 | 142 | /* Fetch register REGNUM from the child process. If REGNUM is -1, do |
53e95fcf JS |
143 | this for all registers (including the floating point and SSE |
144 | registers). */ | |
145 | ||
f6ac5f3d PA |
146 | void |
147 | amd64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) | |
53e95fcf | 148 | { |
ac7936df | 149 | struct gdbarch *gdbarch = regcache->arch (); |
53e95fcf JS |
150 | int tid; |
151 | ||
a4b6fc86 | 152 | /* GNU/Linux LWP ID's are process ID's. */ |
e38504b3 | 153 | tid = regcache->ptid ().lwp (); |
c4f35dd8 | 154 | if (tid == 0) |
e99b03dc | 155 | tid = regcache->ptid ().pid (); /* Not a threaded program. */ |
53e95fcf | 156 | |
f8028488 | 157 | if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 158 | { |
99679982 MK |
159 | elf_gregset_t regs; |
160 | ||
161 | if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 162 | perror_with_name (_("Couldn't get registers")); |
99679982 | 163 | |
56be3814 | 164 | amd64_supply_native_gregset (regcache, ®s, -1); |
60fac5b8 MK |
165 | if (regnum != -1) |
166 | return; | |
53e95fcf JS |
167 | } |
168 | ||
f8028488 | 169 | if (regnum == -1 || !amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 170 | { |
99679982 | 171 | elf_fpregset_t fpregs; |
53e95fcf | 172 | |
0bdb2f78 | 173 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
a055a187 | 174 | { |
df7e5265 | 175 | char xstateregs[X86_XSTATE_MAX_SIZE]; |
a055a187 L |
176 | struct iovec iov; |
177 | ||
178 | iov.iov_base = xstateregs; | |
179 | iov.iov_len = sizeof (xstateregs); | |
180 | if (ptrace (PTRACE_GETREGSET, tid, | |
181 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
182 | perror_with_name (_("Couldn't get extended state status")); | |
99679982 | 183 | |
a055a187 L |
184 | amd64_supply_xsave (regcache, -1, xstateregs); |
185 | } | |
186 | else | |
187 | { | |
188 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (long) &fpregs) < 0) | |
189 | perror_with_name (_("Couldn't get floating point status")); | |
190 | ||
191 | amd64_supply_fxsave (regcache, -1, &fpregs); | |
192 | } | |
2735833d WT |
193 | #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE |
194 | { | |
195 | /* PTRACE_ARCH_PRCTL is obsolete since 2.6.25, where the | |
196 | fs_base and gs_base fields of user_regs_struct can be | |
197 | used directly. */ | |
198 | unsigned long base; | |
199 | ||
200 | if (regnum == -1 || regnum == AMD64_FSBASE_REGNUM) | |
201 | { | |
202 | if (ptrace (PTRACE_ARCH_PRCTL, tid, &base, ARCH_GET_FS) < 0) | |
203 | perror_with_name (_("Couldn't get segment register fs_base")); | |
204 | ||
73e1c03f | 205 | regcache->raw_supply (AMD64_FSBASE_REGNUM, &base); |
2735833d WT |
206 | } |
207 | ||
208 | if (regnum == -1 || regnum == AMD64_GSBASE_REGNUM) | |
209 | { | |
210 | if (ptrace (PTRACE_ARCH_PRCTL, tid, &base, ARCH_GET_GS) < 0) | |
211 | perror_with_name (_("Couldn't get segment register gs_base")); | |
212 | ||
73e1c03f | 213 | regcache->raw_supply (AMD64_GSBASE_REGNUM, &base); |
2735833d WT |
214 | } |
215 | } | |
216 | #endif | |
99679982 | 217 | } |
53e95fcf JS |
218 | } |
219 | ||
60fac5b8 MK |
220 | /* Store register REGNUM back into the child process. If REGNUM is |
221 | -1, do this for all registers (including the floating-point and SSE | |
53e95fcf | 222 | registers). */ |
c4f35dd8 | 223 | |
f6ac5f3d PA |
224 | void |
225 | amd64_linux_nat_target::store_registers (struct regcache *regcache, int regnum) | |
53e95fcf | 226 | { |
ac7936df | 227 | struct gdbarch *gdbarch = regcache->arch (); |
53e95fcf JS |
228 | int tid; |
229 | ||
a4b6fc86 | 230 | /* GNU/Linux LWP ID's are process ID's. */ |
e38504b3 | 231 | tid = regcache->ptid ().lwp (); |
c4f35dd8 | 232 | if (tid == 0) |
e99b03dc | 233 | tid = regcache->ptid ().pid (); /* Not a threaded program. */ |
53e95fcf | 234 | |
f8028488 | 235 | if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 236 | { |
99679982 MK |
237 | elf_gregset_t regs; |
238 | ||
239 | if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 240 | perror_with_name (_("Couldn't get registers")); |
99679982 | 241 | |
56be3814 | 242 | amd64_collect_native_gregset (regcache, ®s, regnum); |
99679982 MK |
243 | |
244 | if (ptrace (PTRACE_SETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 245 | perror_with_name (_("Couldn't write registers")); |
99679982 | 246 | |
60fac5b8 MK |
247 | if (regnum != -1) |
248 | return; | |
53e95fcf JS |
249 | } |
250 | ||
f8028488 | 251 | if (regnum == -1 || !amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 252 | { |
99679982 MK |
253 | elf_fpregset_t fpregs; |
254 | ||
0bdb2f78 | 255 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
a055a187 | 256 | { |
df7e5265 | 257 | char xstateregs[X86_XSTATE_MAX_SIZE]; |
a055a187 L |
258 | struct iovec iov; |
259 | ||
260 | iov.iov_base = xstateregs; | |
261 | iov.iov_len = sizeof (xstateregs); | |
262 | if (ptrace (PTRACE_GETREGSET, tid, | |
263 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
264 | perror_with_name (_("Couldn't get extended state status")); | |
99679982 | 265 | |
a055a187 L |
266 | amd64_collect_xsave (regcache, regnum, xstateregs, 0); |
267 | ||
268 | if (ptrace (PTRACE_SETREGSET, tid, | |
269 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
270 | perror_with_name (_("Couldn't write extended state status")); | |
271 | } | |
272 | else | |
273 | { | |
274 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (long) &fpregs) < 0) | |
275 | perror_with_name (_("Couldn't get floating point status")); | |
99679982 | 276 | |
a055a187 | 277 | amd64_collect_fxsave (regcache, regnum, &fpregs); |
99679982 | 278 | |
a055a187 L |
279 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (long) &fpregs) < 0) |
280 | perror_with_name (_("Couldn't write floating point status")); | |
281 | } | |
2735833d WT |
282 | |
283 | #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE | |
284 | { | |
285 | /* PTRACE_ARCH_PRCTL is obsolete since 2.6.25, where the | |
286 | fs_base and gs_base fields of user_regs_struct can be | |
287 | used directly. */ | |
288 | void *base; | |
289 | ||
290 | if (regnum == -1 || regnum == AMD64_FSBASE_REGNUM) | |
291 | { | |
34a79281 | 292 | regcache->raw_collect (AMD64_FSBASE_REGNUM, &base); |
2735833d WT |
293 | |
294 | if (ptrace (PTRACE_ARCH_PRCTL, tid, base, ARCH_SET_FS) < 0) | |
295 | perror_with_name (_("Couldn't write segment register fs_base")); | |
296 | } | |
297 | if (regnum == -1 || regnum == AMD64_GSBASE_REGNUM) | |
298 | { | |
299 | ||
34a79281 | 300 | regcache->raw_collect (AMD64_GSBASE_REGNUM, &base); |
2735833d WT |
301 | if (ptrace (PTRACE_ARCH_PRCTL, tid, base, ARCH_SET_GS) < 0) |
302 | perror_with_name (_("Couldn't write segment register gs_base")); | |
303 | } | |
304 | } | |
305 | #endif | |
53e95fcf | 306 | } |
53e95fcf JS |
307 | } |
308 | \f | |
1aa7e42c | 309 | |
50d71875 AC |
310 | /* This function is called by libthread_db as part of its handling of |
311 | a request for a thread's local storage address. */ | |
312 | ||
5bca7895 | 313 | ps_err_e |
754653a7 | 314 | ps_get_thread_area (struct ps_prochandle *ph, |
c43af07c EZ |
315 | lwpid_t lwpid, int idx, void **base) |
316 | { | |
f5656ead | 317 | if (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 32) |
50d71875 | 318 | { |
8c420b8d GB |
319 | unsigned int base_addr; |
320 | ps_err_e result; | |
321 | ||
322 | result = x86_linux_get_thread_area (lwpid, (void *) (long) idx, | |
323 | &base_addr); | |
324 | if (result == PS_OK) | |
325 | { | |
326 | /* Extend the value to 64 bits. Here it's assumed that | |
327 | a "long" and a "void *" are the same. */ | |
328 | (*base) = (void *) (long) base_addr; | |
329 | } | |
330 | return result; | |
50d71875 AC |
331 | } |
332 | else | |
333 | { | |
2735833d | 334 | |
50d71875 AC |
335 | /* FIXME: ezannoni-2003-07-09 see comment above about include |
336 | file order. We could be getting bogus values for these two. */ | |
337 | gdb_assert (FS < ELF_NGREG); | |
338 | gdb_assert (GS < ELF_NGREG); | |
339 | switch (idx) | |
340 | { | |
341 | case FS: | |
6fea9e18 L |
342 | #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE |
343 | { | |
344 | /* PTRACE_ARCH_PRCTL is obsolete since 2.6.25, where the | |
345 | fs_base and gs_base fields of user_regs_struct can be | |
346 | used directly. */ | |
347 | unsigned long fs; | |
348 | errno = 0; | |
349 | fs = ptrace (PTRACE_PEEKUSER, lwpid, | |
350 | offsetof (struct user_regs_struct, fs_base), 0); | |
351 | if (errno == 0) | |
352 | { | |
353 | *base = (void *) fs; | |
354 | return PS_OK; | |
355 | } | |
356 | } | |
357 | #endif | |
50d71875 AC |
358 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0) |
359 | return PS_OK; | |
360 | break; | |
361 | case GS: | |
6fea9e18 L |
362 | #ifdef HAVE_STRUCT_USER_REGS_STRUCT_GS_BASE |
363 | { | |
364 | unsigned long gs; | |
365 | errno = 0; | |
366 | gs = ptrace (PTRACE_PEEKUSER, lwpid, | |
367 | offsetof (struct user_regs_struct, gs_base), 0); | |
368 | if (errno == 0) | |
369 | { | |
370 | *base = (void *) gs; | |
371 | return PS_OK; | |
372 | } | |
373 | } | |
374 | #endif | |
50d71875 AC |
375 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0) |
376 | return PS_OK; | |
377 | break; | |
378 | default: /* Should not happen. */ | |
379 | return PS_BADADDR; | |
380 | } | |
c43af07c | 381 | } |
b6d42148 | 382 | return PS_ERR; /* ptrace failed. */ |
c43af07c | 383 | } |
5bca7895 | 384 | \f |
c43af07c | 385 | |
9cf12d57 | 386 | /* Convert a ptrace/host siginfo object, into/from the siginfo in the |
5b009018 PA |
387 | layout of the inferiors' architecture. Returns true if any |
388 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
9cf12d57 | 389 | from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to |
5b009018 PA |
390 | INF. */ |
391 | ||
135340af PA |
392 | bool |
393 | amd64_linux_nat_target::low_siginfo_fixup (siginfo_t *ptrace, | |
394 | gdb_byte *inf, | |
395 | int direction) | |
5b009018 | 396 | { |
ba224c70 L |
397 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); |
398 | ||
5b009018 PA |
399 | /* Is the inferior 32-bit? If so, then do fixup the siginfo |
400 | object. */ | |
ba224c70 | 401 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
135340af PA |
402 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
403 | FIXUP_32); | |
ba224c70 L |
404 | /* No fixup for native x32 GDB. */ |
405 | else if (gdbarch_addr_bit (gdbarch) == 32 && sizeof (void *) == 8) | |
135340af PA |
406 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
407 | FIXUP_X32); | |
5b009018 | 408 | else |
135340af | 409 | return false; |
5b009018 | 410 | } |
c1e246a0 | 411 | |
c1e246a0 GB |
412 | void |
413 | _initialize_amd64_linux_nat (void) | |
414 | { | |
c1e246a0 GB |
415 | amd64_native_gregset32_reg_offset = amd64_linux_gregset32_reg_offset; |
416 | amd64_native_gregset32_num_regs = I386_LINUX_NUM_REGS; | |
417 | amd64_native_gregset64_reg_offset = amd64_linux_gregset_reg_offset; | |
418 | amd64_native_gregset64_num_regs = AMD64_LINUX_NUM_REGS; | |
419 | ||
420 | gdb_assert (ARRAY_SIZE (amd64_linux_gregset32_reg_offset) | |
421 | == amd64_native_gregset32_num_regs); | |
422 | ||
f6ac5f3d | 423 | linux_target = &the_amd64_linux_nat_target; |
c1e246a0 GB |
424 | |
425 | /* Add the target. */ | |
d9f719f1 | 426 | add_inf_child_target (linux_target); |
c1e246a0 | 427 | } |