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Add missing quotes to gdb/testsuite/README
[deliverable/binutils-gdb.git] / gdb / amd64-tdep.c
CommitLineData
e53bef9f 1/* Target-dependent code for AMD64.
ce0eebec 2
618f726f 3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
5ae96ec1
MK		 4
5 Contributed by Jiri Smid, SuSE Labs.
53e95fcf
JS		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
53e95fcf
JS		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
53e95fcf
JS		 21
22#include "defs.h"
35669430
DE		 23#include "opcode/i386.h"
24#include "dis-asm.h"
c4f35dd8
MK		 25#include "arch-utils.h"
26#include "block.h"
27#include "dummy-frame.h"
28#include "frame.h"
29#include "frame-base.h"
30#include "frame-unwind.h"
53e95fcf 31#include "inferior.h"
45741a9c 32#include "infrun.h"
53e95fcf 33#include "gdbcmd.h"
c4f35dd8
MK		 34#include "gdbcore.h"
35#include "objfiles.h"
53e95fcf 36#include "regcache.h"
2c261fae 37#include "regset.h"
53e95fcf 38#include "symfile.h"
eda5a4d7 39#include "disasm.h"
9c1488cb 40#include "amd64-tdep.h"
c4f35dd8 41#include "i387-tdep.h"
97de3545 42#include "x86-xstate.h"
53e95fcf 43
90884b2b 44#include "features/i386/amd64.c"
a055a187 45#include "features/i386/amd64-avx.c"
e43e105e 46#include "features/i386/amd64-mpx.c"
01f9f808
MS		 47#include "features/i386/amd64-avx512.c"
48
ac1438b5
L		 49#include "features/i386/x32.c"
50#include "features/i386/x32-avx.c"
01f9f808 51#include "features/i386/x32-avx512.c"
90884b2b 52
6710bf39
SS		 53#include "ax.h"
54#include "ax-gdb.h"
55
e53bef9f
MK		 56/* Note that the AMD64 architecture was previously known as x86-64.
57 The latter is (forever) engraved into the canonical system name as
90f90721 58 returned by config.guess, and used as the name for the AMD64 port
e53bef9f
MK		 59 of GNU/Linux. The BSD's have renamed their ports to amd64; they
60 don't like to shout. For GDB we prefer the amd64_-prefix over the
61 x86_64_-prefix since it's so much easier to type. */
62
402ecd56 63/* Register information. */
c4f35dd8 64
6707b003 65static const char *amd64_register_names[] =
de220d0f 66{
6707b003 67 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
c4f35dd8
MK		 68
69 /* %r8 is indeed register number 8. */
6707b003
UW		 70 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
c4f35dd8 72
af233647 73 /* %st0 is register number 24. */
6707b003
UW		 74 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
75 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
c4f35dd8 76
af233647 77 /* %xmm0 is register number 40. */
6707b003
UW		 78 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
79 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
80 "mxcsr",
0e04a514
ML		 81};
82
a055a187
L		 83static const char *amd64_ymm_names[] =
84{
85 "ymm0", "ymm1", "ymm2", "ymm3",
86 "ymm4", "ymm5", "ymm6", "ymm7",
87 "ymm8", "ymm9", "ymm10", "ymm11",
88 "ymm12", "ymm13", "ymm14", "ymm15"
89};
90
01f9f808
MS		 91static const char *amd64_ymm_avx512_names[] =
92{
93 "ymm16", "ymm17", "ymm18", "ymm19",
94 "ymm20", "ymm21", "ymm22", "ymm23",
95 "ymm24", "ymm25", "ymm26", "ymm27",
96 "ymm28", "ymm29", "ymm30", "ymm31"
97};
98
a055a187
L		 99static const char *amd64_ymmh_names[] =
100{
101 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
102 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
103 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
104 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
105};
de220d0f 106
01f9f808
MS		 107static const char *amd64_ymmh_avx512_names[] =
108{
109 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
110 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
111 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
112 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
113};
114
e43e105e
WT		 115static const char *amd64_mpx_names[] =
116{
117 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
118};
119
01f9f808
MS		 120static const char *amd64_k_names[] =
121{
122 "k0", "k1", "k2", "k3",
123 "k4", "k5", "k6", "k7"
124};
125
126static const char *amd64_zmmh_names[] =
127{
128 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
129 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
130 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
131 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
132 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
133 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
134 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
135 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
136};
137
138static const char *amd64_zmm_names[] =
139{
140 "zmm0", "zmm1", "zmm2", "zmm3",
141 "zmm4", "zmm5", "zmm6", "zmm7",
142 "zmm8", "zmm9", "zmm10", "zmm11",
143 "zmm12", "zmm13", "zmm14", "zmm15",
144 "zmm16", "zmm17", "zmm18", "zmm19",
145 "zmm20", "zmm21", "zmm22", "zmm23",
146 "zmm24", "zmm25", "zmm26", "zmm27",
147 "zmm28", "zmm29", "zmm30", "zmm31"
148};
149
150static const char *amd64_xmm_avx512_names[] = {
151 "xmm16", "xmm17", "xmm18", "xmm19",
152 "xmm20", "xmm21", "xmm22", "xmm23",
153 "xmm24", "xmm25", "xmm26", "xmm27",
154 "xmm28", "xmm29", "xmm30", "xmm31"
155};
156
c4f35dd8
MK		 157/* DWARF Register Number Mapping as defined in the System V psABI,
158 section 3.6. */
53e95fcf 159
e53bef9f 160static int amd64_dwarf_regmap[] =
0e04a514 161{
c4f35dd8 162 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
90f90721
MK		 163 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
164 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
165 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
c4f35dd8
MK		 166
167 /* Frame Pointer Register RBP. */
90f90721 168 AMD64_RBP_REGNUM,
c4f35dd8
MK		 169
170 /* Stack Pointer Register RSP. */
90f90721 171 AMD64_RSP_REGNUM,
c4f35dd8
MK		 172
173 /* Extended Integer Registers 8 - 15. */
5b856f36
PM		 174 AMD64_R8_REGNUM, /* %r8 */
175 AMD64_R9_REGNUM, /* %r9 */
176 AMD64_R10_REGNUM, /* %r10 */
177 AMD64_R11_REGNUM, /* %r11 */
178 AMD64_R12_REGNUM, /* %r12 */
179 AMD64_R13_REGNUM, /* %r13 */
180 AMD64_R14_REGNUM, /* %r14 */
181 AMD64_R15_REGNUM, /* %r15 */
c4f35dd8 182
59207364 183 /* Return Address RA. Mapped to RIP. */
90f90721 184 AMD64_RIP_REGNUM,
c4f35dd8
MK		 185
186 /* SSE Registers 0 - 7. */
90f90721
MK		 187 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
188 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
189 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
190 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
c4f35dd8
MK		 191
192 /* Extended SSE Registers 8 - 15. */
90f90721
MK		 193 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
194 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
195 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
196 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
c4f35dd8
MK		 197
198 /* Floating Point Registers 0-7. */
90f90721
MK		 199 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
200 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
201 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
c6f4c129 202 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
f7ca3fcf
PM		 203
204 /* MMX Registers 0 - 7.
205 We have to handle those registers specifically, as their register
206 number within GDB depends on the target (or they may even not be
207 available at all). */
208 -1, -1, -1, -1, -1, -1, -1, -1,
209
c6f4c129
JB		 210 /* Control and Status Flags Register. */
211 AMD64_EFLAGS_REGNUM,
212
213 /* Selector Registers. */
214 AMD64_ES_REGNUM,
215 AMD64_CS_REGNUM,
216 AMD64_SS_REGNUM,
217 AMD64_DS_REGNUM,
218 AMD64_FS_REGNUM,
219 AMD64_GS_REGNUM,
220 -1,
221 -1,
222
223 /* Segment Base Address Registers. */
224 -1,
225 -1,
226 -1,
227 -1,
228
229 /* Special Selector Registers. */
230 -1,
231 -1,
232
233 /* Floating Point Control Registers. */
234 AMD64_MXCSR_REGNUM,
235 AMD64_FCTRL_REGNUM,
236 AMD64_FSTAT_REGNUM
c4f35dd8 237};
0e04a514 238
e53bef9f
MK		 239static const int amd64_dwarf_regmap_len =
240 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
0e04a514 241
c4f35dd8
MK		 242/* Convert DWARF register number REG to the appropriate register
243 number used by GDB. */
26abbdc4 244
c4f35dd8 245static int
d3f73121 246amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
53e95fcf 247{
a055a187
L		 248 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
249 int ymm0_regnum = tdep->ymm0_regnum;
c4f35dd8 250 int regnum = -1;
53e95fcf 251
16aff9a6 252 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
e53bef9f 253 regnum = amd64_dwarf_regmap[reg];
53e95fcf 254
0fde2c53 255 if (ymm0_regnum >= 0
a055a187
L		 256 && i386_xmm_regnum_p (gdbarch, regnum))
257 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
c4f35dd8
MK		 258
259 return regnum;
53e95fcf 260}
d532c08f 261
35669430
DE		 262/* Map architectural register numbers to gdb register numbers. */
263
264static const int amd64_arch_regmap[16] =
265{
266 AMD64_RAX_REGNUM, /* %rax */
267 AMD64_RCX_REGNUM, /* %rcx */
268 AMD64_RDX_REGNUM, /* %rdx */
269 AMD64_RBX_REGNUM, /* %rbx */
270 AMD64_RSP_REGNUM, /* %rsp */
271 AMD64_RBP_REGNUM, /* %rbp */
272 AMD64_RSI_REGNUM, /* %rsi */
273 AMD64_RDI_REGNUM, /* %rdi */
274 AMD64_R8_REGNUM, /* %r8 */
275 AMD64_R9_REGNUM, /* %r9 */
276 AMD64_R10_REGNUM, /* %r10 */
277 AMD64_R11_REGNUM, /* %r11 */
278 AMD64_R12_REGNUM, /* %r12 */
279 AMD64_R13_REGNUM, /* %r13 */
280 AMD64_R14_REGNUM, /* %r14 */
281 AMD64_R15_REGNUM /* %r15 */
282};
283
284static const int amd64_arch_regmap_len =
285 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
286
287/* Convert architectural register number REG to the appropriate register
288 number used by GDB. */
289
290static int
291amd64_arch_reg_to_regnum (int reg)
292{
293 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
294
295 return amd64_arch_regmap[reg];
296}
297
1ba53b71
L		 298/* Register names for byte pseudo-registers. */
299
300static const char *amd64_byte_names[] =
301{
302 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
fe01d668
L		 303 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
304 "ah", "bh", "ch", "dh"
1ba53b71
L		 305};
306
fe01d668
L		 307/* Number of lower byte registers. */
308#define AMD64_NUM_LOWER_BYTE_REGS 16
309
1ba53b71
L		 310/* Register names for word pseudo-registers. */
311
312static const char *amd64_word_names[] =
313{
9cad29ac 314 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
1ba53b71
L		 315 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
316};
317
318/* Register names for dword pseudo-registers. */
319
320static const char *amd64_dword_names[] =
321{
322 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
fff4548b
MK		 323 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
324 "eip"
1ba53b71
L		 325};
326
327/* Return the name of register REGNUM. */
328
329static const char *
330amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
331{
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
333 if (i386_byte_regnum_p (gdbarch, regnum))
334 return amd64_byte_names[regnum - tdep->al_regnum];
01f9f808
MS		 335 else if (i386_zmm_regnum_p (gdbarch, regnum))
336 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
a055a187
L		 337 else if (i386_ymm_regnum_p (gdbarch, regnum))
338 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
01f9f808
MS		 339 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
340 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
1ba53b71
L		 341 else if (i386_word_regnum_p (gdbarch, regnum))
342 return amd64_word_names[regnum - tdep->ax_regnum];
343 else if (i386_dword_regnum_p (gdbarch, regnum))
344 return amd64_dword_names[regnum - tdep->eax_regnum];
345 else
346 return i386_pseudo_register_name (gdbarch, regnum);
347}
348
3543a589
TT		 349static struct value *
350amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
351 struct regcache *regcache,
352 int regnum)
1ba53b71
L		 353{
354 gdb_byte raw_buf[MAX_REGISTER_SIZE];
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
05d1431c 356 enum register_status status;
3543a589
TT		 357 struct value *result_value;
358 gdb_byte *buf;
359
360 result_value = allocate_value (register_type (gdbarch, regnum));
361 VALUE_LVAL (result_value) = lval_register;
362 VALUE_REGNUM (result_value) = regnum;
363 buf = value_contents_raw (result_value);
1ba53b71
L		 364
365 if (i386_byte_regnum_p (gdbarch, regnum))
366 {
367 int gpnum = regnum - tdep->al_regnum;
368
369 /* Extract (always little endian). */
fe01d668
L		 370 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
371 {
372 /* Special handling for AH, BH, CH, DH. */
05d1431c
PA		 373 status = regcache_raw_read (regcache,
374 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
375 raw_buf);
376 if (status == REG_VALID)
377 memcpy (buf, raw_buf + 1, 1);
3543a589
TT		 378 else
379 mark_value_bytes_unavailable (result_value, 0,
380 TYPE_LENGTH (value_type (result_value)));
fe01d668
L		 381 }
382 else
383 {
05d1431c
PA		 384 status = regcache_raw_read (regcache, gpnum, raw_buf);
385 if (status == REG_VALID)
386 memcpy (buf, raw_buf, 1);
3543a589
TT		 387 else
388 mark_value_bytes_unavailable (result_value, 0,
389 TYPE_LENGTH (value_type (result_value)));
fe01d668 390 }
1ba53b71
L		 391 }
392 else if (i386_dword_regnum_p (gdbarch, regnum))
393 {
394 int gpnum = regnum - tdep->eax_regnum;
395 /* Extract (always little endian). */
05d1431c
PA		 396 status = regcache_raw_read (regcache, gpnum, raw_buf);
397 if (status == REG_VALID)
398 memcpy (buf, raw_buf, 4);
3543a589
TT		 399 else
400 mark_value_bytes_unavailable (result_value, 0,
401 TYPE_LENGTH (value_type (result_value)));
1ba53b71
L		 402 }
403 else
3543a589
TT		 404 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
405 result_value);
406
407 return result_value;
1ba53b71
L		 408}
409
410static void
411amd64_pseudo_register_write (struct gdbarch *gdbarch,
412 struct regcache *regcache,
413 int regnum, const gdb_byte *buf)
414{
415 gdb_byte raw_buf[MAX_REGISTER_SIZE];
416 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
417
418 if (i386_byte_regnum_p (gdbarch, regnum))
419 {
420 int gpnum = regnum - tdep->al_regnum;
421
fe01d668
L		 422 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
423 {
424 /* Read ... AH, BH, CH, DH. */
425 regcache_raw_read (regcache,
426 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
427 /* ... Modify ... (always little endian). */
428 memcpy (raw_buf + 1, buf, 1);
429 /* ... Write. */
430 regcache_raw_write (regcache,
431 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
432 }
433 else
434 {
435 /* Read ... */
436 regcache_raw_read (regcache, gpnum, raw_buf);
437 /* ... Modify ... (always little endian). */
438 memcpy (raw_buf, buf, 1);
439 /* ... Write. */
440 regcache_raw_write (regcache, gpnum, raw_buf);
441 }
1ba53b71
L		 442 }
443 else if (i386_dword_regnum_p (gdbarch, regnum))
444 {
445 int gpnum = regnum - tdep->eax_regnum;
446
447 /* Read ... */
448 regcache_raw_read (regcache, gpnum, raw_buf);
449 /* ... Modify ... (always little endian). */
450 memcpy (raw_buf, buf, 4);
451 /* ... Write. */
452 regcache_raw_write (regcache, gpnum, raw_buf);
453 }
454 else
455 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
456}
457
62e5fd57
MK		 458/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
459
460static int
461amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
462 struct agent_expr *ax, int regnum)
463{
464 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
465
466 if (i386_byte_regnum_p (gdbarch, regnum))
467 {
468 int gpnum = regnum - tdep->al_regnum;
469
470 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
471 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
472 else
473 ax_reg_mask (ax, gpnum);
474 return 0;
475 }
476 else if (i386_dword_regnum_p (gdbarch, regnum))
477 {
478 int gpnum = regnum - tdep->eax_regnum;
479
480 ax_reg_mask (ax, gpnum);
481 return 0;
482 }
483 else
484 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
485}
486
53e95fcf
JS		 487\f
488
bf4d6c1c
JB		 489/* Register classes as defined in the psABI. */
490
491enum amd64_reg_class
492{
493 AMD64_INTEGER,
494 AMD64_SSE,
495 AMD64_SSEUP,
496 AMD64_X87,
497 AMD64_X87UP,
498 AMD64_COMPLEX_X87,
499 AMD64_NO_CLASS,
500 AMD64_MEMORY
501};
502
efb1c01c
MK		 503/* Return the union class of CLASS1 and CLASS2. See the psABI for
504 details. */
505
506static enum amd64_reg_class
507amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
508{
509 /* Rule (a): If both classes are equal, this is the resulting class. */
510 if (class1 == class2)
511 return class1;
512
513 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
514 is the other class. */
515 if (class1 == AMD64_NO_CLASS)
516 return class2;
517 if (class2 == AMD64_NO_CLASS)
518 return class1;
519
520 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
521 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
522 return AMD64_MEMORY;
523
524 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
525 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
526 return AMD64_INTEGER;
527
528 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
529 MEMORY is used as class. */
530 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
531 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
532 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
533 return AMD64_MEMORY;
534
535 /* Rule (f): Otherwise class SSE is used. */
536 return AMD64_SSE;
537}
538
fe978cb0 539static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
bf4d6c1c 540
79b1ab3d
MK		 541/* Return non-zero if TYPE is a non-POD structure or union type. */
542
543static int
544amd64_non_pod_p (struct type *type)
545{
546 /* ??? A class with a base class certainly isn't POD, but does this
547 catch all non-POD structure types? */
548 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
549 return 1;
550
551 return 0;
552}
553
efb1c01c
MK		 554/* Classify TYPE according to the rules for aggregate (structures and
555 arrays) and union types, and store the result in CLASS. */
c4f35dd8
MK		 556
557static void
fe978cb0 558amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
53e95fcf 559{
efb1c01c
MK		 560 /* 1. If the size of an object is larger than two eightbytes, or in
561 C++, is a non-POD structure or union type, or contains
562 unaligned fields, it has class memory. */
744a8059 563 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
53e95fcf 564 {
fe978cb0 565 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 566 return;
53e95fcf 567 }
efb1c01c
MK		 568
569 /* 2. Both eightbytes get initialized to class NO_CLASS. */
fe978cb0 570 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 571
572 /* 3. Each field of an object is classified recursively so that
573 always two fields are considered. The resulting class is
574 calculated according to the classes of the fields in the
575 eightbyte: */
576
577 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
8ffd9b1b 578 {
efb1c01c
MK		 579 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
580
581 /* All fields in an array have the same type. */
fe978cb0
PA		 582 amd64_classify (subtype, theclass);
583 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
584 theclass[1] = theclass[0];
8ffd9b1b 585 }
53e95fcf
JS		 586 else
587 {
efb1c01c 588 int i;
53e95fcf 589
efb1c01c
MK		 590 /* Structure or union. */
591 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
592 || TYPE_CODE (type) == TYPE_CODE_UNION);
593
594 for (i = 0; i < TYPE_NFIELDS (type); i++)
53e95fcf 595 {
efb1c01c
MK		 596 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
597 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
598 enum amd64_reg_class subclass[2];
e4e2711a
JB		 599 int bitsize = TYPE_FIELD_BITSIZE (type, i);
600 int endpos;
601
602 if (bitsize == 0)
603 bitsize = TYPE_LENGTH (subtype) * 8;
604 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
efb1c01c 605
562c50c2 606 /* Ignore static fields. */
d6a843b5 607 if (field_is_static (&TYPE_FIELD (type, i)))
562c50c2
MK		 608 continue;
609
efb1c01c
MK		 610 gdb_assert (pos == 0 || pos == 1);
611
612 amd64_classify (subtype, subclass);
fe978cb0 613 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
e4e2711a
JB		 614 if (bitsize <= 64 && pos == 0 && endpos == 1)
615 /* This is a bit of an odd case: We have a field that would
616 normally fit in one of the two eightbytes, except that
617 it is placed in a way that this field straddles them.
618 This has been seen with a structure containing an array.
619
620 The ABI is a bit unclear in this case, but we assume that
621 this field's class (stored in subclass[0]) must also be merged
622 into class[1]. In other words, our field has a piece stored
623 in the second eight-byte, and thus its class applies to
624 the second eight-byte as well.
625
626 In the case where the field length exceeds 8 bytes,
627 it should not be necessary to merge the field class
628 into class[1]. As LEN > 8, subclass[1] is necessarily
629 different from AMD64_NO_CLASS. If subclass[1] is equal
630 to subclass[0], then the normal class[1]/subclass[1]
631 merging will take care of everything. For subclass[1]
632 to be different from subclass[0], I can only see the case
633 where we have a SSE/SSEUP or X87/X87UP pair, which both
634 use up all 16 bytes of the aggregate, and are already
635 handled just fine (because each portion sits on its own
636 8-byte). */
fe978cb0 637 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
efb1c01c 638 if (pos == 0)
fe978cb0 639 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
53e95fcf 640 }
53e95fcf 641 }
efb1c01c
MK		 642
643 /* 4. Then a post merger cleanup is done: */
644
645 /* Rule (a): If one of the classes is MEMORY, the whole argument is
646 passed in memory. */
fe978cb0
PA		 647 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
648 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 649
177b42fe 650 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
efb1c01c 651 SSE. */
fe978cb0
PA		 652 if (theclass[0] == AMD64_SSEUP)
653 theclass[0] = AMD64_SSE;
654 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
655 theclass[1] = AMD64_SSE;
efb1c01c
MK		 656}
657
658/* Classify TYPE, and store the result in CLASS. */
659
bf4d6c1c 660static void
fe978cb0 661amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
efb1c01c
MK		 662{
663 enum type_code code = TYPE_CODE (type);
664 int len = TYPE_LENGTH (type);
665
fe978cb0 666 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 667
668 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
5a7225ed
JB		 669 long, long long, and pointers are in the INTEGER class. Similarly,
670 range types, used by languages such as Ada, are also in the INTEGER
671 class. */
efb1c01c 672 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
b929c77f 673 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
9db13498 674 || code == TYPE_CODE_CHAR
efb1c01c
MK		 675 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
676 && (len == 1 || len == 2 || len == 4 || len == 8))
fe978cb0 677 theclass[0] = AMD64_INTEGER;
efb1c01c 678
5daa78cc
TJB		 679 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
680 are in class SSE. */
681 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
682 && (len == 4 || len == 8))
efb1c01c 683 /* FIXME: __m64 . */
fe978cb0 684 theclass[0] = AMD64_SSE;
efb1c01c 685
5daa78cc
TJB		 686 /* Arguments of types __float128, _Decimal128 and __m128 are split into
687 two halves. The least significant ones belong to class SSE, the most
efb1c01c 688 significant one to class SSEUP. */
5daa78cc
TJB		 689 else if (code == TYPE_CODE_DECFLOAT && len == 16)
690 /* FIXME: __float128, __m128. */
fe978cb0 691 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
efb1c01c
MK		 692
693 /* The 64-bit mantissa of arguments of type long double belongs to
694 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
695 class X87UP. */
696 else if (code == TYPE_CODE_FLT && len == 16)
697 /* Class X87 and X87UP. */
fe978cb0 698 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
efb1c01c 699
7f7930dd
MK		 700 /* Arguments of complex T where T is one of the types float or
701 double get treated as if they are implemented as:
702
703 struct complexT {
704 T real;
705 T imag;
5f52445b
YQ		 706 };
707
708 */
7f7930dd 709 else if (code == TYPE_CODE_COMPLEX && len == 8)
fe978cb0 710 theclass[0] = AMD64_SSE;
7f7930dd 711 else if (code == TYPE_CODE_COMPLEX && len == 16)
fe978cb0 712 theclass[0] = theclass[1] = AMD64_SSE;
7f7930dd
MK		 713
714 /* A variable of type complex long double is classified as type
715 COMPLEX_X87. */
716 else if (code == TYPE_CODE_COMPLEX && len == 32)
fe978cb0 717 theclass[0] = AMD64_COMPLEX_X87;
7f7930dd 718
efb1c01c
MK		 719 /* Aggregates. */
720 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
721 || code == TYPE_CODE_UNION)
fe978cb0 722 amd64_classify_aggregate (type, theclass);
efb1c01c
MK		 723}
724
725static enum return_value_convention
6a3a010b 726amd64_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 727 struct type *type, struct regcache *regcache,
42835c2b 728 gdb_byte *readbuf, const gdb_byte *writebuf)
efb1c01c 729{
fe978cb0 730 enum amd64_reg_class theclass[2];
efb1c01c 731 int len = TYPE_LENGTH (type);
90f90721
MK		 732 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
733 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
efb1c01c
MK		 734 int integer_reg = 0;
735 int sse_reg = 0;
736 int i;
737
738 gdb_assert (!(readbuf && writebuf));
739
740 /* 1. Classify the return type with the classification algorithm. */
fe978cb0 741 amd64_classify (type, theclass);
efb1c01c
MK		 742
743 /* 2. If the type has class MEMORY, then the caller provides space
6fa57a7d 744 for the return value and passes the address of this storage in
0963b4bd 745 %rdi as if it were the first argument to the function. In effect,
6fa57a7d
MK		 746 this address becomes a hidden first argument.
747
748 On return %rax will contain the address that has been passed in
749 by the caller in %rdi. */
fe978cb0 750 if (theclass[0] == AMD64_MEMORY)
6fa57a7d
MK		 751 {
752 /* As indicated by the comment above, the ABI guarantees that we
753 can always find the return value just after the function has
754 returned. */
755
756 if (readbuf)
757 {
758 ULONGEST addr;
759
760 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
761 read_memory (addr, readbuf, TYPE_LENGTH (type));
762 }
763
764 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
765 }
efb1c01c 766
7f7930dd
MK		 767 /* 8. If the class is COMPLEX_X87, the real part of the value is
768 returned in %st0 and the imaginary part in %st1. */
fe978cb0 769 if (theclass[0] == AMD64_COMPLEX_X87)
7f7930dd
MK		 770 {
771 if (readbuf)
772 {
773 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
774 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
775 }
776
777 if (writebuf)
778 {
779 i387_return_value (gdbarch, regcache);
780 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
781 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
782
783 /* Fix up the tag word such that both %st(0) and %st(1) are
784 marked as valid. */
785 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
786 }
787
788 return RETURN_VALUE_REGISTER_CONVENTION;
789 }
790
fe978cb0 791 gdb_assert (theclass[1] != AMD64_MEMORY);
bad43aa5 792 gdb_assert (len <= 16);
efb1c01c
MK		 793
794 for (i = 0; len > 0; i++, len -= 8)
795 {
796 int regnum = -1;
797 int offset = 0;
798
fe978cb0 799 switch (theclass[i])
efb1c01c
MK		 800 {
801 case AMD64_INTEGER:
802 /* 3. If the class is INTEGER, the next available register
803 of the sequence %rax, %rdx is used. */
804 regnum = integer_regnum[integer_reg++];
805 break;
806
807 case AMD64_SSE:
808 /* 4. If the class is SSE, the next available SSE register
809 of the sequence %xmm0, %xmm1 is used. */
810 regnum = sse_regnum[sse_reg++];
811 break;
812
813 case AMD64_SSEUP:
814 /* 5. If the class is SSEUP, the eightbyte is passed in the
815 upper half of the last used SSE register. */
816 gdb_assert (sse_reg > 0);
817 regnum = sse_regnum[sse_reg - 1];
818 offset = 8;
819 break;
820
821 case AMD64_X87:
822 /* 6. If the class is X87, the value is returned on the X87
823 stack in %st0 as 80-bit x87 number. */
90f90721 824 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 825 if (writebuf)
826 i387_return_value (gdbarch, regcache);
827 break;
828
829 case AMD64_X87UP:
830 /* 7. If the class is X87UP, the value is returned together
831 with the previous X87 value in %st0. */
fe978cb0 832 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
90f90721 833 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 834 offset = 8;
835 len = 2;
836 break;
837
838 case AMD64_NO_CLASS:
839 continue;
840
841 default:
842 gdb_assert (!"Unexpected register class.");
843 }
844
845 gdb_assert (regnum != -1);
846
847 if (readbuf)
848 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
42835c2b 849 readbuf + i * 8);
efb1c01c
MK		 850 if (writebuf)
851 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
42835c2b 852 writebuf + i * 8);
efb1c01c
MK		 853 }
854
855 return RETURN_VALUE_REGISTER_CONVENTION;
53e95fcf
JS		 856}
857\f
858
720aa428
MK		 859static CORE_ADDR
860amd64_push_arguments (struct regcache *regcache, int nargs,
6470d250 861 struct value **args, CORE_ADDR sp, int struct_return)
720aa428 862{
bf4d6c1c
JB		 863 static int integer_regnum[] =
864 {
865 AMD64_RDI_REGNUM, /* %rdi */
866 AMD64_RSI_REGNUM, /* %rsi */
867 AMD64_RDX_REGNUM, /* %rdx */
868 AMD64_RCX_REGNUM, /* %rcx */
5b856f36
PM		 869 AMD64_R8_REGNUM, /* %r8 */
870 AMD64_R9_REGNUM /* %r9 */
bf4d6c1c 871 };
720aa428
MK		 872 static int sse_regnum[] =
873 {
874 /* %xmm0 ... %xmm7 */
90f90721
MK		 875 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
876 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
877 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
878 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
720aa428 879 };
224c3ddb 880 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
720aa428
MK		 881 int num_stack_args = 0;
882 int num_elements = 0;
883 int element = 0;
884 int integer_reg = 0;
885 int sse_reg = 0;
886 int i;
887
6470d250
MK		 888 /* Reserve a register for the "hidden" argument. */
889 if (struct_return)
890 integer_reg++;
891
720aa428
MK		 892 for (i = 0; i < nargs; i++)
893 {
4991999e 894 struct type *type = value_type (args[i]);
720aa428 895 int len = TYPE_LENGTH (type);
fe978cb0 896 enum amd64_reg_class theclass[2];
720aa428
MK		 897 int needed_integer_regs = 0;
898 int needed_sse_regs = 0;
899 int j;
900
901 /* Classify argument. */
fe978cb0 902 amd64_classify (type, theclass);
720aa428
MK		 903
904 /* Calculate the number of integer and SSE registers needed for
905 this argument. */
906 for (j = 0; j < 2; j++)
907 {
fe978cb0 908 if (theclass[j] == AMD64_INTEGER)
720aa428 909 needed_integer_regs++;
fe978cb0 910 else if (theclass[j] == AMD64_SSE)
720aa428
MK		 911 needed_sse_regs++;
912 }
913
914 /* Check whether enough registers are available, and if the
915 argument should be passed in registers at all. */
bf4d6c1c 916 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
720aa428
MK		 917 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
918 || (needed_integer_regs == 0 && needed_sse_regs == 0))
919 {
920 /* The argument will be passed on the stack. */
921 num_elements += ((len + 7) / 8);
849e9755 922 stack_args[num_stack_args++] = args[i];
720aa428
MK		 923 }
924 else
925 {
926 /* The argument will be passed in registers. */
d8de1ef7
MK		 927 const gdb_byte *valbuf = value_contents (args[i]);
928 gdb_byte buf[8];
720aa428
MK		 929
930 gdb_assert (len <= 16);
931
932 for (j = 0; len > 0; j++, len -= 8)
933 {
934 int regnum = -1;
935 int offset = 0;
936
fe978cb0 937 switch (theclass[j])
720aa428
MK		 938 {
939 case AMD64_INTEGER:
bf4d6c1c 940 regnum = integer_regnum[integer_reg++];
720aa428
MK		 941 break;
942
943 case AMD64_SSE:
944 regnum = sse_regnum[sse_reg++];
945 break;
946
947 case AMD64_SSEUP:
948 gdb_assert (sse_reg > 0);
949 regnum = sse_regnum[sse_reg - 1];
950 offset = 8;
951 break;
952
953 default:
954 gdb_assert (!"Unexpected register class.");
955 }
956
957 gdb_assert (regnum != -1);
958 memset (buf, 0, sizeof buf);
959 memcpy (buf, valbuf + j * 8, min (len, 8));
960 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
961 }
962 }
963 }
964
965 /* Allocate space for the arguments on the stack. */
966 sp -= num_elements * 8;
967
968 /* The psABI says that "The end of the input argument area shall be
969 aligned on a 16 byte boundary." */
970 sp &= ~0xf;
971
972 /* Write out the arguments to the stack. */
973 for (i = 0; i < num_stack_args; i++)
974 {
4991999e 975 struct type *type = value_type (stack_args[i]);
d8de1ef7 976 const gdb_byte *valbuf = value_contents (stack_args[i]);
849e9755
JB		 977 int len = TYPE_LENGTH (type);
978
979 write_memory (sp + element * 8, valbuf, len);
980 element += ((len + 7) / 8);
720aa428
MK		 981 }
982
983 /* The psABI says that "For calls that may call functions that use
984 varargs or stdargs (prototype-less calls or calls to functions
985 containing ellipsis (...) in the declaration) %al is used as
986 hidden argument to specify the number of SSE registers used. */
90f90721 987 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
720aa428
MK		 988 return sp;
989}
990
c4f35dd8 991static CORE_ADDR
7d9b040b 992amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
e53bef9f
MK		 993 struct regcache *regcache, CORE_ADDR bp_addr,
994 int nargs, struct value **args, CORE_ADDR sp,
995 int struct_return, CORE_ADDR struct_addr)
53e95fcf 996{
e17a4113 997 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 998 gdb_byte buf[8];
c4f35dd8
MK		 999
1000 /* Pass arguments. */
6470d250 1001 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
c4f35dd8
MK		 1002
1003 /* Pass "hidden" argument". */
1004 if (struct_return)
1005 {
e17a4113 1006 store_unsigned_integer (buf, 8, byte_order, struct_addr);
bf4d6c1c 1007 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
c4f35dd8
MK		 1008 }
1009
1010 /* Store return address. */
1011 sp -= 8;
e17a4113 1012 store_unsigned_integer (buf, 8, byte_order, bp_addr);
c4f35dd8
MK		 1013 write_memory (sp, buf, 8);
1014
1015 /* Finally, update the stack pointer... */
e17a4113 1016 store_unsigned_integer (buf, 8, byte_order, sp);
90f90721 1017 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
c4f35dd8
MK		 1018
1019 /* ...and fake a frame pointer. */
90f90721 1020 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
c4f35dd8 1021
3e210248 1022 return sp + 16;
53e95fcf 1023}
c4f35dd8 1024\f
35669430
DE		 1025/* Displaced instruction handling. */
1026
1027/* A partially decoded instruction.
1028 This contains enough details for displaced stepping purposes. */
1029
1030struct amd64_insn
1031{
1032 /* The number of opcode bytes. */
1033 int opcode_len;
1034 /* The offset of the rex prefix or -1 if not present. */
1035 int rex_offset;
1036 /* The offset to the first opcode byte. */
1037 int opcode_offset;
1038 /* The offset to the modrm byte or -1 if not present. */
1039 int modrm_offset;
1040
1041 /* The raw instruction. */
1042 gdb_byte *raw_insn;
1043};
1044
1045struct displaced_step_closure
1046{
1047 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1048 int tmp_used;
1049 int tmp_regno;
1050 ULONGEST tmp_save;
1051
1052 /* Details of the instruction. */
1053 struct amd64_insn insn_details;
1054
1055 /* Amount of space allocated to insn_buf. */
1056 int max_len;
1057
1058 /* The possibly modified insn.
1059 This is a variable-length field. */
1060 gdb_byte insn_buf[1];
1061};
1062
1063/* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1064 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1065 at which point delete these in favor of libopcodes' versions). */
1066
1067static const unsigned char onebyte_has_modrm[256] = {
1068 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1069 /* ------------------------------- */
1070 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1071 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1072 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1073 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1074 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1075 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1076 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1077 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1078 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1079 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1080 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1081 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1082 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1083 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1084 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1085 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1086 /* ------------------------------- */
1087 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1088};
1089
1090static const unsigned char twobyte_has_modrm[256] = {
1091 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1092 /* ------------------------------- */
1093 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1094 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1095 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1096 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1097 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1098 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1099 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1100 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1101 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1102 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1103 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1104 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1105 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1106 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1107 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1108 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1109 /* ------------------------------- */
1110 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1111};
1112
1113static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1114
1115static int
1116rex_prefix_p (gdb_byte pfx)
1117{
1118 return REX_PREFIX_P (pfx);
1119}
1120
1121/* Skip the legacy instruction prefixes in INSN.
1122 We assume INSN is properly sentineled so we don't have to worry
1123 about falling off the end of the buffer. */
1124
1125static gdb_byte *
1903f0e6 1126amd64_skip_prefixes (gdb_byte *insn)
35669430
DE		 1127{
1128 while (1)
1129 {
1130 switch (*insn)
1131 {
1132 case DATA_PREFIX_OPCODE:
1133 case ADDR_PREFIX_OPCODE:
1134 case CS_PREFIX_OPCODE:
1135 case DS_PREFIX_OPCODE:
1136 case ES_PREFIX_OPCODE:
1137 case FS_PREFIX_OPCODE:
1138 case GS_PREFIX_OPCODE:
1139 case SS_PREFIX_OPCODE:
1140 case LOCK_PREFIX_OPCODE:
1141 case REPE_PREFIX_OPCODE:
1142 case REPNE_PREFIX_OPCODE:
1143 ++insn;
1144 continue;
1145 default:
1146 break;
1147 }
1148 break;
1149 }
1150
1151 return insn;
1152}
1153
35669430
DE		 1154/* Return an integer register (other than RSP) that is unused as an input
1155 operand in INSN.
1156 In order to not require adding a rex prefix if the insn doesn't already
1157 have one, the result is restricted to RAX ... RDI, sans RSP.
1158 The register numbering of the result follows architecture ordering,
1159 e.g. RDI = 7. */
1160
1161static int
1162amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1163{
1164 /* 1 bit for each reg */
1165 int used_regs_mask = 0;
1166
1167 /* There can be at most 3 int regs used as inputs in an insn, and we have
1168 7 to choose from (RAX ... RDI, sans RSP).
1169 This allows us to take a conservative approach and keep things simple.
1170 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1171 that implicitly specify RAX. */
1172
1173 /* Avoid RAX. */
1174 used_regs_mask |= 1 << EAX_REG_NUM;
1175 /* Similarily avoid RDX, implicit operand in divides. */
1176 used_regs_mask |= 1 << EDX_REG_NUM;
1177 /* Avoid RSP. */
1178 used_regs_mask |= 1 << ESP_REG_NUM;
1179
1180 /* If the opcode is one byte long and there's no ModRM byte,
1181 assume the opcode specifies a register. */
1182 if (details->opcode_len == 1 && details->modrm_offset == -1)
1183 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1184
1185 /* Mark used regs in the modrm/sib bytes. */
1186 if (details->modrm_offset != -1)
1187 {
1188 int modrm = details->raw_insn[details->modrm_offset];
1189 int mod = MODRM_MOD_FIELD (modrm);
1190 int reg = MODRM_REG_FIELD (modrm);
1191 int rm = MODRM_RM_FIELD (modrm);
1192 int have_sib = mod != 3 && rm == 4;
1193
1194 /* Assume the reg field of the modrm byte specifies a register. */
1195 used_regs_mask |= 1 << reg;
1196
1197 if (have_sib)
1198 {
1199 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
d48ebb5b 1200 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
35669430 1201 used_regs_mask |= 1 << base;
d48ebb5b 1202 used_regs_mask |= 1 << idx;
35669430
DE		 1203 }
1204 else
1205 {
1206 used_regs_mask |= 1 << rm;
1207 }
1208 }
1209
1210 gdb_assert (used_regs_mask < 256);
1211 gdb_assert (used_regs_mask != 255);
1212
1213 /* Finally, find a free reg. */
1214 {
1215 int i;
1216
1217 for (i = 0; i < 8; ++i)
1218 {
1219 if (! (used_regs_mask & (1 << i)))
1220 return i;
1221 }
1222
1223 /* We shouldn't get here. */
1224 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1225 }
1226}
1227
1228/* Extract the details of INSN that we need. */
1229
1230static void
1231amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1232{
1233 gdb_byte *start = insn;
1234 int need_modrm;
1235
1236 details->raw_insn = insn;
1237
1238 details->opcode_len = -1;
1239 details->rex_offset = -1;
1240 details->opcode_offset = -1;
1241 details->modrm_offset = -1;
1242
1243 /* Skip legacy instruction prefixes. */
1903f0e6 1244 insn = amd64_skip_prefixes (insn);
35669430
DE		 1245
1246 /* Skip REX instruction prefix. */
1247 if (rex_prefix_p (*insn))
1248 {
1249 details->rex_offset = insn - start;
1250 ++insn;
1251 }
1252
1253 details->opcode_offset = insn - start;
1254
1255 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1256 {
1257 /* Two or three-byte opcode. */
1258 ++insn;
1259 need_modrm = twobyte_has_modrm[*insn];
1260
1261 /* Check for three-byte opcode. */
1903f0e6 1262 switch (*insn)
35669430 1263 {
1903f0e6
DE		 1264 case 0x24:
1265 case 0x25:
1266 case 0x38:
1267 case 0x3a:
1268 case 0x7a:
1269 case 0x7b:
35669430
DE		 1270 ++insn;
1271 details->opcode_len = 3;
1903f0e6
DE		 1272 break;
1273 default:
1274 details->opcode_len = 2;
1275 break;
35669430 1276 }
35669430
DE		 1277 }
1278 else
1279 {
1280 /* One-byte opcode. */
1281 need_modrm = onebyte_has_modrm[*insn];
1282 details->opcode_len = 1;
1283 }
1284
1285 if (need_modrm)
1286 {
1287 ++insn;
1288 details->modrm_offset = insn - start;
1289 }
1290}
1291
1292/* Update %rip-relative addressing in INSN.
1293
1294 %rip-relative addressing only uses a 32-bit displacement.
1295 32 bits is not enough to be guaranteed to cover the distance between where
1296 the real instruction is and where its copy is.
1297 Convert the insn to use base+disp addressing.
1298 We set base = pc + insn_length so we can leave disp unchanged. */
c4f35dd8 1299
35669430
DE		 1300static void
1301fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1302 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1303{
e17a4113 1304 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
35669430
DE		 1305 const struct amd64_insn *insn_details = &dsc->insn_details;
1306 int modrm_offset = insn_details->modrm_offset;
1307 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1308 CORE_ADDR rip_base;
1309 int32_t disp;
1310 int insn_length;
1311 int arch_tmp_regno, tmp_regno;
1312 ULONGEST orig_value;
1313
1314 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1315 ++insn;
1316
1317 /* Compute the rip-relative address. */
e17a4113 1318 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
eda5a4d7
PA		 1319 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1320 dsc->max_len, from);
35669430
DE		 1321 rip_base = from + insn_length;
1322
1323 /* We need a register to hold the address.
1324 Pick one not used in the insn.
1325 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1326 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1327 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1328
1329 /* REX.B should be unset as we were using rip-relative addressing,
1330 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1331 if (insn_details->rex_offset != -1)
1332 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1333
1334 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1335 dsc->tmp_regno = tmp_regno;
1336 dsc->tmp_save = orig_value;
1337 dsc->tmp_used = 1;
1338
1339 /* Convert the ModRM field to be base+disp. */
1340 dsc->insn_buf[modrm_offset] &= ~0xc7;
1341 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1342
1343 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1344
1345 if (debug_displaced)
1346 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
5af949e3
UW		 1347 "displaced: using temp reg %d, old value %s, new value %s\n",
1348 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1349 paddress (gdbarch, rip_base));
35669430
DE		 1350}
1351
1352static void
1353fixup_displaced_copy (struct gdbarch *gdbarch,
1354 struct displaced_step_closure *dsc,
1355 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1356{
1357 const struct amd64_insn *details = &dsc->insn_details;
1358
1359 if (details->modrm_offset != -1)
1360 {
1361 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1362
1363 if ((modrm & 0xc7) == 0x05)
1364 {
1365 /* The insn uses rip-relative addressing.
1366 Deal with it. */
1367 fixup_riprel (gdbarch, dsc, from, to, regs);
1368 }
1369 }
1370}
1371
1372struct displaced_step_closure *
1373amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1374 CORE_ADDR from, CORE_ADDR to,
1375 struct regcache *regs)
1376{
1377 int len = gdbarch_max_insn_length (gdbarch);
741e63d7 1378 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
35669430
DE		 1379 continually watch for running off the end of the buffer. */
1380 int fixup_sentinel_space = len;
224c3ddb
SM		 1381 struct displaced_step_closure *dsc
1382 = ((struct displaced_step_closure *)
1383 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space));
35669430
DE		 1384 gdb_byte *buf = &dsc->insn_buf[0];
1385 struct amd64_insn *details = &dsc->insn_details;
1386
1387 dsc->tmp_used = 0;
1388 dsc->max_len = len + fixup_sentinel_space;
1389
1390 read_memory (from, buf, len);
1391
1392 /* Set up the sentinel space so we don't have to worry about running
1393 off the end of the buffer. An excessive number of leading prefixes
1394 could otherwise cause this. */
1395 memset (buf + len, 0, fixup_sentinel_space);
1396
1397 amd64_get_insn_details (buf, details);
1398
1399 /* GDB may get control back after the insn after the syscall.
1400 Presumably this is a kernel bug.
1401 If this is a syscall, make sure there's a nop afterwards. */
1402 {
1403 int syscall_length;
1404
1405 if (amd64_syscall_p (details, &syscall_length))
1406 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1407 }
1408
1409 /* Modify the insn to cope with the address where it will be executed from.
1410 In particular, handle any rip-relative addressing. */
1411 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1412
1413 write_memory (to, buf, len);
1414
1415 if (debug_displaced)
1416 {
5af949e3
UW		 1417 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1418 paddress (gdbarch, from), paddress (gdbarch, to));
35669430
DE		 1419 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1420 }
1421
1422 return dsc;
1423}
1424
1425static int
1426amd64_absolute_jmp_p (const struct amd64_insn *details)
1427{
1428 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1429
1430 if (insn[0] == 0xff)
1431 {
1432 /* jump near, absolute indirect (/4) */
1433 if ((insn[1] & 0x38) == 0x20)
1434 return 1;
1435
1436 /* jump far, absolute indirect (/5) */
1437 if ((insn[1] & 0x38) == 0x28)
1438 return 1;
1439 }
1440
1441 return 0;
1442}
1443
c2170eef
MM		 1444/* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1445
1446static int
1447amd64_jmp_p (const struct amd64_insn *details)
1448{
1449 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1450
1451 /* jump short, relative. */
1452 if (insn[0] == 0xeb)
1453 return 1;
1454
1455 /* jump near, relative. */
1456 if (insn[0] == 0xe9)
1457 return 1;
1458
1459 return amd64_absolute_jmp_p (details);
1460}
1461
35669430
DE		 1462static int
1463amd64_absolute_call_p (const struct amd64_insn *details)
1464{
1465 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1466
1467 if (insn[0] == 0xff)
1468 {
1469 /* Call near, absolute indirect (/2) */
1470 if ((insn[1] & 0x38) == 0x10)
1471 return 1;
1472
1473 /* Call far, absolute indirect (/3) */
1474 if ((insn[1] & 0x38) == 0x18)
1475 return 1;
1476 }
1477
1478 return 0;
1479}
1480
1481static int
1482amd64_ret_p (const struct amd64_insn *details)
1483{
1484 /* NOTE: gcc can emit "repz ; ret". */
1485 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1486
1487 switch (insn[0])
1488 {
1489 case 0xc2: /* ret near, pop N bytes */
1490 case 0xc3: /* ret near */
1491 case 0xca: /* ret far, pop N bytes */
1492 case 0xcb: /* ret far */
1493 case 0xcf: /* iret */
1494 return 1;
1495
1496 default:
1497 return 0;
1498 }
1499}
1500
1501static int
1502amd64_call_p (const struct amd64_insn *details)
1503{
1504 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1505
1506 if (amd64_absolute_call_p (details))
1507 return 1;
1508
1509 /* call near, relative */
1510 if (insn[0] == 0xe8)
1511 return 1;
1512
1513 return 0;
1514}
1515
35669430
DE		 1516/* Return non-zero if INSN is a system call, and set *LENGTHP to its
1517 length in bytes. Otherwise, return zero. */
1518
1519static int
1520amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1521{
1522 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1523
1524 if (insn[0] == 0x0f && insn[1] == 0x05)
1525 {
1526 *lengthp = 2;
1527 return 1;
1528 }
1529
1530 return 0;
1531}
1532
c2170eef
MM		 1533/* Classify the instruction at ADDR using PRED.
1534 Throw an error if the memory can't be read. */
1535
1536static int
1537amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1538 int (*pred) (const struct amd64_insn *))
1539{
1540 struct amd64_insn details;
1541 gdb_byte *buf;
1542 int len, classification;
1543
1544 len = gdbarch_max_insn_length (gdbarch);
224c3ddb 1545 buf = (gdb_byte *) alloca (len);
c2170eef
MM		 1546
1547 read_code (addr, buf, len);
1548 amd64_get_insn_details (buf, &details);
1549
1550 classification = pred (&details);
1551
1552 return classification;
1553}
1554
1555/* The gdbarch insn_is_call method. */
1556
1557static int
1558amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1559{
1560 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1561}
1562
1563/* The gdbarch insn_is_ret method. */
1564
1565static int
1566amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1567{
1568 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1569}
1570
1571/* The gdbarch insn_is_jump method. */
1572
1573static int
1574amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1575{
1576 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1577}
1578
35669430
DE		 1579/* Fix up the state of registers and memory after having single-stepped
1580 a displaced instruction. */
1581
1582void
1583amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1584 struct displaced_step_closure *dsc,
1585 CORE_ADDR from, CORE_ADDR to,
1586 struct regcache *regs)
1587{
e17a4113 1588 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
35669430
DE		 1589 /* The offset we applied to the instruction's address. */
1590 ULONGEST insn_offset = to - from;
1591 gdb_byte *insn = dsc->insn_buf;
1592 const struct amd64_insn *insn_details = &dsc->insn_details;
1593
1594 if (debug_displaced)
1595 fprintf_unfiltered (gdb_stdlog,
5af949e3 1596 "displaced: fixup (%s, %s), "
35669430 1597 "insn = 0x%02x 0x%02x ...\n",
5af949e3
UW		 1598 paddress (gdbarch, from), paddress (gdbarch, to),
1599 insn[0], insn[1]);
35669430
DE		 1600
1601 /* If we used a tmp reg, restore it. */
1602
1603 if (dsc->tmp_used)
1604 {
1605 if (debug_displaced)
5af949e3
UW		 1606 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1607 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
35669430
DE		 1608 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1609 }
1610
1611 /* The list of issues to contend with here is taken from
1612 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1613 Yay for Free Software! */
1614
1615 /* Relocate the %rip back to the program's instruction stream,
1616 if necessary. */
1617
1618 /* Except in the case of absolute or indirect jump or call
1619 instructions, or a return instruction, the new rip is relative to
1620 the displaced instruction; make it relative to the original insn.
1621 Well, signal handler returns don't need relocation either, but we use the
1622 value of %rip to recognize those; see below. */
1623 if (! amd64_absolute_jmp_p (insn_details)
1624 && ! amd64_absolute_call_p (insn_details)
1625 && ! amd64_ret_p (insn_details))
1626 {
1627 ULONGEST orig_rip;
1628 int insn_len;
1629
1630 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1631
1632 /* A signal trampoline system call changes the %rip, resuming
1633 execution of the main program after the signal handler has
1634 returned. That makes them like 'return' instructions; we
1635 shouldn't relocate %rip.
1636
1637 But most system calls don't, and we do need to relocate %rip.
1638
1639 Our heuristic for distinguishing these cases: if stepping
1640 over the system call instruction left control directly after
1641 the instruction, the we relocate --- control almost certainly
1642 doesn't belong in the displaced copy. Otherwise, we assume
1643 the instruction has put control where it belongs, and leave
1644 it unrelocated. Goodness help us if there are PC-relative
1645 system calls. */
1646 if (amd64_syscall_p (insn_details, &insn_len)
1647 && orig_rip != to + insn_len
1648 /* GDB can get control back after the insn after the syscall.
1649 Presumably this is a kernel bug.
1650 Fixup ensures its a nop, we add one to the length for it. */
1651 && orig_rip != to + insn_len + 1)
1652 {
1653 if (debug_displaced)
1654 fprintf_unfiltered (gdb_stdlog,
1655 "displaced: syscall changed %%rip; "
1656 "not relocating\n");
1657 }
1658 else
1659 {
1660 ULONGEST rip = orig_rip - insn_offset;
1661
1903f0e6
DE		 1662 /* If we just stepped over a breakpoint insn, we don't backup
1663 the pc on purpose; this is to match behaviour without
1664 stepping. */
35669430
DE		 1665
1666 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1667
1668 if (debug_displaced)
1669 fprintf_unfiltered (gdb_stdlog,
1670 "displaced: "
5af949e3
UW		 1671 "relocated %%rip from %s to %s\n",
1672 paddress (gdbarch, orig_rip),
1673 paddress (gdbarch, rip));
35669430
DE		 1674 }
1675 }
1676
1677 /* If the instruction was PUSHFL, then the TF bit will be set in the
1678 pushed value, and should be cleared. We'll leave this for later,
1679 since GDB already messes up the TF flag when stepping over a
1680 pushfl. */
1681
1682 /* If the instruction was a call, the return address now atop the
1683 stack is the address following the copied instruction. We need
1684 to make it the address following the original instruction. */
1685 if (amd64_call_p (insn_details))
1686 {
1687 ULONGEST rsp;
1688 ULONGEST retaddr;
1689 const ULONGEST retaddr_len = 8;
1690
1691 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
e17a4113 1692 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
4dafcdeb 1693 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
e17a4113 1694 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
35669430
DE		 1695
1696 if (debug_displaced)
1697 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1698 "displaced: relocated return addr at %s "
1699 "to %s\n",
1700 paddress (gdbarch, rsp),
1701 paddress (gdbarch, retaddr));
35669430
DE		 1702 }
1703}
dde08ee1
PA		 1704
1705/* If the instruction INSN uses RIP-relative addressing, return the
1706 offset into the raw INSN where the displacement to be adjusted is
1707 found. Returns 0 if the instruction doesn't use RIP-relative
1708 addressing. */
1709
1710static int
1711rip_relative_offset (struct amd64_insn *insn)
1712{
1713 if (insn->modrm_offset != -1)
1714 {
1715 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1716
1717 if ((modrm & 0xc7) == 0x05)
1718 {
1719 /* The displacement is found right after the ModRM byte. */
1720 return insn->modrm_offset + 1;
1721 }
1722 }
1723
1724 return 0;
1725}
1726
1727static void
1728append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1729{
1730 target_write_memory (*to, buf, len);
1731 *to += len;
1732}
1733
60965737 1734static void
dde08ee1
PA		 1735amd64_relocate_instruction (struct gdbarch *gdbarch,
1736 CORE_ADDR *to, CORE_ADDR oldloc)
1737{
1738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1739 int len = gdbarch_max_insn_length (gdbarch);
1740 /* Extra space for sentinels. */
1741 int fixup_sentinel_space = len;
224c3ddb 1742 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
dde08ee1
PA		 1743 struct amd64_insn insn_details;
1744 int offset = 0;
1745 LONGEST rel32, newrel;
1746 gdb_byte *insn;
1747 int insn_length;
1748
1749 read_memory (oldloc, buf, len);
1750
1751 /* Set up the sentinel space so we don't have to worry about running
1752 off the end of the buffer. An excessive number of leading prefixes
1753 could otherwise cause this. */
1754 memset (buf + len, 0, fixup_sentinel_space);
1755
1756 insn = buf;
1757 amd64_get_insn_details (insn, &insn_details);
1758
1759 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1760
1761 /* Skip legacy instruction prefixes. */
1762 insn = amd64_skip_prefixes (insn);
1763
1764 /* Adjust calls with 32-bit relative addresses as push/jump, with
1765 the address pushed being the location where the original call in
1766 the user program would return to. */
1767 if (insn[0] == 0xe8)
1768 {
1769 gdb_byte push_buf[16];
1770 unsigned int ret_addr;
1771
1772 /* Where "ret" in the original code will return to. */
1773 ret_addr = oldloc + insn_length;
0963b4bd 1774 push_buf[0] = 0x68; /* pushq $... */
144db827 1775 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
dde08ee1
PA		 1776 /* Push the push. */
1777 append_insns (to, 5, push_buf);
1778
1779 /* Convert the relative call to a relative jump. */
1780 insn[0] = 0xe9;
1781
1782 /* Adjust the destination offset. */
1783 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1784 newrel = (oldloc - *to) + rel32;
f4a1794a
KY		 1785 store_signed_integer (insn + 1, 4, byte_order, newrel);
1786
1787 if (debug_displaced)
1788 fprintf_unfiltered (gdb_stdlog,
1789 "Adjusted insn rel32=%s at %s to"
1790 " rel32=%s at %s\n",
1791 hex_string (rel32), paddress (gdbarch, oldloc),
1792 hex_string (newrel), paddress (gdbarch, *to));
dde08ee1
PA		 1793
1794 /* Write the adjusted jump into its displaced location. */
1795 append_insns (to, 5, insn);
1796 return;
1797 }
1798
1799 offset = rip_relative_offset (&insn_details);
1800 if (!offset)
1801 {
1802 /* Adjust jumps with 32-bit relative addresses. Calls are
1803 already handled above. */
1804 if (insn[0] == 0xe9)
1805 offset = 1;
1806 /* Adjust conditional jumps. */
1807 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1808 offset = 2;
1809 }
1810
1811 if (offset)
1812 {
1813 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1814 newrel = (oldloc - *to) + rel32;
f4a1794a 1815 store_signed_integer (insn + offset, 4, byte_order, newrel);
dde08ee1
PA		 1816 if (debug_displaced)
1817 fprintf_unfiltered (gdb_stdlog,
f4a1794a
KY		 1818 "Adjusted insn rel32=%s at %s to"
1819 " rel32=%s at %s\n",
dde08ee1
PA		 1820 hex_string (rel32), paddress (gdbarch, oldloc),
1821 hex_string (newrel), paddress (gdbarch, *to));
1822 }
1823
1824 /* Write the adjusted instruction into its displaced location. */
1825 append_insns (to, insn_length, buf);
1826}
1827
35669430 1828\f
c4f35dd8 1829/* The maximum number of saved registers. This should include %rip. */
90f90721 1830#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
c4f35dd8 1831
e53bef9f 1832struct amd64_frame_cache
c4f35dd8
MK		 1833{
1834 /* Base address. */
1835 CORE_ADDR base;
8fbca658 1836 int base_p;
c4f35dd8
MK		 1837 CORE_ADDR sp_offset;
1838 CORE_ADDR pc;
1839
1840 /* Saved registers. */
e53bef9f 1841 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
c4f35dd8 1842 CORE_ADDR saved_sp;
e0c62198 1843 int saved_sp_reg;
c4f35dd8
MK		 1844
1845 /* Do we have a frame? */
1846 int frameless_p;
1847};
8dda9770 1848
d2449ee8 1849/* Initialize a frame cache. */
c4f35dd8 1850
d2449ee8
DJ		 1851static void
1852amd64_init_frame_cache (struct amd64_frame_cache *cache)
8dda9770 1853{
c4f35dd8
MK		 1854 int i;
1855
c4f35dd8
MK		 1856 /* Base address. */
1857 cache->base = 0;
8fbca658 1858 cache->base_p = 0;
c4f35dd8
MK		 1859 cache->sp_offset = -8;
1860 cache->pc = 0;
1861
1862 /* Saved registers. We initialize these to -1 since zero is a valid
bba66b87
DE		 1863 offset (that's where %rbp is supposed to be stored).
1864 The values start out as being offsets, and are later converted to
1865 addresses (at which point -1 is interpreted as an address, still meaning
1866 "invalid"). */
e53bef9f 1867 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 1868 cache->saved_regs[i] = -1;
1869 cache->saved_sp = 0;
e0c62198 1870 cache->saved_sp_reg = -1;
c4f35dd8
MK		 1871
1872 /* Frameless until proven otherwise. */
1873 cache->frameless_p = 1;
d2449ee8 1874}
c4f35dd8 1875
d2449ee8
DJ		 1876/* Allocate and initialize a frame cache. */
1877
1878static struct amd64_frame_cache *
1879amd64_alloc_frame_cache (void)
1880{
1881 struct amd64_frame_cache *cache;
1882
1883 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1884 amd64_init_frame_cache (cache);
c4f35dd8 1885 return cache;
8dda9770 1886}
53e95fcf 1887
e0c62198
L		 1888/* GCC 4.4 and later, can put code in the prologue to realign the
1889 stack pointer. Check whether PC points to such code, and update
1890 CACHE accordingly. Return the first instruction after the code
1891 sequence or CURRENT_PC, whichever is smaller. If we don't
1892 recognize the code, return PC. */
1893
1894static CORE_ADDR
1895amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1896 struct amd64_frame_cache *cache)
1897{
1898 /* There are 2 code sequences to re-align stack before the frame
1899 gets set up:
1900
1901 1. Use a caller-saved saved register:
1902
1903 leaq 8(%rsp), %reg
1904 andq $-XXX, %rsp
1905 pushq -8(%reg)
1906
1907 2. Use a callee-saved saved register:
1908
1909 pushq %reg
1910 leaq 16(%rsp), %reg
1911 andq $-XXX, %rsp
1912 pushq -8(%reg)
1913
1914 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1915
1916 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1917 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1918 */
1919
1920 gdb_byte buf[18];
1921 int reg, r;
1922 int offset, offset_and;
e0c62198 1923
bae8a07a 1924 if (target_read_code (pc, buf, sizeof buf))
e0c62198
L		 1925 return pc;
1926
1927 /* Check caller-saved saved register. The first instruction has
1928 to be "leaq 8(%rsp), %reg". */
1929 if ((buf[0] & 0xfb) == 0x48
1930 && buf[1] == 0x8d
1931 && buf[3] == 0x24
1932 && buf[4] == 0x8)
1933 {
1934 /* MOD must be binary 10 and R/M must be binary 100. */
1935 if ((buf[2] & 0xc7) != 0x44)
1936 return pc;
1937
1938 /* REG has register number. */
1939 reg = (buf[2] >> 3) & 7;
1940
1941 /* Check the REX.R bit. */
1942 if (buf[0] == 0x4c)
1943 reg += 8;
1944
1945 offset = 5;
1946 }
1947 else
1948 {
1949 /* Check callee-saved saved register. The first instruction
1950 has to be "pushq %reg". */
1951 reg = 0;
1952 if ((buf[0] & 0xf8) == 0x50)
1953 offset = 0;
1954 else if ((buf[0] & 0xf6) == 0x40
1955 && (buf[1] & 0xf8) == 0x50)
1956 {
1957 /* Check the REX.B bit. */
1958 if ((buf[0] & 1) != 0)
1959 reg = 8;
1960
1961 offset = 1;
1962 }
1963 else
1964 return pc;
1965
1966 /* Get register. */
1967 reg += buf[offset] & 0x7;
1968
1969 offset++;
1970
1971 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1972 if ((buf[offset] & 0xfb) != 0x48
1973 || buf[offset + 1] != 0x8d
1974 || buf[offset + 3] != 0x24
1975 || buf[offset + 4] != 0x10)
1976 return pc;
1977
1978 /* MOD must be binary 10 and R/M must be binary 100. */
1979 if ((buf[offset + 2] & 0xc7) != 0x44)
1980 return pc;
1981
1982 /* REG has register number. */
1983 r = (buf[offset + 2] >> 3) & 7;
1984
1985 /* Check the REX.R bit. */
1986 if (buf[offset] == 0x4c)
1987 r += 8;
1988
1989 /* Registers in pushq and leaq have to be the same. */
1990 if (reg != r)
1991 return pc;
1992
1993 offset += 5;
1994 }
1995
1996 /* Rigister can't be %rsp nor %rbp. */
1997 if (reg == 4 || reg == 5)
1998 return pc;
1999
2000 /* The next instruction has to be "andq $-XXX, %rsp". */
2001 if (buf[offset] != 0x48
2002 || buf[offset + 2] != 0xe4
2003 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2004 return pc;
2005
2006 offset_and = offset;
2007 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2008
2009 /* The next instruction has to be "pushq -8(%reg)". */
2010 r = 0;
2011 if (buf[offset] == 0xff)
2012 offset++;
2013 else if ((buf[offset] & 0xf6) == 0x40
2014 && buf[offset + 1] == 0xff)
2015 {
2016 /* Check the REX.B bit. */
2017 if ((buf[offset] & 0x1) != 0)
2018 r = 8;
2019 offset += 2;
2020 }
2021 else
2022 return pc;
2023
2024 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2025 01. */
2026 if (buf[offset + 1] != 0xf8
2027 || (buf[offset] & 0xf8) != 0x70)
2028 return pc;
2029
2030 /* R/M has register. */
2031 r += buf[offset] & 7;
2032
2033 /* Registers in leaq and pushq have to be the same. */
2034 if (reg != r)
2035 return pc;
2036
2037 if (current_pc > pc + offset_and)
35669430 2038 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
e0c62198
L		 2039
2040 return min (pc + offset + 2, current_pc);
2041}
2042
ac142d96
L		 2043/* Similar to amd64_analyze_stack_align for x32. */
2044
2045static CORE_ADDR
2046amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2047 struct amd64_frame_cache *cache)
2048{
2049 /* There are 2 code sequences to re-align stack before the frame
2050 gets set up:
2051
2052 1. Use a caller-saved saved register:
2053
2054 leaq 8(%rsp), %reg
2055 andq $-XXX, %rsp
2056 pushq -8(%reg)
2057
2058 or
2059
2060 [addr32] leal 8(%rsp), %reg
2061 andl $-XXX, %esp
2062 [addr32] pushq -8(%reg)
2063
2064 2. Use a callee-saved saved register:
2065
2066 pushq %reg
2067 leaq 16(%rsp), %reg
2068 andq $-XXX, %rsp
2069 pushq -8(%reg)
2070
2071 or
2072
2073 pushq %reg
2074 [addr32] leal 16(%rsp), %reg
2075 andl $-XXX, %esp
2076 [addr32] pushq -8(%reg)
2077
2078 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2079
2080 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2081 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2082
2083 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2084
2085 0x83 0xe4 0xf0 andl $-16, %esp
2086 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2087 */
2088
2089 gdb_byte buf[19];
2090 int reg, r;
2091 int offset, offset_and;
2092
2093 if (target_read_memory (pc, buf, sizeof buf))
2094 return pc;
2095
2096 /* Skip optional addr32 prefix. */
2097 offset = buf[0] == 0x67 ? 1 : 0;
2098
2099 /* Check caller-saved saved register. The first instruction has
2100 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2101 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2102 && buf[offset + 1] == 0x8d
2103 && buf[offset + 3] == 0x24
2104 && buf[offset + 4] == 0x8)
2105 {
2106 /* MOD must be binary 10 and R/M must be binary 100. */
2107 if ((buf[offset + 2] & 0xc7) != 0x44)
2108 return pc;
2109
2110 /* REG has register number. */
2111 reg = (buf[offset + 2] >> 3) & 7;
2112
2113 /* Check the REX.R bit. */
2114 if ((buf[offset] & 0x4) != 0)
2115 reg += 8;
2116
2117 offset += 5;
2118 }
2119 else
2120 {
2121 /* Check callee-saved saved register. The first instruction
2122 has to be "pushq %reg". */
2123 reg = 0;
2124 if ((buf[offset] & 0xf6) == 0x40
2125 && (buf[offset + 1] & 0xf8) == 0x50)
2126 {
2127 /* Check the REX.B bit. */
2128 if ((buf[offset] & 1) != 0)
2129 reg = 8;
2130
2131 offset += 1;
2132 }
2133 else if ((buf[offset] & 0xf8) != 0x50)
2134 return pc;
2135
2136 /* Get register. */
2137 reg += buf[offset] & 0x7;
2138
2139 offset++;
2140
2141 /* Skip optional addr32 prefix. */
2142 if (buf[offset] == 0x67)
2143 offset++;
2144
2145 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2146 "leal 16(%rsp), %reg". */
2147 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2148 || buf[offset + 1] != 0x8d
2149 || buf[offset + 3] != 0x24
2150 || buf[offset + 4] != 0x10)
2151 return pc;
2152
2153 /* MOD must be binary 10 and R/M must be binary 100. */
2154 if ((buf[offset + 2] & 0xc7) != 0x44)
2155 return pc;
2156
2157 /* REG has register number. */
2158 r = (buf[offset + 2] >> 3) & 7;
2159
2160 /* Check the REX.R bit. */
2161 if ((buf[offset] & 0x4) != 0)
2162 r += 8;
2163
2164 /* Registers in pushq and leaq have to be the same. */
2165 if (reg != r)
2166 return pc;
2167
2168 offset += 5;
2169 }
2170
2171 /* Rigister can't be %rsp nor %rbp. */
2172 if (reg == 4 || reg == 5)
2173 return pc;
2174
2175 /* The next instruction may be "andq $-XXX, %rsp" or
2176 "andl $-XXX, %esp". */
2177 if (buf[offset] != 0x48)
2178 offset--;
2179
2180 if (buf[offset + 2] != 0xe4
2181 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2182 return pc;
2183
2184 offset_and = offset;
2185 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2186
2187 /* Skip optional addr32 prefix. */
2188 if (buf[offset] == 0x67)
2189 offset++;
2190
2191 /* The next instruction has to be "pushq -8(%reg)". */
2192 r = 0;
2193 if (buf[offset] == 0xff)
2194 offset++;
2195 else if ((buf[offset] & 0xf6) == 0x40
2196 && buf[offset + 1] == 0xff)
2197 {
2198 /* Check the REX.B bit. */
2199 if ((buf[offset] & 0x1) != 0)
2200 r = 8;
2201 offset += 2;
2202 }
2203 else
2204 return pc;
2205
2206 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2207 01. */
2208 if (buf[offset + 1] != 0xf8
2209 || (buf[offset] & 0xf8) != 0x70)
2210 return pc;
2211
2212 /* R/M has register. */
2213 r += buf[offset] & 7;
2214
2215 /* Registers in leaq and pushq have to be the same. */
2216 if (reg != r)
2217 return pc;
2218
2219 if (current_pc > pc + offset_and)
2220 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2221
2222 return min (pc + offset + 2, current_pc);
2223}
2224
c4f35dd8
MK		 2225/* Do a limited analysis of the prologue at PC and update CACHE
2226 accordingly. Bail out early if CURRENT_PC is reached. Return the
2227 address where the analysis stopped.
2228
2229 We will handle only functions beginning with:
2230
2231 pushq %rbp 0x55
50f1ae7b 2232 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
c4f35dd8 2233
649e6d92
MK		 2234 or (for the X32 ABI):
2235
2236 pushq %rbp 0x55
2237 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2238
2239 Any function that doesn't start with one of these sequences will be
2240 assumed to have no prologue and thus no valid frame pointer in
2241 %rbp. */
c4f35dd8
MK		 2242
2243static CORE_ADDR
e17a4113
UW		 2244amd64_analyze_prologue (struct gdbarch *gdbarch,
2245 CORE_ADDR pc, CORE_ADDR current_pc,
e53bef9f 2246 struct amd64_frame_cache *cache)
53e95fcf 2247{
e17a4113 2248 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
50f1ae7b
DE		 2249 /* There are two variations of movq %rsp, %rbp. */
2250 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2251 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
649e6d92
MK		 2252 /* Ditto for movl %esp, %ebp. */
2253 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2254 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2255
d8de1ef7
MK		 2256 gdb_byte buf[3];
2257 gdb_byte op;
c4f35dd8
MK		 2258
2259 if (current_pc <= pc)
2260 return current_pc;
2261
ac142d96
L		 2262 if (gdbarch_ptr_bit (gdbarch) == 32)
2263 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2264 else
2265 pc = amd64_analyze_stack_align (pc, current_pc, cache);
e0c62198 2266
bae8a07a 2267 op = read_code_unsigned_integer (pc, 1, byte_order);
c4f35dd8
MK		 2268
2269 if (op == 0x55) /* pushq %rbp */
2270 {
2271 /* Take into account that we've executed the `pushq %rbp' that
2272 starts this instruction sequence. */
90f90721 2273 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
c4f35dd8
MK		 2274 cache->sp_offset += 8;
2275
2276 /* If that's all, return now. */
2277 if (current_pc <= pc + 1)
2278 return current_pc;
2279
bae8a07a 2280 read_code (pc + 1, buf, 3);
c4f35dd8 2281
649e6d92
MK		 2282 /* Check for `movq %rsp, %rbp'. */
2283 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2284 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2285 {
2286 /* OK, we actually have a frame. */
2287 cache->frameless_p = 0;
2288 return pc + 4;
2289 }
2290
2291 /* For X32, also check for `movq %esp, %ebp'. */
2292 if (gdbarch_ptr_bit (gdbarch) == 32)
2293 {
2294 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2295 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2296 {
2297 /* OK, we actually have a frame. */
2298 cache->frameless_p = 0;
2299 return pc + 3;
2300 }
2301 }
2302
2303 return pc + 1;
c4f35dd8
MK		 2304 }
2305
2306 return pc;
53e95fcf
JS		 2307}
2308
df15bd07
JK		 2309/* Work around false termination of prologue - GCC PR debug/48827.
2310
2311 START_PC is the first instruction of a function, PC is its minimal already
2312 determined advanced address. Function returns PC if it has nothing to do.
2313
2314 84 c0 test %al,%al
2315 74 23 je after
2316 <-- here is 0 lines advance - the false prologue end marker.
2317 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2318 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2319 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2320 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2321 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2322 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2323 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2324 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2325 after: */
c4f35dd8
MK		 2326
2327static CORE_ADDR
df15bd07 2328amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
53e95fcf 2329{
08711b9a
JK		 2330 struct symtab_and_line start_pc_sal, next_sal;
2331 gdb_byte buf[4 + 8 * 7];
2332 int offset, xmmreg;
c4f35dd8 2333
08711b9a
JK		 2334 if (pc == start_pc)
2335 return pc;
2336
2337 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2338 if (start_pc_sal.symtab == NULL
43f3e411
DE		 2339 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2340 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
08711b9a
JK		 2341 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2342 return pc;
2343
2344 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2345 if (next_sal.line != start_pc_sal.line)
2346 return pc;
2347
2348 /* START_PC can be from overlayed memory, ignored here. */
bae8a07a 2349 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
08711b9a
JK		 2350 return pc;
2351
2352 /* test %al,%al */
2353 if (buf[0] != 0x84 || buf[1] != 0xc0)
2354 return pc;
2355 /* je AFTER */
2356 if (buf[2] != 0x74)
2357 return pc;
2358
2359 offset = 4;
2360 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2361 {
bede5f5f 2362 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
08711b9a 2363 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
bede5f5f 2364 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
08711b9a
JK		 2365 return pc;
2366
bede5f5f
JK		 2367 /* 0b01?????? */
2368 if ((buf[offset + 2] & 0xc0) == 0x40)
08711b9a
JK		 2369 {
2370 /* 8-bit displacement. */
2371 offset += 4;
2372 }
bede5f5f
JK		 2373 /* 0b10?????? */
2374 else if ((buf[offset + 2] & 0xc0) == 0x80)
08711b9a
JK		 2375 {
2376 /* 32-bit displacement. */
2377 offset += 7;
2378 }
2379 else
2380 return pc;
2381 }
2382
2383 /* je AFTER */
2384 if (offset - 4 != buf[3])
2385 return pc;
2386
2387 return next_sal.end;
53e95fcf 2388}
df15bd07
JK		 2389
2390/* Return PC of first real instruction. */
2391
2392static CORE_ADDR
2393amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2394{
2395 struct amd64_frame_cache cache;
2396 CORE_ADDR pc;
56bf0743
KB		 2397 CORE_ADDR func_addr;
2398
2399 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2400 {
2401 CORE_ADDR post_prologue_pc
2402 = skip_prologue_using_sal (gdbarch, func_addr);
43f3e411 2403 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
56bf0743
KB		 2404
2405 /* Clang always emits a line note before the prologue and another
2406 one after. We trust clang to emit usable line notes. */
2407 if (post_prologue_pc
43f3e411
DE		 2408 && (cust != NULL
2409 && COMPUNIT_PRODUCER (cust) != NULL
61012eef 2410 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
56bf0743
KB		 2411 return max (start_pc, post_prologue_pc);
2412 }
df15bd07
JK		 2413
2414 amd64_init_frame_cache (&cache);
2415 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2416 &cache);
2417 if (cache.frameless_p)
2418 return start_pc;
2419
2420 return amd64_skip_xmm_prologue (pc, start_pc);
2421}
c4f35dd8 2422\f
53e95fcf 2423
c4f35dd8
MK		 2424/* Normal frames. */
2425
8fbca658
PA		 2426static void
2427amd64_frame_cache_1 (struct frame_info *this_frame,
2428 struct amd64_frame_cache *cache)
6d686a84 2429{
e17a4113
UW		 2430 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2431 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 2432 gdb_byte buf[8];
6d686a84 2433 int i;
6d686a84 2434
10458914 2435 cache->pc = get_frame_func (this_frame);
c4f35dd8 2436 if (cache->pc != 0)
e17a4113
UW		 2437 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2438 cache);
c4f35dd8
MK		 2439
2440 if (cache->frameless_p)
2441 {
4a28816e
MK		 2442 /* We didn't find a valid frame. If we're at the start of a
2443 function, or somewhere half-way its prologue, the function's
2444 frame probably hasn't been fully setup yet. Try to
2445 reconstruct the base address for the stack frame by looking
2446 at the stack pointer. For truly "frameless" functions this
2447 might work too. */
c4f35dd8 2448
e0c62198
L		 2449 if (cache->saved_sp_reg != -1)
2450 {
8fbca658
PA		 2451 /* Stack pointer has been saved. */
2452 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2453 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2454
e0c62198
L		 2455 /* We're halfway aligning the stack. */
2456 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2457 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2458
2459 /* This will be added back below. */
2460 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2461 }
2462 else
2463 {
2464 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
e17a4113
UW		 2465 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2466 + cache->sp_offset;
e0c62198 2467 }
c4f35dd8 2468 }
35883a3f
MK		 2469 else
2470 {
10458914 2471 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
e17a4113 2472 cache->base = extract_unsigned_integer (buf, 8, byte_order);
35883a3f 2473 }
c4f35dd8
MK		 2474
2475 /* Now that we have the base address for the stack frame we can
2476 calculate the value of %rsp in the calling frame. */
2477 cache->saved_sp = cache->base + 16;
2478
35883a3f
MK		 2479 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2480 frame we find it at the same offset from the reconstructed base
e0c62198
L		 2481 address. If we're halfway aligning the stack, %rip is handled
2482 differently (see above). */
2483 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2484 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
35883a3f 2485
c4f35dd8
MK		 2486 /* Adjust all the saved registers such that they contain addresses
2487 instead of offsets. */
e53bef9f 2488 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 2489 if (cache->saved_regs[i] != -1)
2490 cache->saved_regs[i] += cache->base;
2491
8fbca658
PA		 2492 cache->base_p = 1;
2493}
2494
2495static struct amd64_frame_cache *
2496amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2497{
8fbca658
PA		 2498 struct amd64_frame_cache *cache;
2499
2500 if (*this_cache)
9a3c8263 2501 return (struct amd64_frame_cache *) *this_cache;
8fbca658
PA		 2502
2503 cache = amd64_alloc_frame_cache ();
2504 *this_cache = cache;
2505
492d29ea 2506 TRY
8fbca658
PA		 2507 {
2508 amd64_frame_cache_1 (this_frame, cache);
2509 }
492d29ea 2510 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2511 {
2512 if (ex.error != NOT_AVAILABLE_ERROR)
2513 throw_exception (ex);
2514 }
492d29ea 2515 END_CATCH
8fbca658 2516
c4f35dd8 2517 return cache;
6d686a84
ML		 2518}
2519
8fbca658
PA		 2520static enum unwind_stop_reason
2521amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2522 void **this_cache)
2523{
2524 struct amd64_frame_cache *cache =
2525 amd64_frame_cache (this_frame, this_cache);
2526
2527 if (!cache->base_p)
2528 return UNWIND_UNAVAILABLE;
2529
2530 /* This marks the outermost frame. */
2531 if (cache->base == 0)
2532 return UNWIND_OUTERMOST;
2533
2534 return UNWIND_NO_REASON;
2535}
2536
c4f35dd8 2537static void
10458914 2538amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
e53bef9f 2539 struct frame_id *this_id)
c4f35dd8 2540{
e53bef9f 2541 struct amd64_frame_cache *cache =
10458914 2542 amd64_frame_cache (this_frame, this_cache);
c4f35dd8 2543
8fbca658 2544 if (!cache->base_p)
5ce0145d
PA		 2545 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2546 else if (cache->base == 0)
2547 {
2548 /* This marks the outermost frame. */
2549 return;
2550 }
2551 else
2552 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
c4f35dd8 2553}
e76e1718 2554
10458914
DJ		 2555static struct value *
2556amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2557 int regnum)
53e95fcf 2558{
10458914 2559 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e53bef9f 2560 struct amd64_frame_cache *cache =
10458914 2561 amd64_frame_cache (this_frame, this_cache);
e76e1718 2562
c4f35dd8 2563 gdb_assert (regnum >= 0);
b1ab997b 2564
2ae02b47 2565 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
10458914 2566 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
e76e1718 2567
e53bef9f 2568 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
10458914
DJ		 2569 return frame_unwind_got_memory (this_frame, regnum,
2570 cache->saved_regs[regnum]);
e76e1718 2571
10458914 2572 return frame_unwind_got_register (this_frame, regnum, regnum);
c4f35dd8 2573}
e76e1718 2574
e53bef9f 2575static const struct frame_unwind amd64_frame_unwind =
c4f35dd8
MK		 2576{
2577 NORMAL_FRAME,
8fbca658 2578 amd64_frame_unwind_stop_reason,
e53bef9f 2579 amd64_frame_this_id,
10458914
DJ		 2580 amd64_frame_prev_register,
2581 NULL,
2582 default_frame_sniffer
c4f35dd8 2583};
c4f35dd8 2584\f
6710bf39
SS		 2585/* Generate a bytecode expression to get the value of the saved PC. */
2586
2587static void
2588amd64_gen_return_address (struct gdbarch *gdbarch,
2589 struct agent_expr *ax, struct axs_value *value,
2590 CORE_ADDR scope)
2591{
2592 /* The following sequence assumes the traditional use of the base
2593 register. */
2594 ax_reg (ax, AMD64_RBP_REGNUM);
2595 ax_const_l (ax, 8);
2596 ax_simple (ax, aop_add);
2597 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2598 value->kind = axs_lvalue_memory;
2599}
2600\f
e76e1718 2601
c4f35dd8
MK		 2602/* Signal trampolines. */
2603
2604/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2605 64-bit variants. This would require using identical frame caches
2606 on both platforms. */
2607
e53bef9f 2608static struct amd64_frame_cache *
10458914 2609amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2610{
e17a4113
UW		 2611 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2612 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2613 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e53bef9f 2614 struct amd64_frame_cache *cache;
c4f35dd8 2615 CORE_ADDR addr;
d8de1ef7 2616 gdb_byte buf[8];
2b5e0749 2617 int i;
c4f35dd8
MK		 2618
2619 if (*this_cache)
9a3c8263 2620 return (struct amd64_frame_cache *) *this_cache;
c4f35dd8 2621
e53bef9f 2622 cache = amd64_alloc_frame_cache ();
c4f35dd8 2623
492d29ea 2624 TRY
8fbca658
PA		 2625 {
2626 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2627 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2628
2629 addr = tdep->sigcontext_addr (this_frame);
2630 gdb_assert (tdep->sc_reg_offset);
2631 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2632 for (i = 0; i < tdep->sc_num_regs; i++)
2633 if (tdep->sc_reg_offset[i] != -1)
2634 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8 2635
8fbca658
PA		 2636 cache->base_p = 1;
2637 }
492d29ea 2638 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2639 {
2640 if (ex.error != NOT_AVAILABLE_ERROR)
2641 throw_exception (ex);
2642 }
492d29ea 2643 END_CATCH
c4f35dd8
MK		 2644
2645 *this_cache = cache;
2646 return cache;
53e95fcf
JS		 2647}
2648
8fbca658
PA		 2649static enum unwind_stop_reason
2650amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2651 void **this_cache)
2652{
2653 struct amd64_frame_cache *cache =
2654 amd64_sigtramp_frame_cache (this_frame, this_cache);
2655
2656 if (!cache->base_p)
2657 return UNWIND_UNAVAILABLE;
2658
2659 return UNWIND_NO_REASON;
2660}
2661
c4f35dd8 2662static void
10458914 2663amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
e53bef9f 2664 void **this_cache, struct frame_id *this_id)
c4f35dd8 2665{
e53bef9f 2666 struct amd64_frame_cache *cache =
10458914 2667 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2668
8fbca658 2669 if (!cache->base_p)
5ce0145d
PA		 2670 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2671 else if (cache->base == 0)
2672 {
2673 /* This marks the outermost frame. */
2674 return;
2675 }
2676 else
2677 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
c4f35dd8
MK		 2678}
2679
10458914
DJ		 2680static struct value *
2681amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2682 void **this_cache, int regnum)
c4f35dd8
MK		 2683{
2684 /* Make sure we've initialized the cache. */
10458914 2685 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2686
10458914 2687 return amd64_frame_prev_register (this_frame, this_cache, regnum);
c4f35dd8
MK		 2688}
2689
10458914
DJ		 2690static int
2691amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2692 struct frame_info *this_frame,
2693 void **this_cache)
c4f35dd8 2694{
10458914 2695 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
911bc6ee
MK		 2696
2697 /* We shouldn't even bother if we don't have a sigcontext_addr
2698 handler. */
2699 if (tdep->sigcontext_addr == NULL)
10458914 2700 return 0;
911bc6ee
MK		 2701
2702 if (tdep->sigtramp_p != NULL)
2703 {
10458914
DJ		 2704 if (tdep->sigtramp_p (this_frame))
2705 return 1;
911bc6ee 2706 }
c4f35dd8 2707
911bc6ee 2708 if (tdep->sigtramp_start != 0)
1c3545ae 2709 {
10458914 2710 CORE_ADDR pc = get_frame_pc (this_frame);
1c3545ae 2711
911bc6ee
MK		 2712 gdb_assert (tdep->sigtramp_end != 0);
2713 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
10458914 2714 return 1;
1c3545ae 2715 }
c4f35dd8 2716
10458914 2717 return 0;
c4f35dd8 2718}
10458914
DJ		 2719
2720static const struct frame_unwind amd64_sigtramp_frame_unwind =
2721{
2722 SIGTRAMP_FRAME,
8fbca658 2723 amd64_sigtramp_frame_unwind_stop_reason,
10458914
DJ		 2724 amd64_sigtramp_frame_this_id,
2725 amd64_sigtramp_frame_prev_register,
2726 NULL,
2727 amd64_sigtramp_frame_sniffer
2728};
c4f35dd8
MK		 2729\f
2730
2731static CORE_ADDR
10458914 2732amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2733{
e53bef9f 2734 struct amd64_frame_cache *cache =
10458914 2735 amd64_frame_cache (this_frame, this_cache);
c4f35dd8
MK		 2736
2737 return cache->base;
2738}
2739
e53bef9f 2740static const struct frame_base amd64_frame_base =
c4f35dd8 2741{
e53bef9f
MK		 2742 &amd64_frame_unwind,
2743 amd64_frame_base_address,
2744 amd64_frame_base_address,
2745 amd64_frame_base_address
c4f35dd8
MK		 2746};
2747
872761f4
MS		 2748/* Normal frames, but in a function epilogue. */
2749
c9cf6e20
MG		 2750/* Implement the stack_frame_destroyed_p gdbarch method.
2751
2752 The epilogue is defined here as the 'ret' instruction, which will
872761f4
MS		 2753 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2754 the function's stack frame. */
2755
2756static int
c9cf6e20 2757amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
872761f4
MS		 2758{
2759 gdb_byte insn;
43f3e411 2760 struct compunit_symtab *cust;
e0d00bc7 2761
43f3e411
DE		 2762 cust = find_pc_compunit_symtab (pc);
2763 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
e0d00bc7 2764 return 0;
872761f4
MS		 2765
2766 if (target_read_memory (pc, &insn, 1))
2767 return 0; /* Can't read memory at pc. */
2768
2769 if (insn != 0xc3) /* 'ret' instruction. */
2770 return 0;
2771
2772 return 1;
2773}
2774
2775static int
2776amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2777 struct frame_info *this_frame,
2778 void **this_prologue_cache)
2779{
2780 if (frame_relative_level (this_frame) == 0)
c9cf6e20
MG		 2781 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2782 get_frame_pc (this_frame));
872761f4
MS		 2783 else
2784 return 0;
2785}
2786
2787static struct amd64_frame_cache *
2788amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2789{
2790 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2791 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2792 struct amd64_frame_cache *cache;
6c10c06b 2793 gdb_byte buf[8];
872761f4
MS		 2794
2795 if (*this_cache)
9a3c8263 2796 return (struct amd64_frame_cache *) *this_cache;
872761f4
MS		 2797
2798 cache = amd64_alloc_frame_cache ();
2799 *this_cache = cache;
2800
492d29ea 2801 TRY
8fbca658
PA		 2802 {
2803 /* Cache base will be %esp plus cache->sp_offset (-8). */
2804 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2805 cache->base = extract_unsigned_integer (buf, 8,
2806 byte_order) + cache->sp_offset;
2807
2808 /* Cache pc will be the frame func. */
2809 cache->pc = get_frame_pc (this_frame);
872761f4 2810
8fbca658
PA		 2811 /* The saved %esp will be at cache->base plus 16. */
2812 cache->saved_sp = cache->base + 16;
872761f4 2813
8fbca658
PA		 2814 /* The saved %eip will be at cache->base plus 8. */
2815 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
872761f4 2816
8fbca658
PA		 2817 cache->base_p = 1;
2818 }
492d29ea 2819 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2820 {
2821 if (ex.error != NOT_AVAILABLE_ERROR)
2822 throw_exception (ex);
2823 }
492d29ea 2824 END_CATCH
872761f4
MS		 2825
2826 return cache;
2827}
2828
8fbca658
PA		 2829static enum unwind_stop_reason
2830amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2831 void **this_cache)
2832{
2833 struct amd64_frame_cache *cache
2834 = amd64_epilogue_frame_cache (this_frame, this_cache);
2835
2836 if (!cache->base_p)
2837 return UNWIND_UNAVAILABLE;
2838
2839 return UNWIND_NO_REASON;
2840}
2841
872761f4
MS		 2842static void
2843amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2844 void **this_cache,
2845 struct frame_id *this_id)
2846{
2847 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2848 this_cache);
2849
8fbca658 2850 if (!cache->base_p)
5ce0145d
PA		 2851 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2852 else
2853 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
872761f4
MS		 2854}
2855
2856static const struct frame_unwind amd64_epilogue_frame_unwind =
2857{
2858 NORMAL_FRAME,
8fbca658 2859 amd64_epilogue_frame_unwind_stop_reason,
872761f4
MS		 2860 amd64_epilogue_frame_this_id,
2861 amd64_frame_prev_register,
2862 NULL,
2863 amd64_epilogue_frame_sniffer
2864};
2865
166f4c7b 2866static struct frame_id
10458914 2867amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
166f4c7b 2868{
c4f35dd8
MK		 2869 CORE_ADDR fp;
2870
10458914 2871 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
c4f35dd8 2872
10458914 2873 return frame_id_build (fp + 16, get_frame_pc (this_frame));
166f4c7b
ML		 2874}
2875
8b148df9
AC		 2876/* 16 byte align the SP per frame requirements. */
2877
2878static CORE_ADDR
e53bef9f 2879amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
8b148df9
AC		 2880{
2881 return sp & -(CORE_ADDR)16;
2882}
473f17b0
MK		 2883\f
2884
593adc23
MK		 2885/* Supply register REGNUM from the buffer specified by FPREGS and LEN
2886 in the floating-point register set REGSET to register cache
2887 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
473f17b0
MK		 2888
2889static void
e53bef9f
MK		 2890amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2891 int regnum, const void *fpregs, size_t len)
473f17b0 2892{
09424cff
AA		 2893 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2894 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
473f17b0 2895
1528345d 2896 gdb_assert (len >= tdep->sizeof_fpregset);
90f90721 2897 amd64_supply_fxsave (regcache, regnum, fpregs);
473f17b0 2898}
8b148df9 2899
593adc23
MK		 2900/* Collect register REGNUM from the register cache REGCACHE and store
2901 it in the buffer specified by FPREGS and LEN as described by the
2902 floating-point register set REGSET. If REGNUM is -1, do this for
2903 all registers in REGSET. */
2904
2905static void
2906amd64_collect_fpregset (const struct regset *regset,
2907 const struct regcache *regcache,
2908 int regnum, void *fpregs, size_t len)
2909{
09424cff
AA		 2910 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2911 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
593adc23 2912
1528345d 2913 gdb_assert (len >= tdep->sizeof_fpregset);
593adc23
MK		 2914 amd64_collect_fxsave (regcache, regnum, fpregs);
2915}
2916
8f0435f7 2917const struct regset amd64_fpregset =
ecc37a5a
AA		 2918 {
2919 NULL, amd64_supply_fpregset, amd64_collect_fpregset
2920 };
c6b33596
MK		 2921\f
2922
436675d3
PA		 2923/* Figure out where the longjmp will land. Slurp the jmp_buf out of
2924 %rdi. We expect its value to be a pointer to the jmp_buf structure
2925 from which we extract the address that we will land at. This
2926 address is copied into PC. This routine returns non-zero on
2927 success. */
2928
2929static int
2930amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2931{
2932 gdb_byte buf[8];
2933 CORE_ADDR jb_addr;
2934 struct gdbarch *gdbarch = get_frame_arch (frame);
2935 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
0dfff4cb 2936 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 2937
2938 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2939 longjmp will land. */
2940 if (jb_pc_offset == -1)
2941 return 0;
2942
2943 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
0dfff4cb
UW		 2944 jb_addr= extract_typed_address
2945 (buf, builtin_type (gdbarch)->builtin_data_ptr);
436675d3
PA		 2946 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2947 return 0;
2948
0dfff4cb 2949 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 2950
2951 return 1;
2952}
2953
cf648174
HZ		 2954static const int amd64_record_regmap[] =
2955{
2956 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2957 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2958 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2959 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2960 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2961 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2962};
2963
2213a65d 2964void
90f90721 2965amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
53e95fcf 2966{
0c1a73d6 2967 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
90884b2b 2968 const struct target_desc *tdesc = info.target_desc;
05c0465e
SDJ		 2969 static const char *const stap_integer_prefixes[] = { "$", NULL };
2970 static const char *const stap_register_prefixes[] = { "%", NULL };
2971 static const char *const stap_register_indirection_prefixes[] = { "(",
2972 NULL };
2973 static const char *const stap_register_indirection_suffixes[] = { ")",
2974 NULL };
53e95fcf 2975
473f17b0
MK		 2976 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2977 floating-point registers. */
2978 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
8f0435f7 2979 tdep->fpregset = &amd64_fpregset;
473f17b0 2980
90884b2b
L		 2981 if (! tdesc_has_registers (tdesc))
2982 tdesc = tdesc_amd64;
2983 tdep->tdesc = tdesc;
2984
2985 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
2986 tdep->register_names = amd64_register_names;
2987
01f9f808
MS		 2988 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
2989 {
2990 tdep->zmmh_register_names = amd64_zmmh_names;
2991 tdep->k_register_names = amd64_k_names;
2992 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
2993 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
2994
2995 tdep->num_zmm_regs = 32;
2996 tdep->num_xmm_avx512_regs = 16;
2997 tdep->num_ymm_avx512_regs = 16;
2998
2999 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3000 tdep->k0_regnum = AMD64_K0_REGNUM;
3001 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3002 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3003 }
3004
a055a187
L		 3005 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3006 {
3007 tdep->ymmh_register_names = amd64_ymmh_names;
3008 tdep->num_ymm_regs = 16;
3009 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3010 }
3011
e43e105e
WT		 3012 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3013 {
3014 tdep->mpx_register_names = amd64_mpx_names;
3015 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3016 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3017 }
3018
fe01d668 3019 tdep->num_byte_regs = 20;
1ba53b71
L		 3020 tdep->num_word_regs = 16;
3021 tdep->num_dword_regs = 16;
3022 /* Avoid wiring in the MMX registers for now. */
3023 tdep->num_mmx_regs = 0;
3024
3543a589
TT		 3025 set_gdbarch_pseudo_register_read_value (gdbarch,
3026 amd64_pseudo_register_read_value);
1ba53b71
L		 3027 set_gdbarch_pseudo_register_write (gdbarch,
3028 amd64_pseudo_register_write);
62e5fd57
MK		 3029 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3030 amd64_ax_pseudo_register_collect);
1ba53b71
L		 3031
3032 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3033
5716833c 3034 /* AMD64 has an FPU and 16 SSE registers. */
90f90721 3035 tdep->st0_regnum = AMD64_ST0_REGNUM;
0c1a73d6 3036 tdep->num_xmm_regs = 16;
53e95fcf 3037
0c1a73d6 3038 /* This is what all the fuss is about. */
53e95fcf
JS		 3039 set_gdbarch_long_bit (gdbarch, 64);
3040 set_gdbarch_long_long_bit (gdbarch, 64);
3041 set_gdbarch_ptr_bit (gdbarch, 64);
3042
e53bef9f
MK		 3043 /* In contrast to the i386, on AMD64 a `long double' actually takes
3044 up 128 bits, even though it's still based on the i387 extended
3045 floating-point format which has only 80 significant bits. */
b83b026c
MK		 3046 set_gdbarch_long_double_bit (gdbarch, 128);
3047
e53bef9f 3048 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
b83b026c
MK		 3049
3050 /* Register numbers of various important registers. */
90f90721
MK		 3051 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3052 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3053 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3054 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
b83b026c 3055
e53bef9f
MK		 3056 /* The "default" register numbering scheme for AMD64 is referred to
3057 as the "DWARF Register Number Mapping" in the System V psABI.
3058 The preferred debugging format for all known AMD64 targets is
3059 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3060 DWARF-1), but we provide the same mapping just in case. This
3061 mapping is also used for stabs, which GCC does support. */
3062 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
e53bef9f 3063 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
de220d0f 3064
c4f35dd8 3065 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
e53bef9f 3066 be in use on any of the supported AMD64 targets. */
53e95fcf 3067
c4f35dd8 3068 /* Call dummy code. */
e53bef9f
MK		 3069 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3070 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
8b148df9 3071 set_gdbarch_frame_red_zone_size (gdbarch, 128);
53e95fcf 3072
83acabca 3073 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
d532c08f
MK		 3074 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3075 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3076
efb1c01c 3077 set_gdbarch_return_value (gdbarch, amd64_return_value);
53e95fcf 3078
e53bef9f 3079 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
53e95fcf 3080
cf648174
HZ		 3081 tdep->record_regmap = amd64_record_regmap;
3082
10458914 3083 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
53e95fcf 3084
872761f4
MS		 3085 /* Hook the function epilogue frame unwinder. This unwinder is
3086 appended to the list first, so that it supercedes the other
3087 unwinders in function epilogues. */
3088 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3089
3090 /* Hook the prologue-based frame unwinders. */
10458914
DJ		 3091 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3092 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
e53bef9f 3093 frame_base_set_default (gdbarch, &amd64_frame_base);
c6b33596 3094
436675d3 3095 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
dde08ee1
PA		 3096
3097 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
6710bf39
SS		 3098
3099 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
55aa24fb
SDJ		 3100
3101 /* SystemTap variables and functions. */
05c0465e
SDJ		 3102 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3103 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3104 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3105 stap_register_indirection_prefixes);
3106 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3107 stap_register_indirection_suffixes);
55aa24fb
SDJ		 3108 set_gdbarch_stap_is_single_operand (gdbarch,
3109 i386_stap_is_single_operand);
3110 set_gdbarch_stap_parse_special_token (gdbarch,
3111 i386_stap_parse_special_token);
c2170eef
MM		 3112 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3113 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3114 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
c4f35dd8 3115}
fff4548b
MK		 3116\f
3117
3118static struct type *
3119amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3120{
3121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3122
3123 switch (regnum - tdep->eax_regnum)
3124 {
3125 case AMD64_RBP_REGNUM: /* %ebp */
3126 case AMD64_RSP_REGNUM: /* %esp */
3127 return builtin_type (gdbarch)->builtin_data_ptr;
3128 case AMD64_RIP_REGNUM: /* %eip */
3129 return builtin_type (gdbarch)->builtin_func_ptr;
3130 }
3131
3132 return i386_pseudo_register_type (gdbarch, regnum);
3133}
3134
3135void
3136amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3137{
3138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3139 const struct target_desc *tdesc = info.target_desc;
3140
3141 amd64_init_abi (info, gdbarch);
3142
3143 if (! tdesc_has_registers (tdesc))
3144 tdesc = tdesc_x32;
3145 tdep->tdesc = tdesc;
3146
3147 tdep->num_dword_regs = 17;
3148 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3149
3150 set_gdbarch_long_bit (gdbarch, 32);
3151 set_gdbarch_ptr_bit (gdbarch, 32);
3152}
90884b2b 3153
97de3545
JB		 3154/* Return the target description for a specified XSAVE feature mask. */
3155
3156const struct target_desc *
3157amd64_target_description (uint64_t xcr0)
3158{
3159 switch (xcr0 & X86_XSTATE_ALL_MASK)
3160 {
3161 case X86_XSTATE_MPX_AVX512_MASK:
3162 case X86_XSTATE_AVX512_MASK:
3163 return tdesc_amd64_avx512;
3164 case X86_XSTATE_MPX_MASK:
3165 return tdesc_amd64_mpx;
3166 case X86_XSTATE_AVX_MASK:
3167 return tdesc_amd64_avx;
3168 default:
3169 return tdesc_amd64;
3170 }
3171}
3172
90884b2b
L		 3173/* Provide a prototype to silence -Wmissing-prototypes. */
3174void _initialize_amd64_tdep (void);
3175
3176void
3177_initialize_amd64_tdep (void)
3178{
3179 initialize_tdesc_amd64 ();
a055a187 3180 initialize_tdesc_amd64_avx ();
e43e105e 3181 initialize_tdesc_amd64_mpx ();
01f9f808
MS		 3182 initialize_tdesc_amd64_avx512 ();
3183
ac1438b5
L		 3184 initialize_tdesc_x32 ();
3185 initialize_tdesc_x32_avx ();
01f9f808 3186 initialize_tdesc_x32_avx512 ();
90884b2b 3187}
c4f35dd8
MK		 3188\f
3189
41d041d6
MK		 3190/* The 64-bit FXSAVE format differs from the 32-bit format in the
3191 sense that the instruction pointer and data pointer are simply
3192 64-bit offsets into the code segment and the data segment instead
3193 of a selector offset pair. The functions below store the upper 32
3194 bits of these pointers (instead of just the 16-bits of the segment
3195 selector). */
3196
3197/* Fill register REGNUM in REGCACHE with the appropriate
0485f6ad
MK		 3198 floating-point or SSE register value from *FXSAVE. If REGNUM is
3199 -1, do this for all registers. This function masks off any of the
3200 reserved bits in *FXSAVE. */
c4f35dd8
MK		 3201
3202void
90f90721 3203amd64_supply_fxsave (struct regcache *regcache, int regnum,
20a6ec49 3204 const void *fxsave)
c4f35dd8 3205{
20a6ec49
MD		 3206 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3207 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3208
41d041d6 3209 i387_supply_fxsave (regcache, regnum, fxsave);
c4f35dd8 3210
233dfcf0
L		 3211 if (fxsave
3212 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
c4f35dd8 3213 {
9a3c8263 3214 const gdb_byte *regs = (const gdb_byte *) fxsave;
41d041d6 3215
20a6ec49
MD		 3216 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3217 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3218 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3219 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
c4f35dd8 3220 }
0c1a73d6
MK		 3221}
3222
a055a187
L		 3223/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3224
3225void
3226amd64_supply_xsave (struct regcache *regcache, int regnum,
3227 const void *xsave)
3228{
3229 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3231
3232 i387_supply_xsave (regcache, regnum, xsave);
3233
233dfcf0
L		 3234 if (xsave
3235 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187 3236 {
9a3c8263 3237 const gdb_byte *regs = (const gdb_byte *) xsave;
a055a187
L		 3238
3239 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3240 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3241 regs + 12);
3242 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3243 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3244 regs + 20);
3245 }
3246}
3247
3c017e40
MK		 3248/* Fill register REGNUM (if it is a floating-point or SSE register) in
3249 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3250 all registers. This function doesn't touch any of the reserved
3251 bits in *FXSAVE. */
3252
3253void
3254amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3255 void *fxsave)
3256{
20a6ec49
MD		 3257 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3258 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3259 gdb_byte *regs = (gdb_byte *) fxsave;
3c017e40
MK		 3260
3261 i387_collect_fxsave (regcache, regnum, fxsave);
3262
233dfcf0 3263 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
f0ef85a5 3264 {
20a6ec49
MD		 3265 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3266 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3267 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3268 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
f0ef85a5 3269 }
3c017e40 3270}
a055a187 3271
7a9dd1b2 3272/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
a055a187
L		 3273
3274void
3275amd64_collect_xsave (const struct regcache *regcache, int regnum,
3276 void *xsave, int gcore)
3277{
3278 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3279 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3280 gdb_byte *regs = (gdb_byte *) xsave;
a055a187
L		 3281
3282 i387_collect_xsave (regcache, regnum, xsave, gcore);
3283
233dfcf0 3284 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187
L		 3285 {
3286 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3287 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3288 regs + 12);
3289 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3290 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),
3291 regs + 20);
3292 }
3293}
GDB Binutils - Deliverables
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