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Improve alignment of "info threads" output, align "Target Id" column
[deliverable/binutils-gdb.git] / gdb / amd64-tdep.c
CommitLineData
e53bef9f 1/* Target-dependent code for AMD64.
ce0eebec 2
e2882c85 3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
5ae96ec1
MK		 4
5 Contributed by Jiri Smid, SuSE Labs.
53e95fcf
JS		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
53e95fcf
JS		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
53e95fcf
JS		 21
22#include "defs.h"
35669430
DE		 23#include "opcode/i386.h"
24#include "dis-asm.h"
c4f35dd8
MK		 25#include "arch-utils.h"
26#include "block.h"
27#include "dummy-frame.h"
28#include "frame.h"
29#include "frame-base.h"
30#include "frame-unwind.h"
53e95fcf 31#include "inferior.h"
45741a9c 32#include "infrun.h"
53e95fcf 33#include "gdbcmd.h"
c4f35dd8
MK		 34#include "gdbcore.h"
35#include "objfiles.h"
53e95fcf 36#include "regcache.h"
2c261fae 37#include "regset.h"
53e95fcf 38#include "symfile.h"
eda5a4d7 39#include "disasm.h"
9c1488cb 40#include "amd64-tdep.h"
c4f35dd8 41#include "i387-tdep.h"
97de3545 42#include "x86-xstate.h"
325fac50 43#include <algorithm>
22916b07
YQ		 44#include "target-descriptions.h"
45#include "arch/amd64.h"
b32b108a 46#include "producer.h"
6710bf39
SS		 47#include "ax.h"
48#include "ax-gdb.h"
cfba9872 49#include "common/byte-vector.h"
c912f608 50#include "osabi.h"
1d509aa6 51#include "x86-tdep.h"
6710bf39 52
e53bef9f
MK		 53/* Note that the AMD64 architecture was previously known as x86-64.
54 The latter is (forever) engraved into the canonical system name as
90f90721 55 returned by config.guess, and used as the name for the AMD64 port
e53bef9f
MK		 56 of GNU/Linux. The BSD's have renamed their ports to amd64; they
57 don't like to shout. For GDB we prefer the amd64_-prefix over the
58 x86_64_-prefix since it's so much easier to type. */
59
402ecd56 60/* Register information. */
c4f35dd8 61
6707b003 62static const char *amd64_register_names[] =
de220d0f 63{
6707b003 64 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
c4f35dd8
MK		 65
66 /* %r8 is indeed register number 8. */
6707b003
UW		 67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
c4f35dd8 69
af233647 70 /* %st0 is register number 24. */
6707b003
UW		 71 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
c4f35dd8 73
af233647 74 /* %xmm0 is register number 40. */
6707b003
UW		 75 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
76 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
77 "mxcsr",
0e04a514
ML		 78};
79
a055a187
L		 80static const char *amd64_ymm_names[] =
81{
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
84 "ymm8", "ymm9", "ymm10", "ymm11",
85 "ymm12", "ymm13", "ymm14", "ymm15"
86};
87
01f9f808
MS		 88static const char *amd64_ymm_avx512_names[] =
89{
90 "ymm16", "ymm17", "ymm18", "ymm19",
91 "ymm20", "ymm21", "ymm22", "ymm23",
92 "ymm24", "ymm25", "ymm26", "ymm27",
93 "ymm28", "ymm29", "ymm30", "ymm31"
94};
95
a055a187
L		 96static const char *amd64_ymmh_names[] =
97{
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
101 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
102};
de220d0f 103
01f9f808
MS		 104static const char *amd64_ymmh_avx512_names[] =
105{
106 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
107 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
108 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
109 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
110};
111
e43e105e
WT		 112static const char *amd64_mpx_names[] =
113{
114 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
115};
116
01f9f808
MS		 117static const char *amd64_k_names[] =
118{
119 "k0", "k1", "k2", "k3",
120 "k4", "k5", "k6", "k7"
121};
122
123static const char *amd64_zmmh_names[] =
124{
125 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
126 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
127 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
128 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
129 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
130 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
131 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
132 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
133};
134
135static const char *amd64_zmm_names[] =
136{
137 "zmm0", "zmm1", "zmm2", "zmm3",
138 "zmm4", "zmm5", "zmm6", "zmm7",
139 "zmm8", "zmm9", "zmm10", "zmm11",
140 "zmm12", "zmm13", "zmm14", "zmm15",
141 "zmm16", "zmm17", "zmm18", "zmm19",
142 "zmm20", "zmm21", "zmm22", "zmm23",
143 "zmm24", "zmm25", "zmm26", "zmm27",
144 "zmm28", "zmm29", "zmm30", "zmm31"
145};
146
147static const char *amd64_xmm_avx512_names[] = {
148 "xmm16", "xmm17", "xmm18", "xmm19",
149 "xmm20", "xmm21", "xmm22", "xmm23",
150 "xmm24", "xmm25", "xmm26", "xmm27",
151 "xmm28", "xmm29", "xmm30", "xmm31"
152};
153
51547df6
MS		 154static const char *amd64_pkeys_names[] = {
155 "pkru"
156};
157
c4f35dd8
MK		 158/* DWARF Register Number Mapping as defined in the System V psABI,
159 section 3.6. */
53e95fcf 160
e53bef9f 161static int amd64_dwarf_regmap[] =
0e04a514 162{
c4f35dd8 163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
90f90721
MK		 164 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
165 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
166 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
c4f35dd8
MK		 167
168 /* Frame Pointer Register RBP. */
90f90721 169 AMD64_RBP_REGNUM,
c4f35dd8
MK		 170
171 /* Stack Pointer Register RSP. */
90f90721 172 AMD64_RSP_REGNUM,
c4f35dd8
MK		 173
174 /* Extended Integer Registers 8 - 15. */
5b856f36
PM		 175 AMD64_R8_REGNUM, /* %r8 */
176 AMD64_R9_REGNUM, /* %r9 */
177 AMD64_R10_REGNUM, /* %r10 */
178 AMD64_R11_REGNUM, /* %r11 */
179 AMD64_R12_REGNUM, /* %r12 */
180 AMD64_R13_REGNUM, /* %r13 */
181 AMD64_R14_REGNUM, /* %r14 */
182 AMD64_R15_REGNUM, /* %r15 */
c4f35dd8 183
59207364 184 /* Return Address RA. Mapped to RIP. */
90f90721 185 AMD64_RIP_REGNUM,
c4f35dd8
MK		 186
187 /* SSE Registers 0 - 7. */
90f90721
MK		 188 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
189 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
190 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
191 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
c4f35dd8
MK		 192
193 /* Extended SSE Registers 8 - 15. */
90f90721
MK		 194 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
195 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
196 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
197 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
c4f35dd8
MK		 198
199 /* Floating Point Registers 0-7. */
90f90721
MK		 200 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
201 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
202 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
c6f4c129 203 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
f7ca3fcf
PM		 204
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
210
c6f4c129
JB		 211 /* Control and Status Flags Register. */
212 AMD64_EFLAGS_REGNUM,
213
214 /* Selector Registers. */
215 AMD64_ES_REGNUM,
216 AMD64_CS_REGNUM,
217 AMD64_SS_REGNUM,
218 AMD64_DS_REGNUM,
219 AMD64_FS_REGNUM,
220 AMD64_GS_REGNUM,
221 -1,
222 -1,
223
224 /* Segment Base Address Registers. */
225 -1,
226 -1,
227 -1,
228 -1,
229
230 /* Special Selector Registers. */
231 -1,
232 -1,
233
234 /* Floating Point Control Registers. */
235 AMD64_MXCSR_REGNUM,
236 AMD64_FCTRL_REGNUM,
237 AMD64_FSTAT_REGNUM
c4f35dd8 238};
0e04a514 239
e53bef9f
MK		 240static const int amd64_dwarf_regmap_len =
241 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
0e04a514 242
c4f35dd8
MK		 243/* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
26abbdc4 245
c4f35dd8 246static int
d3f73121 247amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
53e95fcf 248{
a055a187
L		 249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 int ymm0_regnum = tdep->ymm0_regnum;
c4f35dd8 251 int regnum = -1;
53e95fcf 252
16aff9a6 253 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
e53bef9f 254 regnum = amd64_dwarf_regmap[reg];
53e95fcf 255
0fde2c53 256 if (ymm0_regnum >= 0
a055a187
L		 257 && i386_xmm_regnum_p (gdbarch, regnum))
258 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
c4f35dd8
MK		 259
260 return regnum;
53e95fcf 261}
d532c08f 262
35669430
DE		 263/* Map architectural register numbers to gdb register numbers. */
264
265static const int amd64_arch_regmap[16] =
266{
267 AMD64_RAX_REGNUM, /* %rax */
268 AMD64_RCX_REGNUM, /* %rcx */
269 AMD64_RDX_REGNUM, /* %rdx */
270 AMD64_RBX_REGNUM, /* %rbx */
271 AMD64_RSP_REGNUM, /* %rsp */
272 AMD64_RBP_REGNUM, /* %rbp */
273 AMD64_RSI_REGNUM, /* %rsi */
274 AMD64_RDI_REGNUM, /* %rdi */
275 AMD64_R8_REGNUM, /* %r8 */
276 AMD64_R9_REGNUM, /* %r9 */
277 AMD64_R10_REGNUM, /* %r10 */
278 AMD64_R11_REGNUM, /* %r11 */
279 AMD64_R12_REGNUM, /* %r12 */
280 AMD64_R13_REGNUM, /* %r13 */
281 AMD64_R14_REGNUM, /* %r14 */
282 AMD64_R15_REGNUM /* %r15 */
283};
284
285static const int amd64_arch_regmap_len =
286 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
287
288/* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
290
291static int
292amd64_arch_reg_to_regnum (int reg)
293{
294 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
295
296 return amd64_arch_regmap[reg];
297}
298
1ba53b71
L		 299/* Register names for byte pseudo-registers. */
300
301static const char *amd64_byte_names[] =
302{
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
fe01d668
L		 304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
1ba53b71
L		 306};
307
fe01d668
L		 308/* Number of lower byte registers. */
309#define AMD64_NUM_LOWER_BYTE_REGS 16
310
1ba53b71
L		 311/* Register names for word pseudo-registers. */
312
313static const char *amd64_word_names[] =
314{
9cad29ac 315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
1ba53b71
L		 316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
317};
318
319/* Register names for dword pseudo-registers. */
320
321static const char *amd64_dword_names[] =
322{
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
fff4548b
MK		 324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
325 "eip"
1ba53b71
L		 326};
327
328/* Return the name of register REGNUM. */
329
330static const char *
331amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
332{
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 if (i386_byte_regnum_p (gdbarch, regnum))
335 return amd64_byte_names[regnum - tdep->al_regnum];
01f9f808
MS		 336 else if (i386_zmm_regnum_p (gdbarch, regnum))
337 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
a055a187
L		 338 else if (i386_ymm_regnum_p (gdbarch, regnum))
339 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
01f9f808
MS		 340 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
341 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
1ba53b71
L		 342 else if (i386_word_regnum_p (gdbarch, regnum))
343 return amd64_word_names[regnum - tdep->ax_regnum];
344 else if (i386_dword_regnum_p (gdbarch, regnum))
345 return amd64_dword_names[regnum - tdep->eax_regnum];
346 else
347 return i386_pseudo_register_name (gdbarch, regnum);
348}
349
3543a589
TT		 350static struct value *
351amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
849d0ba8 352 readable_regcache *regcache,
3543a589 353 int regnum)
1ba53b71 354{
9890e433 355 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1ba53b71 356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
05d1431c 357 enum register_status status;
3543a589
TT		 358 struct value *result_value;
359 gdb_byte *buf;
360
361 result_value = allocate_value (register_type (gdbarch, regnum));
362 VALUE_LVAL (result_value) = lval_register;
363 VALUE_REGNUM (result_value) = regnum;
364 buf = value_contents_raw (result_value);
1ba53b71
L		 365
366 if (i386_byte_regnum_p (gdbarch, regnum))
367 {
368 int gpnum = regnum - tdep->al_regnum;
369
370 /* Extract (always little endian). */
fe01d668
L		 371 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
372 {
373 /* Special handling for AH, BH, CH, DH. */
03f50fc8
YQ		 374 status = regcache->raw_read (gpnum - AMD64_NUM_LOWER_BYTE_REGS,
375 raw_buf);
05d1431c
PA		 376 if (status == REG_VALID)
377 memcpy (buf, raw_buf + 1, 1);
3543a589
TT		 378 else
379 mark_value_bytes_unavailable (result_value, 0,
380 TYPE_LENGTH (value_type (result_value)));
fe01d668
L		 381 }
382 else
383 {
03f50fc8 384 status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 385 if (status == REG_VALID)
386 memcpy (buf, raw_buf, 1);
3543a589
TT		 387 else
388 mark_value_bytes_unavailable (result_value, 0,
389 TYPE_LENGTH (value_type (result_value)));
fe01d668 390 }
1ba53b71
L		 391 }
392 else if (i386_dword_regnum_p (gdbarch, regnum))
393 {
394 int gpnum = regnum - tdep->eax_regnum;
395 /* Extract (always little endian). */
03f50fc8 396 status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 397 if (status == REG_VALID)
398 memcpy (buf, raw_buf, 4);
3543a589
TT		 399 else
400 mark_value_bytes_unavailable (result_value, 0,
401 TYPE_LENGTH (value_type (result_value)));
1ba53b71
L		 402 }
403 else
3543a589
TT		 404 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
405 result_value);
406
407 return result_value;
1ba53b71
L		 408}
409
410static void
411amd64_pseudo_register_write (struct gdbarch *gdbarch,
412 struct regcache *regcache,
413 int regnum, const gdb_byte *buf)
414{
9890e433 415 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1ba53b71
L		 416 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
417
418 if (i386_byte_regnum_p (gdbarch, regnum))
419 {
420 int gpnum = regnum - tdep->al_regnum;
421
fe01d668
L		 422 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
423 {
424 /* Read ... AH, BH, CH, DH. */
0b883586 425 regcache->raw_read (gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
fe01d668
L		 426 /* ... Modify ... (always little endian). */
427 memcpy (raw_buf + 1, buf, 1);
428 /* ... Write. */
10eaee5f 429 regcache->raw_write (gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
fe01d668
L		 430 }
431 else
432 {
433 /* Read ... */
0b883586 434 regcache->raw_read (gpnum, raw_buf);
fe01d668
L		 435 /* ... Modify ... (always little endian). */
436 memcpy (raw_buf, buf, 1);
437 /* ... Write. */
10eaee5f 438 regcache->raw_write (gpnum, raw_buf);
fe01d668 439 }
1ba53b71
L		 440 }
441 else if (i386_dword_regnum_p (gdbarch, regnum))
442 {
443 int gpnum = regnum - tdep->eax_regnum;
444
445 /* Read ... */
0b883586 446 regcache->raw_read (gpnum, raw_buf);
1ba53b71
L		 447 /* ... Modify ... (always little endian). */
448 memcpy (raw_buf, buf, 4);
449 /* ... Write. */
10eaee5f 450 regcache->raw_write (gpnum, raw_buf);
1ba53b71
L		 451 }
452 else
453 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
454}
455
62e5fd57
MK		 456/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
457
458static int
459amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
460 struct agent_expr *ax, int regnum)
461{
462 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
463
464 if (i386_byte_regnum_p (gdbarch, regnum))
465 {
466 int gpnum = regnum - tdep->al_regnum;
467
468 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
469 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
470 else
471 ax_reg_mask (ax, gpnum);
472 return 0;
473 }
474 else if (i386_dword_regnum_p (gdbarch, regnum))
475 {
476 int gpnum = regnum - tdep->eax_regnum;
477
478 ax_reg_mask (ax, gpnum);
479 return 0;
480 }
481 else
482 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
483}
484
53e95fcf
JS		 485\f
486
bf4d6c1c
JB		 487/* Register classes as defined in the psABI. */
488
489enum amd64_reg_class
490{
491 AMD64_INTEGER,
492 AMD64_SSE,
493 AMD64_SSEUP,
494 AMD64_X87,
495 AMD64_X87UP,
496 AMD64_COMPLEX_X87,
497 AMD64_NO_CLASS,
498 AMD64_MEMORY
499};
500
efb1c01c
MK		 501/* Return the union class of CLASS1 and CLASS2. See the psABI for
502 details. */
503
504static enum amd64_reg_class
505amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
506{
507 /* Rule (a): If both classes are equal, this is the resulting class. */
508 if (class1 == class2)
509 return class1;
510
511 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
512 is the other class. */
513 if (class1 == AMD64_NO_CLASS)
514 return class2;
515 if (class2 == AMD64_NO_CLASS)
516 return class1;
517
518 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
519 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
520 return AMD64_MEMORY;
521
522 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
523 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
524 return AMD64_INTEGER;
525
526 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
527 MEMORY is used as class. */
528 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
529 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
530 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
531 return AMD64_MEMORY;
532
533 /* Rule (f): Otherwise class SSE is used. */
534 return AMD64_SSE;
535}
536
fe978cb0 537static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
bf4d6c1c 538
79b1ab3d
MK		 539/* Return non-zero if TYPE is a non-POD structure or union type. */
540
541static int
542amd64_non_pod_p (struct type *type)
543{
544 /* ??? A class with a base class certainly isn't POD, but does this
545 catch all non-POD structure types? */
546 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
547 return 1;
548
549 return 0;
550}
551
efb1c01c
MK		 552/* Classify TYPE according to the rules for aggregate (structures and
553 arrays) and union types, and store the result in CLASS. */
c4f35dd8
MK		 554
555static void
fe978cb0 556amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
53e95fcf 557{
efb1c01c
MK		 558 /* 1. If the size of an object is larger than two eightbytes, or in
559 C++, is a non-POD structure or union type, or contains
560 unaligned fields, it has class memory. */
744a8059 561 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
53e95fcf 562 {
fe978cb0 563 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 564 return;
53e95fcf 565 }
efb1c01c
MK		 566
567 /* 2. Both eightbytes get initialized to class NO_CLASS. */
fe978cb0 568 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 569
570 /* 3. Each field of an object is classified recursively so that
571 always two fields are considered. The resulting class is
572 calculated according to the classes of the fields in the
573 eightbyte: */
574
575 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
8ffd9b1b 576 {
efb1c01c
MK		 577 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
578
579 /* All fields in an array have the same type. */
fe978cb0
PA		 580 amd64_classify (subtype, theclass);
581 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
582 theclass[1] = theclass[0];
8ffd9b1b 583 }
53e95fcf
JS		 584 else
585 {
efb1c01c 586 int i;
53e95fcf 587
efb1c01c
MK		 588 /* Structure or union. */
589 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
590 || TYPE_CODE (type) == TYPE_CODE_UNION);
591
592 for (i = 0; i < TYPE_NFIELDS (type); i++)
53e95fcf 593 {
efb1c01c
MK		 594 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
595 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
596 enum amd64_reg_class subclass[2];
e4e2711a
JB		 597 int bitsize = TYPE_FIELD_BITSIZE (type, i);
598 int endpos;
599
600 if (bitsize == 0)
601 bitsize = TYPE_LENGTH (subtype) * 8;
602 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
efb1c01c 603
5dc43913
AB		 604 /* Ignore static fields, or empty fields, for example nested
605 empty structures.*/
606 if (field_is_static (&TYPE_FIELD (type, i)) || bitsize == 0)
562c50c2
MK		 607 continue;
608
efb1c01c
MK		 609 gdb_assert (pos == 0 || pos == 1);
610
611 amd64_classify (subtype, subclass);
fe978cb0 612 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
e4e2711a
JB		 613 if (bitsize <= 64 && pos == 0 && endpos == 1)
614 /* This is a bit of an odd case: We have a field that would
615 normally fit in one of the two eightbytes, except that
616 it is placed in a way that this field straddles them.
617 This has been seen with a structure containing an array.
618
619 The ABI is a bit unclear in this case, but we assume that
620 this field's class (stored in subclass[0]) must also be merged
621 into class[1]. In other words, our field has a piece stored
622 in the second eight-byte, and thus its class applies to
623 the second eight-byte as well.
624
625 In the case where the field length exceeds 8 bytes,
626 it should not be necessary to merge the field class
627 into class[1]. As LEN > 8, subclass[1] is necessarily
628 different from AMD64_NO_CLASS. If subclass[1] is equal
629 to subclass[0], then the normal class[1]/subclass[1]
630 merging will take care of everything. For subclass[1]
631 to be different from subclass[0], I can only see the case
632 where we have a SSE/SSEUP or X87/X87UP pair, which both
633 use up all 16 bytes of the aggregate, and are already
634 handled just fine (because each portion sits on its own
635 8-byte). */
fe978cb0 636 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
efb1c01c 637 if (pos == 0)
fe978cb0 638 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
53e95fcf 639 }
53e95fcf 640 }
efb1c01c
MK		 641
642 /* 4. Then a post merger cleanup is done: */
643
644 /* Rule (a): If one of the classes is MEMORY, the whole argument is
645 passed in memory. */
fe978cb0
PA		 646 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
647 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 648
177b42fe 649 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
efb1c01c 650 SSE. */
fe978cb0
PA		 651 if (theclass[0] == AMD64_SSEUP)
652 theclass[0] = AMD64_SSE;
653 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
654 theclass[1] = AMD64_SSE;
efb1c01c
MK		 655}
656
657/* Classify TYPE, and store the result in CLASS. */
658
bf4d6c1c 659static void
fe978cb0 660amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
efb1c01c
MK		 661{
662 enum type_code code = TYPE_CODE (type);
663 int len = TYPE_LENGTH (type);
664
fe978cb0 665 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 666
667 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
5a7225ed
JB		 668 long, long long, and pointers are in the INTEGER class. Similarly,
669 range types, used by languages such as Ada, are also in the INTEGER
670 class. */
efb1c01c 671 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
b929c77f 672 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
9db13498 673 || code == TYPE_CODE_CHAR
aa006118 674 || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
efb1c01c 675 && (len == 1 || len == 2 || len == 4 || len == 8))
fe978cb0 676 theclass[0] = AMD64_INTEGER;
efb1c01c 677
5daa78cc
TJB		 678 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
679 are in class SSE. */
680 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
681 && (len == 4 || len == 8))
efb1c01c 682 /* FIXME: __m64 . */
fe978cb0 683 theclass[0] = AMD64_SSE;
efb1c01c 684
5daa78cc
TJB		 685 /* Arguments of types __float128, _Decimal128 and __m128 are split into
686 two halves. The least significant ones belong to class SSE, the most
efb1c01c 687 significant one to class SSEUP. */
5daa78cc
TJB		 688 else if (code == TYPE_CODE_DECFLOAT && len == 16)
689 /* FIXME: __float128, __m128. */
fe978cb0 690 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
efb1c01c
MK		 691
692 /* The 64-bit mantissa of arguments of type long double belongs to
693 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
694 class X87UP. */
695 else if (code == TYPE_CODE_FLT && len == 16)
696 /* Class X87 and X87UP. */
fe978cb0 697 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
efb1c01c 698
7f7930dd
MK		 699 /* Arguments of complex T where T is one of the types float or
700 double get treated as if they are implemented as:
701
702 struct complexT {
703 T real;
704 T imag;
5f52445b
YQ		 705 };
706
707 */
7f7930dd 708 else if (code == TYPE_CODE_COMPLEX && len == 8)
fe978cb0 709 theclass[0] = AMD64_SSE;
7f7930dd 710 else if (code == TYPE_CODE_COMPLEX && len == 16)
fe978cb0 711 theclass[0] = theclass[1] = AMD64_SSE;
7f7930dd
MK		 712
713 /* A variable of type complex long double is classified as type
714 COMPLEX_X87. */
715 else if (code == TYPE_CODE_COMPLEX && len == 32)
fe978cb0 716 theclass[0] = AMD64_COMPLEX_X87;
7f7930dd 717
efb1c01c
MK		 718 /* Aggregates. */
719 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
720 || code == TYPE_CODE_UNION)
fe978cb0 721 amd64_classify_aggregate (type, theclass);
efb1c01c
MK		 722}
723
724static enum return_value_convention
6a3a010b 725amd64_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 726 struct type *type, struct regcache *regcache,
42835c2b 727 gdb_byte *readbuf, const gdb_byte *writebuf)
efb1c01c 728{
fe978cb0 729 enum amd64_reg_class theclass[2];
efb1c01c 730 int len = TYPE_LENGTH (type);
90f90721
MK		 731 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
732 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
efb1c01c
MK		 733 int integer_reg = 0;
734 int sse_reg = 0;
735 int i;
736
737 gdb_assert (!(readbuf && writebuf));
738
739 /* 1. Classify the return type with the classification algorithm. */
fe978cb0 740 amd64_classify (type, theclass);
efb1c01c
MK		 741
742 /* 2. If the type has class MEMORY, then the caller provides space
6fa57a7d 743 for the return value and passes the address of this storage in
0963b4bd 744 %rdi as if it were the first argument to the function. In effect,
6fa57a7d
MK		 745 this address becomes a hidden first argument.
746
747 On return %rax will contain the address that has been passed in
748 by the caller in %rdi. */
fe978cb0 749 if (theclass[0] == AMD64_MEMORY)
6fa57a7d
MK		 750 {
751 /* As indicated by the comment above, the ABI guarantees that we
752 can always find the return value just after the function has
753 returned. */
754
755 if (readbuf)
756 {
757 ULONGEST addr;
758
759 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
760 read_memory (addr, readbuf, TYPE_LENGTH (type));
761 }
762
763 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
764 }
efb1c01c 765
7f7930dd
MK		 766 /* 8. If the class is COMPLEX_X87, the real part of the value is
767 returned in %st0 and the imaginary part in %st1. */
fe978cb0 768 if (theclass[0] == AMD64_COMPLEX_X87)
7f7930dd
MK		 769 {
770 if (readbuf)
771 {
0b883586
SM		 772 regcache->raw_read (AMD64_ST0_REGNUM, readbuf);
773 regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16);
7f7930dd
MK		 774 }
775
776 if (writebuf)
777 {
778 i387_return_value (gdbarch, regcache);
10eaee5f
SM		 779 regcache->raw_write (AMD64_ST0_REGNUM, writebuf);
780 regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16);
7f7930dd
MK		 781
782 /* Fix up the tag word such that both %st(0) and %st(1) are
783 marked as valid. */
784 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
785 }
786
787 return RETURN_VALUE_REGISTER_CONVENTION;
788 }
789
fe978cb0 790 gdb_assert (theclass[1] != AMD64_MEMORY);
bad43aa5 791 gdb_assert (len <= 16);
efb1c01c
MK		 792
793 for (i = 0; len > 0; i++, len -= 8)
794 {
795 int regnum = -1;
796 int offset = 0;
797
fe978cb0 798 switch (theclass[i])
efb1c01c
MK		 799 {
800 case AMD64_INTEGER:
801 /* 3. If the class is INTEGER, the next available register
802 of the sequence %rax, %rdx is used. */
803 regnum = integer_regnum[integer_reg++];
804 break;
805
806 case AMD64_SSE:
807 /* 4. If the class is SSE, the next available SSE register
808 of the sequence %xmm0, %xmm1 is used. */
809 regnum = sse_regnum[sse_reg++];
810 break;
811
812 case AMD64_SSEUP:
813 /* 5. If the class is SSEUP, the eightbyte is passed in the
814 upper half of the last used SSE register. */
815 gdb_assert (sse_reg > 0);
816 regnum = sse_regnum[sse_reg - 1];
817 offset = 8;
818 break;
819
820 case AMD64_X87:
821 /* 6. If the class is X87, the value is returned on the X87
822 stack in %st0 as 80-bit x87 number. */
90f90721 823 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 824 if (writebuf)
825 i387_return_value (gdbarch, regcache);
826 break;
827
828 case AMD64_X87UP:
829 /* 7. If the class is X87UP, the value is returned together
830 with the previous X87 value in %st0. */
fe978cb0 831 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
90f90721 832 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 833 offset = 8;
834 len = 2;
835 break;
836
837 case AMD64_NO_CLASS:
838 continue;
839
840 default:
841 gdb_assert (!"Unexpected register class.");
842 }
843
844 gdb_assert (regnum != -1);
845
846 if (readbuf)
502fe83e
SM		 847 regcache->raw_read_part (regnum, offset, std::min (len, 8),
848 readbuf + i * 8);
efb1c01c 849 if (writebuf)
4f0420fd
SM		 850 regcache->raw_write_part (regnum, offset, std::min (len, 8),
851 writebuf + i * 8);
efb1c01c
MK		 852 }
853
854 return RETURN_VALUE_REGISTER_CONVENTION;
53e95fcf
JS		 855}
856\f
857
720aa428
MK		 858static CORE_ADDR
859amd64_push_arguments (struct regcache *regcache, int nargs,
6470d250 860 struct value **args, CORE_ADDR sp, int struct_return)
720aa428 861{
bf4d6c1c
JB		 862 static int integer_regnum[] =
863 {
864 AMD64_RDI_REGNUM, /* %rdi */
865 AMD64_RSI_REGNUM, /* %rsi */
866 AMD64_RDX_REGNUM, /* %rdx */
867 AMD64_RCX_REGNUM, /* %rcx */
5b856f36
PM		 868 AMD64_R8_REGNUM, /* %r8 */
869 AMD64_R9_REGNUM /* %r9 */
bf4d6c1c 870 };
720aa428
MK		 871 static int sse_regnum[] =
872 {
873 /* %xmm0 ... %xmm7 */
90f90721
MK		 874 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
875 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
876 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
877 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
720aa428 878 };
224c3ddb 879 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
720aa428
MK		 880 int num_stack_args = 0;
881 int num_elements = 0;
882 int element = 0;
883 int integer_reg = 0;
884 int sse_reg = 0;
885 int i;
886
6470d250
MK		 887 /* Reserve a register for the "hidden" argument. */
888 if (struct_return)
889 integer_reg++;
890
720aa428
MK		 891 for (i = 0; i < nargs; i++)
892 {
4991999e 893 struct type *type = value_type (args[i]);
720aa428 894 int len = TYPE_LENGTH (type);
fe978cb0 895 enum amd64_reg_class theclass[2];
720aa428
MK		 896 int needed_integer_regs = 0;
897 int needed_sse_regs = 0;
898 int j;
899
900 /* Classify argument. */
fe978cb0 901 amd64_classify (type, theclass);
720aa428
MK		 902
903 /* Calculate the number of integer and SSE registers needed for
904 this argument. */
905 for (j = 0; j < 2; j++)
906 {
fe978cb0 907 if (theclass[j] == AMD64_INTEGER)
720aa428 908 needed_integer_regs++;
fe978cb0 909 else if (theclass[j] == AMD64_SSE)
720aa428
MK		 910 needed_sse_regs++;
911 }
912
913 /* Check whether enough registers are available, and if the
914 argument should be passed in registers at all. */
bf4d6c1c 915 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
720aa428
MK		 916 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
917 || (needed_integer_regs == 0 && needed_sse_regs == 0))
918 {
919 /* The argument will be passed on the stack. */
920 num_elements += ((len + 7) / 8);
849e9755 921 stack_args[num_stack_args++] = args[i];
720aa428
MK		 922 }
923 else
924 {
925 /* The argument will be passed in registers. */
d8de1ef7
MK		 926 const gdb_byte *valbuf = value_contents (args[i]);
927 gdb_byte buf[8];
720aa428
MK		 928
929 gdb_assert (len <= 16);
930
931 for (j = 0; len > 0; j++, len -= 8)
932 {
933 int regnum = -1;
934 int offset = 0;
935
fe978cb0 936 switch (theclass[j])
720aa428
MK		 937 {
938 case AMD64_INTEGER:
bf4d6c1c 939 regnum = integer_regnum[integer_reg++];
720aa428
MK		 940 break;
941
942 case AMD64_SSE:
943 regnum = sse_regnum[sse_reg++];
944 break;
945
946 case AMD64_SSEUP:
947 gdb_assert (sse_reg > 0);
948 regnum = sse_regnum[sse_reg - 1];
949 offset = 8;
950 break;
951
952 default:
953 gdb_assert (!"Unexpected register class.");
954 }
955
956 gdb_assert (regnum != -1);
957 memset (buf, 0, sizeof buf);
325fac50 958 memcpy (buf, valbuf + j * 8, std::min (len, 8));
4f0420fd 959 regcache->raw_write_part (regnum, offset, 8, buf);
720aa428
MK		 960 }
961 }
962 }
963
964 /* Allocate space for the arguments on the stack. */
965 sp -= num_elements * 8;
966
967 /* The psABI says that "The end of the input argument area shall be
968 aligned on a 16 byte boundary." */
969 sp &= ~0xf;
970
971 /* Write out the arguments to the stack. */
972 for (i = 0; i < num_stack_args; i++)
973 {
4991999e 974 struct type *type = value_type (stack_args[i]);
d8de1ef7 975 const gdb_byte *valbuf = value_contents (stack_args[i]);
849e9755
JB		 976 int len = TYPE_LENGTH (type);
977
978 write_memory (sp + element * 8, valbuf, len);
979 element += ((len + 7) / 8);
720aa428
MK		 980 }
981
982 /* The psABI says that "For calls that may call functions that use
983 varargs or stdargs (prototype-less calls or calls to functions
984 containing ellipsis (...) in the declaration) %al is used as
985 hidden argument to specify the number of SSE registers used. */
90f90721 986 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
720aa428
MK		 987 return sp;
988}
989
c4f35dd8 990static CORE_ADDR
7d9b040b 991amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
e53bef9f
MK		 992 struct regcache *regcache, CORE_ADDR bp_addr,
993 int nargs, struct value **args, CORE_ADDR sp,
994 int struct_return, CORE_ADDR struct_addr)
53e95fcf 995{
e17a4113 996 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 997 gdb_byte buf[8];
c4f35dd8 998
4a612d6f
WT		 999 /* BND registers can be in arbitrary values at the moment of the
1000 inferior call. This can cause boundary violations that are not
1001 due to a real bug or even desired by the user. The best to be done
1002 is set the BND registers to allow access to the whole memory, INIT
1003 state, before pushing the inferior call. */
1004 i387_reset_bnd_regs (gdbarch, regcache);
1005
c4f35dd8 1006 /* Pass arguments. */
6470d250 1007 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
c4f35dd8
MK		 1008
1009 /* Pass "hidden" argument". */
1010 if (struct_return)
1011 {
e17a4113 1012 store_unsigned_integer (buf, 8, byte_order, struct_addr);
b66f5587 1013 regcache->cooked_write (AMD64_RDI_REGNUM, buf);
c4f35dd8
MK		 1014 }
1015
1016 /* Store return address. */
1017 sp -= 8;
e17a4113 1018 store_unsigned_integer (buf, 8, byte_order, bp_addr);
c4f35dd8
MK		 1019 write_memory (sp, buf, 8);
1020
1021 /* Finally, update the stack pointer... */
e17a4113 1022 store_unsigned_integer (buf, 8, byte_order, sp);
b66f5587 1023 regcache->cooked_write (AMD64_RSP_REGNUM, buf);
c4f35dd8
MK		 1024
1025 /* ...and fake a frame pointer. */
b66f5587 1026 regcache->cooked_write (AMD64_RBP_REGNUM, buf);
c4f35dd8 1027
3e210248 1028 return sp + 16;
53e95fcf 1029}
c4f35dd8 1030\f
35669430
DE		 1031/* Displaced instruction handling. */
1032
1033/* A partially decoded instruction.
1034 This contains enough details for displaced stepping purposes. */
1035
1036struct amd64_insn
1037{
1038 /* The number of opcode bytes. */
1039 int opcode_len;
50a1fdd5
PA		 1040 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1041 not present. */
1042 int enc_prefix_offset;
35669430
DE		 1043 /* The offset to the first opcode byte. */
1044 int opcode_offset;
1045 /* The offset to the modrm byte or -1 if not present. */
1046 int modrm_offset;
1047
1048 /* The raw instruction. */
1049 gdb_byte *raw_insn;
1050};
1051
cfba9872 1052struct amd64_displaced_step_closure : public displaced_step_closure
35669430 1053{
cfba9872
SM		 1054 amd64_displaced_step_closure (int insn_buf_len)
1055 : insn_buf (insn_buf_len, 0)
1056 {}
1057
35669430 1058 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
cfba9872 1059 int tmp_used = 0;
35669430
DE		 1060 int tmp_regno;
1061 ULONGEST tmp_save;
1062
1063 /* Details of the instruction. */
1064 struct amd64_insn insn_details;
1065
cfba9872
SM		 1066 /* The possibly modified insn. */
1067 gdb::byte_vector insn_buf;
35669430
DE		 1068};
1069
1070/* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1071 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1072 at which point delete these in favor of libopcodes' versions). */
1073
1074static const unsigned char onebyte_has_modrm[256] = {
1075 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1076 /* ------------------------------- */
1077 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1078 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1079 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1080 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1081 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1082 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1083 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1084 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1085 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1086 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1087 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1088 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1089 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1090 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1091 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1092 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1093 /* ------------------------------- */
1094 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1095};
1096
1097static const unsigned char twobyte_has_modrm[256] = {
1098 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1099 /* ------------------------------- */
1100 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1101 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1102 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1103 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1104 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1105 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1106 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1107 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1108 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1109 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1110 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1111 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1112 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1113 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1114 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1115 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1116 /* ------------------------------- */
1117 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1118};
1119
1120static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1121
1122static int
1123rex_prefix_p (gdb_byte pfx)
1124{
1125 return REX_PREFIX_P (pfx);
1126}
1127
50a1fdd5
PA		 1128/* True if PFX is the start of the 2-byte VEX prefix. */
1129
1130static bool
1131vex2_prefix_p (gdb_byte pfx)
1132{
1133 return pfx == 0xc5;
1134}
1135
1136/* True if PFX is the start of the 3-byte VEX prefix. */
1137
1138static bool
1139vex3_prefix_p (gdb_byte pfx)
1140{
1141 return pfx == 0xc4;
1142}
1143
35669430
DE		 1144/* Skip the legacy instruction prefixes in INSN.
1145 We assume INSN is properly sentineled so we don't have to worry
1146 about falling off the end of the buffer. */
1147
1148static gdb_byte *
1903f0e6 1149amd64_skip_prefixes (gdb_byte *insn)
35669430
DE		 1150{
1151 while (1)
1152 {
1153 switch (*insn)
1154 {
1155 case DATA_PREFIX_OPCODE:
1156 case ADDR_PREFIX_OPCODE:
1157 case CS_PREFIX_OPCODE:
1158 case DS_PREFIX_OPCODE:
1159 case ES_PREFIX_OPCODE:
1160 case FS_PREFIX_OPCODE:
1161 case GS_PREFIX_OPCODE:
1162 case SS_PREFIX_OPCODE:
1163 case LOCK_PREFIX_OPCODE:
1164 case REPE_PREFIX_OPCODE:
1165 case REPNE_PREFIX_OPCODE:
1166 ++insn;
1167 continue;
1168 default:
1169 break;
1170 }
1171 break;
1172 }
1173
1174 return insn;
1175}
1176
35669430
DE		 1177/* Return an integer register (other than RSP) that is unused as an input
1178 operand in INSN.
1179 In order to not require adding a rex prefix if the insn doesn't already
1180 have one, the result is restricted to RAX ... RDI, sans RSP.
1181 The register numbering of the result follows architecture ordering,
1182 e.g. RDI = 7. */
1183
1184static int
1185amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1186{
1187 /* 1 bit for each reg */
1188 int used_regs_mask = 0;
1189
1190 /* There can be at most 3 int regs used as inputs in an insn, and we have
1191 7 to choose from (RAX ... RDI, sans RSP).
1192 This allows us to take a conservative approach and keep things simple.
1193 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1194 that implicitly specify RAX. */
1195
1196 /* Avoid RAX. */
1197 used_regs_mask |= 1 << EAX_REG_NUM;
1198 /* Similarily avoid RDX, implicit operand in divides. */
1199 used_regs_mask |= 1 << EDX_REG_NUM;
1200 /* Avoid RSP. */
1201 used_regs_mask |= 1 << ESP_REG_NUM;
1202
1203 /* If the opcode is one byte long and there's no ModRM byte,
1204 assume the opcode specifies a register. */
1205 if (details->opcode_len == 1 && details->modrm_offset == -1)
1206 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1207
1208 /* Mark used regs in the modrm/sib bytes. */
1209 if (details->modrm_offset != -1)
1210 {
1211 int modrm = details->raw_insn[details->modrm_offset];
1212 int mod = MODRM_MOD_FIELD (modrm);
1213 int reg = MODRM_REG_FIELD (modrm);
1214 int rm = MODRM_RM_FIELD (modrm);
1215 int have_sib = mod != 3 && rm == 4;
1216
1217 /* Assume the reg field of the modrm byte specifies a register. */
1218 used_regs_mask |= 1 << reg;
1219
1220 if (have_sib)
1221 {
1222 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
d48ebb5b 1223 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
35669430 1224 used_regs_mask |= 1 << base;
d48ebb5b 1225 used_regs_mask |= 1 << idx;
35669430
DE		 1226 }
1227 else
1228 {
1229 used_regs_mask |= 1 << rm;
1230 }
1231 }
1232
1233 gdb_assert (used_regs_mask < 256);
1234 gdb_assert (used_regs_mask != 255);
1235
1236 /* Finally, find a free reg. */
1237 {
1238 int i;
1239
1240 for (i = 0; i < 8; ++i)
1241 {
1242 if (! (used_regs_mask & (1 << i)))
1243 return i;
1244 }
1245
1246 /* We shouldn't get here. */
1247 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1248 }
1249}
1250
1251/* Extract the details of INSN that we need. */
1252
1253static void
1254amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1255{
1256 gdb_byte *start = insn;
1257 int need_modrm;
1258
1259 details->raw_insn = insn;
1260
1261 details->opcode_len = -1;
50a1fdd5 1262 details->enc_prefix_offset = -1;
35669430
DE		 1263 details->opcode_offset = -1;
1264 details->modrm_offset = -1;
1265
1266 /* Skip legacy instruction prefixes. */
1903f0e6 1267 insn = amd64_skip_prefixes (insn);
35669430 1268
50a1fdd5 1269 /* Skip REX/VEX instruction encoding prefixes. */
35669430
DE		 1270 if (rex_prefix_p (*insn))
1271 {
50a1fdd5 1272 details->enc_prefix_offset = insn - start;
35669430
DE		 1273 ++insn;
1274 }
50a1fdd5
PA		 1275 else if (vex2_prefix_p (*insn))
1276 {
1277 /* Don't record the offset in this case because this prefix has
1278 no REX.B equivalent. */
1279 insn += 2;
1280 }
1281 else if (vex3_prefix_p (*insn))
1282 {
1283 details->enc_prefix_offset = insn - start;
1284 insn += 3;
1285 }
35669430
DE		 1286
1287 details->opcode_offset = insn - start;
1288
1289 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1290 {
1291 /* Two or three-byte opcode. */
1292 ++insn;
1293 need_modrm = twobyte_has_modrm[*insn];
1294
1295 /* Check for three-byte opcode. */
1903f0e6 1296 switch (*insn)
35669430 1297 {
1903f0e6
DE		 1298 case 0x24:
1299 case 0x25:
1300 case 0x38:
1301 case 0x3a:
1302 case 0x7a:
1303 case 0x7b:
35669430
DE		 1304 ++insn;
1305 details->opcode_len = 3;
1903f0e6
DE		 1306 break;
1307 default:
1308 details->opcode_len = 2;
1309 break;
35669430 1310 }
35669430
DE		 1311 }
1312 else
1313 {
1314 /* One-byte opcode. */
1315 need_modrm = onebyte_has_modrm[*insn];
1316 details->opcode_len = 1;
1317 }
1318
1319 if (need_modrm)
1320 {
1321 ++insn;
1322 details->modrm_offset = insn - start;
1323 }
1324}
1325
1326/* Update %rip-relative addressing in INSN.
1327
1328 %rip-relative addressing only uses a 32-bit displacement.
1329 32 bits is not enough to be guaranteed to cover the distance between where
1330 the real instruction is and where its copy is.
1331 Convert the insn to use base+disp addressing.
1332 We set base = pc + insn_length so we can leave disp unchanged. */
c4f35dd8 1333
35669430 1334static void
cfba9872 1335fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc,
35669430
DE		 1336 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1337{
1338 const struct amd64_insn *insn_details = &dsc->insn_details;
1339 int modrm_offset = insn_details->modrm_offset;
1340 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1341 CORE_ADDR rip_base;
35669430
DE		 1342 int insn_length;
1343 int arch_tmp_regno, tmp_regno;
1344 ULONGEST orig_value;
1345
1346 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1347 ++insn;
1348
1349 /* Compute the rip-relative address. */
cfba9872
SM		 1350 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (),
1351 dsc->insn_buf.size (), from);
35669430
DE		 1352 rip_base = from + insn_length;
1353
1354 /* We need a register to hold the address.
1355 Pick one not used in the insn.
1356 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1357 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1358 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1359
50a1fdd5
PA		 1360 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1361 static constexpr gdb_byte VEX3_NOT_B = 0x20;
1362
1363 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1364 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1365 is not r8-r15. */
1366 if (insn_details->enc_prefix_offset != -1)
1367 {
1368 gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset];
1369 if (rex_prefix_p (pfx[0]))
1370 pfx[0] &= ~REX_B;
1371 else if (vex3_prefix_p (pfx[0]))
1372 pfx[1] |= VEX3_NOT_B;
1373 else
1374 gdb_assert_not_reached ("unhandled prefix");
1375 }
35669430
DE		 1376
1377 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1378 dsc->tmp_regno = tmp_regno;
1379 dsc->tmp_save = orig_value;
1380 dsc->tmp_used = 1;
1381
1382 /* Convert the ModRM field to be base+disp. */
1383 dsc->insn_buf[modrm_offset] &= ~0xc7;
1384 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1385
1386 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1387
1388 if (debug_displaced)
1389 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
5af949e3
UW		 1390 "displaced: using temp reg %d, old value %s, new value %s\n",
1391 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1392 paddress (gdbarch, rip_base));
35669430
DE		 1393}
1394
1395static void
1396fixup_displaced_copy (struct gdbarch *gdbarch,
cfba9872 1397 amd64_displaced_step_closure *dsc,
35669430
DE		 1398 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1399{
1400 const struct amd64_insn *details = &dsc->insn_details;
1401
1402 if (details->modrm_offset != -1)
1403 {
1404 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1405
1406 if ((modrm & 0xc7) == 0x05)
1407 {
1408 /* The insn uses rip-relative addressing.
1409 Deal with it. */
1410 fixup_riprel (gdbarch, dsc, from, to, regs);
1411 }
1412 }
1413}
1414
1415struct displaced_step_closure *
1416amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1417 CORE_ADDR from, CORE_ADDR to,
1418 struct regcache *regs)
1419{
1420 int len = gdbarch_max_insn_length (gdbarch);
741e63d7 1421 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
35669430
DE		 1422 continually watch for running off the end of the buffer. */
1423 int fixup_sentinel_space = len;
cfba9872
SM		 1424 amd64_displaced_step_closure *dsc
1425 = new amd64_displaced_step_closure (len + fixup_sentinel_space);
35669430
DE		 1426 gdb_byte *buf = &dsc->insn_buf[0];
1427 struct amd64_insn *details = &dsc->insn_details;
1428
35669430
DE		 1429 read_memory (from, buf, len);
1430
1431 /* Set up the sentinel space so we don't have to worry about running
1432 off the end of the buffer. An excessive number of leading prefixes
1433 could otherwise cause this. */
1434 memset (buf + len, 0, fixup_sentinel_space);
1435
1436 amd64_get_insn_details (buf, details);
1437
1438 /* GDB may get control back after the insn after the syscall.
1439 Presumably this is a kernel bug.
1440 If this is a syscall, make sure there's a nop afterwards. */
1441 {
1442 int syscall_length;
1443
1444 if (amd64_syscall_p (details, &syscall_length))
1445 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1446 }
1447
1448 /* Modify the insn to cope with the address where it will be executed from.
1449 In particular, handle any rip-relative addressing. */
1450 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1451
1452 write_memory (to, buf, len);
1453
1454 if (debug_displaced)
1455 {
5af949e3
UW		 1456 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1457 paddress (gdbarch, from), paddress (gdbarch, to));
35669430
DE		 1458 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1459 }
1460
1461 return dsc;
1462}
1463
1464static int
1465amd64_absolute_jmp_p (const struct amd64_insn *details)
1466{
1467 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1468
1469 if (insn[0] == 0xff)
1470 {
1471 /* jump near, absolute indirect (/4) */
1472 if ((insn[1] & 0x38) == 0x20)
1473 return 1;
1474
1475 /* jump far, absolute indirect (/5) */
1476 if ((insn[1] & 0x38) == 0x28)
1477 return 1;
1478 }
1479
1480 return 0;
1481}
1482
c2170eef
MM		 1483/* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1484
1485static int
1486amd64_jmp_p (const struct amd64_insn *details)
1487{
1488 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1489
1490 /* jump short, relative. */
1491 if (insn[0] == 0xeb)
1492 return 1;
1493
1494 /* jump near, relative. */
1495 if (insn[0] == 0xe9)
1496 return 1;
1497
1498 return amd64_absolute_jmp_p (details);
1499}
1500
35669430
DE		 1501static int
1502amd64_absolute_call_p (const struct amd64_insn *details)
1503{
1504 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1505
1506 if (insn[0] == 0xff)
1507 {
1508 /* Call near, absolute indirect (/2) */
1509 if ((insn[1] & 0x38) == 0x10)
1510 return 1;
1511
1512 /* Call far, absolute indirect (/3) */
1513 if ((insn[1] & 0x38) == 0x18)
1514 return 1;
1515 }
1516
1517 return 0;
1518}
1519
1520static int
1521amd64_ret_p (const struct amd64_insn *details)
1522{
1523 /* NOTE: gcc can emit "repz ; ret". */
1524 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1525
1526 switch (insn[0])
1527 {
1528 case 0xc2: /* ret near, pop N bytes */
1529 case 0xc3: /* ret near */
1530 case 0xca: /* ret far, pop N bytes */
1531 case 0xcb: /* ret far */
1532 case 0xcf: /* iret */
1533 return 1;
1534
1535 default:
1536 return 0;
1537 }
1538}
1539
1540static int
1541amd64_call_p (const struct amd64_insn *details)
1542{
1543 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1544
1545 if (amd64_absolute_call_p (details))
1546 return 1;
1547
1548 /* call near, relative */
1549 if (insn[0] == 0xe8)
1550 return 1;
1551
1552 return 0;
1553}
1554
35669430
DE		 1555/* Return non-zero if INSN is a system call, and set *LENGTHP to its
1556 length in bytes. Otherwise, return zero. */
1557
1558static int
1559amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1560{
1561 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1562
1563 if (insn[0] == 0x0f && insn[1] == 0x05)
1564 {
1565 *lengthp = 2;
1566 return 1;
1567 }
1568
1569 return 0;
1570}
1571
c2170eef
MM		 1572/* Classify the instruction at ADDR using PRED.
1573 Throw an error if the memory can't be read. */
1574
1575static int
1576amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1577 int (*pred) (const struct amd64_insn *))
1578{
1579 struct amd64_insn details;
1580 gdb_byte *buf;
1581 int len, classification;
1582
1583 len = gdbarch_max_insn_length (gdbarch);
224c3ddb 1584 buf = (gdb_byte *) alloca (len);
c2170eef
MM		 1585
1586 read_code (addr, buf, len);
1587 amd64_get_insn_details (buf, &details);
1588
1589 classification = pred (&details);
1590
1591 return classification;
1592}
1593
1594/* The gdbarch insn_is_call method. */
1595
1596static int
1597amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1598{
1599 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1600}
1601
1602/* The gdbarch insn_is_ret method. */
1603
1604static int
1605amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1606{
1607 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1608}
1609
1610/* The gdbarch insn_is_jump method. */
1611
1612static int
1613amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1614{
1615 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1616}
1617
35669430
DE		 1618/* Fix up the state of registers and memory after having single-stepped
1619 a displaced instruction. */
1620
1621void
1622amd64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 1623 struct displaced_step_closure *dsc_,
35669430
DE		 1624 CORE_ADDR from, CORE_ADDR to,
1625 struct regcache *regs)
1626{
cfba9872 1627 amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_;
e17a4113 1628 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
35669430
DE		 1629 /* The offset we applied to the instruction's address. */
1630 ULONGEST insn_offset = to - from;
cfba9872 1631 gdb_byte *insn = dsc->insn_buf.data ();
35669430
DE		 1632 const struct amd64_insn *insn_details = &dsc->insn_details;
1633
1634 if (debug_displaced)
1635 fprintf_unfiltered (gdb_stdlog,
5af949e3 1636 "displaced: fixup (%s, %s), "
35669430 1637 "insn = 0x%02x 0x%02x ...\n",
5af949e3
UW		 1638 paddress (gdbarch, from), paddress (gdbarch, to),
1639 insn[0], insn[1]);
35669430
DE		 1640
1641 /* If we used a tmp reg, restore it. */
1642
1643 if (dsc->tmp_used)
1644 {
1645 if (debug_displaced)
5af949e3
UW		 1646 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1647 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
35669430
DE		 1648 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1649 }
1650
1651 /* The list of issues to contend with here is taken from
1652 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1653 Yay for Free Software! */
1654
1655 /* Relocate the %rip back to the program's instruction stream,
1656 if necessary. */
1657
1658 /* Except in the case of absolute or indirect jump or call
1659 instructions, or a return instruction, the new rip is relative to
1660 the displaced instruction; make it relative to the original insn.
1661 Well, signal handler returns don't need relocation either, but we use the
1662 value of %rip to recognize those; see below. */
1663 if (! amd64_absolute_jmp_p (insn_details)
1664 && ! amd64_absolute_call_p (insn_details)
1665 && ! amd64_ret_p (insn_details))
1666 {
1667 ULONGEST orig_rip;
1668 int insn_len;
1669
1670 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1671
1672 /* A signal trampoline system call changes the %rip, resuming
1673 execution of the main program after the signal handler has
1674 returned. That makes them like 'return' instructions; we
1675 shouldn't relocate %rip.
1676
1677 But most system calls don't, and we do need to relocate %rip.
1678
1679 Our heuristic for distinguishing these cases: if stepping
1680 over the system call instruction left control directly after
1681 the instruction, the we relocate --- control almost certainly
1682 doesn't belong in the displaced copy. Otherwise, we assume
1683 the instruction has put control where it belongs, and leave
1684 it unrelocated. Goodness help us if there are PC-relative
1685 system calls. */
1686 if (amd64_syscall_p (insn_details, &insn_len)
1687 && orig_rip != to + insn_len
1688 /* GDB can get control back after the insn after the syscall.
1689 Presumably this is a kernel bug.
1690 Fixup ensures its a nop, we add one to the length for it. */
1691 && orig_rip != to + insn_len + 1)
1692 {
1693 if (debug_displaced)
1694 fprintf_unfiltered (gdb_stdlog,
1695 "displaced: syscall changed %%rip; "
1696 "not relocating\n");
1697 }
1698 else
1699 {
1700 ULONGEST rip = orig_rip - insn_offset;
1701
1903f0e6
DE		 1702 /* If we just stepped over a breakpoint insn, we don't backup
1703 the pc on purpose; this is to match behaviour without
1704 stepping. */
35669430
DE		 1705
1706 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1707
1708 if (debug_displaced)
1709 fprintf_unfiltered (gdb_stdlog,
1710 "displaced: "
5af949e3
UW		 1711 "relocated %%rip from %s to %s\n",
1712 paddress (gdbarch, orig_rip),
1713 paddress (gdbarch, rip));
35669430
DE		 1714 }
1715 }
1716
1717 /* If the instruction was PUSHFL, then the TF bit will be set in the
1718 pushed value, and should be cleared. We'll leave this for later,
1719 since GDB already messes up the TF flag when stepping over a
1720 pushfl. */
1721
1722 /* If the instruction was a call, the return address now atop the
1723 stack is the address following the copied instruction. We need
1724 to make it the address following the original instruction. */
1725 if (amd64_call_p (insn_details))
1726 {
1727 ULONGEST rsp;
1728 ULONGEST retaddr;
1729 const ULONGEST retaddr_len = 8;
1730
1731 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
e17a4113 1732 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
4dafcdeb 1733 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
e17a4113 1734 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
35669430
DE		 1735
1736 if (debug_displaced)
1737 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1738 "displaced: relocated return addr at %s "
1739 "to %s\n",
1740 paddress (gdbarch, rsp),
1741 paddress (gdbarch, retaddr));
35669430
DE		 1742 }
1743}
dde08ee1
PA		 1744
1745/* If the instruction INSN uses RIP-relative addressing, return the
1746 offset into the raw INSN where the displacement to be adjusted is
1747 found. Returns 0 if the instruction doesn't use RIP-relative
1748 addressing. */
1749
1750static int
1751rip_relative_offset (struct amd64_insn *insn)
1752{
1753 if (insn->modrm_offset != -1)
1754 {
1755 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1756
1757 if ((modrm & 0xc7) == 0x05)
1758 {
1759 /* The displacement is found right after the ModRM byte. */
1760 return insn->modrm_offset + 1;
1761 }
1762 }
1763
1764 return 0;
1765}
1766
1767static void
1768append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1769{
1770 target_write_memory (*to, buf, len);
1771 *to += len;
1772}
1773
60965737 1774static void
dde08ee1
PA		 1775amd64_relocate_instruction (struct gdbarch *gdbarch,
1776 CORE_ADDR *to, CORE_ADDR oldloc)
1777{
1778 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1779 int len = gdbarch_max_insn_length (gdbarch);
1780 /* Extra space for sentinels. */
1781 int fixup_sentinel_space = len;
224c3ddb 1782 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
dde08ee1
PA		 1783 struct amd64_insn insn_details;
1784 int offset = 0;
1785 LONGEST rel32, newrel;
1786 gdb_byte *insn;
1787 int insn_length;
1788
1789 read_memory (oldloc, buf, len);
1790
1791 /* Set up the sentinel space so we don't have to worry about running
1792 off the end of the buffer. An excessive number of leading prefixes
1793 could otherwise cause this. */
1794 memset (buf + len, 0, fixup_sentinel_space);
1795
1796 insn = buf;
1797 amd64_get_insn_details (insn, &insn_details);
1798
1799 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1800
1801 /* Skip legacy instruction prefixes. */
1802 insn = amd64_skip_prefixes (insn);
1803
1804 /* Adjust calls with 32-bit relative addresses as push/jump, with
1805 the address pushed being the location where the original call in
1806 the user program would return to. */
1807 if (insn[0] == 0xe8)
1808 {
f077e978
PA		 1809 gdb_byte push_buf[32];
1810 CORE_ADDR ret_addr;
1811 int i = 0;
dde08ee1
PA		 1812
1813 /* Where "ret" in the original code will return to. */
1814 ret_addr = oldloc + insn_length;
f077e978
PA		 1815
1816 /* If pushing an address higher than or equal to 0x80000000,
1817 avoid 'pushq', as that sign extends its 32-bit operand, which
1818 would be incorrect. */
1819 if (ret_addr <= 0x7fffffff)
1820 {
1821 push_buf[0] = 0x68; /* pushq $... */
1822 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1823 i = 5;
1824 }
1825 else
1826 {
1827 push_buf[i++] = 0x48; /* sub $0x8,%rsp */
1828 push_buf[i++] = 0x83;
1829 push_buf[i++] = 0xec;
1830 push_buf[i++] = 0x08;
1831
1832 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
1833 push_buf[i++] = 0x04;
1834 push_buf[i++] = 0x24;
1835 store_unsigned_integer (&push_buf[i], 4, byte_order,
1836 ret_addr & 0xffffffff);
1837 i += 4;
1838
1839 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
1840 push_buf[i++] = 0x44;
1841 push_buf[i++] = 0x24;
1842 push_buf[i++] = 0x04;
1843 store_unsigned_integer (&push_buf[i], 4, byte_order,
1844 ret_addr >> 32);
1845 i += 4;
1846 }
1847 gdb_assert (i <= sizeof (push_buf));
dde08ee1 1848 /* Push the push. */
f077e978 1849 append_insns (to, i, push_buf);
dde08ee1
PA		 1850
1851 /* Convert the relative call to a relative jump. */
1852 insn[0] = 0xe9;
1853
1854 /* Adjust the destination offset. */
1855 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1856 newrel = (oldloc - *to) + rel32;
f4a1794a
KY		 1857 store_signed_integer (insn + 1, 4, byte_order, newrel);
1858
1859 if (debug_displaced)
1860 fprintf_unfiltered (gdb_stdlog,
1861 "Adjusted insn rel32=%s at %s to"
1862 " rel32=%s at %s\n",
1863 hex_string (rel32), paddress (gdbarch, oldloc),
1864 hex_string (newrel), paddress (gdbarch, *to));
dde08ee1
PA		 1865
1866 /* Write the adjusted jump into its displaced location. */
1867 append_insns (to, 5, insn);
1868 return;
1869 }
1870
1871 offset = rip_relative_offset (&insn_details);
1872 if (!offset)
1873 {
1874 /* Adjust jumps with 32-bit relative addresses. Calls are
1875 already handled above. */
1876 if (insn[0] == 0xe9)
1877 offset = 1;
1878 /* Adjust conditional jumps. */
1879 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1880 offset = 2;
1881 }
1882
1883 if (offset)
1884 {
1885 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1886 newrel = (oldloc - *to) + rel32;
f4a1794a 1887 store_signed_integer (insn + offset, 4, byte_order, newrel);
dde08ee1
PA		 1888 if (debug_displaced)
1889 fprintf_unfiltered (gdb_stdlog,
f4a1794a
KY		 1890 "Adjusted insn rel32=%s at %s to"
1891 " rel32=%s at %s\n",
dde08ee1
PA		 1892 hex_string (rel32), paddress (gdbarch, oldloc),
1893 hex_string (newrel), paddress (gdbarch, *to));
1894 }
1895
1896 /* Write the adjusted instruction into its displaced location. */
1897 append_insns (to, insn_length, buf);
1898}
1899
35669430 1900\f
c4f35dd8 1901/* The maximum number of saved registers. This should include %rip. */
90f90721 1902#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
c4f35dd8 1903
e53bef9f 1904struct amd64_frame_cache
c4f35dd8
MK		 1905{
1906 /* Base address. */
1907 CORE_ADDR base;
8fbca658 1908 int base_p;
c4f35dd8
MK		 1909 CORE_ADDR sp_offset;
1910 CORE_ADDR pc;
1911
1912 /* Saved registers. */
e53bef9f 1913 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
c4f35dd8 1914 CORE_ADDR saved_sp;
e0c62198 1915 int saved_sp_reg;
c4f35dd8
MK		 1916
1917 /* Do we have a frame? */
1918 int frameless_p;
1919};
8dda9770 1920
d2449ee8 1921/* Initialize a frame cache. */
c4f35dd8 1922
d2449ee8
DJ		 1923static void
1924amd64_init_frame_cache (struct amd64_frame_cache *cache)
8dda9770 1925{
c4f35dd8
MK		 1926 int i;
1927
c4f35dd8
MK		 1928 /* Base address. */
1929 cache->base = 0;
8fbca658 1930 cache->base_p = 0;
c4f35dd8
MK		 1931 cache->sp_offset = -8;
1932 cache->pc = 0;
1933
1934 /* Saved registers. We initialize these to -1 since zero is a valid
bba66b87
DE		 1935 offset (that's where %rbp is supposed to be stored).
1936 The values start out as being offsets, and are later converted to
1937 addresses (at which point -1 is interpreted as an address, still meaning
1938 "invalid"). */
e53bef9f 1939 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 1940 cache->saved_regs[i] = -1;
1941 cache->saved_sp = 0;
e0c62198 1942 cache->saved_sp_reg = -1;
c4f35dd8
MK		 1943
1944 /* Frameless until proven otherwise. */
1945 cache->frameless_p = 1;
d2449ee8 1946}
c4f35dd8 1947
d2449ee8
DJ		 1948/* Allocate and initialize a frame cache. */
1949
1950static struct amd64_frame_cache *
1951amd64_alloc_frame_cache (void)
1952{
1953 struct amd64_frame_cache *cache;
1954
1955 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1956 amd64_init_frame_cache (cache);
c4f35dd8 1957 return cache;
8dda9770 1958}
53e95fcf 1959
e0c62198
L		 1960/* GCC 4.4 and later, can put code in the prologue to realign the
1961 stack pointer. Check whether PC points to such code, and update
1962 CACHE accordingly. Return the first instruction after the code
1963 sequence or CURRENT_PC, whichever is smaller. If we don't
1964 recognize the code, return PC. */
1965
1966static CORE_ADDR
1967amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1968 struct amd64_frame_cache *cache)
1969{
1970 /* There are 2 code sequences to re-align stack before the frame
1971 gets set up:
1972
1973 1. Use a caller-saved saved register:
1974
1975 leaq 8(%rsp), %reg
1976 andq $-XXX, %rsp
1977 pushq -8(%reg)
1978
1979 2. Use a callee-saved saved register:
1980
1981 pushq %reg
1982 leaq 16(%rsp), %reg
1983 andq $-XXX, %rsp
1984 pushq -8(%reg)
1985
1986 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1987
1988 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1989 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1990 */
1991
1992 gdb_byte buf[18];
1993 int reg, r;
1994 int offset, offset_and;
e0c62198 1995
bae8a07a 1996 if (target_read_code (pc, buf, sizeof buf))
e0c62198
L		 1997 return pc;
1998
1999 /* Check caller-saved saved register. The first instruction has
2000 to be "leaq 8(%rsp), %reg". */
2001 if ((buf[0] & 0xfb) == 0x48
2002 && buf[1] == 0x8d
2003 && buf[3] == 0x24
2004 && buf[4] == 0x8)
2005 {
2006 /* MOD must be binary 10 and R/M must be binary 100. */
2007 if ((buf[2] & 0xc7) != 0x44)
2008 return pc;
2009
2010 /* REG has register number. */
2011 reg = (buf[2] >> 3) & 7;
2012
2013 /* Check the REX.R bit. */
2014 if (buf[0] == 0x4c)
2015 reg += 8;
2016
2017 offset = 5;
2018 }
2019 else
2020 {
2021 /* Check callee-saved saved register. The first instruction
2022 has to be "pushq %reg". */
2023 reg = 0;
2024 if ((buf[0] & 0xf8) == 0x50)
2025 offset = 0;
2026 else if ((buf[0] & 0xf6) == 0x40
2027 && (buf[1] & 0xf8) == 0x50)
2028 {
2029 /* Check the REX.B bit. */
2030 if ((buf[0] & 1) != 0)
2031 reg = 8;
2032
2033 offset = 1;
2034 }
2035 else
2036 return pc;
2037
2038 /* Get register. */
2039 reg += buf[offset] & 0x7;
2040
2041 offset++;
2042
2043 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2044 if ((buf[offset] & 0xfb) != 0x48
2045 || buf[offset + 1] != 0x8d
2046 || buf[offset + 3] != 0x24
2047 || buf[offset + 4] != 0x10)
2048 return pc;
2049
2050 /* MOD must be binary 10 and R/M must be binary 100. */
2051 if ((buf[offset + 2] & 0xc7) != 0x44)
2052 return pc;
2053
2054 /* REG has register number. */
2055 r = (buf[offset + 2] >> 3) & 7;
2056
2057 /* Check the REX.R bit. */
2058 if (buf[offset] == 0x4c)
2059 r += 8;
2060
2061 /* Registers in pushq and leaq have to be the same. */
2062 if (reg != r)
2063 return pc;
2064
2065 offset += 5;
2066 }
2067
2068 /* Rigister can't be %rsp nor %rbp. */
2069 if (reg == 4 || reg == 5)
2070 return pc;
2071
2072 /* The next instruction has to be "andq $-XXX, %rsp". */
2073 if (buf[offset] != 0x48
2074 || buf[offset + 2] != 0xe4
2075 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2076 return pc;
2077
2078 offset_and = offset;
2079 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2080
2081 /* The next instruction has to be "pushq -8(%reg)". */
2082 r = 0;
2083 if (buf[offset] == 0xff)
2084 offset++;
2085 else if ((buf[offset] & 0xf6) == 0x40
2086 && buf[offset + 1] == 0xff)
2087 {
2088 /* Check the REX.B bit. */
2089 if ((buf[offset] & 0x1) != 0)
2090 r = 8;
2091 offset += 2;
2092 }
2093 else
2094 return pc;
2095
2096 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2097 01. */
2098 if (buf[offset + 1] != 0xf8
2099 || (buf[offset] & 0xf8) != 0x70)
2100 return pc;
2101
2102 /* R/M has register. */
2103 r += buf[offset] & 7;
2104
2105 /* Registers in leaq and pushq have to be the same. */
2106 if (reg != r)
2107 return pc;
2108
2109 if (current_pc > pc + offset_and)
35669430 2110 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
e0c62198 2111
325fac50 2112 return std::min (pc + offset + 2, current_pc);
e0c62198
L		 2113}
2114
ac142d96
L		 2115/* Similar to amd64_analyze_stack_align for x32. */
2116
2117static CORE_ADDR
2118amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2119 struct amd64_frame_cache *cache)
2120{
2121 /* There are 2 code sequences to re-align stack before the frame
2122 gets set up:
2123
2124 1. Use a caller-saved saved register:
2125
2126 leaq 8(%rsp), %reg
2127 andq $-XXX, %rsp
2128 pushq -8(%reg)
2129
2130 or
2131
2132 [addr32] leal 8(%rsp), %reg
2133 andl $-XXX, %esp
2134 [addr32] pushq -8(%reg)
2135
2136 2. Use a callee-saved saved register:
2137
2138 pushq %reg
2139 leaq 16(%rsp), %reg
2140 andq $-XXX, %rsp
2141 pushq -8(%reg)
2142
2143 or
2144
2145 pushq %reg
2146 [addr32] leal 16(%rsp), %reg
2147 andl $-XXX, %esp
2148 [addr32] pushq -8(%reg)
2149
2150 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2151
2152 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2153 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2154
2155 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2156
2157 0x83 0xe4 0xf0 andl $-16, %esp
2158 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2159 */
2160
2161 gdb_byte buf[19];
2162 int reg, r;
2163 int offset, offset_and;
2164
2165 if (target_read_memory (pc, buf, sizeof buf))
2166 return pc;
2167
2168 /* Skip optional addr32 prefix. */
2169 offset = buf[0] == 0x67 ? 1 : 0;
2170
2171 /* Check caller-saved saved register. The first instruction has
2172 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2173 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2174 && buf[offset + 1] == 0x8d
2175 && buf[offset + 3] == 0x24
2176 && buf[offset + 4] == 0x8)
2177 {
2178 /* MOD must be binary 10 and R/M must be binary 100. */
2179 if ((buf[offset + 2] & 0xc7) != 0x44)
2180 return pc;
2181
2182 /* REG has register number. */
2183 reg = (buf[offset + 2] >> 3) & 7;
2184
2185 /* Check the REX.R bit. */
2186 if ((buf[offset] & 0x4) != 0)
2187 reg += 8;
2188
2189 offset += 5;
2190 }
2191 else
2192 {
2193 /* Check callee-saved saved register. The first instruction
2194 has to be "pushq %reg". */
2195 reg = 0;
2196 if ((buf[offset] & 0xf6) == 0x40
2197 && (buf[offset + 1] & 0xf8) == 0x50)
2198 {
2199 /* Check the REX.B bit. */
2200 if ((buf[offset] & 1) != 0)
2201 reg = 8;
2202
2203 offset += 1;
2204 }
2205 else if ((buf[offset] & 0xf8) != 0x50)
2206 return pc;
2207
2208 /* Get register. */
2209 reg += buf[offset] & 0x7;
2210
2211 offset++;
2212
2213 /* Skip optional addr32 prefix. */
2214 if (buf[offset] == 0x67)
2215 offset++;
2216
2217 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2218 "leal 16(%rsp), %reg". */
2219 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2220 || buf[offset + 1] != 0x8d
2221 || buf[offset + 3] != 0x24
2222 || buf[offset + 4] != 0x10)
2223 return pc;
2224
2225 /* MOD must be binary 10 and R/M must be binary 100. */
2226 if ((buf[offset + 2] & 0xc7) != 0x44)
2227 return pc;
2228
2229 /* REG has register number. */
2230 r = (buf[offset + 2] >> 3) & 7;
2231
2232 /* Check the REX.R bit. */
2233 if ((buf[offset] & 0x4) != 0)
2234 r += 8;
2235
2236 /* Registers in pushq and leaq have to be the same. */
2237 if (reg != r)
2238 return pc;
2239
2240 offset += 5;
2241 }
2242
2243 /* Rigister can't be %rsp nor %rbp. */
2244 if (reg == 4 || reg == 5)
2245 return pc;
2246
2247 /* The next instruction may be "andq $-XXX, %rsp" or
2248 "andl $-XXX, %esp". */
2249 if (buf[offset] != 0x48)
2250 offset--;
2251
2252 if (buf[offset + 2] != 0xe4
2253 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2254 return pc;
2255
2256 offset_and = offset;
2257 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2258
2259 /* Skip optional addr32 prefix. */
2260 if (buf[offset] == 0x67)
2261 offset++;
2262
2263 /* The next instruction has to be "pushq -8(%reg)". */
2264 r = 0;
2265 if (buf[offset] == 0xff)
2266 offset++;
2267 else if ((buf[offset] & 0xf6) == 0x40
2268 && buf[offset + 1] == 0xff)
2269 {
2270 /* Check the REX.B bit. */
2271 if ((buf[offset] & 0x1) != 0)
2272 r = 8;
2273 offset += 2;
2274 }
2275 else
2276 return pc;
2277
2278 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2279 01. */
2280 if (buf[offset + 1] != 0xf8
2281 || (buf[offset] & 0xf8) != 0x70)
2282 return pc;
2283
2284 /* R/M has register. */
2285 r += buf[offset] & 7;
2286
2287 /* Registers in leaq and pushq have to be the same. */
2288 if (reg != r)
2289 return pc;
2290
2291 if (current_pc > pc + offset_and)
2292 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2293
325fac50 2294 return std::min (pc + offset + 2, current_pc);
ac142d96
L		 2295}
2296
c4f35dd8
MK		 2297/* Do a limited analysis of the prologue at PC and update CACHE
2298 accordingly. Bail out early if CURRENT_PC is reached. Return the
2299 address where the analysis stopped.
2300
2301 We will handle only functions beginning with:
2302
2303 pushq %rbp 0x55
50f1ae7b 2304 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
c4f35dd8 2305
649e6d92
MK		 2306 or (for the X32 ABI):
2307
2308 pushq %rbp 0x55
2309 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2310
2311 Any function that doesn't start with one of these sequences will be
2312 assumed to have no prologue and thus no valid frame pointer in
2313 %rbp. */
c4f35dd8
MK		 2314
2315static CORE_ADDR
e17a4113
UW		 2316amd64_analyze_prologue (struct gdbarch *gdbarch,
2317 CORE_ADDR pc, CORE_ADDR current_pc,
e53bef9f 2318 struct amd64_frame_cache *cache)
53e95fcf 2319{
e17a4113 2320 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
50f1ae7b
DE		 2321 /* There are two variations of movq %rsp, %rbp. */
2322 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2323 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
649e6d92
MK		 2324 /* Ditto for movl %esp, %ebp. */
2325 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2326 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2327
d8de1ef7
MK		 2328 gdb_byte buf[3];
2329 gdb_byte op;
c4f35dd8
MK		 2330
2331 if (current_pc <= pc)
2332 return current_pc;
2333
ac142d96
L		 2334 if (gdbarch_ptr_bit (gdbarch) == 32)
2335 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2336 else
2337 pc = amd64_analyze_stack_align (pc, current_pc, cache);
e0c62198 2338
bae8a07a 2339 op = read_code_unsigned_integer (pc, 1, byte_order);
c4f35dd8
MK		 2340
2341 if (op == 0x55) /* pushq %rbp */
2342 {
2343 /* Take into account that we've executed the `pushq %rbp' that
2344 starts this instruction sequence. */
90f90721 2345 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
c4f35dd8
MK		 2346 cache->sp_offset += 8;
2347
2348 /* If that's all, return now. */
2349 if (current_pc <= pc + 1)
2350 return current_pc;
2351
bae8a07a 2352 read_code (pc + 1, buf, 3);
c4f35dd8 2353
649e6d92
MK		 2354 /* Check for `movq %rsp, %rbp'. */
2355 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2356 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2357 {
2358 /* OK, we actually have a frame. */
2359 cache->frameless_p = 0;
2360 return pc + 4;
2361 }
2362
2363 /* For X32, also check for `movq %esp, %ebp'. */
2364 if (gdbarch_ptr_bit (gdbarch) == 32)
2365 {
2366 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2367 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2368 {
2369 /* OK, we actually have a frame. */
2370 cache->frameless_p = 0;
2371 return pc + 3;
2372 }
2373 }
2374
2375 return pc + 1;
c4f35dd8
MK		 2376 }
2377
2378 return pc;
53e95fcf
JS		 2379}
2380
df15bd07
JK		 2381/* Work around false termination of prologue - GCC PR debug/48827.
2382
2383 START_PC is the first instruction of a function, PC is its minimal already
2384 determined advanced address. Function returns PC if it has nothing to do.
2385
2386 84 c0 test %al,%al
2387 74 23 je after
2388 <-- here is 0 lines advance - the false prologue end marker.
2389 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2390 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2391 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2392 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2393 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2394 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2395 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2396 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2397 after: */
c4f35dd8
MK		 2398
2399static CORE_ADDR
df15bd07 2400amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
53e95fcf 2401{
08711b9a
JK		 2402 struct symtab_and_line start_pc_sal, next_sal;
2403 gdb_byte buf[4 + 8 * 7];
2404 int offset, xmmreg;
c4f35dd8 2405
08711b9a
JK		 2406 if (pc == start_pc)
2407 return pc;
2408
2409 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2410 if (start_pc_sal.symtab == NULL
43f3e411
DE		 2411 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2412 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
08711b9a
JK		 2413 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2414 return pc;
2415
2416 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2417 if (next_sal.line != start_pc_sal.line)
2418 return pc;
2419
2420 /* START_PC can be from overlayed memory, ignored here. */
bae8a07a 2421 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
08711b9a
JK		 2422 return pc;
2423
2424 /* test %al,%al */
2425 if (buf[0] != 0x84 || buf[1] != 0xc0)
2426 return pc;
2427 /* je AFTER */
2428 if (buf[2] != 0x74)
2429 return pc;
2430
2431 offset = 4;
2432 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2433 {
bede5f5f 2434 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
08711b9a 2435 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
bede5f5f 2436 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
08711b9a
JK		 2437 return pc;
2438
bede5f5f
JK		 2439 /* 0b01?????? */
2440 if ((buf[offset + 2] & 0xc0) == 0x40)
08711b9a
JK		 2441 {
2442 /* 8-bit displacement. */
2443 offset += 4;
2444 }
bede5f5f
JK		 2445 /* 0b10?????? */
2446 else if ((buf[offset + 2] & 0xc0) == 0x80)
08711b9a
JK		 2447 {
2448 /* 32-bit displacement. */
2449 offset += 7;
2450 }
2451 else
2452 return pc;
2453 }
2454
2455 /* je AFTER */
2456 if (offset - 4 != buf[3])
2457 return pc;
2458
2459 return next_sal.end;
53e95fcf 2460}
df15bd07
JK		 2461
2462/* Return PC of first real instruction. */
2463
2464static CORE_ADDR
2465amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2466{
2467 struct amd64_frame_cache cache;
2468 CORE_ADDR pc;
56bf0743
KB		 2469 CORE_ADDR func_addr;
2470
2471 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2472 {
2473 CORE_ADDR post_prologue_pc
2474 = skip_prologue_using_sal (gdbarch, func_addr);
43f3e411 2475 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
56bf0743
KB		 2476
2477 /* Clang always emits a line note before the prologue and another
2478 one after. We trust clang to emit usable line notes. */
2479 if (post_prologue_pc
43f3e411
DE		 2480 && (cust != NULL
2481 && COMPUNIT_PRODUCER (cust) != NULL
61012eef 2482 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
325fac50 2483 return std::max (start_pc, post_prologue_pc);
56bf0743 2484 }
df15bd07
JK		 2485
2486 amd64_init_frame_cache (&cache);
2487 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2488 &cache);
2489 if (cache.frameless_p)
2490 return start_pc;
2491
2492 return amd64_skip_xmm_prologue (pc, start_pc);
2493}
c4f35dd8 2494\f
53e95fcf 2495
c4f35dd8
MK		 2496/* Normal frames. */
2497
8fbca658
PA		 2498static void
2499amd64_frame_cache_1 (struct frame_info *this_frame,
2500 struct amd64_frame_cache *cache)
6d686a84 2501{
e17a4113
UW		 2502 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2503 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 2504 gdb_byte buf[8];
6d686a84 2505 int i;
6d686a84 2506
10458914 2507 cache->pc = get_frame_func (this_frame);
c4f35dd8 2508 if (cache->pc != 0)
e17a4113
UW		 2509 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2510 cache);
c4f35dd8
MK		 2511
2512 if (cache->frameless_p)
2513 {
4a28816e
MK		 2514 /* We didn't find a valid frame. If we're at the start of a
2515 function, or somewhere half-way its prologue, the function's
2516 frame probably hasn't been fully setup yet. Try to
2517 reconstruct the base address for the stack frame by looking
2518 at the stack pointer. For truly "frameless" functions this
2519 might work too. */
c4f35dd8 2520
e0c62198
L		 2521 if (cache->saved_sp_reg != -1)
2522 {
8fbca658
PA		 2523 /* Stack pointer has been saved. */
2524 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2525 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2526
e0c62198
L		 2527 /* We're halfway aligning the stack. */
2528 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2529 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2530
2531 /* This will be added back below. */
2532 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2533 }
2534 else
2535 {
2536 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
e17a4113
UW		 2537 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2538 + cache->sp_offset;
e0c62198 2539 }
c4f35dd8 2540 }
35883a3f
MK		 2541 else
2542 {
10458914 2543 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
e17a4113 2544 cache->base = extract_unsigned_integer (buf, 8, byte_order);
35883a3f 2545 }
c4f35dd8
MK		 2546
2547 /* Now that we have the base address for the stack frame we can
2548 calculate the value of %rsp in the calling frame. */
2549 cache->saved_sp = cache->base + 16;
2550
35883a3f
MK		 2551 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2552 frame we find it at the same offset from the reconstructed base
e0c62198
L		 2553 address. If we're halfway aligning the stack, %rip is handled
2554 differently (see above). */
2555 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2556 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
35883a3f 2557
c4f35dd8
MK		 2558 /* Adjust all the saved registers such that they contain addresses
2559 instead of offsets. */
e53bef9f 2560 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 2561 if (cache->saved_regs[i] != -1)
2562 cache->saved_regs[i] += cache->base;
2563
8fbca658
PA		 2564 cache->base_p = 1;
2565}
2566
2567static struct amd64_frame_cache *
2568amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2569{
8fbca658
PA		 2570 struct amd64_frame_cache *cache;
2571
2572 if (*this_cache)
9a3c8263 2573 return (struct amd64_frame_cache *) *this_cache;
8fbca658
PA		 2574
2575 cache = amd64_alloc_frame_cache ();
2576 *this_cache = cache;
2577
492d29ea 2578 TRY
8fbca658
PA		 2579 {
2580 amd64_frame_cache_1 (this_frame, cache);
2581 }
492d29ea 2582 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2583 {
2584 if (ex.error != NOT_AVAILABLE_ERROR)
2585 throw_exception (ex);
2586 }
492d29ea 2587 END_CATCH
8fbca658 2588
c4f35dd8 2589 return cache;
6d686a84
ML		 2590}
2591
8fbca658
PA		 2592static enum unwind_stop_reason
2593amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2594 void **this_cache)
2595{
2596 struct amd64_frame_cache *cache =
2597 amd64_frame_cache (this_frame, this_cache);
2598
2599 if (!cache->base_p)
2600 return UNWIND_UNAVAILABLE;
2601
2602 /* This marks the outermost frame. */
2603 if (cache->base == 0)
2604 return UNWIND_OUTERMOST;
2605
2606 return UNWIND_NO_REASON;
2607}
2608
c4f35dd8 2609static void
10458914 2610amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
e53bef9f 2611 struct frame_id *this_id)
c4f35dd8 2612{
e53bef9f 2613 struct amd64_frame_cache *cache =
10458914 2614 amd64_frame_cache (this_frame, this_cache);
c4f35dd8 2615
8fbca658 2616 if (!cache->base_p)
5ce0145d
PA		 2617 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2618 else if (cache->base == 0)
2619 {
2620 /* This marks the outermost frame. */
2621 return;
2622 }
2623 else
2624 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
c4f35dd8 2625}
e76e1718 2626
10458914
DJ		 2627static struct value *
2628amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2629 int regnum)
53e95fcf 2630{
10458914 2631 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e53bef9f 2632 struct amd64_frame_cache *cache =
10458914 2633 amd64_frame_cache (this_frame, this_cache);
e76e1718 2634
c4f35dd8 2635 gdb_assert (regnum >= 0);
b1ab997b 2636
2ae02b47 2637 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
10458914 2638 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
e76e1718 2639
e53bef9f 2640 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
10458914
DJ		 2641 return frame_unwind_got_memory (this_frame, regnum,
2642 cache->saved_regs[regnum]);
e76e1718 2643
10458914 2644 return frame_unwind_got_register (this_frame, regnum, regnum);
c4f35dd8 2645}
e76e1718 2646
e53bef9f 2647static const struct frame_unwind amd64_frame_unwind =
c4f35dd8
MK		 2648{
2649 NORMAL_FRAME,
8fbca658 2650 amd64_frame_unwind_stop_reason,
e53bef9f 2651 amd64_frame_this_id,
10458914
DJ		 2652 amd64_frame_prev_register,
2653 NULL,
2654 default_frame_sniffer
c4f35dd8 2655};
c4f35dd8 2656\f
6710bf39
SS		 2657/* Generate a bytecode expression to get the value of the saved PC. */
2658
2659static void
2660amd64_gen_return_address (struct gdbarch *gdbarch,
2661 struct agent_expr *ax, struct axs_value *value,
2662 CORE_ADDR scope)
2663{
2664 /* The following sequence assumes the traditional use of the base
2665 register. */
2666 ax_reg (ax, AMD64_RBP_REGNUM);
2667 ax_const_l (ax, 8);
2668 ax_simple (ax, aop_add);
2669 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2670 value->kind = axs_lvalue_memory;
2671}
2672\f
e76e1718 2673
c4f35dd8
MK		 2674/* Signal trampolines. */
2675
2676/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2677 64-bit variants. This would require using identical frame caches
2678 on both platforms. */
2679
e53bef9f 2680static struct amd64_frame_cache *
10458914 2681amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2682{
e17a4113
UW		 2683 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2684 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2685 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e53bef9f 2686 struct amd64_frame_cache *cache;
c4f35dd8 2687 CORE_ADDR addr;
d8de1ef7 2688 gdb_byte buf[8];
2b5e0749 2689 int i;
c4f35dd8
MK		 2690
2691 if (*this_cache)
9a3c8263 2692 return (struct amd64_frame_cache *) *this_cache;
c4f35dd8 2693
e53bef9f 2694 cache = amd64_alloc_frame_cache ();
c4f35dd8 2695
492d29ea 2696 TRY
8fbca658
PA		 2697 {
2698 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2699 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2700
2701 addr = tdep->sigcontext_addr (this_frame);
2702 gdb_assert (tdep->sc_reg_offset);
2703 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2704 for (i = 0; i < tdep->sc_num_regs; i++)
2705 if (tdep->sc_reg_offset[i] != -1)
2706 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8 2707
8fbca658
PA		 2708 cache->base_p = 1;
2709 }
492d29ea 2710 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2711 {
2712 if (ex.error != NOT_AVAILABLE_ERROR)
2713 throw_exception (ex);
2714 }
492d29ea 2715 END_CATCH
c4f35dd8
MK		 2716
2717 *this_cache = cache;
2718 return cache;
53e95fcf
JS		 2719}
2720
8fbca658
PA		 2721static enum unwind_stop_reason
2722amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2723 void **this_cache)
2724{
2725 struct amd64_frame_cache *cache =
2726 amd64_sigtramp_frame_cache (this_frame, this_cache);
2727
2728 if (!cache->base_p)
2729 return UNWIND_UNAVAILABLE;
2730
2731 return UNWIND_NO_REASON;
2732}
2733
c4f35dd8 2734static void
10458914 2735amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
e53bef9f 2736 void **this_cache, struct frame_id *this_id)
c4f35dd8 2737{
e53bef9f 2738 struct amd64_frame_cache *cache =
10458914 2739 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2740
8fbca658 2741 if (!cache->base_p)
5ce0145d
PA		 2742 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2743 else if (cache->base == 0)
2744 {
2745 /* This marks the outermost frame. */
2746 return;
2747 }
2748 else
2749 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
c4f35dd8
MK		 2750}
2751
10458914
DJ		 2752static struct value *
2753amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2754 void **this_cache, int regnum)
c4f35dd8
MK		 2755{
2756 /* Make sure we've initialized the cache. */
10458914 2757 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2758
10458914 2759 return amd64_frame_prev_register (this_frame, this_cache, regnum);
c4f35dd8
MK		 2760}
2761
10458914
DJ		 2762static int
2763amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2764 struct frame_info *this_frame,
2765 void **this_cache)
c4f35dd8 2766{
10458914 2767 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
911bc6ee
MK		 2768
2769 /* We shouldn't even bother if we don't have a sigcontext_addr
2770 handler. */
2771 if (tdep->sigcontext_addr == NULL)
10458914 2772 return 0;
911bc6ee
MK		 2773
2774 if (tdep->sigtramp_p != NULL)
2775 {
10458914
DJ		 2776 if (tdep->sigtramp_p (this_frame))
2777 return 1;
911bc6ee 2778 }
c4f35dd8 2779
911bc6ee 2780 if (tdep->sigtramp_start != 0)
1c3545ae 2781 {
10458914 2782 CORE_ADDR pc = get_frame_pc (this_frame);
1c3545ae 2783
911bc6ee
MK		 2784 gdb_assert (tdep->sigtramp_end != 0);
2785 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
10458914 2786 return 1;
1c3545ae 2787 }
c4f35dd8 2788
10458914 2789 return 0;
c4f35dd8 2790}
10458914
DJ		 2791
2792static const struct frame_unwind amd64_sigtramp_frame_unwind =
2793{
2794 SIGTRAMP_FRAME,
8fbca658 2795 amd64_sigtramp_frame_unwind_stop_reason,
10458914
DJ		 2796 amd64_sigtramp_frame_this_id,
2797 amd64_sigtramp_frame_prev_register,
2798 NULL,
2799 amd64_sigtramp_frame_sniffer
2800};
c4f35dd8
MK		 2801\f
2802
2803static CORE_ADDR
10458914 2804amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2805{
e53bef9f 2806 struct amd64_frame_cache *cache =
10458914 2807 amd64_frame_cache (this_frame, this_cache);
c4f35dd8
MK		 2808
2809 return cache->base;
2810}
2811
e53bef9f 2812static const struct frame_base amd64_frame_base =
c4f35dd8 2813{
e53bef9f
MK		 2814 &amd64_frame_unwind,
2815 amd64_frame_base_address,
2816 amd64_frame_base_address,
2817 amd64_frame_base_address
c4f35dd8
MK		 2818};
2819
872761f4
MS		 2820/* Normal frames, but in a function epilogue. */
2821
c9cf6e20
MG		 2822/* Implement the stack_frame_destroyed_p gdbarch method.
2823
2824 The epilogue is defined here as the 'ret' instruction, which will
872761f4
MS		 2825 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2826 the function's stack frame. */
2827
2828static int
c9cf6e20 2829amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
872761f4
MS		 2830{
2831 gdb_byte insn;
43f3e411 2832 struct compunit_symtab *cust;
e0d00bc7 2833
43f3e411
DE		 2834 cust = find_pc_compunit_symtab (pc);
2835 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
e0d00bc7 2836 return 0;
872761f4
MS		 2837
2838 if (target_read_memory (pc, &insn, 1))
2839 return 0; /* Can't read memory at pc. */
2840
2841 if (insn != 0xc3) /* 'ret' instruction. */
2842 return 0;
2843
2844 return 1;
2845}
2846
2847static int
2848amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2849 struct frame_info *this_frame,
2850 void **this_prologue_cache)
2851{
2852 if (frame_relative_level (this_frame) == 0)
c9cf6e20
MG		 2853 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2854 get_frame_pc (this_frame));
872761f4
MS		 2855 else
2856 return 0;
2857}
2858
2859static struct amd64_frame_cache *
2860amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2861{
2862 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2863 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2864 struct amd64_frame_cache *cache;
6c10c06b 2865 gdb_byte buf[8];
872761f4
MS		 2866
2867 if (*this_cache)
9a3c8263 2868 return (struct amd64_frame_cache *) *this_cache;
872761f4
MS		 2869
2870 cache = amd64_alloc_frame_cache ();
2871 *this_cache = cache;
2872
492d29ea 2873 TRY
8fbca658
PA		 2874 {
2875 /* Cache base will be %esp plus cache->sp_offset (-8). */
2876 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2877 cache->base = extract_unsigned_integer (buf, 8,
2878 byte_order) + cache->sp_offset;
2879
2880 /* Cache pc will be the frame func. */
2881 cache->pc = get_frame_pc (this_frame);
872761f4 2882
8fbca658
PA		 2883 /* The saved %esp will be at cache->base plus 16. */
2884 cache->saved_sp = cache->base + 16;
872761f4 2885
8fbca658
PA		 2886 /* The saved %eip will be at cache->base plus 8. */
2887 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
872761f4 2888
8fbca658
PA		 2889 cache->base_p = 1;
2890 }
492d29ea 2891 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2892 {
2893 if (ex.error != NOT_AVAILABLE_ERROR)
2894 throw_exception (ex);
2895 }
492d29ea 2896 END_CATCH
872761f4
MS		 2897
2898 return cache;
2899}
2900
8fbca658
PA		 2901static enum unwind_stop_reason
2902amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2903 void **this_cache)
2904{
2905 struct amd64_frame_cache *cache
2906 = amd64_epilogue_frame_cache (this_frame, this_cache);
2907
2908 if (!cache->base_p)
2909 return UNWIND_UNAVAILABLE;
2910
2911 return UNWIND_NO_REASON;
2912}
2913
872761f4
MS		 2914static void
2915amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2916 void **this_cache,
2917 struct frame_id *this_id)
2918{
2919 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2920 this_cache);
2921
8fbca658 2922 if (!cache->base_p)
5ce0145d
PA		 2923 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2924 else
2925 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
872761f4
MS		 2926}
2927
2928static const struct frame_unwind amd64_epilogue_frame_unwind =
2929{
2930 NORMAL_FRAME,
8fbca658 2931 amd64_epilogue_frame_unwind_stop_reason,
872761f4
MS		 2932 amd64_epilogue_frame_this_id,
2933 amd64_frame_prev_register,
2934 NULL,
2935 amd64_epilogue_frame_sniffer
2936};
2937
166f4c7b 2938static struct frame_id
10458914 2939amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
166f4c7b 2940{
c4f35dd8
MK		 2941 CORE_ADDR fp;
2942
10458914 2943 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
c4f35dd8 2944
10458914 2945 return frame_id_build (fp + 16, get_frame_pc (this_frame));
166f4c7b
ML		 2946}
2947
8b148df9
AC		 2948/* 16 byte align the SP per frame requirements. */
2949
2950static CORE_ADDR
e53bef9f 2951amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
8b148df9
AC		 2952{
2953 return sp & -(CORE_ADDR)16;
2954}
473f17b0
MK		 2955\f
2956
593adc23
MK		 2957/* Supply register REGNUM from the buffer specified by FPREGS and LEN
2958 in the floating-point register set REGSET to register cache
2959 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
473f17b0
MK		 2960
2961static void
e53bef9f
MK		 2962amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2963 int regnum, const void *fpregs, size_t len)
473f17b0 2964{
ac7936df 2965 struct gdbarch *gdbarch = regcache->arch ();
09424cff 2966 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
473f17b0 2967
1528345d 2968 gdb_assert (len >= tdep->sizeof_fpregset);
90f90721 2969 amd64_supply_fxsave (regcache, regnum, fpregs);
473f17b0 2970}
8b148df9 2971
593adc23
MK		 2972/* Collect register REGNUM from the register cache REGCACHE and store
2973 it in the buffer specified by FPREGS and LEN as described by the
2974 floating-point register set REGSET. If REGNUM is -1, do this for
2975 all registers in REGSET. */
2976
2977static void
2978amd64_collect_fpregset (const struct regset *regset,
2979 const struct regcache *regcache,
2980 int regnum, void *fpregs, size_t len)
2981{
ac7936df 2982 struct gdbarch *gdbarch = regcache->arch ();
09424cff 2983 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
593adc23 2984
1528345d 2985 gdb_assert (len >= tdep->sizeof_fpregset);
593adc23
MK		 2986 amd64_collect_fxsave (regcache, regnum, fpregs);
2987}
2988
8f0435f7 2989const struct regset amd64_fpregset =
ecc37a5a
AA		 2990 {
2991 NULL, amd64_supply_fpregset, amd64_collect_fpregset
2992 };
c6b33596
MK		 2993\f
2994
436675d3
PA		 2995/* Figure out where the longjmp will land. Slurp the jmp_buf out of
2996 %rdi. We expect its value to be a pointer to the jmp_buf structure
2997 from which we extract the address that we will land at. This
2998 address is copied into PC. This routine returns non-zero on
2999 success. */
3000
3001static int
3002amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
3003{
3004 gdb_byte buf[8];
3005 CORE_ADDR jb_addr;
3006 struct gdbarch *gdbarch = get_frame_arch (frame);
3007 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
0dfff4cb 3008 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3009
3010 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3011 longjmp will land. */
3012 if (jb_pc_offset == -1)
3013 return 0;
3014
3015 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
0dfff4cb
UW		 3016 jb_addr= extract_typed_address
3017 (buf, builtin_type (gdbarch)->builtin_data_ptr);
436675d3
PA		 3018 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
3019 return 0;
3020
0dfff4cb 3021 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3022
3023 return 1;
3024}
3025
cf648174
HZ		 3026static const int amd64_record_regmap[] =
3027{
3028 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
3029 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
3030 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
3031 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
3032 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
3033 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
3034};
3035
1d509aa6
MM		 3036/* Implement the "in_indirect_branch_thunk" gdbarch function. */
3037
3038static bool
3039amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc)
3040{
3041 return x86_in_indirect_branch_thunk (pc, amd64_register_names,
3042 AMD64_RAX_REGNUM,
3043 AMD64_RIP_REGNUM);
3044}
3045
2213a65d 3046void
c55a47e7 3047amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3048 const target_desc *default_tdesc)
53e95fcf 3049{
0c1a73d6 3050 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
90884b2b 3051 const struct target_desc *tdesc = info.target_desc;
05c0465e
SDJ		 3052 static const char *const stap_integer_prefixes[] = { "$", NULL };
3053 static const char *const stap_register_prefixes[] = { "%", NULL };
3054 static const char *const stap_register_indirection_prefixes[] = { "(",
3055 NULL };
3056 static const char *const stap_register_indirection_suffixes[] = { ")",
3057 NULL };
53e95fcf 3058
473f17b0
MK		 3059 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3060 floating-point registers. */
3061 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
8f0435f7 3062 tdep->fpregset = &amd64_fpregset;
473f17b0 3063
90884b2b 3064 if (! tdesc_has_registers (tdesc))
c55a47e7 3065 tdesc = default_tdesc;
90884b2b
L		 3066 tdep->tdesc = tdesc;
3067
3068 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
3069 tdep->register_names = amd64_register_names;
3070
01f9f808
MS		 3071 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
3072 {
3073 tdep->zmmh_register_names = amd64_zmmh_names;
3074 tdep->k_register_names = amd64_k_names;
3075 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
3076 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
3077
3078 tdep->num_zmm_regs = 32;
3079 tdep->num_xmm_avx512_regs = 16;
3080 tdep->num_ymm_avx512_regs = 16;
3081
3082 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3083 tdep->k0_regnum = AMD64_K0_REGNUM;
3084 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3085 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3086 }
3087
a055a187
L		 3088 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3089 {
3090 tdep->ymmh_register_names = amd64_ymmh_names;
3091 tdep->num_ymm_regs = 16;
3092 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3093 }
3094
e43e105e
WT		 3095 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3096 {
3097 tdep->mpx_register_names = amd64_mpx_names;
3098 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3099 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3100 }
3101
2735833d
WT		 3102 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
3103 {
3104 const struct tdesc_feature *feature =
3105 tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments");
3106 struct tdesc_arch_data *tdesc_data_segments =
3107 (struct tdesc_arch_data *) info.tdep_info;
3108
3109 tdesc_numbered_register (feature, tdesc_data_segments,
3110 AMD64_FSBASE_REGNUM, "fs_base");
3111 tdesc_numbered_register (feature, tdesc_data_segments,
3112 AMD64_GSBASE_REGNUM, "gs_base");
3113 }
3114
51547df6
MS		 3115 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
3116 {
3117 tdep->pkeys_register_names = amd64_pkeys_names;
3118 tdep->pkru_regnum = AMD64_PKRU_REGNUM;
3119 tdep->num_pkeys_regs = 1;
3120 }
3121
fe01d668 3122 tdep->num_byte_regs = 20;
1ba53b71
L		 3123 tdep->num_word_regs = 16;
3124 tdep->num_dword_regs = 16;
3125 /* Avoid wiring in the MMX registers for now. */
3126 tdep->num_mmx_regs = 0;
3127
3543a589
TT		 3128 set_gdbarch_pseudo_register_read_value (gdbarch,
3129 amd64_pseudo_register_read_value);
1ba53b71
L		 3130 set_gdbarch_pseudo_register_write (gdbarch,
3131 amd64_pseudo_register_write);
62e5fd57
MK		 3132 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3133 amd64_ax_pseudo_register_collect);
1ba53b71
L		 3134
3135 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3136
5716833c 3137 /* AMD64 has an FPU and 16 SSE registers. */
90f90721 3138 tdep->st0_regnum = AMD64_ST0_REGNUM;
0c1a73d6 3139 tdep->num_xmm_regs = 16;
53e95fcf 3140
0c1a73d6 3141 /* This is what all the fuss is about. */
53e95fcf
JS		 3142 set_gdbarch_long_bit (gdbarch, 64);
3143 set_gdbarch_long_long_bit (gdbarch, 64);
3144 set_gdbarch_ptr_bit (gdbarch, 64);
3145
e53bef9f
MK		 3146 /* In contrast to the i386, on AMD64 a `long double' actually takes
3147 up 128 bits, even though it's still based on the i387 extended
3148 floating-point format which has only 80 significant bits. */
b83b026c
MK		 3149 set_gdbarch_long_double_bit (gdbarch, 128);
3150
e53bef9f 3151 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
b83b026c
MK		 3152
3153 /* Register numbers of various important registers. */
90f90721
MK		 3154 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3155 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3156 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3157 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
b83b026c 3158
e53bef9f
MK		 3159 /* The "default" register numbering scheme for AMD64 is referred to
3160 as the "DWARF Register Number Mapping" in the System V psABI.
3161 The preferred debugging format for all known AMD64 targets is
3162 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3163 DWARF-1), but we provide the same mapping just in case. This
3164 mapping is also used for stabs, which GCC does support. */
3165 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
e53bef9f 3166 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
de220d0f 3167
c4f35dd8 3168 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
e53bef9f 3169 be in use on any of the supported AMD64 targets. */
53e95fcf 3170
c4f35dd8 3171 /* Call dummy code. */
e53bef9f
MK		 3172 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3173 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
8b148df9 3174 set_gdbarch_frame_red_zone_size (gdbarch, 128);
53e95fcf 3175
83acabca 3176 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
d532c08f
MK		 3177 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3178 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3179
efb1c01c 3180 set_gdbarch_return_value (gdbarch, amd64_return_value);
53e95fcf 3181
e53bef9f 3182 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
53e95fcf 3183
cf648174
HZ		 3184 tdep->record_regmap = amd64_record_regmap;
3185
10458914 3186 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
53e95fcf 3187
872761f4
MS		 3188 /* Hook the function epilogue frame unwinder. This unwinder is
3189 appended to the list first, so that it supercedes the other
3190 unwinders in function epilogues. */
3191 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3192
3193 /* Hook the prologue-based frame unwinders. */
10458914
DJ		 3194 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3195 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
e53bef9f 3196 frame_base_set_default (gdbarch, &amd64_frame_base);
c6b33596 3197
436675d3 3198 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
dde08ee1
PA		 3199
3200 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
6710bf39
SS		 3201
3202 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
55aa24fb
SDJ		 3203
3204 /* SystemTap variables and functions. */
05c0465e
SDJ		 3205 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3206 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3207 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3208 stap_register_indirection_prefixes);
3209 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3210 stap_register_indirection_suffixes);
55aa24fb
SDJ		 3211 set_gdbarch_stap_is_single_operand (gdbarch,
3212 i386_stap_is_single_operand);
3213 set_gdbarch_stap_parse_special_token (gdbarch,
3214 i386_stap_parse_special_token);
c2170eef
MM		 3215 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3216 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3217 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
1d509aa6
MM		 3218
3219 set_gdbarch_in_indirect_branch_thunk (gdbarch,
3220 amd64_in_indirect_branch_thunk);
c4f35dd8 3221}
c912f608
SM		 3222
3223/* Initialize ARCH for x86-64, no osabi. */
3224
3225static void
3226amd64_none_init_abi (gdbarch_info info, gdbarch *arch)
3227{
3228 amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK));
3229}
fff4548b
MK		 3230
3231static struct type *
3232amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3233{
3234 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3235
3236 switch (regnum - tdep->eax_regnum)
3237 {
3238 case AMD64_RBP_REGNUM: /* %ebp */
3239 case AMD64_RSP_REGNUM: /* %esp */
3240 return builtin_type (gdbarch)->builtin_data_ptr;
3241 case AMD64_RIP_REGNUM: /* %eip */
3242 return builtin_type (gdbarch)->builtin_func_ptr;
3243 }
3244
3245 return i386_pseudo_register_type (gdbarch, regnum);
3246}
3247
3248void
c55a47e7 3249amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3250 const target_desc *default_tdesc)
fff4548b
MK		 3251{
3252 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
fff4548b 3253
c55a47e7 3254 amd64_init_abi (info, gdbarch, default_tdesc);
fff4548b
MK		 3255
3256 tdep->num_dword_regs = 17;
3257 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3258
3259 set_gdbarch_long_bit (gdbarch, 32);
3260 set_gdbarch_ptr_bit (gdbarch, 32);
3261}
90884b2b 3262
c912f608
SM		 3263/* Initialize ARCH for x64-32, no osabi. */
3264
3265static void
3266amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch)
3267{
3268 amd64_x32_init_abi (info, arch,
3269 amd64_target_description (X86_XSTATE_SSE_MASK));
3270}
3271
97de3545
JB		 3272/* Return the target description for a specified XSAVE feature mask. */
3273
3274const struct target_desc *
3275amd64_target_description (uint64_t xcr0)
3276{
22916b07
YQ		 3277 static target_desc *amd64_tdescs \
3278 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
3279 target_desc **tdesc;
3280
3281 tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
3282 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
3283 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
3284 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
3285
3286 if (*tdesc == NULL)
3287 *tdesc = amd64_create_target_description (xcr0, false, false);
3288
3289 return *tdesc;
97de3545
JB		 3290}
3291
90884b2b
L		 3292void
3293_initialize_amd64_tdep (void)
3294{
c912f608
SM		 3295 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE,
3296 amd64_none_init_abi);
3297 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE,
3298 amd64_x32_none_init_abi);
3299
22916b07
YQ		 3300#if GDB_SELF_TEST
3301 struct
3302 {
3303 const char *xml;
3304 uint64_t mask;
3305 } xml_masks[] = {
3306 { "i386/amd64.xml", X86_XSTATE_SSE_MASK },
3307 { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK },
3308 { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK },
3309 { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
3310 { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
3311 { "i386/amd64-avx-mpx-avx512-pku.xml",
3312 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
3313 };
3314
3315 for (auto &a : xml_masks)
3316 {
3317 auto tdesc = amd64_target_description (a.mask);
3318
3319 selftests::record_xml_tdesc (a.xml, tdesc);
3320 }
3321#endif /* GDB_SELF_TEST */
90884b2b 3322}
c4f35dd8
MK		 3323\f
3324
41d041d6
MK		 3325/* The 64-bit FXSAVE format differs from the 32-bit format in the
3326 sense that the instruction pointer and data pointer are simply
3327 64-bit offsets into the code segment and the data segment instead
3328 of a selector offset pair. The functions below store the upper 32
3329 bits of these pointers (instead of just the 16-bits of the segment
3330 selector). */
3331
3332/* Fill register REGNUM in REGCACHE with the appropriate
0485f6ad
MK		 3333 floating-point or SSE register value from *FXSAVE. If REGNUM is
3334 -1, do this for all registers. This function masks off any of the
3335 reserved bits in *FXSAVE. */
c4f35dd8
MK		 3336
3337void
90f90721 3338amd64_supply_fxsave (struct regcache *regcache, int regnum,
20a6ec49 3339 const void *fxsave)
c4f35dd8 3340{
ac7936df 3341 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49
MD		 3342 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3343
41d041d6 3344 i387_supply_fxsave (regcache, regnum, fxsave);
c4f35dd8 3345
233dfcf0
L		 3346 if (fxsave
3347 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
c4f35dd8 3348 {
9a3c8263 3349 const gdb_byte *regs = (const gdb_byte *) fxsave;
41d041d6 3350
20a6ec49 3351 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
73e1c03f 3352 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
20a6ec49 3353 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
73e1c03f 3354 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
c4f35dd8 3355 }
0c1a73d6
MK		 3356}
3357
a055a187
L		 3358/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3359
3360void
3361amd64_supply_xsave (struct regcache *regcache, int regnum,
3362 const void *xsave)
3363{
ac7936df 3364 struct gdbarch *gdbarch = regcache->arch ();
a055a187
L		 3365 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3366
3367 i387_supply_xsave (regcache, regnum, xsave);
3368
233dfcf0
L		 3369 if (xsave
3370 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187 3371 {
9a3c8263 3372 const gdb_byte *regs = (const gdb_byte *) xsave;
8ee22052
AB		 3373 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
3374 ULONGEST clear_bv;
a055a187 3375
8ee22052
AB		 3376 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
3377
3378 /* If the FISEG and FOSEG registers have not been initialised yet
3379 (their CLEAR_BV bit is set) then their default values of zero will
3380 have already been setup by I387_SUPPLY_XSAVE. */
3381 if (!(clear_bv & X86_XSTATE_X87))
3382 {
3383 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
73e1c03f 3384 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
8ee22052 3385 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
73e1c03f 3386 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
8ee22052 3387 }
a055a187
L		 3388 }
3389}
3390
3c017e40
MK		 3391/* Fill register REGNUM (if it is a floating-point or SSE register) in
3392 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3393 all registers. This function doesn't touch any of the reserved
3394 bits in *FXSAVE. */
3395
3396void
3397amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3398 void *fxsave)
3399{
ac7936df 3400 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49 3401 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3402 gdb_byte *regs = (gdb_byte *) fxsave;
3c017e40
MK		 3403
3404 i387_collect_fxsave (regcache, regnum, fxsave);
3405
233dfcf0 3406 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
f0ef85a5 3407 {
20a6ec49 3408 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
34a79281 3409 regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12);
20a6ec49 3410 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
34a79281 3411 regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20);
f0ef85a5 3412 }
3c017e40 3413}
a055a187 3414
7a9dd1b2 3415/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
a055a187
L		 3416
3417void
3418amd64_collect_xsave (const struct regcache *regcache, int regnum,
3419 void *xsave, int gcore)
3420{
ac7936df 3421 struct gdbarch *gdbarch = regcache->arch ();
a055a187 3422 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3423 gdb_byte *regs = (gdb_byte *) xsave;
a055a187
L		 3424
3425 i387_collect_xsave (regcache, regnum, xsave, gcore);
3426
233dfcf0 3427 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187
L		 3428 {
3429 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
34a79281 3430 regcache->raw_collect (I387_FISEG_REGNUM (tdep),
a055a187
L		 3431 regs + 12);
3432 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
34a79281 3433 regcache->raw_collect (I387_FOSEG_REGNUM (tdep),
a055a187
L		 3434 regs + 20);
3435 }
3436}
GDB Binutils - Deliverables
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