Commit | Line | Data |
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c906108c | 1 | /* ARC target-dependent stuff. |
b6ba6518 | 2 | Copyright 1995, 1996, 1999, 2000, 2001 Free Software Foundation, Inc. |
c906108c | 3 | |
c5aa993b | 4 | This file is part of GDB. |
c906108c | 5 | |
c5aa993b JM |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
c5aa993b JM |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
c5aa993b JM |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
20 | |
21 | #include "defs.h" | |
22 | #include "frame.h" | |
23 | #include "inferior.h" | |
24 | #include "gdbcore.h" | |
25 | #include "target.h" | |
26 | #include "floatformat.h" | |
27 | #include "symtab.h" | |
28 | #include "gdbcmd.h" | |
4e052eda | 29 | #include "regcache.h" |
5f8a3188 | 30 | #include "gdb_string.h" |
c906108c | 31 | |
d4f3574e SS |
32 | /* Local functions */ |
33 | ||
34 | static int arc_set_cpu_type (char *str); | |
35 | ||
c906108c SS |
36 | /* Current CPU, set with the "set cpu" command. */ |
37 | static int arc_bfd_mach_type; | |
38 | char *arc_cpu_type; | |
39 | char *tmp_arc_cpu_type; | |
40 | ||
41 | /* Table of cpu names. */ | |
c5aa993b JM |
42 | struct |
43 | { | |
44 | char *name; | |
45 | int value; | |
46 | } | |
47 | arc_cpu_type_table[] = | |
48 | { | |
ea8d0b28 NC |
49 | { "arc5", bfd_mach_arc_5 }, |
50 | { "arc6", bfd_mach_arc_6 }, | |
51 | { "arc7", bfd_mach_arc_7 }, | |
52 | { "arc8", bfd_mach_arc_8 }, | |
53 | { NULL, 0 } | |
c906108c SS |
54 | }; |
55 | ||
56 | /* Used by simulator. */ | |
57 | int display_pipeline_p; | |
58 | int cpu_timer; | |
59 | /* This one must have the same type as used in the emulator. | |
60 | It's currently an enum so this should be ok for now. */ | |
61 | int debug_pipeline_p; | |
62 | ||
63 | #define ARC_CALL_SAVED_REG(r) ((r) >= 16 && (r) < 24) | |
64 | ||
65 | #define OPMASK 0xf8000000 | |
66 | ||
67 | /* Instruction field accessor macros. | |
68 | See the Programmer's Reference Manual. */ | |
69 | #define X_OP(i) (((i) >> 27) & 0x1f) | |
70 | #define X_A(i) (((i) >> 21) & 0x3f) | |
71 | #define X_B(i) (((i) >> 15) & 0x3f) | |
72 | #define X_C(i) (((i) >> 9) & 0x3f) | |
73 | #define X_D(i) ((((i) & 0x1ff) ^ 0x100) - 0x100) | |
74 | #define X_L(i) (((((i) >> 5) & 0x3ffffc) ^ 0x200000) - 0x200000) | |
75 | #define X_N(i) (((i) >> 5) & 3) | |
76 | #define X_Q(i) ((i) & 0x1f) | |
77 | ||
78 | /* Return non-zero if X is a short immediate data indicator. */ | |
79 | #define SHIMM_P(x) ((x) == 61 || (x) == 63) | |
80 | ||
81 | /* Return non-zero if X is a "long" (32 bit) immediate data indicator. */ | |
82 | #define LIMM_P(x) ((x) == 62) | |
83 | ||
84 | /* Build a simple instruction. */ | |
85 | #define BUILD_INSN(op, a, b, c, d) \ | |
86 | ((((op) & 31) << 27) \ | |
87 | | (((a) & 63) << 21) \ | |
88 | | (((b) & 63) << 15) \ | |
89 | | (((c) & 63) << 9) \ | |
90 | | ((d) & 511)) | |
91 | \f | |
92 | /* Codestream stuff. */ | |
a14ed312 KB |
93 | static void codestream_read (unsigned int *, int); |
94 | static void codestream_seek (CORE_ADDR); | |
95 | static unsigned int codestream_fill (int); | |
c906108c | 96 | |
c5aa993b | 97 | #define CODESTREAM_BUFSIZ 16 |
c906108c SS |
98 | static CORE_ADDR codestream_next_addr; |
99 | static CORE_ADDR codestream_addr; | |
c2d11a7d | 100 | /* FIXME assumes sizeof (int) == 32? */ |
c906108c SS |
101 | static unsigned int codestream_buf[CODESTREAM_BUFSIZ]; |
102 | static int codestream_off; | |
103 | static int codestream_cnt; | |
104 | ||
105 | #define codestream_tell() \ | |
106 | (codestream_addr + codestream_off * sizeof (codestream_buf[0])) | |
107 | #define codestream_peek() \ | |
108 | (codestream_cnt == 0 \ | |
109 | ? codestream_fill (1) \ | |
110 | : codestream_buf[codestream_off]) | |
111 | #define codestream_get() \ | |
112 | (codestream_cnt-- == 0 \ | |
113 | ? codestream_fill (0) \ | |
114 | : codestream_buf[codestream_off++]) | |
115 | ||
c5aa993b | 116 | static unsigned int |
fba45db2 | 117 | codestream_fill (int peek_flag) |
c906108c SS |
118 | { |
119 | codestream_addr = codestream_next_addr; | |
120 | codestream_next_addr += CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]); | |
121 | codestream_off = 0; | |
122 | codestream_cnt = CODESTREAM_BUFSIZ; | |
123 | read_memory (codestream_addr, (char *) codestream_buf, | |
124 | CODESTREAM_BUFSIZ * sizeof (codestream_buf[0])); | |
125 | /* FIXME: check return code? */ | |
126 | ||
c2d11a7d JM |
127 | |
128 | /* Handle byte order differences -> convert to host byte ordering. */ | |
129 | { | |
130 | int i; | |
131 | for (i = 0; i < CODESTREAM_BUFSIZ; i++) | |
132 | codestream_buf[i] = | |
133 | extract_unsigned_integer (&codestream_buf[i], | |
134 | sizeof (codestream_buf[i])); | |
135 | } | |
c5aa993b | 136 | |
c906108c SS |
137 | if (peek_flag) |
138 | return codestream_peek (); | |
139 | else | |
140 | return codestream_get (); | |
141 | } | |
142 | ||
143 | static void | |
fba45db2 | 144 | codestream_seek (CORE_ADDR place) |
c906108c SS |
145 | { |
146 | codestream_next_addr = place / CODESTREAM_BUFSIZ; | |
147 | codestream_next_addr *= CODESTREAM_BUFSIZ; | |
148 | codestream_cnt = 0; | |
149 | codestream_fill (1); | |
150 | while (codestream_tell () != place) | |
151 | codestream_get (); | |
152 | } | |
153 | ||
154 | /* This function is currently unused but leave in for now. */ | |
155 | ||
156 | static void | |
fba45db2 | 157 | codestream_read (unsigned int *buf, int count) |
c906108c SS |
158 | { |
159 | unsigned int *p; | |
160 | int i; | |
161 | p = buf; | |
162 | for (i = 0; i < count; i++) | |
163 | *p++ = codestream_get (); | |
164 | } | |
165 | \f | |
166 | /* Set up prologue scanning and return the first insn. */ | |
167 | ||
168 | static unsigned int | |
fba45db2 | 169 | setup_prologue_scan (CORE_ADDR pc) |
c906108c SS |
170 | { |
171 | unsigned int insn; | |
172 | ||
173 | codestream_seek (pc); | |
174 | insn = codestream_get (); | |
175 | ||
176 | return insn; | |
177 | } | |
178 | ||
179 | /* | |
180 | * Find & return amount a local space allocated, and advance codestream to | |
181 | * first register push (if any). | |
182 | * If entry sequence doesn't make sense, return -1, and leave | |
183 | * codestream pointer random. | |
184 | */ | |
185 | ||
186 | static long | |
fba45db2 | 187 | arc_get_frame_setup (CORE_ADDR pc) |
c906108c SS |
188 | { |
189 | unsigned int insn; | |
190 | /* Size of frame or -1 if unrecognizable prologue. */ | |
191 | int frame_size = -1; | |
192 | /* An initial "sub sp,sp,N" may or may not be for a stdarg fn. */ | |
193 | int maybe_stdarg_decr = -1; | |
194 | ||
195 | insn = setup_prologue_scan (pc); | |
196 | ||
197 | /* The authority for what appears here is the home-grown ABI. | |
198 | The most recent version is 1.2. */ | |
199 | ||
200 | /* First insn may be "sub sp,sp,N" if stdarg fn. */ | |
201 | if ((insn & BUILD_INSN (-1, -1, -1, -1, 0)) | |
202 | == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0)) | |
203 | { | |
204 | maybe_stdarg_decr = X_D (insn); | |
205 | insn = codestream_get (); | |
206 | } | |
207 | ||
208 | if ((insn & BUILD_INSN (-1, 0, -1, -1, -1)) /* st blink,[sp,4] */ | |
209 | == BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4)) | |
210 | { | |
211 | insn = codestream_get (); | |
212 | /* Frame may not be necessary, even though blink is saved. | |
c5aa993b | 213 | At least this is something we recognize. */ |
c906108c SS |
214 | frame_size = 0; |
215 | } | |
216 | ||
c5aa993b | 217 | if ((insn & BUILD_INSN (-1, 0, -1, -1, -1)) /* st fp,[sp] */ |
c906108c | 218 | == BUILD_INSN (2, 0, SP_REGNUM, FP_REGNUM, 0)) |
c5aa993b | 219 | { |
c906108c SS |
220 | insn = codestream_get (); |
221 | if ((insn & BUILD_INSN (-1, -1, -1, -1, 0)) | |
c5aa993b | 222 | != BUILD_INSN (12, FP_REGNUM, SP_REGNUM, SP_REGNUM, 0)) |
c906108c SS |
223 | return -1; |
224 | ||
225 | /* Check for stack adjustment sub sp,sp,N. */ | |
226 | insn = codestream_peek (); | |
227 | if ((insn & BUILD_INSN (-1, -1, -1, 0, 0)) | |
228 | == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, 0, 0)) | |
229 | { | |
230 | if (LIMM_P (X_C (insn))) | |
231 | frame_size = codestream_get (); | |
232 | else if (SHIMM_P (X_C (insn))) | |
233 | frame_size = X_D (insn); | |
234 | else | |
235 | return -1; | |
236 | if (frame_size < 0) | |
237 | return -1; | |
238 | ||
c5aa993b | 239 | codestream_get (); |
c906108c SS |
240 | |
241 | /* This sequence is used to get the address of the return | |
242 | buffer for a function that returns a structure. */ | |
243 | insn = codestream_peek (); | |
7a292a7a | 244 | if ((insn & OPMASK) == 0x60000000) |
c906108c SS |
245 | codestream_get (); |
246 | } | |
247 | /* Frameless fn. */ | |
248 | else | |
249 | { | |
250 | frame_size = 0; | |
251 | } | |
252 | } | |
253 | ||
254 | /* If we found a "sub sp,sp,N" and nothing else, it may or may not be a | |
255 | stdarg fn. The stdarg decrement is not treated as part of the frame size, | |
256 | so we have a dilemma: what do we return? For now, if we get a | |
257 | "sub sp,sp,N" and nothing else assume this isn't a stdarg fn. One way | |
258 | to fix this completely would be to add a bit to the function descriptor | |
259 | that says the function is a stdarg function. */ | |
260 | ||
261 | if (frame_size < 0 && maybe_stdarg_decr > 0) | |
262 | return maybe_stdarg_decr; | |
263 | return frame_size; | |
264 | } | |
265 | ||
266 | /* Given a pc value, skip it forward past the function prologue by | |
267 | disassembling instructions that appear to be a prologue. | |
268 | ||
269 | If FRAMELESS_P is set, we are only testing to see if the function | |
270 | is frameless. If it is a frameless function, return PC unchanged. | |
271 | This allows a quicker answer. */ | |
272 | ||
273 | CORE_ADDR | |
fba45db2 | 274 | arc_skip_prologue (CORE_ADDR pc, int frameless_p) |
c906108c SS |
275 | { |
276 | unsigned int insn; | |
277 | int i, frame_size; | |
278 | ||
279 | if ((frame_size = arc_get_frame_setup (pc)) < 0) | |
280 | return (pc); | |
281 | ||
282 | if (frameless_p) | |
283 | return frame_size == 0 ? pc : codestream_tell (); | |
284 | ||
285 | /* Skip over register saves. */ | |
286 | for (i = 0; i < 8; i++) | |
287 | { | |
288 | insn = codestream_peek (); | |
289 | if ((insn & BUILD_INSN (-1, 0, -1, 0, 0)) | |
290 | != BUILD_INSN (2, 0, SP_REGNUM, 0, 0)) | |
c5aa993b JM |
291 | break; /* not st insn */ |
292 | if (!ARC_CALL_SAVED_REG (X_C (insn))) | |
c906108c SS |
293 | break; |
294 | codestream_get (); | |
295 | } | |
296 | ||
297 | return codestream_tell (); | |
298 | } | |
299 | ||
9319a2fe DM |
300 | /* Is the prologue at PC frameless? */ |
301 | ||
302 | int | |
303 | arc_prologue_frameless_p (CORE_ADDR pc) | |
304 | { | |
6cc1c0a8 | 305 | return (pc == arc_skip_prologue (pc, 1)); |
9319a2fe DM |
306 | } |
307 | ||
c906108c SS |
308 | /* Return the return address for a frame. |
309 | This is used to implement FRAME_SAVED_PC. | |
310 | This is taken from frameless_look_for_prologue. */ | |
311 | ||
312 | CORE_ADDR | |
fba45db2 | 313 | arc_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
314 | { |
315 | CORE_ADDR func_start; | |
316 | unsigned int insn; | |
317 | ||
318 | func_start = get_pc_function_start (frame->pc) + FUNCTION_START_OFFSET; | |
319 | if (func_start == 0) | |
320 | { | |
321 | /* Best guess. */ | |
322 | return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4)); | |
323 | } | |
324 | ||
325 | /* The authority for what appears here is the home-grown ABI. | |
326 | The most recent version is 1.2. */ | |
327 | ||
328 | insn = setup_prologue_scan (func_start); | |
329 | ||
330 | /* First insn may be "sub sp,sp,N" if stdarg fn. */ | |
331 | if ((insn & BUILD_INSN (-1, -1, -1, -1, 0)) | |
332 | == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0)) | |
333 | insn = codestream_get (); | |
334 | ||
335 | /* If the next insn is "st blink,[sp,4]" we can get blink from there. | |
336 | Otherwise this is a leaf function and we can use blink. Note that | |
337 | this still allows for the case where a leaf function saves/clobbers/ | |
338 | restores blink. */ | |
339 | ||
340 | if ((insn & BUILD_INSN (-1, 0, -1, -1, -1)) /* st blink,[sp,4] */ | |
341 | != BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4)) | |
342 | return ARC_PC_TO_REAL_ADDRESS (read_register (BLINK_REGNUM)); | |
343 | else | |
344 | return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4)); | |
345 | } | |
346 | ||
347 | /* | |
348 | * Parse the first few instructions of the function to see | |
349 | * what registers were stored. | |
350 | * | |
351 | * The startup sequence can be at the start of the function. | |
352 | * 'st blink,[sp+4], st fp,[sp], mov fp,sp' | |
353 | * | |
354 | * Local space is allocated just below by sub sp,sp,nnn. | |
355 | * Next, the registers used by this function are stored (as offsets from sp). | |
356 | */ | |
357 | ||
358 | void | |
fba45db2 | 359 | frame_find_saved_regs (struct frame_info *fip, struct frame_saved_regs *fsrp) |
c906108c SS |
360 | { |
361 | long locals; | |
362 | unsigned int insn; | |
363 | CORE_ADDR dummy_bottom; | |
364 | CORE_ADDR adr; | |
365 | int i, regnum, offset; | |
366 | ||
367 | memset (fsrp, 0, sizeof *fsrp); | |
368 | ||
369 | /* If frame is the end of a dummy, compute where the beginning would be. */ | |
370 | dummy_bottom = fip->frame - 4 - REGISTER_BYTES - CALL_DUMMY_LENGTH; | |
371 | ||
372 | /* Check if the PC is in the stack, in a dummy frame. */ | |
c5aa993b | 373 | if (dummy_bottom <= fip->pc && fip->pc <= fip->frame) |
c906108c SS |
374 | { |
375 | /* all regs were saved by push_call_dummy () */ | |
376 | adr = fip->frame; | |
c5aa993b | 377 | for (i = 0; i < NUM_REGS; i++) |
c906108c SS |
378 | { |
379 | adr -= REGISTER_RAW_SIZE (i); | |
380 | fsrp->regs[i] = adr; | |
381 | } | |
382 | return; | |
383 | } | |
384 | ||
385 | locals = arc_get_frame_setup (get_pc_function_start (fip->pc)); | |
386 | ||
c5aa993b | 387 | if (locals >= 0) |
c906108c SS |
388 | { |
389 | /* Set `adr' to the value of `sp'. */ | |
390 | adr = fip->frame - locals; | |
391 | for (i = 0; i < 8; i++) | |
392 | { | |
393 | insn = codestream_get (); | |
394 | if ((insn & BUILD_INSN (-1, 0, -1, 0, 0)) | |
c5aa993b | 395 | != BUILD_INSN (2, 0, SP_REGNUM, 0, 0)) |
c906108c | 396 | break; |
c5aa993b | 397 | regnum = X_C (insn); |
c906108c SS |
398 | offset = X_D (insn); |
399 | fsrp->regs[regnum] = adr + offset; | |
400 | } | |
401 | } | |
402 | ||
403 | fsrp->regs[PC_REGNUM] = fip->frame + 4; | |
404 | fsrp->regs[FP_REGNUM] = fip->frame; | |
405 | } | |
406 | ||
407 | void | |
d4f3574e | 408 | arc_push_dummy_frame (void) |
c906108c SS |
409 | { |
410 | CORE_ADDR sp = read_register (SP_REGNUM); | |
411 | int regnum; | |
412 | char regbuf[MAX_REGISTER_RAW_SIZE]; | |
413 | ||
414 | read_register_gen (PC_REGNUM, regbuf); | |
c5aa993b | 415 | write_memory (sp + 4, regbuf, REGISTER_SIZE); |
c906108c SS |
416 | read_register_gen (FP_REGNUM, regbuf); |
417 | write_memory (sp, regbuf, REGISTER_SIZE); | |
418 | write_register (FP_REGNUM, sp); | |
419 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
420 | { | |
421 | read_register_gen (regnum, regbuf); | |
422 | sp = push_bytes (sp, regbuf, REGISTER_RAW_SIZE (regnum)); | |
423 | } | |
c5aa993b | 424 | sp += (2 * REGISTER_SIZE); |
c906108c SS |
425 | write_register (SP_REGNUM, sp); |
426 | } | |
427 | ||
428 | void | |
d4f3574e | 429 | arc_pop_frame (void) |
c906108c SS |
430 | { |
431 | struct frame_info *frame = get_current_frame (); | |
432 | CORE_ADDR fp; | |
433 | int regnum; | |
434 | struct frame_saved_regs fsr; | |
435 | char regbuf[MAX_REGISTER_RAW_SIZE]; | |
c5aa993b | 436 | |
c906108c SS |
437 | fp = FRAME_FP (frame); |
438 | get_frame_saved_regs (frame, &fsr); | |
c5aa993b | 439 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c906108c SS |
440 | { |
441 | CORE_ADDR adr; | |
442 | adr = fsr.regs[regnum]; | |
443 | if (adr) | |
444 | { | |
445 | read_memory (adr, regbuf, REGISTER_RAW_SIZE (regnum)); | |
446 | write_register_bytes (REGISTER_BYTE (regnum), regbuf, | |
447 | REGISTER_RAW_SIZE (regnum)); | |
448 | } | |
449 | } | |
450 | write_register (FP_REGNUM, read_memory_integer (fp, 4)); | |
451 | write_register (PC_REGNUM, read_memory_integer (fp + 4, 4)); | |
452 | write_register (SP_REGNUM, fp + 8); | |
453 | flush_cached_frames (); | |
454 | } | |
455 | \f | |
456 | /* Simulate single-step. */ | |
457 | ||
458 | typedef enum | |
459 | { | |
c5aa993b JM |
460 | NORMAL4, /* a normal 4 byte insn */ |
461 | NORMAL8, /* a normal 8 byte insn */ | |
462 | BRANCH4, /* a 4 byte branch insn, including ones without delay slots */ | |
463 | BRANCH8, /* an 8 byte branch insn, including ones with delay slots */ | |
464 | } | |
465 | insn_type; | |
c906108c SS |
466 | |
467 | /* Return the type of INSN and store in TARGET the destination address of a | |
468 | branch if this is one. */ | |
469 | /* ??? Need to verify all cases are properly handled. */ | |
470 | ||
471 | static insn_type | |
fba45db2 | 472 | get_insn_type (unsigned long insn, CORE_ADDR pc, CORE_ADDR *target) |
c906108c SS |
473 | { |
474 | unsigned long limm; | |
475 | ||
476 | switch (insn >> 27) | |
477 | { | |
c5aa993b JM |
478 | case 0: |
479 | case 1: | |
480 | case 2: /* load/store insns */ | |
c906108c SS |
481 | if (LIMM_P (X_A (insn)) |
482 | || LIMM_P (X_B (insn)) | |
483 | || LIMM_P (X_C (insn))) | |
484 | return NORMAL8; | |
485 | return NORMAL4; | |
c5aa993b JM |
486 | case 4: |
487 | case 5: | |
488 | case 6: /* branch insns */ | |
c906108c SS |
489 | *target = pc + 4 + X_L (insn); |
490 | /* ??? It isn't clear that this is always the right answer. | |
c5aa993b JM |
491 | The problem occurs when the next insn is an 8 byte insn. If the |
492 | branch is conditional there's no worry as there shouldn't be an 8 | |
493 | byte insn following. The programmer may be cheating if s/he knows | |
494 | the branch will never be taken, but we don't deal with that. | |
495 | Note that the programmer is also allowed to play games by putting | |
496 | an insn with long immediate data in the delay slot and then duplicate | |
497 | the long immediate data at the branch target. Ugh! */ | |
c906108c SS |
498 | if (X_N (insn) == 0) |
499 | return BRANCH4; | |
500 | return BRANCH8; | |
c5aa993b | 501 | case 7: /* jump insns */ |
c906108c SS |
502 | if (LIMM_P (X_B (insn))) |
503 | { | |
504 | limm = read_memory_integer (pc + 4, 4); | |
505 | *target = ARC_PC_TO_REAL_ADDRESS (limm); | |
506 | return BRANCH8; | |
507 | } | |
508 | if (SHIMM_P (X_B (insn))) | |
509 | *target = ARC_PC_TO_REAL_ADDRESS (X_D (insn)); | |
510 | else | |
511 | *target = ARC_PC_TO_REAL_ADDRESS (read_register (X_B (insn))); | |
512 | if (X_Q (insn) == 0 && X_N (insn) == 0) | |
513 | return BRANCH4; | |
514 | return BRANCH8; | |
c5aa993b | 515 | default: /* arithmetic insns, etc. */ |
c906108c SS |
516 | if (LIMM_P (X_A (insn)) |
517 | || LIMM_P (X_B (insn)) | |
518 | || LIMM_P (X_C (insn))) | |
519 | return NORMAL8; | |
520 | return NORMAL4; | |
521 | } | |
522 | } | |
523 | ||
524 | /* single_step() is called just before we want to resume the inferior, if we | |
525 | want to single-step it but there is no hardware or kernel single-step | |
526 | support. We find all the possible targets of the coming instruction and | |
527 | breakpoint them. | |
528 | ||
529 | single_step is also called just after the inferior stops. If we had | |
530 | set up a simulated single-step, we undo our damage. */ | |
531 | ||
532 | void | |
fba45db2 KB |
533 | arc_software_single_step (enum target_signal ignore, /* sig but we don't need it */ |
534 | int insert_breakpoints_p) | |
c906108c SS |
535 | { |
536 | static CORE_ADDR next_pc, target; | |
537 | static int brktrg_p; | |
538 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
539 | static binsn_quantum break_mem[2]; | |
540 | ||
541 | if (insert_breakpoints_p) | |
542 | { | |
543 | insn_type type; | |
544 | CORE_ADDR pc; | |
545 | unsigned long insn; | |
546 | ||
547 | pc = read_register (PC_REGNUM); | |
548 | insn = read_memory_integer (pc, 4); | |
549 | type = get_insn_type (insn, pc, &target); | |
550 | ||
551 | /* Always set a breakpoint for the insn after the branch. */ | |
552 | next_pc = pc + ((type == NORMAL8 || type == BRANCH8) ? 8 : 4); | |
553 | target_insert_breakpoint (next_pc, break_mem[0]); | |
554 | ||
555 | brktrg_p = 0; | |
556 | ||
557 | if ((type == BRANCH4 || type == BRANCH8) | |
c5aa993b JM |
558 | /* Watch out for branches to the following location. |
559 | We just stored a breakpoint there and another call to | |
560 | target_insert_breakpoint will think the real insn is the | |
561 | breakpoint we just stored there. */ | |
c906108c SS |
562 | && target != next_pc) |
563 | { | |
564 | brktrg_p = 1; | |
565 | target_insert_breakpoint (target, break_mem[1]); | |
566 | } | |
567 | ||
568 | } | |
569 | else | |
570 | { | |
571 | /* Remove breakpoints. */ | |
572 | target_remove_breakpoint (next_pc, break_mem[0]); | |
573 | ||
574 | if (brktrg_p) | |
575 | target_remove_breakpoint (target, break_mem[1]); | |
576 | ||
577 | /* Fix the pc. */ | |
578 | stop_pc -= DECR_PC_AFTER_BREAK; | |
579 | write_pc (stop_pc); | |
580 | } | |
581 | } | |
582 | \f | |
a48442a0 RE |
583 | /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test |
584 | for a definition of JB_PC. */ | |
585 | #ifdef JB_PC | |
c906108c SS |
586 | /* Figure out where the longjmp will land. Slurp the args out of the stack. |
587 | We expect the first arg to be a pointer to the jmp_buf structure from which | |
588 | we extract the pc (JB_PC) that we will land at. The pc is copied into PC. | |
589 | This routine returns true on success. */ | |
590 | ||
591 | int | |
fba45db2 | 592 | get_longjmp_target (CORE_ADDR *pc) |
c906108c SS |
593 | { |
594 | char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT]; | |
595 | CORE_ADDR sp, jb_addr; | |
596 | ||
597 | sp = read_register (SP_REGNUM); | |
598 | ||
c5aa993b | 599 | if (target_read_memory (sp + SP_ARG0, /* Offset of first arg on stack */ |
c906108c SS |
600 | buf, |
601 | TARGET_PTR_BIT / TARGET_CHAR_BIT)) | |
602 | return 0; | |
603 | ||
604 | jb_addr = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); | |
605 | ||
606 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, | |
607 | TARGET_PTR_BIT / TARGET_CHAR_BIT)) | |
608 | return 0; | |
609 | ||
610 | *pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); | |
611 | ||
612 | return 1; | |
613 | } | |
614 | #endif /* GET_LONGJMP_TARGET */ | |
615 | \f | |
616 | /* Disassemble one instruction. */ | |
617 | ||
618 | static int | |
fba45db2 | 619 | arc_print_insn (bfd_vma vma, disassemble_info *info) |
c906108c SS |
620 | { |
621 | static int current_mach; | |
622 | static int current_endian; | |
623 | static disassembler_ftype current_disasm; | |
624 | ||
625 | if (current_disasm == NULL | |
626 | || arc_bfd_mach_type != current_mach | |
627 | || TARGET_BYTE_ORDER != current_endian) | |
628 | { | |
629 | current_mach = arc_bfd_mach_type; | |
630 | current_endian = TARGET_BYTE_ORDER; | |
ea8d0b28 | 631 | current_disasm = arc_get_disassembler (NULL); |
c906108c SS |
632 | } |
633 | ||
634 | return (*current_disasm) (vma, info); | |
635 | } | |
636 | \f | |
637 | /* Command to set cpu type. */ | |
638 | ||
639 | void | |
d4f3574e | 640 | arc_set_cpu_type_command (char *args, int from_tty) |
c906108c SS |
641 | { |
642 | int i; | |
643 | ||
644 | if (tmp_arc_cpu_type == NULL || *tmp_arc_cpu_type == '\0') | |
645 | { | |
646 | printf_unfiltered ("The known ARC cpu types are as follows:\n"); | |
647 | for (i = 0; arc_cpu_type_table[i].name != NULL; ++i) | |
648 | printf_unfiltered ("%s\n", arc_cpu_type_table[i].name); | |
649 | ||
650 | /* Restore the value. */ | |
4fcf66da | 651 | tmp_arc_cpu_type = xstrdup (arc_cpu_type); |
c906108c SS |
652 | |
653 | return; | |
654 | } | |
c5aa993b | 655 | |
c906108c SS |
656 | if (!arc_set_cpu_type (tmp_arc_cpu_type)) |
657 | { | |
658 | error ("Unknown cpu type `%s'.", tmp_arc_cpu_type); | |
659 | /* Restore its value. */ | |
4fcf66da | 660 | tmp_arc_cpu_type = xstrdup (arc_cpu_type); |
c906108c SS |
661 | } |
662 | } | |
663 | ||
664 | static void | |
fba45db2 | 665 | arc_show_cpu_type_command (char *args, int from_tty) |
c906108c SS |
666 | { |
667 | } | |
668 | ||
669 | /* Modify the actual cpu type. | |
670 | Result is a boolean indicating success. */ | |
671 | ||
d4f3574e | 672 | static int |
fba45db2 | 673 | arc_set_cpu_type (char *str) |
c906108c SS |
674 | { |
675 | int i, j; | |
676 | ||
677 | if (str == NULL) | |
678 | return 0; | |
679 | ||
680 | for (i = 0; arc_cpu_type_table[i].name != NULL; ++i) | |
681 | { | |
682 | if (strcasecmp (str, arc_cpu_type_table[i].name) == 0) | |
683 | { | |
684 | arc_cpu_type = str; | |
685 | arc_bfd_mach_type = arc_cpu_type_table[i].value; | |
686 | return 1; | |
687 | } | |
688 | } | |
689 | ||
690 | return 0; | |
691 | } | |
692 | \f | |
693 | void | |
fba45db2 | 694 | _initialize_arc_tdep (void) |
c906108c SS |
695 | { |
696 | struct cmd_list_element *c; | |
697 | ||
698 | c = add_set_cmd ("cpu", class_support, var_string_noescape, | |
699 | (char *) &tmp_arc_cpu_type, | |
700 | "Set the type of ARC cpu in use.\n\ | |
701 | This command has two purposes. In a multi-cpu system it lets one\n\ | |
702 | change the cpu being debugged. It also gives one access to\n\ | |
703 | cpu-type-specific registers and recognize cpu-type-specific instructions.\ | |
704 | ", | |
705 | &setlist); | |
9f60d481 | 706 | set_cmd_cfunc (c, arc_set_cpu_type_command); |
c906108c | 707 | c = add_show_from_set (c, &showlist); |
9f60d481 | 708 | set_cmd_cfunc (c, arc_show_cpu_type_command); |
c906108c | 709 | |
4fcf66da AC |
710 | /* We have to use xstrdup() here because the `set' command frees it |
711 | before setting a new value. */ | |
712 | tmp_arc_cpu_type = xstrdup (DEFAULT_ARC_CPU_TYPE); | |
c906108c SS |
713 | arc_set_cpu_type (tmp_arc_cpu_type); |
714 | ||
715 | c = add_set_cmd ("displaypipeline", class_support, var_zinteger, | |
716 | (char *) &display_pipeline_p, | |
717 | "Set pipeline display (simulator only).\n\ | |
718 | When enabled, the state of the pipeline after each cycle is displayed.", | |
719 | &setlist); | |
720 | c = add_show_from_set (c, &showlist); | |
721 | ||
722 | c = add_set_cmd ("debugpipeline", class_support, var_zinteger, | |
723 | (char *) &debug_pipeline_p, | |
724 | "Set pipeline debug display (simulator only).\n\ | |
725 | When enabled, debugging information about the pipeline is displayed.", | |
726 | &setlist); | |
727 | c = add_show_from_set (c, &showlist); | |
728 | ||
729 | c = add_set_cmd ("cputimer", class_support, var_zinteger, | |
730 | (char *) &cpu_timer, | |
731 | "Set maximum cycle count (simulator only).\n\ | |
732 | Control will return to gdb if the timer expires.\n\ | |
733 | A negative value disables the timer.", | |
734 | &setlist); | |
735 | c = add_show_from_set (c, &showlist); | |
736 | ||
737 | tm_print_insn = arc_print_insn; | |
738 | } |