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ec741292 | 1 | /* Common target dependent code for GDB on ARM systems. |
b811d2c2 | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
ec741292 YQ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
1a5c2598 TT |
19 | #ifndef ARCH_ARM_H |
20 | #define ARCH_ARM_H | |
ec741292 | 21 | |
d105cce5 AH |
22 | #include "gdbsupport/tdesc.h" |
23 | ||
ec741292 YQ |
24 | /* Register numbers of various important registers. */ |
25 | ||
26 | enum gdb_regnum { | |
27 | ARM_A1_REGNUM = 0, /* first integer-like argument */ | |
28 | ARM_A4_REGNUM = 3, /* last integer-like argument */ | |
29 | ARM_AP_REGNUM = 11, | |
30 | ARM_IP_REGNUM = 12, | |
31 | ARM_SP_REGNUM = 13, /* Contains address of top of stack */ | |
32 | ARM_LR_REGNUM = 14, /* address to return to from a function call */ | |
33 | ARM_PC_REGNUM = 15, /* Contains program counter */ | |
34 | ARM_F0_REGNUM = 16, /* first floating point register */ | |
35 | ARM_F3_REGNUM = 19, /* last floating point argument register */ | |
36 | ARM_F7_REGNUM = 23, /* last floating point register */ | |
37 | ARM_FPS_REGNUM = 24, /* floating point status register */ | |
38 | ARM_PS_REGNUM = 25, /* Contains processor status */ | |
39 | ARM_WR0_REGNUM, /* WMMX data registers. */ | |
40 | ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15, | |
41 | ARM_WC0_REGNUM, /* WMMX control registers. */ | |
42 | ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2, | |
43 | ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3, | |
44 | ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7, | |
45 | ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */ | |
46 | ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3, | |
47 | ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7, | |
48 | ARM_D0_REGNUM, /* VFP double-precision registers. */ | |
49 | ARM_D31_REGNUM = ARM_D0_REGNUM + 31, | |
50 | ARM_FPSCR_REGNUM, | |
51 | ||
52 | ARM_NUM_REGS, | |
53 | ||
54 | /* Other useful registers. */ | |
55 | ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */ | |
56 | THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */ | |
57 | ARM_NUM_ARG_REGS = 4, | |
58 | ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM, | |
59 | ARM_NUM_FP_ARG_REGS = 4, | |
60 | ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM | |
61 | }; | |
62 | ||
a1078bea YQ |
63 | /* Enum describing the different kinds of breakpoints. */ |
64 | enum arm_breakpoint_kinds | |
65 | { | |
66 | ARM_BP_KIND_THUMB = 2, | |
67 | ARM_BP_KIND_THUMB2 = 3, | |
68 | ARM_BP_KIND_ARM = 4, | |
69 | }; | |
70 | ||
d105cce5 AH |
71 | /* Supported Arm FP hardware types. */ |
72 | enum arm_fp_type { | |
73 | ARM_FP_TYPE_NONE = 0, | |
74 | ARM_FP_TYPE_VFPV2, | |
75 | ARM_FP_TYPE_VFPV3, | |
76 | ARM_FP_TYPE_IWMMXT, | |
77 | ARM_FP_TYPE_INVALID | |
78 | }; | |
79 | ||
80 | /* Supported M-profile Arm types. */ | |
81 | enum arm_m_profile_type { | |
82 | ARM_M_TYPE_M_PROFILE, | |
83 | ARM_M_TYPE_VFP_D16, | |
84 | ARM_M_TYPE_WITH_FPA, | |
85 | ARM_M_TYPE_INVALID | |
86 | }; | |
87 | ||
cba7e83f AT |
88 | /* Instruction condition field values. */ |
89 | #define INST_EQ 0x0 | |
90 | #define INST_NE 0x1 | |
91 | #define INST_CS 0x2 | |
92 | #define INST_CC 0x3 | |
93 | #define INST_MI 0x4 | |
94 | #define INST_PL 0x5 | |
95 | #define INST_VS 0x6 | |
96 | #define INST_VC 0x7 | |
97 | #define INST_HI 0x8 | |
98 | #define INST_LS 0x9 | |
99 | #define INST_GE 0xa | |
100 | #define INST_LT 0xb | |
101 | #define INST_GT 0xc | |
102 | #define INST_LE 0xd | |
103 | #define INST_AL 0xe | |
104 | #define INST_NV 0xf | |
105 | ||
106 | #define FLAG_N 0x80000000 | |
107 | #define FLAG_Z 0x40000000 | |
108 | #define FLAG_C 0x20000000 | |
109 | #define FLAG_V 0x10000000 | |
110 | ||
111 | #define CPSR_T 0x20 | |
112 | ||
113 | #define XPSR_T 0x01000000 | |
114 | ||
f0452268 AH |
115 | /* Size of registers. */ |
116 | ||
117 | #define ARM_INT_REGISTER_SIZE 4 | |
118 | /* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */ | |
119 | #define ARM_FP_REGISTER_SIZE 12 | |
120 | #define ARM_VFP_REGISTER_SIZE 8 | |
350fab54 AH |
121 | #define IWMMXT_VEC_REGISTER_SIZE 8 |
122 | ||
123 | /* Size of register sets. */ | |
124 | ||
125 | /* r0-r12,sp,lr,pc,cpsr. */ | |
126 | #define ARM_CORE_REGS_SIZE (17 * ARM_INT_REGISTER_SIZE) | |
127 | /* f0-f8,fps. */ | |
128 | #define ARM_FP_REGS_SIZE (8 * ARM_FP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) | |
129 | /* d0-d15,fpscr. */ | |
130 | #define ARM_VFP2_REGS_SIZE (16 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) | |
131 | /* d0-d31,fpscr. */ | |
132 | #define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) | |
133 | /* wR0-wR15,fpscr. */ | |
134 | #define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \ | |
135 | + 6 * ARM_INT_REGISTER_SIZE) | |
cba7e83f | 136 | |
8689682c AT |
137 | /* Addresses for calling Thumb functions have the bit 0 set. |
138 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
139 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
140 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
141 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
142 | ||
d9311bfa AT |
143 | /* Support routines for instruction parsing. */ |
144 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
145 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
146 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
147 | #define sbits(obj,st,fn) \ | |
148 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
149 | #define BranchDest(addr,instr) \ | |
150 | ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
151 | ||
152 | /* Forward declaration. */ | |
153 | struct regcache; | |
154 | ||
8689682c AT |
155 | /* Return the size in bytes of the complete Thumb instruction whose |
156 | first halfword is INST1. */ | |
157 | int thumb_insn_size (unsigned short inst1); | |
158 | ||
cba7e83f AT |
159 | /* Returns true if the condition evaluates to true. */ |
160 | int condition_true (unsigned long cond, unsigned long status_reg); | |
161 | ||
162 | /* Return number of 1-bits in VAL. */ | |
163 | int bitcount (unsigned long val); | |
164 | ||
d9311bfa AT |
165 | /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */ |
166 | int arm_instruction_changes_pc (uint32_t this_instr); | |
167 | ||
168 | /* Return 1 if the 16-bit Thumb instruction INST might change | |
169 | control flow, 0 otherwise. */ | |
170 | int thumb_instruction_changes_pc (unsigned short inst); | |
171 | ||
172 | /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2 | |
173 | might change control flow, 0 otherwise. */ | |
174 | int thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2); | |
175 | ||
176 | /* Advance the state of the IT block and return that state. */ | |
177 | int thumb_advance_itstate (unsigned int itstate); | |
178 | ||
179 | /* Decode shifted register value. */ | |
180 | ||
181 | unsigned long shifted_reg_val (struct regcache *regcache, | |
182 | unsigned long inst, | |
183 | int carry, | |
184 | unsigned long pc_val, | |
185 | unsigned long status_reg); | |
186 | ||
d105cce5 AH |
187 | /* Create an Arm target description with the given FP hardware type. */ |
188 | ||
189 | target_desc *arm_create_target_description (arm_fp_type fp_type); | |
190 | ||
191 | /* Create an Arm M-profile target description with the given hardware type. */ | |
192 | ||
193 | target_desc *arm_create_mprofile_target_description (arm_m_profile_type m_type); | |
194 | ||
1a5c2598 | 195 | #endif /* ARCH_ARM_H */ |