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ec741292 | 1 | /* Common target dependent code for GDB on ARM systems. |
b811d2c2 | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
ec741292 YQ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
1a5c2598 TT |
19 | #ifndef ARCH_ARM_H |
20 | #define ARCH_ARM_H | |
ec741292 | 21 | |
d105cce5 AH |
22 | #include "gdbsupport/tdesc.h" |
23 | ||
ec741292 YQ |
24 | /* Register numbers of various important registers. */ |
25 | ||
26 | enum gdb_regnum { | |
27 | ARM_A1_REGNUM = 0, /* first integer-like argument */ | |
28 | ARM_A4_REGNUM = 3, /* last integer-like argument */ | |
29 | ARM_AP_REGNUM = 11, | |
30 | ARM_IP_REGNUM = 12, | |
31 | ARM_SP_REGNUM = 13, /* Contains address of top of stack */ | |
32 | ARM_LR_REGNUM = 14, /* address to return to from a function call */ | |
33 | ARM_PC_REGNUM = 15, /* Contains program counter */ | |
bda874f6 | 34 | /* F0..F7 are the fp registers for the (obsolete) FPA architecture. */ |
ec741292 YQ |
35 | ARM_F0_REGNUM = 16, /* first floating point register */ |
36 | ARM_F3_REGNUM = 19, /* last floating point argument register */ | |
37 | ARM_F7_REGNUM = 23, /* last floating point register */ | |
38 | ARM_FPS_REGNUM = 24, /* floating point status register */ | |
39 | ARM_PS_REGNUM = 25, /* Contains processor status */ | |
40 | ARM_WR0_REGNUM, /* WMMX data registers. */ | |
41 | ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15, | |
42 | ARM_WC0_REGNUM, /* WMMX control registers. */ | |
43 | ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2, | |
44 | ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3, | |
45 | ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7, | |
46 | ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */ | |
47 | ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3, | |
48 | ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7, | |
49 | ARM_D0_REGNUM, /* VFP double-precision registers. */ | |
50 | ARM_D31_REGNUM = ARM_D0_REGNUM + 31, | |
51 | ARM_FPSCR_REGNUM, | |
52 | ||
53 | ARM_NUM_REGS, | |
54 | ||
55 | /* Other useful registers. */ | |
56 | ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */ | |
57 | THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */ | |
58 | ARM_NUM_ARG_REGS = 4, | |
59 | ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM, | |
60 | ARM_NUM_FP_ARG_REGS = 4, | |
61 | ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM | |
62 | }; | |
63 | ||
a1078bea YQ |
64 | /* Enum describing the different kinds of breakpoints. */ |
65 | enum arm_breakpoint_kinds | |
66 | { | |
67 | ARM_BP_KIND_THUMB = 2, | |
68 | ARM_BP_KIND_THUMB2 = 3, | |
69 | ARM_BP_KIND_ARM = 4, | |
70 | }; | |
71 | ||
d105cce5 AH |
72 | /* Supported Arm FP hardware types. */ |
73 | enum arm_fp_type { | |
74 | ARM_FP_TYPE_NONE = 0, | |
75 | ARM_FP_TYPE_VFPV2, | |
76 | ARM_FP_TYPE_VFPV3, | |
77 | ARM_FP_TYPE_IWMMXT, | |
78 | ARM_FP_TYPE_INVALID | |
79 | }; | |
80 | ||
81 | /* Supported M-profile Arm types. */ | |
82 | enum arm_m_profile_type { | |
83 | ARM_M_TYPE_M_PROFILE, | |
84 | ARM_M_TYPE_VFP_D16, | |
85 | ARM_M_TYPE_WITH_FPA, | |
86 | ARM_M_TYPE_INVALID | |
87 | }; | |
88 | ||
cba7e83f AT |
89 | /* Instruction condition field values. */ |
90 | #define INST_EQ 0x0 | |
91 | #define INST_NE 0x1 | |
92 | #define INST_CS 0x2 | |
93 | #define INST_CC 0x3 | |
94 | #define INST_MI 0x4 | |
95 | #define INST_PL 0x5 | |
96 | #define INST_VS 0x6 | |
97 | #define INST_VC 0x7 | |
98 | #define INST_HI 0x8 | |
99 | #define INST_LS 0x9 | |
100 | #define INST_GE 0xa | |
101 | #define INST_LT 0xb | |
102 | #define INST_GT 0xc | |
103 | #define INST_LE 0xd | |
104 | #define INST_AL 0xe | |
105 | #define INST_NV 0xf | |
106 | ||
107 | #define FLAG_N 0x80000000 | |
108 | #define FLAG_Z 0x40000000 | |
109 | #define FLAG_C 0x20000000 | |
110 | #define FLAG_V 0x10000000 | |
111 | ||
112 | #define CPSR_T 0x20 | |
113 | ||
114 | #define XPSR_T 0x01000000 | |
115 | ||
f0452268 AH |
116 | /* Size of registers. */ |
117 | ||
118 | #define ARM_INT_REGISTER_SIZE 4 | |
119 | /* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */ | |
120 | #define ARM_FP_REGISTER_SIZE 12 | |
121 | #define ARM_VFP_REGISTER_SIZE 8 | |
350fab54 AH |
122 | #define IWMMXT_VEC_REGISTER_SIZE 8 |
123 | ||
124 | /* Size of register sets. */ | |
125 | ||
126 | /* r0-r12,sp,lr,pc,cpsr. */ | |
127 | #define ARM_CORE_REGS_SIZE (17 * ARM_INT_REGISTER_SIZE) | |
128 | /* f0-f8,fps. */ | |
129 | #define ARM_FP_REGS_SIZE (8 * ARM_FP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) | |
130 | /* d0-d15,fpscr. */ | |
131 | #define ARM_VFP2_REGS_SIZE (16 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) | |
132 | /* d0-d31,fpscr. */ | |
133 | #define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) | |
134 | /* wR0-wR15,fpscr. */ | |
135 | #define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \ | |
136 | + 6 * ARM_INT_REGISTER_SIZE) | |
cba7e83f | 137 | |
8689682c AT |
138 | /* Addresses for calling Thumb functions have the bit 0 set. |
139 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
140 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
141 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
142 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
143 | ||
d9311bfa AT |
144 | /* Support routines for instruction parsing. */ |
145 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
146 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
147 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
148 | #define sbits(obj,st,fn) \ | |
149 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
150 | #define BranchDest(addr,instr) \ | |
151 | ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
152 | ||
153 | /* Forward declaration. */ | |
154 | struct regcache; | |
155 | ||
8689682c AT |
156 | /* Return the size in bytes of the complete Thumb instruction whose |
157 | first halfword is INST1. */ | |
158 | int thumb_insn_size (unsigned short inst1); | |
159 | ||
cba7e83f AT |
160 | /* Returns true if the condition evaluates to true. */ |
161 | int condition_true (unsigned long cond, unsigned long status_reg); | |
162 | ||
d9311bfa AT |
163 | /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */ |
164 | int arm_instruction_changes_pc (uint32_t this_instr); | |
165 | ||
166 | /* Return 1 if the 16-bit Thumb instruction INST might change | |
167 | control flow, 0 otherwise. */ | |
168 | int thumb_instruction_changes_pc (unsigned short inst); | |
169 | ||
170 | /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2 | |
171 | might change control flow, 0 otherwise. */ | |
172 | int thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2); | |
173 | ||
174 | /* Advance the state of the IT block and return that state. */ | |
175 | int thumb_advance_itstate (unsigned int itstate); | |
176 | ||
177 | /* Decode shifted register value. */ | |
178 | ||
179 | unsigned long shifted_reg_val (struct regcache *regcache, | |
180 | unsigned long inst, | |
181 | int carry, | |
182 | unsigned long pc_val, | |
183 | unsigned long status_reg); | |
184 | ||
d105cce5 AH |
185 | /* Create an Arm target description with the given FP hardware type. */ |
186 | ||
187 | target_desc *arm_create_target_description (arm_fp_type fp_type); | |
188 | ||
189 | /* Create an Arm M-profile target description with the given hardware type. */ | |
190 | ||
191 | target_desc *arm_create_mprofile_target_description (arm_m_profile_type m_type); | |
192 | ||
1a5c2598 | 193 | #endif /* ARCH_ARM_H */ |