Commit | Line | Data |
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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
e2882c85 | 2 | Copyright (C) 1999-2018 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
4e052eda | 22 | #include "regcache.h" |
10d6c8cd DJ |
23 | #include "target.h" |
24 | #include "linux-nat.h" | |
05a4558a | 25 | #include "target-descriptions.h" |
3b273a55 | 26 | #include "auxv.h" |
76727919 | 27 | #include "observable.h" |
e3039479 | 28 | #include "gdbthread.h" |
ed9a39eb | 29 | |
aeb98c60 | 30 | #include "arm-tdep.h" |
cb587d83 | 31 | #include "arm-linux-tdep.h" |
f1b67888 | 32 | #include "aarch32-linux-nat.h" |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb | 35 | #include <sys/user.h> |
5826e159 | 36 | #include "nat/gdb_ptrace.h" |
ed9a39eb | 37 | #include <sys/utsname.h> |
41c49b06 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
95855ca8 MS |
40 | #include "nat/linux-ptrace.h" |
41 | ||
0963b4bd | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
43 | #include "gregset.h" |
44 | ||
9308fc88 DJ |
45 | /* Defines ps_err_e, struct ps_prochandle. */ |
46 | #include "gdb_proc_service.h" | |
47 | ||
48 | #ifndef PTRACE_GET_THREAD_AREA | |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
05a4558a DJ |
52 | #ifndef PTRACE_GETWMMXREGS |
53 | #define PTRACE_GETWMMXREGS 18 | |
54 | #define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
3b273a55 RE |
57 | #ifndef PTRACE_GETVFPREGS |
58 | #define PTRACE_GETVFPREGS 27 | |
59 | #define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
e3039479 UW |
62 | #ifndef PTRACE_GETHBPREGS |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
ed9a39eb JM |
67 | extern int arm_apcs_32; |
68 | ||
f6ac5f3d PA |
69 | class arm_linux_nat_target final : public linux_nat_target |
70 | { | |
71 | public: | |
72 | /* Add our register access methods. */ | |
73 | void fetch_registers (struct regcache *, int) override; | |
74 | void store_registers (struct regcache *, int) override; | |
75 | ||
76 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
77 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
78 | ||
79 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
80 | ||
81 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
82 | ||
83 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
84 | ||
85 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
86 | struct expression *) override; | |
87 | ||
88 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
89 | struct expression *) override; | |
57810aa7 | 90 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 91 | |
57810aa7 | 92 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 93 | |
57810aa7 | 94 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d PA |
95 | |
96 | const struct target_desc *read_description () override; | |
135340af PA |
97 | |
98 | /* Override linux_nat_target low methods. */ | |
99 | ||
100 | /* Handle thread creation and exit. */ | |
101 | void low_new_thread (struct lwp_info *lp) override; | |
102 | void low_delete_thread (struct arch_lwp_info *lp) override; | |
103 | void low_prepare_to_resume (struct lwp_info *lp) override; | |
104 | ||
105 | /* Handle process creation and exit. */ | |
106 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
107 | void low_forget_process (pid_t pid) override; | |
f6ac5f3d PA |
108 | }; |
109 | ||
110 | static arm_linux_nat_target the_arm_linux_nat_target; | |
111 | ||
41c49b06 | 112 | /* Get the whole floating point state of the process and store it |
c6b92abd | 113 | into regcache. */ |
ed9a39eb JM |
114 | |
115 | static void | |
56be3814 | 116 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 117 | { |
41c49b06 | 118 | int ret, regno, tid; |
cb587d83 | 119 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 120 | |
41c49b06 | 121 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 122 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
df9d7ec9 | 123 | |
ed9a39eb | 124 | /* Read the floating point state. */ |
0bdb2f78 | 125 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
126 | { |
127 | struct iovec iov; | |
128 | ||
129 | iov.iov_base = &fp; | |
130 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
131 | ||
132 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
133 | } | |
134 | else | |
135 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
136 | ||
ed9a39eb | 137 | if (ret < 0) |
d86feca3 | 138 | perror_with_name (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
139 | |
140 | /* Fetch fpsr. */ | |
56be3814 | 141 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 142 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
143 | |
144 | /* Fetch the floating point registers. */ | |
34e8f22d | 145 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 146 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
147 | } |
148 | ||
149 | /* Save the whole floating point state of the process using | |
c6b92abd | 150 | the contents from regcache. */ |
ed9a39eb JM |
151 | |
152 | static void | |
56be3814 | 153 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 154 | { |
41c49b06 | 155 | int ret, regno, tid; |
cb587d83 | 156 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 157 | |
41c49b06 | 158 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 159 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
df9d7ec9 | 160 | |
41c49b06 | 161 | /* Read the floating point state. */ |
0bdb2f78 | 162 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
163 | { |
164 | elf_fpregset_t fpregs; | |
165 | struct iovec iov; | |
166 | ||
167 | iov.iov_base = &fpregs; | |
168 | iov.iov_len = sizeof (fpregs); | |
169 | ||
170 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
171 | } | |
172 | else | |
173 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
174 | ||
41c49b06 | 175 | if (ret < 0) |
d86feca3 | 176 | perror_with_name (_("Unable to fetch the floating point registers.")); |
41c49b06 | 177 | |
ed9a39eb | 178 | /* Store fpsr. */ |
672c9795 | 179 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 180 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
181 | |
182 | /* Store the floating point registers. */ | |
34e8f22d | 183 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 184 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 185 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 186 | |
0bdb2f78 | 187 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
188 | { |
189 | struct iovec iov; | |
190 | ||
191 | iov.iov_base = &fp; | |
192 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
193 | ||
194 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
195 | } | |
196 | else | |
197 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
198 | ||
ed9a39eb | 199 | if (ret < 0) |
d86feca3 | 200 | perror_with_name (_("Unable to store floating point registers.")); |
ed9a39eb JM |
201 | } |
202 | ||
203 | /* Fetch all general registers of the process and store into | |
c6b92abd | 204 | regcache. */ |
ed9a39eb JM |
205 | |
206 | static void | |
56be3814 | 207 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 208 | { |
41c49b06 | 209 | int ret, regno, tid; |
c2152441 | 210 | elf_gregset_t regs; |
ed9a39eb | 211 | |
41c49b06 | 212 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 213 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
10766686 | 214 | |
0bdb2f78 | 215 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
216 | { |
217 | struct iovec iov; | |
218 | ||
219 | iov.iov_base = ®s; | |
220 | iov.iov_len = sizeof (regs); | |
221 | ||
222 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
223 | } | |
224 | else | |
225 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
226 | ||
ed9a39eb | 227 | if (ret < 0) |
d86feca3 | 228 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 229 | |
f1b67888 | 230 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
231 | } |
232 | ||
ed9a39eb | 233 | static void |
56be3814 | 234 | store_regs (const struct regcache *regcache) |
ed9a39eb | 235 | { |
41c49b06 | 236 | int ret, regno, tid; |
c2152441 | 237 | elf_gregset_t regs; |
ed9a39eb | 238 | |
41c49b06 | 239 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 240 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
10766686 | 241 | |
41c49b06 | 242 | /* Fetch the general registers. */ |
0bdb2f78 | 243 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
244 | { |
245 | struct iovec iov; | |
246 | ||
247 | iov.iov_base = ®s; | |
248 | iov.iov_len = sizeof (regs); | |
249 | ||
250 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
251 | } | |
252 | else | |
253 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
254 | ||
ed9a39eb | 255 | if (ret < 0) |
d86feca3 | 256 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 257 | |
f1b67888 | 258 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 259 | |
0bdb2f78 | 260 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
261 | { |
262 | struct iovec iov; | |
263 | ||
264 | iov.iov_base = ®s; | |
265 | iov.iov_len = sizeof (regs); | |
266 | ||
267 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
268 | } | |
269 | else | |
270 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
271 | |
272 | if (ret < 0) | |
d86feca3 | 273 | perror_with_name (_("Unable to store general registers.")); |
ed9a39eb JM |
274 | } |
275 | ||
05a4558a DJ |
276 | /* Fetch all WMMX registers of the process and store into |
277 | regcache. */ | |
278 | ||
279 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
280 | ||
281 | static void | |
56be3814 | 282 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
283 | { |
284 | char regbuf[IWMMXT_REGS_SIZE]; | |
285 | int ret, regno, tid; | |
286 | ||
287 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 288 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
05a4558a DJ |
289 | |
290 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
291 | if (ret < 0) | |
d86feca3 | 292 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
293 | |
294 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 295 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
296 | ®buf[regno * 8]); |
297 | ||
298 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 299 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
300 | ®buf[16 * 8 + regno * 4]); |
301 | ||
302 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 303 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
304 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
305 | } | |
306 | ||
307 | static void | |
56be3814 | 308 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
309 | { |
310 | char regbuf[IWMMXT_REGS_SIZE]; | |
311 | int ret, regno, tid; | |
312 | ||
313 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 314 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
05a4558a DJ |
315 | |
316 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
317 | if (ret < 0) | |
d86feca3 | 318 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
319 | |
320 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
321 | if (REG_VALID == regcache_register_status (regcache, |
322 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 323 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
324 | ®buf[regno * 8]); |
325 | ||
326 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
327 | if (REG_VALID == regcache_register_status (regcache, |
328 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 329 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
330 | ®buf[16 * 8 + regno * 4]); |
331 | ||
332 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
333 | if (REG_VALID == regcache_register_status (regcache, |
334 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 335 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
336 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
337 | ||
338 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
339 | ||
340 | if (ret < 0) | |
d86feca3 | 341 | perror_with_name (_("Unable to store WMMX registers.")); |
05a4558a DJ |
342 | } |
343 | ||
3b273a55 RE |
344 | static void |
345 | fetch_vfp_regs (struct regcache *regcache) | |
346 | { | |
f1b67888 | 347 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 348 | int ret, regno, tid; |
ac7936df | 349 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 350 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
351 | |
352 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 353 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
3b273a55 | 354 | |
0bdb2f78 | 355 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
356 | { |
357 | struct iovec iov; | |
358 | ||
359 | iov.iov_base = regbuf; | |
360 | iov.iov_len = VFP_REGS_SIZE; | |
361 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
362 | } | |
363 | else | |
364 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
365 | ||
3b273a55 | 366 | if (ret < 0) |
d86feca3 | 367 | perror_with_name (_("Unable to fetch VFP registers.")); |
3b273a55 | 368 | |
f1b67888 YQ |
369 | aarch32_vfp_regcache_supply (regcache, regbuf, |
370 | tdep->vfp_register_count); | |
3b273a55 RE |
371 | } |
372 | ||
373 | static void | |
374 | store_vfp_regs (const struct regcache *regcache) | |
375 | { | |
f1b67888 | 376 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 377 | int ret, regno, tid; |
ac7936df | 378 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 379 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
380 | |
381 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 382 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
3b273a55 | 383 | |
0bdb2f78 | 384 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
385 | { |
386 | struct iovec iov; | |
387 | ||
388 | iov.iov_base = regbuf; | |
389 | iov.iov_len = VFP_REGS_SIZE; | |
390 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
391 | } | |
392 | else | |
393 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
394 | ||
3b273a55 | 395 | if (ret < 0) |
d86feca3 | 396 | perror_with_name (_("Unable to fetch VFP registers (for update).")); |
3b273a55 | 397 | |
f1b67888 YQ |
398 | aarch32_vfp_regcache_collect (regcache, regbuf, |
399 | tdep->vfp_register_count); | |
3b273a55 | 400 | |
0bdb2f78 | 401 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
402 | { |
403 | struct iovec iov; | |
404 | ||
405 | iov.iov_base = regbuf; | |
406 | iov.iov_len = VFP_REGS_SIZE; | |
407 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); | |
408 | } | |
409 | else | |
410 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
411 | |
412 | if (ret < 0) | |
d86feca3 | 413 | perror_with_name (_("Unable to store VFP registers.")); |
3b273a55 RE |
414 | } |
415 | ||
ed9a39eb JM |
416 | /* Fetch registers from the child process. Fetch all registers if |
417 | regno == -1, otherwise fetch all general registers or all floating | |
418 | point registers depending upon the value of regno. */ | |
419 | ||
f6ac5f3d PA |
420 | void |
421 | arm_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 422 | { |
ac7936df | 423 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
424 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
425 | ||
41c49b06 SB |
426 | if (-1 == regno) |
427 | { | |
56be3814 | 428 | fetch_regs (regcache); |
a56cc1ce | 429 | if (tdep->have_wmmx_registers) |
56be3814 | 430 | fetch_wmmx_regs (regcache); |
330c6ca9 | 431 | if (tdep->vfp_register_count > 0) |
3b273a55 | 432 | fetch_vfp_regs (regcache); |
4bd2e1b2 KC |
433 | if (tdep->have_fpa_registers) |
434 | fetch_fpregs (regcache); | |
41c49b06 | 435 | } |
4bd2e1b2 | 436 | else |
41c49b06 | 437 | { |
05a4558a | 438 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 439 | fetch_regs (regcache); |
05a4558a | 440 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 441 | fetch_fpregs (regcache); |
a56cc1ce | 442 | else if (tdep->have_wmmx_registers |
05a4558a | 443 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 444 | fetch_wmmx_regs (regcache); |
330c6ca9 | 445 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 446 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
447 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
448 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 449 | fetch_vfp_regs (regcache); |
41c49b06 | 450 | } |
ed9a39eb JM |
451 | } |
452 | ||
453 | /* Store registers back into the inferior. Store all registers if | |
454 | regno == -1, otherwise store all general registers or all floating | |
455 | point registers depending upon the value of regno. */ | |
456 | ||
f6ac5f3d PA |
457 | void |
458 | arm_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 459 | { |
ac7936df | 460 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
461 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
462 | ||
41c49b06 SB |
463 | if (-1 == regno) |
464 | { | |
56be3814 | 465 | store_regs (regcache); |
a56cc1ce | 466 | if (tdep->have_wmmx_registers) |
56be3814 | 467 | store_wmmx_regs (regcache); |
330c6ca9 | 468 | if (tdep->vfp_register_count > 0) |
3b273a55 | 469 | store_vfp_regs (regcache); |
4bd2e1b2 KC |
470 | if (tdep->have_fpa_registers) |
471 | store_fpregs (regcache); | |
41c49b06 SB |
472 | } |
473 | else | |
474 | { | |
05a4558a | 475 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 476 | store_regs (regcache); |
05a4558a | 477 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 478 | store_fpregs (regcache); |
a56cc1ce | 479 | else if (tdep->have_wmmx_registers |
05a4558a | 480 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 481 | store_wmmx_regs (regcache); |
330c6ca9 | 482 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 483 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
484 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
485 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 486 | store_vfp_regs (regcache); |
41c49b06 | 487 | } |
ed9a39eb JM |
488 | } |
489 | ||
cb587d83 DJ |
490 | /* Wrapper functions for the standard regset handling, used by |
491 | thread debugging. */ | |
41c49b06 SB |
492 | |
493 | void | |
7f7fe91e UW |
494 | fill_gregset (const struct regcache *regcache, |
495 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 496 | { |
7f7fe91e | 497 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
498 | } |
499 | ||
41c49b06 | 500 | void |
7f7fe91e | 501 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 502 | { |
7f7fe91e | 503 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
504 | } |
505 | ||
41c49b06 | 506 | void |
7f7fe91e UW |
507 | fill_fpregset (const struct regcache *regcache, |
508 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 509 | { |
7f7fe91e | 510 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
511 | } |
512 | ||
513 | /* Fill GDB's register array with the floating-point register values | |
514 | in *fpregsetp. */ | |
515 | ||
516 | void | |
7f7fe91e | 517 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 518 | { |
7f7fe91e | 519 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
520 | } |
521 | ||
9308fc88 DJ |
522 | /* Fetch the thread-local storage pointer for libthread_db. */ |
523 | ||
524 | ps_err_e | |
754653a7 | 525 | ps_get_thread_area (struct ps_prochandle *ph, |
9308fc88 DJ |
526 | lwpid_t lwpid, int idx, void **base) |
527 | { | |
528 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
529 | return PS_ERR; | |
530 | ||
531 | /* IDX is the bias from the thread pointer to the beginning of the | |
532 | thread descriptor. It has to be subtracted due to implementation | |
533 | quirks in libthread_db. */ | |
534 | *base = (void *) ((char *)*base - idx); | |
535 | ||
536 | return PS_OK; | |
537 | } | |
538 | ||
f6ac5f3d PA |
539 | const struct target_desc * |
540 | arm_linux_nat_target::read_description () | |
05a4558a | 541 | { |
3b273a55 | 542 | CORE_ADDR arm_hwcap = 0; |
05a4558a | 543 | |
0bdb2f78 | 544 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
545 | { |
546 | elf_gregset_t gpregs; | |
547 | struct iovec iov; | |
d89fa914 | 548 | int tid = ptid_get_lwp (inferior_ptid); |
7efe48d1 YQ |
549 | |
550 | iov.iov_base = &gpregs; | |
551 | iov.iov_len = sizeof (gpregs); | |
552 | ||
553 | /* Check if PTRACE_GETREGSET works. */ | |
554 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 555 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 556 | else |
0bdb2f78 | 557 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
558 | } |
559 | ||
f6ac5f3d | 560 | if (target_auxv_search (this, AT_HWCAP, &arm_hwcap) != 1) |
3b273a55 | 561 | { |
f6ac5f3d | 562 | return this->beneath->read_description (); |
3b273a55 | 563 | } |
81adfced | 564 | |
3b273a55 | 565 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 566 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
567 | |
568 | if (arm_hwcap & HWCAP_VFP) | |
569 | { | |
570 | int pid; | |
571 | char *buf; | |
572 | const struct target_desc * result = NULL; | |
573 | ||
574 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
575 | Neon with VFPv3-D32. */ | |
576 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 577 | result = tdesc_arm_with_neon; |
3b273a55 | 578 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 579 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 580 | else |
330c6ca9 | 581 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
582 | |
583 | /* Now make sure that the kernel supports reading these | |
584 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 585 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 | 586 | errno = 0; |
f844cf0e | 587 | buf = (char *) alloca (VFP_REGS_SIZE); |
3b273a55 RE |
588 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
589 | && errno == EIO) | |
590 | result = NULL; | |
591 | ||
592 | return result; | |
593 | } | |
594 | ||
f6ac5f3d | 595 | return this->beneath->read_description (); |
05a4558a DJ |
596 | } |
597 | ||
e3039479 UW |
598 | /* Information describing the hardware breakpoint capabilities. */ |
599 | struct arm_linux_hwbp_cap | |
600 | { | |
601 | gdb_byte arch; | |
602 | gdb_byte max_wp_length; | |
603 | gdb_byte wp_count; | |
604 | gdb_byte bp_count; | |
605 | }; | |
606 | ||
638c5f49 OJ |
607 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
608 | assume a maximum number of supported break-/watchpoints. */ | |
609 | #define MAX_BPTS 16 | |
610 | #define MAX_WPTS 16 | |
611 | ||
e3039479 UW |
612 | /* Get hold of the Hardware Breakpoint information for the target we are |
613 | attached to. Returns NULL if the kernel doesn't support Hardware | |
614 | breakpoints at all, or a pointer to the information structure. */ | |
615 | static const struct arm_linux_hwbp_cap * | |
616 | arm_linux_get_hwbp_cap (void) | |
617 | { | |
618 | /* The info structure we return. */ | |
619 | static struct arm_linux_hwbp_cap info; | |
620 | ||
621 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
622 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
623 | means INFO is in an initialized state. */ | |
624 | static int available = -1; | |
625 | ||
626 | if (available == -1) | |
627 | { | |
628 | int tid; | |
629 | unsigned int val; | |
630 | ||
d89fa914 | 631 | tid = ptid_get_lwp (inferior_ptid); |
e3039479 UW |
632 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
633 | available = 0; | |
634 | else | |
635 | { | |
636 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
637 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
638 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
639 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
640 | |
641 | if (info.wp_count > MAX_WPTS) | |
642 | { | |
643 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
644 | supports %d"), MAX_WPTS, info.wp_count); | |
645 | info.wp_count = MAX_WPTS; | |
646 | } | |
647 | ||
648 | if (info.bp_count > MAX_BPTS) | |
649 | { | |
650 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
651 | supports %d"), MAX_BPTS, info.bp_count); | |
652 | info.bp_count = MAX_BPTS; | |
653 | } | |
e3039479 UW |
654 | available = (info.arch != 0); |
655 | } | |
656 | } | |
657 | ||
658 | return available == 1 ? &info : NULL; | |
659 | } | |
660 | ||
661 | /* How many hardware breakpoints are available? */ | |
662 | static int | |
663 | arm_linux_get_hw_breakpoint_count (void) | |
664 | { | |
665 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
666 | return cap != NULL ? cap->bp_count : 0; | |
667 | } | |
668 | ||
669 | /* How many hardware watchpoints are available? */ | |
670 | static int | |
671 | arm_linux_get_hw_watchpoint_count (void) | |
672 | { | |
673 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
674 | return cap != NULL ? cap->wp_count : 0; | |
675 | } | |
676 | ||
677 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
678 | there is not an appropriate resource available, otherwise returns 1. */ | |
f6ac5f3d PA |
679 | int |
680 | arm_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
681 | int cnt, int ot) | |
e3039479 UW |
682 | { |
683 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
684 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
685 | { | |
dbbf180a YQ |
686 | int count = arm_linux_get_hw_watchpoint_count (); |
687 | ||
688 | if (count == 0) | |
689 | return 0; | |
690 | else if (cnt + ot > count) | |
e3039479 UW |
691 | return -1; |
692 | } | |
693 | else if (type == bp_hardware_breakpoint) | |
694 | { | |
dbbf180a YQ |
695 | int count = arm_linux_get_hw_breakpoint_count (); |
696 | ||
697 | if (count == 0) | |
698 | return 0; | |
699 | else if (cnt > count) | |
e3039479 UW |
700 | return -1; |
701 | } | |
702 | else | |
703 | gdb_assert (FALSE); | |
704 | ||
705 | return 1; | |
706 | } | |
707 | ||
708 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
709 | typedef enum | |
710 | { | |
711 | arm_hwbp_break = 0, | |
712 | arm_hwbp_load = 1, | |
713 | arm_hwbp_store = 2, | |
714 | arm_hwbp_access = 3 | |
715 | } arm_hwbp_type; | |
716 | ||
717 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
718 | typedef unsigned int arm_hwbp_control_t; | |
719 | ||
720 | /* Structure used to keep track of hardware break-/watch-points. */ | |
721 | struct arm_linux_hw_breakpoint | |
722 | { | |
723 | /* Address to break on, or being watched. */ | |
724 | unsigned int address; | |
725 | /* Control register for break-/watch- point. */ | |
726 | arm_hwbp_control_t control; | |
727 | }; | |
728 | ||
638c5f49 OJ |
729 | /* Structure containing arrays of per process hardware break-/watchpoints |
730 | for caching address and control information. | |
e3039479 UW |
731 | |
732 | The Linux ptrace interface to hardware break-/watch-points presents the | |
733 | values in a vector centred around 0 (which is used fo generic information). | |
734 | Positive indicies refer to breakpoint addresses/control registers, negative | |
735 | indices to watchpoint addresses/control registers. | |
736 | ||
737 | The Linux vector is indexed as follows: | |
738 | -((i << 1) + 2): Control register for watchpoint i. | |
739 | -((i << 1) + 1): Address register for watchpoint i. | |
740 | 0: Information register. | |
741 | ((i << 1) + 1): Address register for breakpoint i. | |
742 | ((i << 1) + 2): Control register for breakpoint i. | |
743 | ||
744 | This structure is used as a per-thread cache of the state stored by the | |
745 | kernel, so that we don't need to keep calling into the kernel to find a | |
746 | free breakpoint. | |
747 | ||
748 | We treat break-/watch-points with their enable bit clear as being deleted. | |
749 | */ | |
638c5f49 | 750 | struct arm_linux_debug_reg_state |
e3039479 | 751 | { |
638c5f49 OJ |
752 | /* Hardware breakpoints for this process. */ |
753 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
754 | /* Hardware watchpoints for this process. */ | |
755 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
756 | }; | |
757 | ||
758 | /* Per-process arch-specific data we want to keep. */ | |
759 | struct arm_linux_process_info | |
e3039479 | 760 | { |
638c5f49 OJ |
761 | /* Linked list. */ |
762 | struct arm_linux_process_info *next; | |
763 | /* The process identifier. */ | |
764 | pid_t pid; | |
765 | /* Hardware break-/watchpoints state information. */ | |
766 | struct arm_linux_debug_reg_state state; | |
e3039479 | 767 | |
638c5f49 OJ |
768 | }; |
769 | ||
770 | /* Per-thread arch-specific data we want to keep. */ | |
771 | struct arch_lwp_info | |
772 | { | |
773 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
774 | char bpts_changed[MAX_BPTS]; | |
775 | char wpts_changed[MAX_WPTS]; | |
776 | }; | |
777 | ||
778 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
779 | ||
780 | /* Find process data for process PID. */ | |
781 | ||
782 | static struct arm_linux_process_info * | |
783 | arm_linux_find_process_pid (pid_t pid) | |
784 | { | |
785 | struct arm_linux_process_info *proc; | |
786 | ||
787 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
788 | if (proc->pid == pid) | |
789 | return proc; | |
790 | ||
791 | return NULL; | |
792 | } | |
793 | ||
794 | /* Add process data for process PID. Returns newly allocated info | |
795 | object. */ | |
796 | ||
797 | static struct arm_linux_process_info * | |
798 | arm_linux_add_process (pid_t pid) | |
799 | { | |
800 | struct arm_linux_process_info *proc; | |
e3039479 | 801 | |
8d749320 | 802 | proc = XCNEW (struct arm_linux_process_info); |
638c5f49 | 803 | proc->pid = pid; |
e3039479 | 804 | |
638c5f49 OJ |
805 | proc->next = arm_linux_process_list; |
806 | arm_linux_process_list = proc; | |
807 | ||
808 | return proc; | |
809 | } | |
810 | ||
811 | /* Get data specific info for process PID, creating it if necessary. | |
812 | Never returns NULL. */ | |
813 | ||
814 | static struct arm_linux_process_info * | |
815 | arm_linux_process_info_get (pid_t pid) | |
816 | { | |
817 | struct arm_linux_process_info *proc; | |
818 | ||
819 | proc = arm_linux_find_process_pid (pid); | |
820 | if (proc == NULL) | |
821 | proc = arm_linux_add_process (pid); | |
822 | ||
823 | return proc; | |
824 | } | |
825 | ||
826 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
827 | data structures that keep track of debug register state. */ | |
828 | ||
135340af PA |
829 | void |
830 | arm_linux_nat_target::low_forget_process (pid_t pid) | |
638c5f49 OJ |
831 | { |
832 | struct arm_linux_process_info *proc, **proc_link; | |
833 | ||
834 | proc = arm_linux_process_list; | |
835 | proc_link = &arm_linux_process_list; | |
836 | ||
837 | while (proc != NULL) | |
838 | { | |
839 | if (proc->pid == pid) | |
e3039479 | 840 | { |
638c5f49 OJ |
841 | *proc_link = proc->next; |
842 | ||
843 | xfree (proc); | |
844 | return; | |
e3039479 UW |
845 | } |
846 | ||
638c5f49 OJ |
847 | proc_link = &proc->next; |
848 | proc = *proc_link; | |
849 | } | |
850 | } | |
851 | ||
852 | /* Get hardware break-/watchpoint state for process PID. */ | |
853 | ||
854 | static struct arm_linux_debug_reg_state * | |
855 | arm_linux_get_debug_reg_state (pid_t pid) | |
856 | { | |
857 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
858 | } |
859 | ||
860 | /* Initialize an ARM hardware break-/watch-point control register value. | |
861 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
862 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
863 | */ | |
864 | static arm_hwbp_control_t | |
865 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
866 | arm_hwbp_type hwbp_type, | |
867 | int enable) | |
868 | { | |
869 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
870 | gdb_assert (hwbp_type != arm_hwbp_break | |
871 | || ((byte_address_select & 0xfU) != 0)); | |
872 | ||
873 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
874 | } | |
875 | ||
876 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
877 | static int | |
878 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
879 | { | |
880 | return control & 0x1; | |
881 | } | |
882 | ||
883 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
884 | static arm_hwbp_control_t | |
885 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
886 | { | |
887 | return control & ~0x1; | |
888 | } | |
889 | ||
890 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
891 | enabled, and will point to the placed address of BP_TGT. */ | |
892 | static void | |
893 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
894 | struct bp_target_info *bp_tgt, | |
895 | struct arm_linux_hw_breakpoint *p) | |
896 | { | |
897 | unsigned mask; | |
0d5ed153 | 898 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
899 | |
900 | /* We have to create a mask for the control register which says which bits | |
901 | of the word pointed to by address to break on. */ | |
902 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
903 | { |
904 | mask = 0x3; | |
905 | address &= ~1; | |
906 | } | |
e3039479 | 907 | else |
fcf303ab UW |
908 | { |
909 | mask = 0xf; | |
910 | address &= ~3; | |
911 | } | |
e3039479 | 912 | |
fcf303ab | 913 | p->address = (unsigned int) address; |
e3039479 UW |
914 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
915 | } | |
916 | ||
8156fe7f | 917 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 918 | given when asked to set a watchpoint. */ |
e3039479 | 919 | static arm_hwbp_type |
f486487f | 920 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 921 | { |
8156fe7f | 922 | if (type == hw_read) |
e3039479 | 923 | return arm_hwbp_load; |
8156fe7f | 924 | else if (type == hw_write) |
e3039479 UW |
925 | return arm_hwbp_store; |
926 | else | |
927 | return arm_hwbp_access; | |
928 | } | |
929 | ||
930 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
931 | to LEN. The type of watchpoint is given in RW. */ | |
932 | static void | |
f486487f SM |
933 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
934 | enum target_hw_bp_type type, | |
e3039479 UW |
935 | struct arm_linux_hw_breakpoint *p) |
936 | { | |
937 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
938 | unsigned mask; | |
939 | ||
940 | gdb_assert (cap != NULL); | |
941 | gdb_assert (cap->max_wp_length != 0); | |
942 | ||
943 | mask = (1 << len) - 1; | |
944 | ||
945 | p->address = (unsigned int) addr; | |
946 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 947 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
948 | } |
949 | ||
950 | /* Are two break-/watch-points equal? */ | |
951 | static int | |
952 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
953 | const struct arm_linux_hw_breakpoint *p2) | |
954 | { | |
955 | return p1->address == p2->address && p1->control == p2->control; | |
956 | } | |
957 | ||
638c5f49 OJ |
958 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
959 | the current process. */ | |
960 | ||
961 | struct update_registers_data | |
962 | { | |
963 | int watch; | |
964 | int index; | |
965 | }; | |
966 | ||
967 | static int | |
968 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
969 | { | |
970 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
971 | ||
972 | if (lwp->arch_private == NULL) | |
973 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
974 | ||
975 | /* The actual update is done later just before resuming the lwp, | |
976 | we just mark that the registers need updating. */ | |
977 | if (data->watch) | |
978 | lwp->arch_private->wpts_changed[data->index] = 1; | |
979 | else | |
980 | lwp->arch_private->bpts_changed[data->index] = 1; | |
981 | ||
982 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
983 | we can update its breakpoint registers. */ | |
984 | if (!lwp->stopped) | |
985 | linux_stop_lwp (lwp); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
e3039479 UW |
990 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
991 | =1) BPT for thread TID. */ | |
992 | static void | |
993 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 994 | int watchpoint) |
e3039479 | 995 | { |
638c5f49 OJ |
996 | int pid; |
997 | ptid_t pid_ptid; | |
e3039479 UW |
998 | gdb_byte count, i; |
999 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 1000 | struct update_registers_data data; |
e3039479 | 1001 | |
638c5f49 OJ |
1002 | pid = ptid_get_pid (inferior_ptid); |
1003 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1004 | |
1005 | if (watchpoint) | |
1006 | { | |
1007 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1008 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1009 | } |
1010 | else | |
1011 | { | |
1012 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1013 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1014 | } |
1015 | ||
1016 | for (i = 0; i < count; ++i) | |
1017 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1018 | { | |
638c5f49 OJ |
1019 | data.watch = watchpoint; |
1020 | data.index = i; | |
1021 | bpts[i] = *bpt; | |
1022 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1023 | break; | |
e3039479 UW |
1024 | } |
1025 | ||
1026 | gdb_assert (i != count); | |
1027 | } | |
1028 | ||
1029 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1030 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1031 | static void | |
1032 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1033 | int watchpoint) |
e3039479 | 1034 | { |
638c5f49 | 1035 | int pid; |
e3039479 | 1036 | gdb_byte count, i; |
638c5f49 OJ |
1037 | ptid_t pid_ptid; |
1038 | struct arm_linux_hw_breakpoint* bpts; | |
1039 | struct update_registers_data data; | |
e3039479 | 1040 | |
638c5f49 OJ |
1041 | pid = ptid_get_pid (inferior_ptid); |
1042 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1043 | |
1044 | if (watchpoint) | |
1045 | { | |
1046 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1047 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1048 | } |
1049 | else | |
1050 | { | |
1051 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1052 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1053 | } |
1054 | ||
1055 | for (i = 0; i < count; ++i) | |
1056 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1057 | { | |
638c5f49 OJ |
1058 | data.watch = watchpoint; |
1059 | data.index = i; | |
1060 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1061 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1062 | break; | |
e3039479 UW |
1063 | } |
1064 | ||
1065 | gdb_assert (i != count); | |
1066 | } | |
1067 | ||
1068 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1069 | int |
1070 | arm_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1071 | struct bp_target_info *bp_tgt) | |
e3039479 | 1072 | { |
e3039479 UW |
1073 | struct lwp_info *lp; |
1074 | struct arm_linux_hw_breakpoint p; | |
1075 | ||
1076 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1077 | return -1; | |
1078 | ||
1079 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1080 | |
1081 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1082 | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1087 | int |
1088 | arm_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1089 | struct bp_target_info *bp_tgt) | |
e3039479 | 1090 | { |
e3039479 UW |
1091 | struct lwp_info *lp; |
1092 | struct arm_linux_hw_breakpoint p; | |
1093 | ||
1094 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1095 | return -1; | |
1096 | ||
1097 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1098 | |
1099 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1100 | |
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1105 | ADDR? */ | |
f6ac5f3d PA |
1106 | int |
1107 | arm_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e3039479 UW |
1108 | { |
1109 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1110 | CORE_ADDR max_wp_length, aligned_addr; | |
1111 | ||
1112 | /* Can not set watchpoints for zero or negative lengths. */ | |
1113 | if (len <= 0) | |
1114 | return 0; | |
1115 | ||
1116 | /* Need to be able to use the ptrace interface. */ | |
1117 | if (cap == NULL || cap->wp_count == 0) | |
1118 | return 0; | |
1119 | ||
1120 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1121 | range covered by a watchpoint. */ | |
1122 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1123 | aligned_addr = addr & ~(max_wp_length - 1); | |
1124 | ||
1125 | if (aligned_addr + max_wp_length < addr + len) | |
1126 | return 0; | |
1127 | ||
1128 | /* The current ptrace interface can only handle watchpoints that are a | |
1129 | power of 2. */ | |
1130 | if ((len & (len - 1)) != 0) | |
1131 | return 0; | |
1132 | ||
1133 | /* All tests passed so we must be able to set a watchpoint. */ | |
1134 | return 1; | |
1135 | } | |
1136 | ||
1137 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1138 | int |
1139 | arm_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
1140 | enum target_hw_bp_type rw, | |
1141 | struct expression *cond) | |
e3039479 | 1142 | { |
e3039479 UW |
1143 | struct lwp_info *lp; |
1144 | struct arm_linux_hw_breakpoint p; | |
1145 | ||
1146 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1147 | return -1; | |
1148 | ||
1149 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1150 | |
1151 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1152 | |
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1157 | int |
1158 | arm_linux_nat_target::remove_watchpoint (CORE_ADDR addr, | |
1159 | int len, enum target_hw_bp_type rw, | |
1160 | struct expression *cond) | |
e3039479 | 1161 | { |
e3039479 UW |
1162 | struct lwp_info *lp; |
1163 | struct arm_linux_hw_breakpoint p; | |
1164 | ||
1165 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1166 | return -1; | |
1167 | ||
1168 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1169 | |
1170 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1171 | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | /* What was the data address the target was stopped on accessing. */ | |
57810aa7 | 1176 | bool |
f6ac5f3d | 1177 | arm_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e3039479 | 1178 | { |
f865ee35 JK |
1179 | siginfo_t siginfo; |
1180 | int slot; | |
1181 | ||
1182 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 1183 | return false; |
e3039479 UW |
1184 | |
1185 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1186 | if (siginfo.si_signo != SIGTRAP |
1187 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 1188 | return false; |
e3039479 UW |
1189 | |
1190 | /* We must be able to set hardware watchpoints. */ | |
1191 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1192 | return 0; | |
1193 | ||
f865ee35 JK |
1194 | slot = siginfo.si_errno; |
1195 | ||
e3039479 UW |
1196 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1197 | a watchpoint. */ | |
1198 | if (slot >= 0) | |
57810aa7 | 1199 | return false; |
e3039479 | 1200 | |
f865ee35 | 1201 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 1202 | return true; |
e3039479 UW |
1203 | } |
1204 | ||
1205 | /* Has the target been stopped by hitting a watchpoint? */ | |
57810aa7 | 1206 | bool |
f6ac5f3d | 1207 | arm_linux_nat_target::stopped_by_watchpoint () |
e3039479 UW |
1208 | { |
1209 | CORE_ADDR addr; | |
f6ac5f3d | 1210 | return stopped_data_address (&addr); |
e3039479 UW |
1211 | } |
1212 | ||
57810aa7 | 1213 | bool |
f6ac5f3d PA |
1214 | arm_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
1215 | CORE_ADDR start, | |
1216 | int length) | |
e3039479 UW |
1217 | { |
1218 | return start <= addr && start + length - 1 >= addr; | |
1219 | } | |
1220 | ||
1221 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1222 | in the parent thread to the child thread. */ | |
135340af PA |
1223 | void |
1224 | arm_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e3039479 | 1225 | { |
638c5f49 OJ |
1226 | int i; |
1227 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1228 | ||
1229 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1230 | for this thread need to be initialized. */ | |
e3039479 | 1231 | |
638c5f49 | 1232 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1233 | { |
638c5f49 OJ |
1234 | info->bpts_changed[i] = 1; |
1235 | info->wpts_changed[i] = 1; | |
e3039479 | 1236 | } |
638c5f49 OJ |
1237 | |
1238 | lp->arch_private = info; | |
e3039479 UW |
1239 | } |
1240 | ||
466eecee SM |
1241 | /* Function to call when a thread is being deleted. */ |
1242 | ||
135340af PA |
1243 | void |
1244 | arm_linux_nat_target::low_delete_thread (struct arch_lwp_info *arch_lwp) | |
466eecee SM |
1245 | { |
1246 | xfree (arch_lwp); | |
1247 | } | |
1248 | ||
638c5f49 OJ |
1249 | /* Called when resuming a thread. |
1250 | The hardware debug registers are updated when there is any change. */ | |
1251 | ||
135340af PA |
1252 | void |
1253 | arm_linux_nat_target::low_prepare_to_resume (struct lwp_info *lwp) | |
e3039479 | 1254 | { |
638c5f49 OJ |
1255 | int pid, i; |
1256 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1257 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1258 | ||
1259 | pid = ptid_get_lwp (lwp->ptid); | |
1260 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1261 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1262 | ||
1263 | /* NULL means this is the main thread still going through the shell, | |
1264 | or, no watchpoint has been set yet. In that case, there's | |
1265 | nothing to do. */ | |
1266 | if (arm_lwp_info == NULL) | |
1267 | return; | |
e3039479 | 1268 | |
638c5f49 OJ |
1269 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1270 | if (arm_lwp_info->bpts_changed[i]) | |
1271 | { | |
1272 | errno = 0; | |
1273 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1274 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1275 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1276 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1277 | ||
1278 | if (bpts[i].control != 0) | |
1279 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1280 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1281 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1282 | ||
1283 | arm_lwp_info->bpts_changed[i] = 0; | |
1284 | } | |
e3039479 | 1285 | |
638c5f49 OJ |
1286 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1287 | if (arm_lwp_info->wpts_changed[i]) | |
1288 | { | |
1289 | errno = 0; | |
1290 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1291 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1292 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1293 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1294 | ||
1295 | if (wpts[i].control != 0) | |
1296 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1297 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1298 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1299 | ||
1300 | arm_lwp_info->wpts_changed[i] = 0; | |
1301 | } | |
1302 | } | |
1303 | ||
1304 | /* linux_nat_new_fork hook. */ | |
1305 | ||
135340af PA |
1306 | void |
1307 | arm_linux_nat_target::low_new_fork (struct lwp_info *parent, pid_t child_pid) | |
638c5f49 OJ |
1308 | { |
1309 | pid_t parent_pid; | |
1310 | struct arm_linux_debug_reg_state *parent_state; | |
1311 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1312 | |
638c5f49 OJ |
1313 | /* NULL means no watchpoint has ever been set in the parent. In |
1314 | that case, there's nothing to do. */ | |
1315 | if (parent->arch_private == NULL) | |
1316 | return; | |
e3039479 | 1317 | |
638c5f49 OJ |
1318 | /* GDB core assumes the child inherits the watchpoints/hw |
1319 | breakpoints of the parent, and will remove them all from the | |
1320 | forked off process. Copy the debug registers mirrors into the | |
1321 | new process so that all breakpoints and watchpoints can be | |
1322 | removed together. */ | |
e3039479 | 1323 | |
638c5f49 OJ |
1324 | parent_pid = ptid_get_pid (parent->ptid); |
1325 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1326 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1327 | *child_state = *parent_state; | |
e3039479 UW |
1328 | } |
1329 | ||
ed9a39eb JM |
1330 | void |
1331 | _initialize_arm_linux_nat (void) | |
1332 | { | |
10d6c8cd | 1333 | /* Register the target. */ |
f6ac5f3d | 1334 | linux_target = &the_arm_linux_nat_target; |
d9f719f1 | 1335 | add_inf_child_target (&the_arm_linux_nat_target); |
ed9a39eb | 1336 | } |