Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
42a4f53d | 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
4de283e4 TT |
20 | #include "inferior.h" |
21 | #include "gdbcore.h" | |
22 | #include "regcache.h" | |
23 | #include "target.h" | |
24 | #include "linux-nat.h" | |
25 | #include "target-descriptions.h" | |
26 | #include "auxv.h" | |
27 | #include "observable.h" | |
28 | #include "gdbthread.h" | |
29 | ||
30 | #include "arm-tdep.h" | |
31 | #include "arm-linux-tdep.h" | |
32 | #include "aarch32-linux-nat.h" | |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb | 35 | #include <sys/user.h> |
4de283e4 | 36 | #include "nat/gdb_ptrace.h" |
ed9a39eb | 37 | #include <sys/utsname.h> |
4de283e4 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
d55e5aa6 | 40 | #include "nat/linux-ptrace.h" |
4de283e4 | 41 | #include "linux-tdep.h" |
95855ca8 | 42 | |
0963b4bd | 43 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
44 | #include "gregset.h" |
45 | ||
9308fc88 DJ |
46 | /* Defines ps_err_e, struct ps_prochandle. */ |
47 | #include "gdb_proc_service.h" | |
48 | ||
49 | #ifndef PTRACE_GET_THREAD_AREA | |
50 | #define PTRACE_GET_THREAD_AREA 22 | |
51 | #endif | |
52 | ||
05a4558a DJ |
53 | #ifndef PTRACE_GETWMMXREGS |
54 | #define PTRACE_GETWMMXREGS 18 | |
55 | #define PTRACE_SETWMMXREGS 19 | |
56 | #endif | |
57 | ||
3b273a55 RE |
58 | #ifndef PTRACE_GETVFPREGS |
59 | #define PTRACE_GETVFPREGS 27 | |
60 | #define PTRACE_SETVFPREGS 28 | |
61 | #endif | |
62 | ||
e3039479 UW |
63 | #ifndef PTRACE_GETHBPREGS |
64 | #define PTRACE_GETHBPREGS 29 | |
65 | #define PTRACE_SETHBPREGS 30 | |
66 | #endif | |
67 | ||
ed9a39eb JM |
68 | extern int arm_apcs_32; |
69 | ||
f6ac5f3d PA |
70 | class arm_linux_nat_target final : public linux_nat_target |
71 | { | |
72 | public: | |
73 | /* Add our register access methods. */ | |
74 | void fetch_registers (struct regcache *, int) override; | |
75 | void store_registers (struct regcache *, int) override; | |
76 | ||
77 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
78 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
79 | ||
80 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
81 | ||
82 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
83 | ||
84 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
85 | ||
86 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
87 | struct expression *) override; | |
88 | ||
89 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
90 | struct expression *) override; | |
57810aa7 | 91 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 92 | |
57810aa7 | 93 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 94 | |
57810aa7 | 95 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d PA |
96 | |
97 | const struct target_desc *read_description () override; | |
135340af PA |
98 | |
99 | /* Override linux_nat_target low methods. */ | |
100 | ||
101 | /* Handle thread creation and exit. */ | |
102 | void low_new_thread (struct lwp_info *lp) override; | |
103 | void low_delete_thread (struct arch_lwp_info *lp) override; | |
104 | void low_prepare_to_resume (struct lwp_info *lp) override; | |
105 | ||
106 | /* Handle process creation and exit. */ | |
107 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
108 | void low_forget_process (pid_t pid) override; | |
f6ac5f3d PA |
109 | }; |
110 | ||
111 | static arm_linux_nat_target the_arm_linux_nat_target; | |
112 | ||
41c49b06 | 113 | /* Get the whole floating point state of the process and store it |
c6b92abd | 114 | into regcache. */ |
ed9a39eb JM |
115 | |
116 | static void | |
56be3814 | 117 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 118 | { |
41c49b06 | 119 | int ret, regno, tid; |
cb587d83 | 120 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 121 | |
41c49b06 | 122 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 123 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 124 | |
ed9a39eb | 125 | /* Read the floating point state. */ |
0bdb2f78 | 126 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
127 | { |
128 | struct iovec iov; | |
129 | ||
130 | iov.iov_base = &fp; | |
131 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
132 | ||
133 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
134 | } | |
135 | else | |
136 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
137 | ||
ed9a39eb | 138 | if (ret < 0) |
d86feca3 | 139 | perror_with_name (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
140 | |
141 | /* Fetch fpsr. */ | |
73e1c03f | 142 | regcache->raw_supply (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
143 | |
144 | /* Fetch the floating point registers. */ | |
34e8f22d | 145 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 146 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
147 | } |
148 | ||
149 | /* Save the whole floating point state of the process using | |
c6b92abd | 150 | the contents from regcache. */ |
ed9a39eb JM |
151 | |
152 | static void | |
56be3814 | 153 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 154 | { |
41c49b06 | 155 | int ret, regno, tid; |
cb587d83 | 156 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 157 | |
41c49b06 | 158 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 159 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 160 | |
41c49b06 | 161 | /* Read the floating point state. */ |
0bdb2f78 | 162 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
163 | { |
164 | elf_fpregset_t fpregs; | |
165 | struct iovec iov; | |
166 | ||
167 | iov.iov_base = &fpregs; | |
168 | iov.iov_len = sizeof (fpregs); | |
169 | ||
170 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
171 | } | |
172 | else | |
173 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
174 | ||
41c49b06 | 175 | if (ret < 0) |
d86feca3 | 176 | perror_with_name (_("Unable to fetch the floating point registers.")); |
41c49b06 | 177 | |
ed9a39eb | 178 | /* Store fpsr. */ |
0ec9f114 | 179 | if (REG_VALID == regcache->get_register_status (ARM_FPS_REGNUM)) |
34a79281 | 180 | regcache->raw_collect (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
181 | |
182 | /* Store the floating point registers. */ | |
34e8f22d | 183 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
0ec9f114 | 184 | if (REG_VALID == regcache->get_register_status (regno)) |
56be3814 | 185 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 186 | |
0bdb2f78 | 187 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
188 | { |
189 | struct iovec iov; | |
190 | ||
191 | iov.iov_base = &fp; | |
192 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
193 | ||
194 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
195 | } | |
196 | else | |
197 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
198 | ||
ed9a39eb | 199 | if (ret < 0) |
d86feca3 | 200 | perror_with_name (_("Unable to store floating point registers.")); |
ed9a39eb JM |
201 | } |
202 | ||
203 | /* Fetch all general registers of the process and store into | |
c6b92abd | 204 | regcache. */ |
ed9a39eb JM |
205 | |
206 | static void | |
56be3814 | 207 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 208 | { |
cf4088a9 | 209 | int ret, tid; |
c2152441 | 210 | elf_gregset_t regs; |
ed9a39eb | 211 | |
41c49b06 | 212 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 213 | tid = regcache->ptid ().lwp (); |
10766686 | 214 | |
0bdb2f78 | 215 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
216 | { |
217 | struct iovec iov; | |
218 | ||
219 | iov.iov_base = ®s; | |
220 | iov.iov_len = sizeof (regs); | |
221 | ||
222 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
223 | } | |
224 | else | |
225 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
226 | ||
ed9a39eb | 227 | if (ret < 0) |
d86feca3 | 228 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 229 | |
f1b67888 | 230 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
231 | } |
232 | ||
ed9a39eb | 233 | static void |
56be3814 | 234 | store_regs (const struct regcache *regcache) |
ed9a39eb | 235 | { |
cf4088a9 | 236 | int ret, tid; |
c2152441 | 237 | elf_gregset_t regs; |
ed9a39eb | 238 | |
41c49b06 | 239 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 240 | tid = regcache->ptid ().lwp (); |
10766686 | 241 | |
41c49b06 | 242 | /* Fetch the general registers. */ |
0bdb2f78 | 243 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
244 | { |
245 | struct iovec iov; | |
246 | ||
247 | iov.iov_base = ®s; | |
248 | iov.iov_len = sizeof (regs); | |
249 | ||
250 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
251 | } | |
252 | else | |
253 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
254 | ||
ed9a39eb | 255 | if (ret < 0) |
d86feca3 | 256 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 257 | |
f1b67888 | 258 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 259 | |
0bdb2f78 | 260 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
261 | { |
262 | struct iovec iov; | |
263 | ||
264 | iov.iov_base = ®s; | |
265 | iov.iov_len = sizeof (regs); | |
266 | ||
267 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
268 | } | |
269 | else | |
270 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
271 | |
272 | if (ret < 0) | |
d86feca3 | 273 | perror_with_name (_("Unable to store general registers.")); |
ed9a39eb JM |
274 | } |
275 | ||
05a4558a DJ |
276 | /* Fetch all WMMX registers of the process and store into |
277 | regcache. */ | |
278 | ||
05a4558a | 279 | static void |
56be3814 | 280 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
281 | { |
282 | char regbuf[IWMMXT_REGS_SIZE]; | |
283 | int ret, regno, tid; | |
284 | ||
285 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 286 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
287 | |
288 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
289 | if (ret < 0) | |
d86feca3 | 290 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
291 | |
292 | for (regno = 0; regno < 16; regno++) | |
73e1c03f | 293 | regcache->raw_supply (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
294 | |
295 | for (regno = 0; regno < 2; regno++) | |
73e1c03f SM |
296 | regcache->raw_supply (regno + ARM_WCSSF_REGNUM, |
297 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
298 | |
299 | for (regno = 0; regno < 4; regno++) | |
73e1c03f SM |
300 | regcache->raw_supply (regno + ARM_WCGR0_REGNUM, |
301 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
302 | } |
303 | ||
304 | static void | |
56be3814 | 305 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
306 | { |
307 | char regbuf[IWMMXT_REGS_SIZE]; | |
308 | int ret, regno, tid; | |
309 | ||
310 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 311 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
312 | |
313 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
314 | if (ret < 0) | |
d86feca3 | 315 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
316 | |
317 | for (regno = 0; regno < 16; regno++) | |
0ec9f114 | 318 | if (REG_VALID == regcache->get_register_status (regno + ARM_WR0_REGNUM)) |
34a79281 | 319 | regcache->raw_collect (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
320 | |
321 | for (regno = 0; regno < 2; regno++) | |
0ec9f114 | 322 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCSSF_REGNUM)) |
34a79281 SM |
323 | regcache->raw_collect (regno + ARM_WCSSF_REGNUM, |
324 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
325 | |
326 | for (regno = 0; regno < 4; regno++) | |
0ec9f114 | 327 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCGR0_REGNUM)) |
34a79281 SM |
328 | regcache->raw_collect (regno + ARM_WCGR0_REGNUM, |
329 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
330 | |
331 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
332 | ||
333 | if (ret < 0) | |
d86feca3 | 334 | perror_with_name (_("Unable to store WMMX registers.")); |
05a4558a DJ |
335 | } |
336 | ||
3b273a55 RE |
337 | static void |
338 | fetch_vfp_regs (struct regcache *regcache) | |
339 | { | |
350fab54 | 340 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 341 | int ret, tid; |
ac7936df | 342 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 343 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
344 | |
345 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 346 | tid = regcache->ptid ().lwp (); |
3b273a55 | 347 | |
0bdb2f78 | 348 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
349 | { |
350 | struct iovec iov; | |
351 | ||
352 | iov.iov_base = regbuf; | |
350fab54 | 353 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
354 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
355 | } | |
356 | else | |
357 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
358 | ||
3b273a55 | 359 | if (ret < 0) |
d86feca3 | 360 | perror_with_name (_("Unable to fetch VFP registers.")); |
3b273a55 | 361 | |
f1b67888 YQ |
362 | aarch32_vfp_regcache_supply (regcache, regbuf, |
363 | tdep->vfp_register_count); | |
3b273a55 RE |
364 | } |
365 | ||
366 | static void | |
367 | store_vfp_regs (const struct regcache *regcache) | |
368 | { | |
350fab54 | 369 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 370 | int ret, tid; |
ac7936df | 371 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 372 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
373 | |
374 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 375 | tid = regcache->ptid ().lwp (); |
3b273a55 | 376 | |
0bdb2f78 | 377 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
378 | { |
379 | struct iovec iov; | |
380 | ||
381 | iov.iov_base = regbuf; | |
350fab54 | 382 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
383 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
384 | } | |
385 | else | |
386 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
387 | ||
3b273a55 | 388 | if (ret < 0) |
d86feca3 | 389 | perror_with_name (_("Unable to fetch VFP registers (for update).")); |
3b273a55 | 390 | |
f1b67888 YQ |
391 | aarch32_vfp_regcache_collect (regcache, regbuf, |
392 | tdep->vfp_register_count); | |
3b273a55 | 393 | |
0bdb2f78 | 394 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
395 | { |
396 | struct iovec iov; | |
397 | ||
398 | iov.iov_base = regbuf; | |
350fab54 | 399 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
400 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); |
401 | } | |
402 | else | |
403 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
404 | |
405 | if (ret < 0) | |
d86feca3 | 406 | perror_with_name (_("Unable to store VFP registers.")); |
3b273a55 RE |
407 | } |
408 | ||
ed9a39eb JM |
409 | /* Fetch registers from the child process. Fetch all registers if |
410 | regno == -1, otherwise fetch all general registers or all floating | |
411 | point registers depending upon the value of regno. */ | |
412 | ||
f6ac5f3d PA |
413 | void |
414 | arm_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 415 | { |
ac7936df | 416 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
417 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
418 | ||
41c49b06 SB |
419 | if (-1 == regno) |
420 | { | |
56be3814 | 421 | fetch_regs (regcache); |
a56cc1ce | 422 | if (tdep->have_wmmx_registers) |
56be3814 | 423 | fetch_wmmx_regs (regcache); |
330c6ca9 | 424 | if (tdep->vfp_register_count > 0) |
3b273a55 | 425 | fetch_vfp_regs (regcache); |
4bd2e1b2 KC |
426 | if (tdep->have_fpa_registers) |
427 | fetch_fpregs (regcache); | |
41c49b06 | 428 | } |
4bd2e1b2 | 429 | else |
41c49b06 | 430 | { |
05a4558a | 431 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 432 | fetch_regs (regcache); |
05a4558a | 433 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 434 | fetch_fpregs (regcache); |
a56cc1ce | 435 | else if (tdep->have_wmmx_registers |
05a4558a | 436 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 437 | fetch_wmmx_regs (regcache); |
330c6ca9 | 438 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 439 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
440 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
441 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 442 | fetch_vfp_regs (regcache); |
41c49b06 | 443 | } |
ed9a39eb JM |
444 | } |
445 | ||
446 | /* Store registers back into the inferior. Store all registers if | |
447 | regno == -1, otherwise store all general registers or all floating | |
448 | point registers depending upon the value of regno. */ | |
449 | ||
f6ac5f3d PA |
450 | void |
451 | arm_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 452 | { |
ac7936df | 453 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
454 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
455 | ||
41c49b06 SB |
456 | if (-1 == regno) |
457 | { | |
56be3814 | 458 | store_regs (regcache); |
a56cc1ce | 459 | if (tdep->have_wmmx_registers) |
56be3814 | 460 | store_wmmx_regs (regcache); |
330c6ca9 | 461 | if (tdep->vfp_register_count > 0) |
3b273a55 | 462 | store_vfp_regs (regcache); |
4bd2e1b2 KC |
463 | if (tdep->have_fpa_registers) |
464 | store_fpregs (regcache); | |
41c49b06 SB |
465 | } |
466 | else | |
467 | { | |
05a4558a | 468 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 469 | store_regs (regcache); |
05a4558a | 470 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 471 | store_fpregs (regcache); |
a56cc1ce | 472 | else if (tdep->have_wmmx_registers |
05a4558a | 473 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 474 | store_wmmx_regs (regcache); |
330c6ca9 | 475 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 476 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
477 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
478 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 479 | store_vfp_regs (regcache); |
41c49b06 | 480 | } |
ed9a39eb JM |
481 | } |
482 | ||
cb587d83 DJ |
483 | /* Wrapper functions for the standard regset handling, used by |
484 | thread debugging. */ | |
41c49b06 SB |
485 | |
486 | void | |
7f7fe91e UW |
487 | fill_gregset (const struct regcache *regcache, |
488 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 489 | { |
7f7fe91e | 490 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
491 | } |
492 | ||
41c49b06 | 493 | void |
7f7fe91e | 494 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 495 | { |
7f7fe91e | 496 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
497 | } |
498 | ||
41c49b06 | 499 | void |
7f7fe91e UW |
500 | fill_fpregset (const struct regcache *regcache, |
501 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 502 | { |
7f7fe91e | 503 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
504 | } |
505 | ||
506 | /* Fill GDB's register array with the floating-point register values | |
507 | in *fpregsetp. */ | |
508 | ||
509 | void | |
7f7fe91e | 510 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 511 | { |
7f7fe91e | 512 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
513 | } |
514 | ||
9308fc88 DJ |
515 | /* Fetch the thread-local storage pointer for libthread_db. */ |
516 | ||
517 | ps_err_e | |
754653a7 | 518 | ps_get_thread_area (struct ps_prochandle *ph, |
9308fc88 DJ |
519 | lwpid_t lwpid, int idx, void **base) |
520 | { | |
521 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
522 | return PS_ERR; | |
523 | ||
524 | /* IDX is the bias from the thread pointer to the beginning of the | |
525 | thread descriptor. It has to be subtracted due to implementation | |
526 | quirks in libthread_db. */ | |
527 | *base = (void *) ((char *)*base - idx); | |
528 | ||
529 | return PS_OK; | |
530 | } | |
531 | ||
f6ac5f3d PA |
532 | const struct target_desc * |
533 | arm_linux_nat_target::read_description () | |
05a4558a | 534 | { |
0f83012e | 535 | CORE_ADDR arm_hwcap = linux_get_hwcap (this); |
05a4558a | 536 | |
0bdb2f78 | 537 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
538 | { |
539 | elf_gregset_t gpregs; | |
540 | struct iovec iov; | |
e38504b3 | 541 | int tid = inferior_ptid.lwp (); |
7efe48d1 YQ |
542 | |
543 | iov.iov_base = &gpregs; | |
544 | iov.iov_len = sizeof (gpregs); | |
545 | ||
546 | /* Check if PTRACE_GETREGSET works. */ | |
547 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 548 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 549 | else |
0bdb2f78 | 550 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
551 | } |
552 | ||
3b273a55 | 553 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 554 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
555 | |
556 | if (arm_hwcap & HWCAP_VFP) | |
557 | { | |
558 | int pid; | |
559 | char *buf; | |
560 | const struct target_desc * result = NULL; | |
561 | ||
562 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
563 | Neon with VFPv3-D32. */ | |
564 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 565 | result = tdesc_arm_with_neon; |
3b273a55 | 566 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 567 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 568 | else |
330c6ca9 | 569 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
570 | |
571 | /* Now make sure that the kernel supports reading these | |
572 | registers. Support was added in 2.6.30. */ | |
e38504b3 | 573 | pid = inferior_ptid.lwp (); |
3b273a55 | 574 | errno = 0; |
350fab54 | 575 | buf = (char *) alloca (ARM_VFP3_REGS_SIZE); |
3b273a55 RE |
576 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
577 | && errno == EIO) | |
578 | result = NULL; | |
579 | ||
580 | return result; | |
581 | } | |
582 | ||
4360561f | 583 | return this->beneath ()->read_description (); |
05a4558a DJ |
584 | } |
585 | ||
e3039479 UW |
586 | /* Information describing the hardware breakpoint capabilities. */ |
587 | struct arm_linux_hwbp_cap | |
588 | { | |
589 | gdb_byte arch; | |
590 | gdb_byte max_wp_length; | |
591 | gdb_byte wp_count; | |
592 | gdb_byte bp_count; | |
593 | }; | |
594 | ||
638c5f49 OJ |
595 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
596 | assume a maximum number of supported break-/watchpoints. */ | |
597 | #define MAX_BPTS 16 | |
598 | #define MAX_WPTS 16 | |
599 | ||
e3039479 UW |
600 | /* Get hold of the Hardware Breakpoint information for the target we are |
601 | attached to. Returns NULL if the kernel doesn't support Hardware | |
602 | breakpoints at all, or a pointer to the information structure. */ | |
603 | static const struct arm_linux_hwbp_cap * | |
604 | arm_linux_get_hwbp_cap (void) | |
605 | { | |
606 | /* The info structure we return. */ | |
607 | static struct arm_linux_hwbp_cap info; | |
608 | ||
609 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
610 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
611 | means INFO is in an initialized state. */ | |
612 | static int available = -1; | |
613 | ||
614 | if (available == -1) | |
615 | { | |
616 | int tid; | |
617 | unsigned int val; | |
618 | ||
e38504b3 | 619 | tid = inferior_ptid.lwp (); |
e3039479 UW |
620 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
621 | available = 0; | |
622 | else | |
623 | { | |
624 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
625 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
626 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
627 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
628 | |
629 | if (info.wp_count > MAX_WPTS) | |
630 | { | |
631 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
632 | supports %d"), MAX_WPTS, info.wp_count); | |
633 | info.wp_count = MAX_WPTS; | |
634 | } | |
635 | ||
636 | if (info.bp_count > MAX_BPTS) | |
637 | { | |
638 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
639 | supports %d"), MAX_BPTS, info.bp_count); | |
640 | info.bp_count = MAX_BPTS; | |
641 | } | |
e3039479 UW |
642 | available = (info.arch != 0); |
643 | } | |
644 | } | |
645 | ||
646 | return available == 1 ? &info : NULL; | |
647 | } | |
648 | ||
649 | /* How many hardware breakpoints are available? */ | |
650 | static int | |
651 | arm_linux_get_hw_breakpoint_count (void) | |
652 | { | |
653 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
654 | return cap != NULL ? cap->bp_count : 0; | |
655 | } | |
656 | ||
657 | /* How many hardware watchpoints are available? */ | |
658 | static int | |
659 | arm_linux_get_hw_watchpoint_count (void) | |
660 | { | |
661 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
662 | return cap != NULL ? cap->wp_count : 0; | |
663 | } | |
664 | ||
665 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
666 | there is not an appropriate resource available, otherwise returns 1. */ | |
f6ac5f3d PA |
667 | int |
668 | arm_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
669 | int cnt, int ot) | |
e3039479 UW |
670 | { |
671 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
672 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
673 | { | |
dbbf180a YQ |
674 | int count = arm_linux_get_hw_watchpoint_count (); |
675 | ||
676 | if (count == 0) | |
677 | return 0; | |
678 | else if (cnt + ot > count) | |
e3039479 UW |
679 | return -1; |
680 | } | |
681 | else if (type == bp_hardware_breakpoint) | |
682 | { | |
dbbf180a YQ |
683 | int count = arm_linux_get_hw_breakpoint_count (); |
684 | ||
685 | if (count == 0) | |
686 | return 0; | |
687 | else if (cnt > count) | |
e3039479 UW |
688 | return -1; |
689 | } | |
690 | else | |
06d16ec9 | 691 | gdb_assert_not_reached ("unknown breakpoint type"); |
e3039479 UW |
692 | |
693 | return 1; | |
694 | } | |
695 | ||
696 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
697 | typedef enum | |
698 | { | |
699 | arm_hwbp_break = 0, | |
700 | arm_hwbp_load = 1, | |
701 | arm_hwbp_store = 2, | |
702 | arm_hwbp_access = 3 | |
703 | } arm_hwbp_type; | |
704 | ||
705 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
706 | typedef unsigned int arm_hwbp_control_t; | |
707 | ||
708 | /* Structure used to keep track of hardware break-/watch-points. */ | |
709 | struct arm_linux_hw_breakpoint | |
710 | { | |
711 | /* Address to break on, or being watched. */ | |
712 | unsigned int address; | |
713 | /* Control register for break-/watch- point. */ | |
714 | arm_hwbp_control_t control; | |
715 | }; | |
716 | ||
638c5f49 OJ |
717 | /* Structure containing arrays of per process hardware break-/watchpoints |
718 | for caching address and control information. | |
e3039479 UW |
719 | |
720 | The Linux ptrace interface to hardware break-/watch-points presents the | |
721 | values in a vector centred around 0 (which is used fo generic information). | |
722 | Positive indicies refer to breakpoint addresses/control registers, negative | |
723 | indices to watchpoint addresses/control registers. | |
724 | ||
725 | The Linux vector is indexed as follows: | |
726 | -((i << 1) + 2): Control register for watchpoint i. | |
727 | -((i << 1) + 1): Address register for watchpoint i. | |
728 | 0: Information register. | |
729 | ((i << 1) + 1): Address register for breakpoint i. | |
730 | ((i << 1) + 2): Control register for breakpoint i. | |
731 | ||
732 | This structure is used as a per-thread cache of the state stored by the | |
733 | kernel, so that we don't need to keep calling into the kernel to find a | |
734 | free breakpoint. | |
735 | ||
736 | We treat break-/watch-points with their enable bit clear as being deleted. | |
737 | */ | |
638c5f49 | 738 | struct arm_linux_debug_reg_state |
e3039479 | 739 | { |
638c5f49 OJ |
740 | /* Hardware breakpoints for this process. */ |
741 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
742 | /* Hardware watchpoints for this process. */ | |
743 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
744 | }; | |
745 | ||
746 | /* Per-process arch-specific data we want to keep. */ | |
747 | struct arm_linux_process_info | |
e3039479 | 748 | { |
638c5f49 OJ |
749 | /* Linked list. */ |
750 | struct arm_linux_process_info *next; | |
751 | /* The process identifier. */ | |
752 | pid_t pid; | |
753 | /* Hardware break-/watchpoints state information. */ | |
754 | struct arm_linux_debug_reg_state state; | |
e3039479 | 755 | |
638c5f49 OJ |
756 | }; |
757 | ||
758 | /* Per-thread arch-specific data we want to keep. */ | |
759 | struct arch_lwp_info | |
760 | { | |
761 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
762 | char bpts_changed[MAX_BPTS]; | |
763 | char wpts_changed[MAX_WPTS]; | |
764 | }; | |
765 | ||
766 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
767 | ||
768 | /* Find process data for process PID. */ | |
769 | ||
770 | static struct arm_linux_process_info * | |
771 | arm_linux_find_process_pid (pid_t pid) | |
772 | { | |
773 | struct arm_linux_process_info *proc; | |
774 | ||
775 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
776 | if (proc->pid == pid) | |
777 | return proc; | |
778 | ||
779 | return NULL; | |
780 | } | |
781 | ||
782 | /* Add process data for process PID. Returns newly allocated info | |
783 | object. */ | |
784 | ||
785 | static struct arm_linux_process_info * | |
786 | arm_linux_add_process (pid_t pid) | |
787 | { | |
788 | struct arm_linux_process_info *proc; | |
e3039479 | 789 | |
8d749320 | 790 | proc = XCNEW (struct arm_linux_process_info); |
638c5f49 | 791 | proc->pid = pid; |
e3039479 | 792 | |
638c5f49 OJ |
793 | proc->next = arm_linux_process_list; |
794 | arm_linux_process_list = proc; | |
795 | ||
796 | return proc; | |
797 | } | |
798 | ||
799 | /* Get data specific info for process PID, creating it if necessary. | |
800 | Never returns NULL. */ | |
801 | ||
802 | static struct arm_linux_process_info * | |
803 | arm_linux_process_info_get (pid_t pid) | |
804 | { | |
805 | struct arm_linux_process_info *proc; | |
806 | ||
807 | proc = arm_linux_find_process_pid (pid); | |
808 | if (proc == NULL) | |
809 | proc = arm_linux_add_process (pid); | |
810 | ||
811 | return proc; | |
812 | } | |
813 | ||
814 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
815 | data structures that keep track of debug register state. */ | |
816 | ||
135340af PA |
817 | void |
818 | arm_linux_nat_target::low_forget_process (pid_t pid) | |
638c5f49 OJ |
819 | { |
820 | struct arm_linux_process_info *proc, **proc_link; | |
821 | ||
822 | proc = arm_linux_process_list; | |
823 | proc_link = &arm_linux_process_list; | |
824 | ||
825 | while (proc != NULL) | |
826 | { | |
827 | if (proc->pid == pid) | |
e3039479 | 828 | { |
638c5f49 OJ |
829 | *proc_link = proc->next; |
830 | ||
831 | xfree (proc); | |
832 | return; | |
e3039479 UW |
833 | } |
834 | ||
638c5f49 OJ |
835 | proc_link = &proc->next; |
836 | proc = *proc_link; | |
837 | } | |
838 | } | |
839 | ||
840 | /* Get hardware break-/watchpoint state for process PID. */ | |
841 | ||
842 | static struct arm_linux_debug_reg_state * | |
843 | arm_linux_get_debug_reg_state (pid_t pid) | |
844 | { | |
845 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
846 | } |
847 | ||
848 | /* Initialize an ARM hardware break-/watch-point control register value. | |
849 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
850 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
851 | */ | |
852 | static arm_hwbp_control_t | |
853 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
854 | arm_hwbp_type hwbp_type, | |
855 | int enable) | |
856 | { | |
857 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
858 | gdb_assert (hwbp_type != arm_hwbp_break | |
859 | || ((byte_address_select & 0xfU) != 0)); | |
860 | ||
861 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
862 | } | |
863 | ||
864 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
865 | static int | |
866 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
867 | { | |
868 | return control & 0x1; | |
869 | } | |
870 | ||
871 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
872 | static arm_hwbp_control_t | |
873 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
874 | { | |
875 | return control & ~0x1; | |
876 | } | |
877 | ||
878 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
879 | enabled, and will point to the placed address of BP_TGT. */ | |
880 | static void | |
881 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
882 | struct bp_target_info *bp_tgt, | |
883 | struct arm_linux_hw_breakpoint *p) | |
884 | { | |
885 | unsigned mask; | |
0d5ed153 | 886 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
887 | |
888 | /* We have to create a mask for the control register which says which bits | |
889 | of the word pointed to by address to break on. */ | |
890 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
891 | { |
892 | mask = 0x3; | |
893 | address &= ~1; | |
894 | } | |
e3039479 | 895 | else |
fcf303ab UW |
896 | { |
897 | mask = 0xf; | |
898 | address &= ~3; | |
899 | } | |
e3039479 | 900 | |
fcf303ab | 901 | p->address = (unsigned int) address; |
e3039479 UW |
902 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
903 | } | |
904 | ||
8156fe7f | 905 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 906 | given when asked to set a watchpoint. */ |
e3039479 | 907 | static arm_hwbp_type |
f486487f | 908 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 909 | { |
8156fe7f | 910 | if (type == hw_read) |
e3039479 | 911 | return arm_hwbp_load; |
8156fe7f | 912 | else if (type == hw_write) |
e3039479 UW |
913 | return arm_hwbp_store; |
914 | else | |
915 | return arm_hwbp_access; | |
916 | } | |
917 | ||
918 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
919 | to LEN. The type of watchpoint is given in RW. */ | |
920 | static void | |
f486487f SM |
921 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
922 | enum target_hw_bp_type type, | |
e3039479 UW |
923 | struct arm_linux_hw_breakpoint *p) |
924 | { | |
925 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
926 | unsigned mask; | |
927 | ||
928 | gdb_assert (cap != NULL); | |
929 | gdb_assert (cap->max_wp_length != 0); | |
930 | ||
931 | mask = (1 << len) - 1; | |
932 | ||
933 | p->address = (unsigned int) addr; | |
934 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 935 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
936 | } |
937 | ||
938 | /* Are two break-/watch-points equal? */ | |
939 | static int | |
940 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
941 | const struct arm_linux_hw_breakpoint *p2) | |
942 | { | |
943 | return p1->address == p2->address && p1->control == p2->control; | |
944 | } | |
945 | ||
638c5f49 OJ |
946 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
947 | the current process. */ | |
948 | ||
638c5f49 | 949 | static int |
d3a70e03 | 950 | update_registers_callback (struct lwp_info *lwp, int watch, int index) |
638c5f49 | 951 | { |
638c5f49 OJ |
952 | if (lwp->arch_private == NULL) |
953 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
954 | ||
955 | /* The actual update is done later just before resuming the lwp, | |
956 | we just mark that the registers need updating. */ | |
d3a70e03 TT |
957 | if (watch) |
958 | lwp->arch_private->wpts_changed[index] = 1; | |
638c5f49 | 959 | else |
d3a70e03 | 960 | lwp->arch_private->bpts_changed[index] = 1; |
638c5f49 OJ |
961 | |
962 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
963 | we can update its breakpoint registers. */ | |
964 | if (!lwp->stopped) | |
965 | linux_stop_lwp (lwp); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
e3039479 UW |
970 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
971 | =1) BPT for thread TID. */ | |
972 | static void | |
973 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 974 | int watchpoint) |
e3039479 | 975 | { |
638c5f49 OJ |
976 | int pid; |
977 | ptid_t pid_ptid; | |
e3039479 UW |
978 | gdb_byte count, i; |
979 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 980 | |
e99b03dc | 981 | pid = inferior_ptid.pid (); |
f2907e49 | 982 | pid_ptid = ptid_t (pid); |
e3039479 UW |
983 | |
984 | if (watchpoint) | |
985 | { | |
986 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 987 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
988 | } |
989 | else | |
990 | { | |
991 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 992 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
993 | } |
994 | ||
995 | for (i = 0; i < count; ++i) | |
996 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
997 | { | |
638c5f49 | 998 | bpts[i] = *bpt; |
d3a70e03 TT |
999 | iterate_over_lwps (pid_ptid, |
1000 | [=] (struct lwp_info *info) | |
1001 | { | |
3a0e45b2 AH |
1002 | return update_registers_callback (info, watchpoint, |
1003 | i); | |
d3a70e03 | 1004 | }); |
638c5f49 | 1005 | break; |
e3039479 UW |
1006 | } |
1007 | ||
1008 | gdb_assert (i != count); | |
1009 | } | |
1010 | ||
1011 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1012 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1013 | static void | |
1014 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1015 | int watchpoint) |
e3039479 | 1016 | { |
638c5f49 | 1017 | int pid; |
e3039479 | 1018 | gdb_byte count, i; |
638c5f49 OJ |
1019 | ptid_t pid_ptid; |
1020 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 1021 | |
e99b03dc | 1022 | pid = inferior_ptid.pid (); |
f2907e49 | 1023 | pid_ptid = ptid_t (pid); |
e3039479 UW |
1024 | |
1025 | if (watchpoint) | |
1026 | { | |
1027 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1028 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1029 | } |
1030 | else | |
1031 | { | |
1032 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1033 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1034 | } |
1035 | ||
1036 | for (i = 0; i < count; ++i) | |
1037 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1038 | { | |
638c5f49 | 1039 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); |
3a0e45b2 AH |
1040 | iterate_over_lwps (pid_ptid, |
1041 | [=] (struct lwp_info *info) | |
1042 | { | |
1043 | return update_registers_callback (info, watchpoint, | |
1044 | i); | |
1045 | }); | |
638c5f49 | 1046 | break; |
e3039479 UW |
1047 | } |
1048 | ||
1049 | gdb_assert (i != count); | |
1050 | } | |
1051 | ||
1052 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1053 | int |
1054 | arm_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1055 | struct bp_target_info *bp_tgt) | |
e3039479 | 1056 | { |
e3039479 UW |
1057 | struct arm_linux_hw_breakpoint p; |
1058 | ||
1059 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1060 | return -1; | |
1061 | ||
1062 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1063 | |
1064 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1065 | |
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1070 | int |
1071 | arm_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1072 | struct bp_target_info *bp_tgt) | |
e3039479 | 1073 | { |
e3039479 UW |
1074 | struct arm_linux_hw_breakpoint p; |
1075 | ||
1076 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1077 | return -1; | |
1078 | ||
1079 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1080 | |
1081 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1082 | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1087 | ADDR? */ | |
f6ac5f3d PA |
1088 | int |
1089 | arm_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e3039479 UW |
1090 | { |
1091 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1092 | CORE_ADDR max_wp_length, aligned_addr; | |
1093 | ||
1094 | /* Can not set watchpoints for zero or negative lengths. */ | |
1095 | if (len <= 0) | |
1096 | return 0; | |
1097 | ||
1098 | /* Need to be able to use the ptrace interface. */ | |
1099 | if (cap == NULL || cap->wp_count == 0) | |
1100 | return 0; | |
1101 | ||
1102 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1103 | range covered by a watchpoint. */ | |
1104 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1105 | aligned_addr = addr & ~(max_wp_length - 1); | |
1106 | ||
1107 | if (aligned_addr + max_wp_length < addr + len) | |
1108 | return 0; | |
1109 | ||
1110 | /* The current ptrace interface can only handle watchpoints that are a | |
1111 | power of 2. */ | |
1112 | if ((len & (len - 1)) != 0) | |
1113 | return 0; | |
1114 | ||
1115 | /* All tests passed so we must be able to set a watchpoint. */ | |
1116 | return 1; | |
1117 | } | |
1118 | ||
1119 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1120 | int |
1121 | arm_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
1122 | enum target_hw_bp_type rw, | |
1123 | struct expression *cond) | |
e3039479 | 1124 | { |
e3039479 UW |
1125 | struct arm_linux_hw_breakpoint p; |
1126 | ||
1127 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1128 | return -1; | |
1129 | ||
1130 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1131 | |
1132 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1133 | |
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1138 | int |
1139 | arm_linux_nat_target::remove_watchpoint (CORE_ADDR addr, | |
1140 | int len, enum target_hw_bp_type rw, | |
1141 | struct expression *cond) | |
e3039479 | 1142 | { |
e3039479 UW |
1143 | struct arm_linux_hw_breakpoint p; |
1144 | ||
1145 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1146 | return -1; | |
1147 | ||
1148 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1149 | |
1150 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1151 | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | /* What was the data address the target was stopped on accessing. */ | |
57810aa7 | 1156 | bool |
f6ac5f3d | 1157 | arm_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e3039479 | 1158 | { |
f865ee35 JK |
1159 | siginfo_t siginfo; |
1160 | int slot; | |
1161 | ||
1162 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 1163 | return false; |
e3039479 UW |
1164 | |
1165 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1166 | if (siginfo.si_signo != SIGTRAP |
1167 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 1168 | return false; |
e3039479 UW |
1169 | |
1170 | /* We must be able to set hardware watchpoints. */ | |
1171 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1172 | return 0; | |
1173 | ||
f865ee35 JK |
1174 | slot = siginfo.si_errno; |
1175 | ||
e3039479 UW |
1176 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1177 | a watchpoint. */ | |
1178 | if (slot >= 0) | |
57810aa7 | 1179 | return false; |
e3039479 | 1180 | |
f865ee35 | 1181 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 1182 | return true; |
e3039479 UW |
1183 | } |
1184 | ||
1185 | /* Has the target been stopped by hitting a watchpoint? */ | |
57810aa7 | 1186 | bool |
f6ac5f3d | 1187 | arm_linux_nat_target::stopped_by_watchpoint () |
e3039479 UW |
1188 | { |
1189 | CORE_ADDR addr; | |
f6ac5f3d | 1190 | return stopped_data_address (&addr); |
e3039479 UW |
1191 | } |
1192 | ||
57810aa7 | 1193 | bool |
f6ac5f3d PA |
1194 | arm_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
1195 | CORE_ADDR start, | |
1196 | int length) | |
e3039479 UW |
1197 | { |
1198 | return start <= addr && start + length - 1 >= addr; | |
1199 | } | |
1200 | ||
1201 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1202 | in the parent thread to the child thread. */ | |
135340af PA |
1203 | void |
1204 | arm_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e3039479 | 1205 | { |
638c5f49 OJ |
1206 | int i; |
1207 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1208 | ||
1209 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1210 | for this thread need to be initialized. */ | |
e3039479 | 1211 | |
638c5f49 | 1212 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1213 | { |
638c5f49 OJ |
1214 | info->bpts_changed[i] = 1; |
1215 | info->wpts_changed[i] = 1; | |
e3039479 | 1216 | } |
638c5f49 OJ |
1217 | |
1218 | lp->arch_private = info; | |
e3039479 UW |
1219 | } |
1220 | ||
466eecee SM |
1221 | /* Function to call when a thread is being deleted. */ |
1222 | ||
135340af PA |
1223 | void |
1224 | arm_linux_nat_target::low_delete_thread (struct arch_lwp_info *arch_lwp) | |
466eecee SM |
1225 | { |
1226 | xfree (arch_lwp); | |
1227 | } | |
1228 | ||
638c5f49 OJ |
1229 | /* Called when resuming a thread. |
1230 | The hardware debug registers are updated when there is any change. */ | |
1231 | ||
135340af PA |
1232 | void |
1233 | arm_linux_nat_target::low_prepare_to_resume (struct lwp_info *lwp) | |
e3039479 | 1234 | { |
638c5f49 OJ |
1235 | int pid, i; |
1236 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1237 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1238 | ||
e38504b3 | 1239 | pid = lwp->ptid.lwp (); |
e99b03dc TT |
1240 | bpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->bpts; |
1241 | wpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->wpts; | |
638c5f49 OJ |
1242 | |
1243 | /* NULL means this is the main thread still going through the shell, | |
1244 | or, no watchpoint has been set yet. In that case, there's | |
1245 | nothing to do. */ | |
1246 | if (arm_lwp_info == NULL) | |
1247 | return; | |
e3039479 | 1248 | |
638c5f49 OJ |
1249 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1250 | if (arm_lwp_info->bpts_changed[i]) | |
1251 | { | |
1252 | errno = 0; | |
1253 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1254 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1255 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1256 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1257 | ||
1258 | if (bpts[i].control != 0) | |
1259 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1260 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1261 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1262 | ||
1263 | arm_lwp_info->bpts_changed[i] = 0; | |
1264 | } | |
e3039479 | 1265 | |
638c5f49 OJ |
1266 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1267 | if (arm_lwp_info->wpts_changed[i]) | |
1268 | { | |
1269 | errno = 0; | |
1270 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1271 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1272 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1273 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1274 | ||
1275 | if (wpts[i].control != 0) | |
1276 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1277 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1278 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1279 | ||
1280 | arm_lwp_info->wpts_changed[i] = 0; | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | /* linux_nat_new_fork hook. */ | |
1285 | ||
135340af PA |
1286 | void |
1287 | arm_linux_nat_target::low_new_fork (struct lwp_info *parent, pid_t child_pid) | |
638c5f49 OJ |
1288 | { |
1289 | pid_t parent_pid; | |
1290 | struct arm_linux_debug_reg_state *parent_state; | |
1291 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1292 | |
638c5f49 OJ |
1293 | /* NULL means no watchpoint has ever been set in the parent. In |
1294 | that case, there's nothing to do. */ | |
1295 | if (parent->arch_private == NULL) | |
1296 | return; | |
e3039479 | 1297 | |
638c5f49 OJ |
1298 | /* GDB core assumes the child inherits the watchpoints/hw |
1299 | breakpoints of the parent, and will remove them all from the | |
1300 | forked off process. Copy the debug registers mirrors into the | |
1301 | new process so that all breakpoints and watchpoints can be | |
1302 | removed together. */ | |
e3039479 | 1303 | |
e99b03dc | 1304 | parent_pid = parent->ptid.pid (); |
638c5f49 OJ |
1305 | parent_state = arm_linux_get_debug_reg_state (parent_pid); |
1306 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1307 | *child_state = *parent_state; | |
e3039479 UW |
1308 | } |
1309 | ||
ed9a39eb JM |
1310 | void |
1311 | _initialize_arm_linux_nat (void) | |
1312 | { | |
10d6c8cd | 1313 | /* Register the target. */ |
f6ac5f3d | 1314 | linux_target = &the_arm_linux_nat_target; |
d9f719f1 | 1315 | add_inf_child_target (&the_arm_linux_nat_target); |
ed9a39eb | 1316 | } |