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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
42a4f53d | 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
4de283e4 TT |
20 | #include "inferior.h" |
21 | #include "gdbcore.h" | |
22 | #include "regcache.h" | |
23 | #include "target.h" | |
24 | #include "linux-nat.h" | |
25 | #include "target-descriptions.h" | |
26 | #include "auxv.h" | |
27 | #include "observable.h" | |
28 | #include "gdbthread.h" | |
29 | ||
30 | #include "arm-tdep.h" | |
31 | #include "arm-linux-tdep.h" | |
32 | #include "aarch32-linux-nat.h" | |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb | 35 | #include <sys/user.h> |
4de283e4 | 36 | #include "nat/gdb_ptrace.h" |
ed9a39eb | 37 | #include <sys/utsname.h> |
4de283e4 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
d55e5aa6 | 40 | #include "nat/linux-ptrace.h" |
4de283e4 | 41 | #include "linux-tdep.h" |
95855ca8 | 42 | |
0963b4bd | 43 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
44 | #include "gregset.h" |
45 | ||
9308fc88 DJ |
46 | /* Defines ps_err_e, struct ps_prochandle. */ |
47 | #include "gdb_proc_service.h" | |
48 | ||
49 | #ifndef PTRACE_GET_THREAD_AREA | |
50 | #define PTRACE_GET_THREAD_AREA 22 | |
51 | #endif | |
52 | ||
05a4558a DJ |
53 | #ifndef PTRACE_GETWMMXREGS |
54 | #define PTRACE_GETWMMXREGS 18 | |
55 | #define PTRACE_SETWMMXREGS 19 | |
56 | #endif | |
57 | ||
3b273a55 RE |
58 | #ifndef PTRACE_GETVFPREGS |
59 | #define PTRACE_GETVFPREGS 27 | |
60 | #define PTRACE_SETVFPREGS 28 | |
61 | #endif | |
62 | ||
e3039479 UW |
63 | #ifndef PTRACE_GETHBPREGS |
64 | #define PTRACE_GETHBPREGS 29 | |
65 | #define PTRACE_SETHBPREGS 30 | |
66 | #endif | |
67 | ||
ed9a39eb JM |
68 | extern int arm_apcs_32; |
69 | ||
f6ac5f3d PA |
70 | class arm_linux_nat_target final : public linux_nat_target |
71 | { | |
72 | public: | |
73 | /* Add our register access methods. */ | |
74 | void fetch_registers (struct regcache *, int) override; | |
75 | void store_registers (struct regcache *, int) override; | |
76 | ||
77 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
78 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
79 | ||
80 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
81 | ||
82 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
83 | ||
84 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
85 | ||
86 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
87 | struct expression *) override; | |
88 | ||
89 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
90 | struct expression *) override; | |
57810aa7 | 91 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 92 | |
57810aa7 | 93 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 94 | |
57810aa7 | 95 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d PA |
96 | |
97 | const struct target_desc *read_description () override; | |
135340af PA |
98 | |
99 | /* Override linux_nat_target low methods. */ | |
100 | ||
101 | /* Handle thread creation and exit. */ | |
102 | void low_new_thread (struct lwp_info *lp) override; | |
103 | void low_delete_thread (struct arch_lwp_info *lp) override; | |
104 | void low_prepare_to_resume (struct lwp_info *lp) override; | |
105 | ||
106 | /* Handle process creation and exit. */ | |
107 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
108 | void low_forget_process (pid_t pid) override; | |
f6ac5f3d PA |
109 | }; |
110 | ||
111 | static arm_linux_nat_target the_arm_linux_nat_target; | |
112 | ||
41c49b06 | 113 | /* Get the whole floating point state of the process and store it |
c6b92abd | 114 | into regcache. */ |
ed9a39eb JM |
115 | |
116 | static void | |
56be3814 | 117 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 118 | { |
41c49b06 | 119 | int ret, regno, tid; |
cb587d83 | 120 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 121 | |
41c49b06 | 122 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 123 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 124 | |
ed9a39eb | 125 | /* Read the floating point state. */ |
0bdb2f78 | 126 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
127 | { |
128 | struct iovec iov; | |
129 | ||
130 | iov.iov_base = &fp; | |
131 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
132 | ||
133 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
134 | } | |
135 | else | |
136 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
137 | ||
ed9a39eb | 138 | if (ret < 0) |
d86feca3 | 139 | perror_with_name (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
140 | |
141 | /* Fetch fpsr. */ | |
73e1c03f | 142 | regcache->raw_supply (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
143 | |
144 | /* Fetch the floating point registers. */ | |
34e8f22d | 145 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 146 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
147 | } |
148 | ||
149 | /* Save the whole floating point state of the process using | |
c6b92abd | 150 | the contents from regcache. */ |
ed9a39eb JM |
151 | |
152 | static void | |
56be3814 | 153 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 154 | { |
41c49b06 | 155 | int ret, regno, tid; |
cb587d83 | 156 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 157 | |
41c49b06 | 158 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 159 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 160 | |
41c49b06 | 161 | /* Read the floating point state. */ |
0bdb2f78 | 162 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
163 | { |
164 | elf_fpregset_t fpregs; | |
165 | struct iovec iov; | |
166 | ||
167 | iov.iov_base = &fpregs; | |
168 | iov.iov_len = sizeof (fpregs); | |
169 | ||
170 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
171 | } | |
172 | else | |
173 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
174 | ||
41c49b06 | 175 | if (ret < 0) |
d86feca3 | 176 | perror_with_name (_("Unable to fetch the floating point registers.")); |
41c49b06 | 177 | |
ed9a39eb | 178 | /* Store fpsr. */ |
0ec9f114 | 179 | if (REG_VALID == regcache->get_register_status (ARM_FPS_REGNUM)) |
34a79281 | 180 | regcache->raw_collect (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
181 | |
182 | /* Store the floating point registers. */ | |
34e8f22d | 183 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
0ec9f114 | 184 | if (REG_VALID == regcache->get_register_status (regno)) |
56be3814 | 185 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 186 | |
0bdb2f78 | 187 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
188 | { |
189 | struct iovec iov; | |
190 | ||
191 | iov.iov_base = &fp; | |
192 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
193 | ||
194 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
195 | } | |
196 | else | |
197 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
198 | ||
ed9a39eb | 199 | if (ret < 0) |
d86feca3 | 200 | perror_with_name (_("Unable to store floating point registers.")); |
ed9a39eb JM |
201 | } |
202 | ||
203 | /* Fetch all general registers of the process and store into | |
c6b92abd | 204 | regcache. */ |
ed9a39eb JM |
205 | |
206 | static void | |
56be3814 | 207 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 208 | { |
cf4088a9 | 209 | int ret, tid; |
c2152441 | 210 | elf_gregset_t regs; |
ed9a39eb | 211 | |
41c49b06 | 212 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 213 | tid = regcache->ptid ().lwp (); |
10766686 | 214 | |
0bdb2f78 | 215 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
216 | { |
217 | struct iovec iov; | |
218 | ||
219 | iov.iov_base = ®s; | |
220 | iov.iov_len = sizeof (regs); | |
221 | ||
222 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
223 | } | |
224 | else | |
225 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
226 | ||
ed9a39eb | 227 | if (ret < 0) |
d86feca3 | 228 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 229 | |
f1b67888 | 230 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
231 | } |
232 | ||
ed9a39eb | 233 | static void |
56be3814 | 234 | store_regs (const struct regcache *regcache) |
ed9a39eb | 235 | { |
cf4088a9 | 236 | int ret, tid; |
c2152441 | 237 | elf_gregset_t regs; |
ed9a39eb | 238 | |
41c49b06 | 239 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 240 | tid = regcache->ptid ().lwp (); |
10766686 | 241 | |
41c49b06 | 242 | /* Fetch the general registers. */ |
0bdb2f78 | 243 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
244 | { |
245 | struct iovec iov; | |
246 | ||
247 | iov.iov_base = ®s; | |
248 | iov.iov_len = sizeof (regs); | |
249 | ||
250 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
251 | } | |
252 | else | |
253 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
254 | ||
ed9a39eb | 255 | if (ret < 0) |
d86feca3 | 256 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 257 | |
f1b67888 | 258 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 259 | |
0bdb2f78 | 260 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
261 | { |
262 | struct iovec iov; | |
263 | ||
264 | iov.iov_base = ®s; | |
265 | iov.iov_len = sizeof (regs); | |
266 | ||
267 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
268 | } | |
269 | else | |
270 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
271 | |
272 | if (ret < 0) | |
d86feca3 | 273 | perror_with_name (_("Unable to store general registers.")); |
ed9a39eb JM |
274 | } |
275 | ||
05a4558a DJ |
276 | /* Fetch all WMMX registers of the process and store into |
277 | regcache. */ | |
278 | ||
05a4558a | 279 | static void |
56be3814 | 280 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
281 | { |
282 | char regbuf[IWMMXT_REGS_SIZE]; | |
283 | int ret, regno, tid; | |
284 | ||
285 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 286 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
287 | |
288 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
289 | if (ret < 0) | |
d86feca3 | 290 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
291 | |
292 | for (regno = 0; regno < 16; regno++) | |
73e1c03f | 293 | regcache->raw_supply (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
294 | |
295 | for (regno = 0; regno < 2; regno++) | |
73e1c03f SM |
296 | regcache->raw_supply (regno + ARM_WCSSF_REGNUM, |
297 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
298 | |
299 | for (regno = 0; regno < 4; regno++) | |
73e1c03f SM |
300 | regcache->raw_supply (regno + ARM_WCGR0_REGNUM, |
301 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
302 | } |
303 | ||
304 | static void | |
56be3814 | 305 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
306 | { |
307 | char regbuf[IWMMXT_REGS_SIZE]; | |
308 | int ret, regno, tid; | |
309 | ||
310 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 311 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
312 | |
313 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
314 | if (ret < 0) | |
d86feca3 | 315 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
316 | |
317 | for (regno = 0; regno < 16; regno++) | |
0ec9f114 | 318 | if (REG_VALID == regcache->get_register_status (regno + ARM_WR0_REGNUM)) |
34a79281 | 319 | regcache->raw_collect (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
320 | |
321 | for (regno = 0; regno < 2; regno++) | |
0ec9f114 | 322 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCSSF_REGNUM)) |
34a79281 SM |
323 | regcache->raw_collect (regno + ARM_WCSSF_REGNUM, |
324 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
325 | |
326 | for (regno = 0; regno < 4; regno++) | |
0ec9f114 | 327 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCGR0_REGNUM)) |
34a79281 SM |
328 | regcache->raw_collect (regno + ARM_WCGR0_REGNUM, |
329 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
330 | |
331 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
332 | ||
333 | if (ret < 0) | |
d86feca3 | 334 | perror_with_name (_("Unable to store WMMX registers.")); |
05a4558a DJ |
335 | } |
336 | ||
3b273a55 RE |
337 | static void |
338 | fetch_vfp_regs (struct regcache *regcache) | |
339 | { | |
350fab54 | 340 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 341 | int ret, tid; |
ac7936df | 342 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 343 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
344 | |
345 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 346 | tid = regcache->ptid ().lwp (); |
3b273a55 | 347 | |
0bdb2f78 | 348 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
349 | { |
350 | struct iovec iov; | |
351 | ||
352 | iov.iov_base = regbuf; | |
350fab54 | 353 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
354 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
355 | } | |
356 | else | |
357 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
358 | ||
3b273a55 | 359 | if (ret < 0) |
d86feca3 | 360 | perror_with_name (_("Unable to fetch VFP registers.")); |
3b273a55 | 361 | |
f1b67888 YQ |
362 | aarch32_vfp_regcache_supply (regcache, regbuf, |
363 | tdep->vfp_register_count); | |
3b273a55 RE |
364 | } |
365 | ||
366 | static void | |
367 | store_vfp_regs (const struct regcache *regcache) | |
368 | { | |
350fab54 | 369 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 370 | int ret, tid; |
ac7936df | 371 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 372 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
373 | |
374 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 375 | tid = regcache->ptid ().lwp (); |
3b273a55 | 376 | |
0bdb2f78 | 377 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
378 | { |
379 | struct iovec iov; | |
380 | ||
381 | iov.iov_base = regbuf; | |
350fab54 | 382 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
383 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
384 | } | |
385 | else | |
386 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
387 | ||
3b273a55 | 388 | if (ret < 0) |
d86feca3 | 389 | perror_with_name (_("Unable to fetch VFP registers (for update).")); |
3b273a55 | 390 | |
f1b67888 YQ |
391 | aarch32_vfp_regcache_collect (regcache, regbuf, |
392 | tdep->vfp_register_count); | |
3b273a55 | 393 | |
0bdb2f78 | 394 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
395 | { |
396 | struct iovec iov; | |
397 | ||
398 | iov.iov_base = regbuf; | |
350fab54 | 399 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
400 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); |
401 | } | |
402 | else | |
403 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
404 | |
405 | if (ret < 0) | |
d86feca3 | 406 | perror_with_name (_("Unable to store VFP registers.")); |
3b273a55 RE |
407 | } |
408 | ||
ed9a39eb JM |
409 | /* Fetch registers from the child process. Fetch all registers if |
410 | regno == -1, otherwise fetch all general registers or all floating | |
411 | point registers depending upon the value of regno. */ | |
412 | ||
f6ac5f3d PA |
413 | void |
414 | arm_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 415 | { |
ac7936df | 416 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
417 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
418 | ||
41c49b06 SB |
419 | if (-1 == regno) |
420 | { | |
56be3814 | 421 | fetch_regs (regcache); |
a56cc1ce | 422 | if (tdep->have_wmmx_registers) |
56be3814 | 423 | fetch_wmmx_regs (regcache); |
330c6ca9 | 424 | if (tdep->vfp_register_count > 0) |
3b273a55 | 425 | fetch_vfp_regs (regcache); |
4bd2e1b2 KC |
426 | if (tdep->have_fpa_registers) |
427 | fetch_fpregs (regcache); | |
41c49b06 | 428 | } |
4bd2e1b2 | 429 | else |
41c49b06 | 430 | { |
05a4558a | 431 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 432 | fetch_regs (regcache); |
05a4558a | 433 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 434 | fetch_fpregs (regcache); |
a56cc1ce | 435 | else if (tdep->have_wmmx_registers |
05a4558a | 436 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 437 | fetch_wmmx_regs (regcache); |
330c6ca9 | 438 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 439 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
440 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
441 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 442 | fetch_vfp_regs (regcache); |
41c49b06 | 443 | } |
ed9a39eb JM |
444 | } |
445 | ||
446 | /* Store registers back into the inferior. Store all registers if | |
447 | regno == -1, otherwise store all general registers or all floating | |
448 | point registers depending upon the value of regno. */ | |
449 | ||
f6ac5f3d PA |
450 | void |
451 | arm_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 452 | { |
ac7936df | 453 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
454 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
455 | ||
41c49b06 SB |
456 | if (-1 == regno) |
457 | { | |
56be3814 | 458 | store_regs (regcache); |
a56cc1ce | 459 | if (tdep->have_wmmx_registers) |
56be3814 | 460 | store_wmmx_regs (regcache); |
330c6ca9 | 461 | if (tdep->vfp_register_count > 0) |
3b273a55 | 462 | store_vfp_regs (regcache); |
4bd2e1b2 KC |
463 | if (tdep->have_fpa_registers) |
464 | store_fpregs (regcache); | |
41c49b06 SB |
465 | } |
466 | else | |
467 | { | |
05a4558a | 468 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 469 | store_regs (regcache); |
05a4558a | 470 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 471 | store_fpregs (regcache); |
a56cc1ce | 472 | else if (tdep->have_wmmx_registers |
05a4558a | 473 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 474 | store_wmmx_regs (regcache); |
330c6ca9 | 475 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 476 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
477 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
478 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 479 | store_vfp_regs (regcache); |
41c49b06 | 480 | } |
ed9a39eb JM |
481 | } |
482 | ||
cb587d83 DJ |
483 | /* Wrapper functions for the standard regset handling, used by |
484 | thread debugging. */ | |
41c49b06 SB |
485 | |
486 | void | |
7f7fe91e UW |
487 | fill_gregset (const struct regcache *regcache, |
488 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 489 | { |
7f7fe91e | 490 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
491 | } |
492 | ||
41c49b06 | 493 | void |
7f7fe91e | 494 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 495 | { |
7f7fe91e | 496 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
497 | } |
498 | ||
41c49b06 | 499 | void |
7f7fe91e UW |
500 | fill_fpregset (const struct regcache *regcache, |
501 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 502 | { |
7f7fe91e | 503 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
504 | } |
505 | ||
506 | /* Fill GDB's register array with the floating-point register values | |
507 | in *fpregsetp. */ | |
508 | ||
509 | void | |
7f7fe91e | 510 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 511 | { |
7f7fe91e | 512 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
513 | } |
514 | ||
9308fc88 DJ |
515 | /* Fetch the thread-local storage pointer for libthread_db. */ |
516 | ||
517 | ps_err_e | |
754653a7 | 518 | ps_get_thread_area (struct ps_prochandle *ph, |
9308fc88 DJ |
519 | lwpid_t lwpid, int idx, void **base) |
520 | { | |
521 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
522 | return PS_ERR; | |
523 | ||
524 | /* IDX is the bias from the thread pointer to the beginning of the | |
525 | thread descriptor. It has to be subtracted due to implementation | |
526 | quirks in libthread_db. */ | |
527 | *base = (void *) ((char *)*base - idx); | |
528 | ||
529 | return PS_OK; | |
530 | } | |
531 | ||
f6ac5f3d PA |
532 | const struct target_desc * |
533 | arm_linux_nat_target::read_description () | |
05a4558a | 534 | { |
0f83012e | 535 | CORE_ADDR arm_hwcap = linux_get_hwcap (this); |
05a4558a | 536 | |
0bdb2f78 | 537 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
538 | { |
539 | elf_gregset_t gpregs; | |
540 | struct iovec iov; | |
e38504b3 | 541 | int tid = inferior_ptid.lwp (); |
7efe48d1 YQ |
542 | |
543 | iov.iov_base = &gpregs; | |
544 | iov.iov_len = sizeof (gpregs); | |
545 | ||
546 | /* Check if PTRACE_GETREGSET works. */ | |
547 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 548 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 549 | else |
0bdb2f78 | 550 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
551 | } |
552 | ||
3b273a55 | 553 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 554 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
555 | |
556 | if (arm_hwcap & HWCAP_VFP) | |
557 | { | |
166a82be AH |
558 | /* Make sure that the kernel supports reading VFP registers. Support was |
559 | added in 2.6.30. */ | |
560 | int pid = inferior_ptid.lwp (); | |
561 | errno = 0; | |
562 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
563 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
564 | return nullptr; | |
3b273a55 RE |
565 | |
566 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
567 | Neon with VFPv3-D32. */ | |
568 | if (arm_hwcap & HWCAP_NEON) | |
166a82be | 569 | return tdesc_arm_with_neon; |
3b273a55 | 570 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
166a82be | 571 | return tdesc_arm_with_vfpv3; |
3b273a55 | 572 | else |
166a82be | 573 | return tdesc_arm_with_vfpv2; |
3b273a55 RE |
574 | } |
575 | ||
4360561f | 576 | return this->beneath ()->read_description (); |
05a4558a DJ |
577 | } |
578 | ||
e3039479 UW |
579 | /* Information describing the hardware breakpoint capabilities. */ |
580 | struct arm_linux_hwbp_cap | |
581 | { | |
582 | gdb_byte arch; | |
583 | gdb_byte max_wp_length; | |
584 | gdb_byte wp_count; | |
585 | gdb_byte bp_count; | |
586 | }; | |
587 | ||
638c5f49 OJ |
588 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
589 | assume a maximum number of supported break-/watchpoints. */ | |
590 | #define MAX_BPTS 16 | |
591 | #define MAX_WPTS 16 | |
592 | ||
e3039479 UW |
593 | /* Get hold of the Hardware Breakpoint information for the target we are |
594 | attached to. Returns NULL if the kernel doesn't support Hardware | |
595 | breakpoints at all, or a pointer to the information structure. */ | |
596 | static const struct arm_linux_hwbp_cap * | |
597 | arm_linux_get_hwbp_cap (void) | |
598 | { | |
599 | /* The info structure we return. */ | |
600 | static struct arm_linux_hwbp_cap info; | |
601 | ||
602 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
603 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
604 | means INFO is in an initialized state. */ | |
605 | static int available = -1; | |
606 | ||
607 | if (available == -1) | |
608 | { | |
609 | int tid; | |
610 | unsigned int val; | |
611 | ||
e38504b3 | 612 | tid = inferior_ptid.lwp (); |
e3039479 UW |
613 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
614 | available = 0; | |
615 | else | |
616 | { | |
617 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
618 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
619 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
620 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
621 | |
622 | if (info.wp_count > MAX_WPTS) | |
623 | { | |
624 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
625 | supports %d"), MAX_WPTS, info.wp_count); | |
626 | info.wp_count = MAX_WPTS; | |
627 | } | |
628 | ||
629 | if (info.bp_count > MAX_BPTS) | |
630 | { | |
631 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
632 | supports %d"), MAX_BPTS, info.bp_count); | |
633 | info.bp_count = MAX_BPTS; | |
634 | } | |
e3039479 UW |
635 | available = (info.arch != 0); |
636 | } | |
637 | } | |
638 | ||
639 | return available == 1 ? &info : NULL; | |
640 | } | |
641 | ||
642 | /* How many hardware breakpoints are available? */ | |
643 | static int | |
644 | arm_linux_get_hw_breakpoint_count (void) | |
645 | { | |
646 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
647 | return cap != NULL ? cap->bp_count : 0; | |
648 | } | |
649 | ||
650 | /* How many hardware watchpoints are available? */ | |
651 | static int | |
652 | arm_linux_get_hw_watchpoint_count (void) | |
653 | { | |
654 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
655 | return cap != NULL ? cap->wp_count : 0; | |
656 | } | |
657 | ||
658 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
659 | there is not an appropriate resource available, otherwise returns 1. */ | |
f6ac5f3d PA |
660 | int |
661 | arm_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
662 | int cnt, int ot) | |
e3039479 UW |
663 | { |
664 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
665 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
666 | { | |
dbbf180a YQ |
667 | int count = arm_linux_get_hw_watchpoint_count (); |
668 | ||
669 | if (count == 0) | |
670 | return 0; | |
671 | else if (cnt + ot > count) | |
e3039479 UW |
672 | return -1; |
673 | } | |
674 | else if (type == bp_hardware_breakpoint) | |
675 | { | |
dbbf180a YQ |
676 | int count = arm_linux_get_hw_breakpoint_count (); |
677 | ||
678 | if (count == 0) | |
679 | return 0; | |
680 | else if (cnt > count) | |
e3039479 UW |
681 | return -1; |
682 | } | |
683 | else | |
06d16ec9 | 684 | gdb_assert_not_reached ("unknown breakpoint type"); |
e3039479 UW |
685 | |
686 | return 1; | |
687 | } | |
688 | ||
689 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
690 | typedef enum | |
691 | { | |
692 | arm_hwbp_break = 0, | |
693 | arm_hwbp_load = 1, | |
694 | arm_hwbp_store = 2, | |
695 | arm_hwbp_access = 3 | |
696 | } arm_hwbp_type; | |
697 | ||
698 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
699 | typedef unsigned int arm_hwbp_control_t; | |
700 | ||
701 | /* Structure used to keep track of hardware break-/watch-points. */ | |
702 | struct arm_linux_hw_breakpoint | |
703 | { | |
704 | /* Address to break on, or being watched. */ | |
705 | unsigned int address; | |
706 | /* Control register for break-/watch- point. */ | |
707 | arm_hwbp_control_t control; | |
708 | }; | |
709 | ||
638c5f49 OJ |
710 | /* Structure containing arrays of per process hardware break-/watchpoints |
711 | for caching address and control information. | |
e3039479 UW |
712 | |
713 | The Linux ptrace interface to hardware break-/watch-points presents the | |
714 | values in a vector centred around 0 (which is used fo generic information). | |
715 | Positive indicies refer to breakpoint addresses/control registers, negative | |
716 | indices to watchpoint addresses/control registers. | |
717 | ||
718 | The Linux vector is indexed as follows: | |
719 | -((i << 1) + 2): Control register for watchpoint i. | |
720 | -((i << 1) + 1): Address register for watchpoint i. | |
721 | 0: Information register. | |
722 | ((i << 1) + 1): Address register for breakpoint i. | |
723 | ((i << 1) + 2): Control register for breakpoint i. | |
724 | ||
725 | This structure is used as a per-thread cache of the state stored by the | |
726 | kernel, so that we don't need to keep calling into the kernel to find a | |
727 | free breakpoint. | |
728 | ||
729 | We treat break-/watch-points with their enable bit clear as being deleted. | |
730 | */ | |
638c5f49 | 731 | struct arm_linux_debug_reg_state |
e3039479 | 732 | { |
638c5f49 OJ |
733 | /* Hardware breakpoints for this process. */ |
734 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
735 | /* Hardware watchpoints for this process. */ | |
736 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
737 | }; | |
738 | ||
739 | /* Per-process arch-specific data we want to keep. */ | |
740 | struct arm_linux_process_info | |
e3039479 | 741 | { |
638c5f49 OJ |
742 | /* Linked list. */ |
743 | struct arm_linux_process_info *next; | |
744 | /* The process identifier. */ | |
745 | pid_t pid; | |
746 | /* Hardware break-/watchpoints state information. */ | |
747 | struct arm_linux_debug_reg_state state; | |
e3039479 | 748 | |
638c5f49 OJ |
749 | }; |
750 | ||
751 | /* Per-thread arch-specific data we want to keep. */ | |
752 | struct arch_lwp_info | |
753 | { | |
754 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
755 | char bpts_changed[MAX_BPTS]; | |
756 | char wpts_changed[MAX_WPTS]; | |
757 | }; | |
758 | ||
759 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
760 | ||
761 | /* Find process data for process PID. */ | |
762 | ||
763 | static struct arm_linux_process_info * | |
764 | arm_linux_find_process_pid (pid_t pid) | |
765 | { | |
766 | struct arm_linux_process_info *proc; | |
767 | ||
768 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
769 | if (proc->pid == pid) | |
770 | return proc; | |
771 | ||
772 | return NULL; | |
773 | } | |
774 | ||
775 | /* Add process data for process PID. Returns newly allocated info | |
776 | object. */ | |
777 | ||
778 | static struct arm_linux_process_info * | |
779 | arm_linux_add_process (pid_t pid) | |
780 | { | |
781 | struct arm_linux_process_info *proc; | |
e3039479 | 782 | |
8d749320 | 783 | proc = XCNEW (struct arm_linux_process_info); |
638c5f49 | 784 | proc->pid = pid; |
e3039479 | 785 | |
638c5f49 OJ |
786 | proc->next = arm_linux_process_list; |
787 | arm_linux_process_list = proc; | |
788 | ||
789 | return proc; | |
790 | } | |
791 | ||
792 | /* Get data specific info for process PID, creating it if necessary. | |
793 | Never returns NULL. */ | |
794 | ||
795 | static struct arm_linux_process_info * | |
796 | arm_linux_process_info_get (pid_t pid) | |
797 | { | |
798 | struct arm_linux_process_info *proc; | |
799 | ||
800 | proc = arm_linux_find_process_pid (pid); | |
801 | if (proc == NULL) | |
802 | proc = arm_linux_add_process (pid); | |
803 | ||
804 | return proc; | |
805 | } | |
806 | ||
807 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
808 | data structures that keep track of debug register state. */ | |
809 | ||
135340af PA |
810 | void |
811 | arm_linux_nat_target::low_forget_process (pid_t pid) | |
638c5f49 OJ |
812 | { |
813 | struct arm_linux_process_info *proc, **proc_link; | |
814 | ||
815 | proc = arm_linux_process_list; | |
816 | proc_link = &arm_linux_process_list; | |
817 | ||
818 | while (proc != NULL) | |
819 | { | |
820 | if (proc->pid == pid) | |
e3039479 | 821 | { |
638c5f49 OJ |
822 | *proc_link = proc->next; |
823 | ||
824 | xfree (proc); | |
825 | return; | |
e3039479 UW |
826 | } |
827 | ||
638c5f49 OJ |
828 | proc_link = &proc->next; |
829 | proc = *proc_link; | |
830 | } | |
831 | } | |
832 | ||
833 | /* Get hardware break-/watchpoint state for process PID. */ | |
834 | ||
835 | static struct arm_linux_debug_reg_state * | |
836 | arm_linux_get_debug_reg_state (pid_t pid) | |
837 | { | |
838 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
839 | } |
840 | ||
841 | /* Initialize an ARM hardware break-/watch-point control register value. | |
842 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
843 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
844 | */ | |
845 | static arm_hwbp_control_t | |
846 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
847 | arm_hwbp_type hwbp_type, | |
848 | int enable) | |
849 | { | |
850 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
851 | gdb_assert (hwbp_type != arm_hwbp_break | |
852 | || ((byte_address_select & 0xfU) != 0)); | |
853 | ||
854 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
855 | } | |
856 | ||
857 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
858 | static int | |
859 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
860 | { | |
861 | return control & 0x1; | |
862 | } | |
863 | ||
864 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
865 | static arm_hwbp_control_t | |
866 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
867 | { | |
868 | return control & ~0x1; | |
869 | } | |
870 | ||
871 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
872 | enabled, and will point to the placed address of BP_TGT. */ | |
873 | static void | |
874 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
875 | struct bp_target_info *bp_tgt, | |
876 | struct arm_linux_hw_breakpoint *p) | |
877 | { | |
878 | unsigned mask; | |
0d5ed153 | 879 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
880 | |
881 | /* We have to create a mask for the control register which says which bits | |
882 | of the word pointed to by address to break on. */ | |
883 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
884 | { |
885 | mask = 0x3; | |
886 | address &= ~1; | |
887 | } | |
e3039479 | 888 | else |
fcf303ab UW |
889 | { |
890 | mask = 0xf; | |
891 | address &= ~3; | |
892 | } | |
e3039479 | 893 | |
fcf303ab | 894 | p->address = (unsigned int) address; |
e3039479 UW |
895 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
896 | } | |
897 | ||
8156fe7f | 898 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 899 | given when asked to set a watchpoint. */ |
e3039479 | 900 | static arm_hwbp_type |
f486487f | 901 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 902 | { |
8156fe7f | 903 | if (type == hw_read) |
e3039479 | 904 | return arm_hwbp_load; |
8156fe7f | 905 | else if (type == hw_write) |
e3039479 UW |
906 | return arm_hwbp_store; |
907 | else | |
908 | return arm_hwbp_access; | |
909 | } | |
910 | ||
911 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
912 | to LEN. The type of watchpoint is given in RW. */ | |
913 | static void | |
f486487f SM |
914 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
915 | enum target_hw_bp_type type, | |
e3039479 UW |
916 | struct arm_linux_hw_breakpoint *p) |
917 | { | |
918 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
919 | unsigned mask; | |
920 | ||
921 | gdb_assert (cap != NULL); | |
922 | gdb_assert (cap->max_wp_length != 0); | |
923 | ||
924 | mask = (1 << len) - 1; | |
925 | ||
926 | p->address = (unsigned int) addr; | |
927 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 928 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
929 | } |
930 | ||
931 | /* Are two break-/watch-points equal? */ | |
932 | static int | |
933 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
934 | const struct arm_linux_hw_breakpoint *p2) | |
935 | { | |
936 | return p1->address == p2->address && p1->control == p2->control; | |
937 | } | |
938 | ||
638c5f49 OJ |
939 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
940 | the current process. */ | |
941 | ||
638c5f49 | 942 | static int |
d3a70e03 | 943 | update_registers_callback (struct lwp_info *lwp, int watch, int index) |
638c5f49 | 944 | { |
638c5f49 OJ |
945 | if (lwp->arch_private == NULL) |
946 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
947 | ||
948 | /* The actual update is done later just before resuming the lwp, | |
949 | we just mark that the registers need updating. */ | |
d3a70e03 TT |
950 | if (watch) |
951 | lwp->arch_private->wpts_changed[index] = 1; | |
638c5f49 | 952 | else |
d3a70e03 | 953 | lwp->arch_private->bpts_changed[index] = 1; |
638c5f49 OJ |
954 | |
955 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
956 | we can update its breakpoint registers. */ | |
957 | if (!lwp->stopped) | |
958 | linux_stop_lwp (lwp); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
e3039479 UW |
963 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
964 | =1) BPT for thread TID. */ | |
965 | static void | |
966 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 967 | int watchpoint) |
e3039479 | 968 | { |
638c5f49 OJ |
969 | int pid; |
970 | ptid_t pid_ptid; | |
e3039479 UW |
971 | gdb_byte count, i; |
972 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 973 | |
e99b03dc | 974 | pid = inferior_ptid.pid (); |
f2907e49 | 975 | pid_ptid = ptid_t (pid); |
e3039479 UW |
976 | |
977 | if (watchpoint) | |
978 | { | |
979 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 980 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
981 | } |
982 | else | |
983 | { | |
984 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 985 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
986 | } |
987 | ||
988 | for (i = 0; i < count; ++i) | |
989 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
990 | { | |
638c5f49 | 991 | bpts[i] = *bpt; |
d3a70e03 TT |
992 | iterate_over_lwps (pid_ptid, |
993 | [=] (struct lwp_info *info) | |
994 | { | |
3a0e45b2 AH |
995 | return update_registers_callback (info, watchpoint, |
996 | i); | |
d3a70e03 | 997 | }); |
638c5f49 | 998 | break; |
e3039479 UW |
999 | } |
1000 | ||
1001 | gdb_assert (i != count); | |
1002 | } | |
1003 | ||
1004 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1005 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1006 | static void | |
1007 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1008 | int watchpoint) |
e3039479 | 1009 | { |
638c5f49 | 1010 | int pid; |
e3039479 | 1011 | gdb_byte count, i; |
638c5f49 OJ |
1012 | ptid_t pid_ptid; |
1013 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 1014 | |
e99b03dc | 1015 | pid = inferior_ptid.pid (); |
f2907e49 | 1016 | pid_ptid = ptid_t (pid); |
e3039479 UW |
1017 | |
1018 | if (watchpoint) | |
1019 | { | |
1020 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1021 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1022 | } |
1023 | else | |
1024 | { | |
1025 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1026 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1027 | } |
1028 | ||
1029 | for (i = 0; i < count; ++i) | |
1030 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1031 | { | |
638c5f49 | 1032 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); |
3a0e45b2 AH |
1033 | iterate_over_lwps (pid_ptid, |
1034 | [=] (struct lwp_info *info) | |
1035 | { | |
1036 | return update_registers_callback (info, watchpoint, | |
1037 | i); | |
1038 | }); | |
638c5f49 | 1039 | break; |
e3039479 UW |
1040 | } |
1041 | ||
1042 | gdb_assert (i != count); | |
1043 | } | |
1044 | ||
1045 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1046 | int |
1047 | arm_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1048 | struct bp_target_info *bp_tgt) | |
e3039479 | 1049 | { |
e3039479 UW |
1050 | struct arm_linux_hw_breakpoint p; |
1051 | ||
1052 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1053 | return -1; | |
1054 | ||
1055 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1056 | |
1057 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1058 | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1063 | int |
1064 | arm_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1065 | struct bp_target_info *bp_tgt) | |
e3039479 | 1066 | { |
e3039479 UW |
1067 | struct arm_linux_hw_breakpoint p; |
1068 | ||
1069 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1070 | return -1; | |
1071 | ||
1072 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1073 | |
1074 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1075 | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1080 | ADDR? */ | |
f6ac5f3d PA |
1081 | int |
1082 | arm_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e3039479 UW |
1083 | { |
1084 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1085 | CORE_ADDR max_wp_length, aligned_addr; | |
1086 | ||
1087 | /* Can not set watchpoints for zero or negative lengths. */ | |
1088 | if (len <= 0) | |
1089 | return 0; | |
1090 | ||
1091 | /* Need to be able to use the ptrace interface. */ | |
1092 | if (cap == NULL || cap->wp_count == 0) | |
1093 | return 0; | |
1094 | ||
1095 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1096 | range covered by a watchpoint. */ | |
1097 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1098 | aligned_addr = addr & ~(max_wp_length - 1); | |
1099 | ||
1100 | if (aligned_addr + max_wp_length < addr + len) | |
1101 | return 0; | |
1102 | ||
1103 | /* The current ptrace interface can only handle watchpoints that are a | |
1104 | power of 2. */ | |
1105 | if ((len & (len - 1)) != 0) | |
1106 | return 0; | |
1107 | ||
1108 | /* All tests passed so we must be able to set a watchpoint. */ | |
1109 | return 1; | |
1110 | } | |
1111 | ||
1112 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1113 | int |
1114 | arm_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
1115 | enum target_hw_bp_type rw, | |
1116 | struct expression *cond) | |
e3039479 | 1117 | { |
e3039479 UW |
1118 | struct arm_linux_hw_breakpoint p; |
1119 | ||
1120 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1121 | return -1; | |
1122 | ||
1123 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1124 | |
1125 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1126 | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1131 | int |
1132 | arm_linux_nat_target::remove_watchpoint (CORE_ADDR addr, | |
1133 | int len, enum target_hw_bp_type rw, | |
1134 | struct expression *cond) | |
e3039479 | 1135 | { |
e3039479 UW |
1136 | struct arm_linux_hw_breakpoint p; |
1137 | ||
1138 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1139 | return -1; | |
1140 | ||
1141 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1142 | |
1143 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1144 | |
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | /* What was the data address the target was stopped on accessing. */ | |
57810aa7 | 1149 | bool |
f6ac5f3d | 1150 | arm_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e3039479 | 1151 | { |
f865ee35 JK |
1152 | siginfo_t siginfo; |
1153 | int slot; | |
1154 | ||
1155 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 1156 | return false; |
e3039479 UW |
1157 | |
1158 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1159 | if (siginfo.si_signo != SIGTRAP |
1160 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 1161 | return false; |
e3039479 UW |
1162 | |
1163 | /* We must be able to set hardware watchpoints. */ | |
1164 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1165 | return 0; | |
1166 | ||
f865ee35 JK |
1167 | slot = siginfo.si_errno; |
1168 | ||
e3039479 UW |
1169 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1170 | a watchpoint. */ | |
1171 | if (slot >= 0) | |
57810aa7 | 1172 | return false; |
e3039479 | 1173 | |
f865ee35 | 1174 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 1175 | return true; |
e3039479 UW |
1176 | } |
1177 | ||
1178 | /* Has the target been stopped by hitting a watchpoint? */ | |
57810aa7 | 1179 | bool |
f6ac5f3d | 1180 | arm_linux_nat_target::stopped_by_watchpoint () |
e3039479 UW |
1181 | { |
1182 | CORE_ADDR addr; | |
f6ac5f3d | 1183 | return stopped_data_address (&addr); |
e3039479 UW |
1184 | } |
1185 | ||
57810aa7 | 1186 | bool |
f6ac5f3d PA |
1187 | arm_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
1188 | CORE_ADDR start, | |
1189 | int length) | |
e3039479 UW |
1190 | { |
1191 | return start <= addr && start + length - 1 >= addr; | |
1192 | } | |
1193 | ||
1194 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1195 | in the parent thread to the child thread. */ | |
135340af PA |
1196 | void |
1197 | arm_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e3039479 | 1198 | { |
638c5f49 OJ |
1199 | int i; |
1200 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1201 | ||
1202 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1203 | for this thread need to be initialized. */ | |
e3039479 | 1204 | |
638c5f49 | 1205 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1206 | { |
638c5f49 OJ |
1207 | info->bpts_changed[i] = 1; |
1208 | info->wpts_changed[i] = 1; | |
e3039479 | 1209 | } |
638c5f49 OJ |
1210 | |
1211 | lp->arch_private = info; | |
e3039479 UW |
1212 | } |
1213 | ||
466eecee SM |
1214 | /* Function to call when a thread is being deleted. */ |
1215 | ||
135340af PA |
1216 | void |
1217 | arm_linux_nat_target::low_delete_thread (struct arch_lwp_info *arch_lwp) | |
466eecee SM |
1218 | { |
1219 | xfree (arch_lwp); | |
1220 | } | |
1221 | ||
638c5f49 OJ |
1222 | /* Called when resuming a thread. |
1223 | The hardware debug registers are updated when there is any change. */ | |
1224 | ||
135340af PA |
1225 | void |
1226 | arm_linux_nat_target::low_prepare_to_resume (struct lwp_info *lwp) | |
e3039479 | 1227 | { |
638c5f49 OJ |
1228 | int pid, i; |
1229 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1230 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1231 | ||
e38504b3 | 1232 | pid = lwp->ptid.lwp (); |
e99b03dc TT |
1233 | bpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->bpts; |
1234 | wpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->wpts; | |
638c5f49 OJ |
1235 | |
1236 | /* NULL means this is the main thread still going through the shell, | |
1237 | or, no watchpoint has been set yet. In that case, there's | |
1238 | nothing to do. */ | |
1239 | if (arm_lwp_info == NULL) | |
1240 | return; | |
e3039479 | 1241 | |
638c5f49 OJ |
1242 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1243 | if (arm_lwp_info->bpts_changed[i]) | |
1244 | { | |
1245 | errno = 0; | |
1246 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1247 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1248 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1249 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1250 | ||
1251 | if (bpts[i].control != 0) | |
1252 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1253 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1254 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1255 | ||
1256 | arm_lwp_info->bpts_changed[i] = 0; | |
1257 | } | |
e3039479 | 1258 | |
638c5f49 OJ |
1259 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1260 | if (arm_lwp_info->wpts_changed[i]) | |
1261 | { | |
1262 | errno = 0; | |
1263 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1264 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1265 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1266 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1267 | ||
1268 | if (wpts[i].control != 0) | |
1269 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1270 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1271 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1272 | ||
1273 | arm_lwp_info->wpts_changed[i] = 0; | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | /* linux_nat_new_fork hook. */ | |
1278 | ||
135340af PA |
1279 | void |
1280 | arm_linux_nat_target::low_new_fork (struct lwp_info *parent, pid_t child_pid) | |
638c5f49 OJ |
1281 | { |
1282 | pid_t parent_pid; | |
1283 | struct arm_linux_debug_reg_state *parent_state; | |
1284 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1285 | |
638c5f49 OJ |
1286 | /* NULL means no watchpoint has ever been set in the parent. In |
1287 | that case, there's nothing to do. */ | |
1288 | if (parent->arch_private == NULL) | |
1289 | return; | |
e3039479 | 1290 | |
638c5f49 OJ |
1291 | /* GDB core assumes the child inherits the watchpoints/hw |
1292 | breakpoints of the parent, and will remove them all from the | |
1293 | forked off process. Copy the debug registers mirrors into the | |
1294 | new process so that all breakpoints and watchpoints can be | |
1295 | removed together. */ | |
e3039479 | 1296 | |
e99b03dc | 1297 | parent_pid = parent->ptid.pid (); |
638c5f49 OJ |
1298 | parent_state = arm_linux_get_debug_reg_state (parent_pid); |
1299 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1300 | *child_state = *parent_state; | |
e3039479 UW |
1301 | } |
1302 | ||
ed9a39eb JM |
1303 | void |
1304 | _initialize_arm_linux_nat (void) | |
1305 | { | |
10d6c8cd | 1306 | /* Register the target. */ |
f6ac5f3d | 1307 | linux_target = &the_arm_linux_nat_target; |
d9f719f1 | 1308 | add_inf_child_target (&the_arm_linux_nat_target); |
ed9a39eb | 1309 | } |