[deliverable/binutils-gdb.git] / gdb / arm-pinsn.c

/* Print Acorn Risc Machine instructions for GDB, the GNU debugger.
   Copyright 1986, 1989, 1991, 1992 Free Software Foundation, Inc.

This file is part of GDB.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */

#include "defs.h"
#include <ctype.h>
#include <assert.h>

#include "symtab.h"
#include "opcode/arm.h"

static char *shift_names[] = {
    "lsl", "lsr", "asr", "ror",
};

static char *cond_names[] = {
	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
	"hi", "ls", "ge", "lt", "gt", "le", "", "nv"
};

static char float_precision[] = "sdep";
static char float_rounding[] = " pmz";
static float float_immed[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 0.5, 10.0 };

static void print_ldr_str_offset();
static void print_ldc_stc_offset();
static long immediate_value();
\f
/* Print the ARM instruction at address MEMADDR in debugged memory,
   on STREAM.  Returns length of the instruction, in bytes.  */

int
print_insn (memaddr, stream)
     CORE_ADDR memaddr;
     FILE *stream;
{
    unsigned long ins;
    register struct opcode *op;
    register char *p;
    register int i, c;
    int s, e, val;

    ins = read_memory_integer(memaddr, 4);
    for (i = 0, op = opcodes; i < N_OPCODES; i++, op++)
	if ((ins & op->mask) == op->value) break;
    assert(i != N_OPCODES);
    
    for (p = op->assembler; *p;) {
	c = *p++;
	if (c == '%') {
	    s = e = 0;
	    while (isdigit(*p))
		s = s*10 + (*p++ - '0');
	    if (*p == '-') {
		p++;
		while (isdigit(*p))
		    e = e*10 + (*p++ - '0');
	    } else
		e = s;
	    assert(s >= 0 && s <= 31 && e >= 0 && e <= 31);
	    val = (ins >> s) & ((1 << (e + 1 - s)) - 1);
	    switch (*p++) {
	    case '%' :
		putc('%', stream);
		break;
	    case 'd' :
		fprintf(stream, "%d", val);
		break;
	    case 'x' :
		fprintf(stream, "%x", val);
		break;
	    case 'r' :
		assert(val >= 0 && val <= 15);
		fprintf(stream, "%s", reg_names[val]);
		break;
	    case 'c' :
		fprintf(stream, "%s", cond_names[ins >> 28]);
		break;
	    case '\'' :
		assert(*p);
		c = *p++;
		if (val)
		    putc(c, stream);
		break;
	    case '`' :
		assert(*p);
		c = *p++;
		if (!val)
		    putc(c, stream);
		break;
	    case '?' :
		assert(*p);
		c = *p++;
		assert(*p);
		if (val)
		    p++;
		else
		    c = *p++;
		putc(c, stream);
		break;
	    case 'p' :
		if (((ins >> 12) & 0xf) == 0xf)
		    putc('p', stream);
		break;
	    case 'o' :
		if (ins & (1<<25)) {
		    int immed = immediate_value(ins & 0xfff);
		    fprintf (stream, "#%d (0x%x)", immed, immed);
		} else {
		    int operand2 = ins & 0xfff;
		    /* in operand2 :
		       bits 0-3 are the base register
		       bits 5-6 are the shift (0=lsl, 1=lsr, 2=asr, 3=ror)
		       if bit 4 is zero then bits 7-11 are an immediate shift count
		       else bit 7 must be zero and bits 8-11 are the register
		       to be used as a shift count.
		       Note: no shift at all is encoded as "reg lsl #0" */
		    fprintf (stream, "%s", reg_names[operand2 & 0xf]);
		    if (operand2 & 0xff0) {
			/* ror #0 is really rrx (rotate right extend) */
			if ((operand2 & 0xff0) == 0x060)
			    fprintf (stream, ", rrx");
			else {
			    fprintf (stream, ", %s ",
				     shift_names[(operand2 >> 5) & 3]);
			    if (operand2 & (1<<4)) /* register shift */
				fprintf (stream, "%s",
					 reg_names[operand2 >> 8]);
			    else	/* immediate shift */
				fprintf (stream, "#%d",
					 operand2 >> 7);
			}
		    }
		}
		break;
	    case 'a' :
		fprintf (stream, "[%s", reg_names[(ins >> 16) & 0xf]);
		if (ins & (1<<24)) {
		    fprintf (stream, ", ");
		    print_ldr_str_offset (ins, stream);
		    putc (']', stream);
		    if (ins & (1<<21)) putc('!', stream);
		    /* If it is a pc relative load, then it is probably
		       a constant so print it */
		    if (((ins >> 16) & 0xf) == 15 &&
			(ins & (1<<25)) == 0 &&
			(ins & (1<<20))) {
			int addr = memaddr + 8 +
			    (ins & 0xfff) * ((ins & (1<<23)) ? 1 : -1);
			fprintf (stream, " (contents=");
			print_address (read_memory_integer(addr, 4), stream);
			fprintf (stream, ")");
		    }
		} else {
		    fprintf (stream, "]," );
		    print_ldr_str_offset (ins, stream);
		}
		break;
	    case 'b' :
		print_address (memaddr + 8 + (((int)ins << 8) >> 6), stream);
		break;
	    case 'A' :
		fprintf (stream, "[%s", reg_names[(ins >> 16) & 0xf]);
		if (ins & (1<<24)) {
		    fprintf (stream, ", ");
		    print_ldc_stc_offset (ins, stream);
		    putc(']', stream);
		    if (ins & (1<<21))
			putc('!', stream);
		} else {
		    fprintf (stream, "], ");
		    print_ldc_stc_offset (ins, stream);
		}
		break;
	    case 'm' :
		{
		    int regnum, first = 1;
		    putc('{', stream);
		    for (regnum = 0; regnum < 16; regnum++)
			if (ins & (1<<regnum)) {
			    if (!first)
				putc (',', stream);
			    first = 0;
			    fprintf (stream, "%s", reg_names[regnum]);
			}
		    putc('}', stream);
		}
		break;
	    case 'P' :
		val = ((ins >> 18) & 2) | ((ins >> 7) & 1);
		putc(float_precision[val], stream);
		break;
	    case 'Q' :
		val = ((ins >> 21) & 2) | ((ins >> 15) & 1);
		putc(float_precision[val], stream);
		break;
	    case 'R' :
		val = ((ins >> 5) & 3);
		if (val) putc(float_rounding[val], stream);
		break;
	    case 'f' :
		assert(val >= 0 && val <= 15);
		if (val > 7)
		    fprintf (stream, "#%3.1f", float_immed[val - 8]);
		else
		    fprintf (stream, "f%d", val);
		break;
	    default:
		abort();
	    }
	} else
	    putc(c, stream);
    }
    return 4;
}

static long
immediate_value(operand)
int operand;
{
    int val = operand & 0xff;
    int shift = 2*(operand >> 8);
    /* immediate value is (val ror shift) */
    return (val >> shift) | (val << (32 - shift));
}

static void
print_ldr_str_offset(ins, stream)
unsigned long ins;
FILE *stream;
{
    if ((ins & (1<<25)) == 0)
	fprintf (stream, "#%d",
		 (ins & 0xfff) * ((ins & (1<<23)) ? 1 : -1));
    else {
	fprintf (stream, "%s%s", reg_names[ins & 0xf],
		 (ins & (1<<23)) ? "" : "-");
	if (ins & 0xff0)
	    fprintf (stream, ", %s #%d",
		     shift_names[(ins >> 5) & 3],
		     (ins >> 7) & 0x1f);
    }
}

static void
print_ldc_stc_offset(ins, stream)
unsigned long ins;
FILE *stream;
{
    fprintf (stream, "#%d",
	     4 * (ins & 0xff) * ((ins & (1<<23)) ? 1 : -1));
}
Commit	Line	Data
7d9884b9	1	/* Print Acorn Risc Machine instructions for GDB, the GNU debugger.
609f87d4	2	Copyright 1986, 1989, 1991, 1992 Free Software Foundation, Inc.
dd3b648e RP	3
	4	This file is part of GDB.
	5
99a7de40	6	This program is free software; you can redistribute it and/or modify
dd3b648e	7	it under the terms of the GNU General Public License as published by
99a7de40 JG	8	the Free Software Foundation; either version 2 of the License, or
99a7de40 JG	9	(at your option) any later version.
dd3b648e	10
99a7de40	11	This program is distributed in the hope that it will be useful,
dd3b648e RP	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
99a7de40 JG	17	along with this program; if not, write to the Free Software
99a7de40 JG	18	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
dd3b648e	19
d747e0af	20	#include "defs.h"
dd3b648e RP	21	#include <ctype.h>
	22	#include <assert.h>
	23
dd3b648e	24	#include "symtab.h"
aab77d5f	25	#include "opcode/arm.h"
dd3b648e	26
dd3b648e RP	27	static char *shift_names[] = {
	28	"lsl", "lsr", "asr", "ror",
	29	};
	30
	31	static char *cond_names[] = {
	32	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
	33	"hi", "ls", "ge", "lt", "gt", "le", "", "nv"
	34	};
	35
	36	static char float_precision[] = "sdep";
	37	static char float_rounding[] = " pmz";
	38	static float float_immed[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 0.5, 10.0 };
	39
	40	static void print_ldr_str_offset();
	41	static void print_ldc_stc_offset();
	42	static long immediate_value();
	43	\f
	44	/* Print the ARM instruction at address MEMADDR in debugged memory,
	45	on STREAM. Returns length of the instruction, in bytes. */
	46
	47	int
	48	print_insn (memaddr, stream)
	49	CORE_ADDR memaddr;
	50	FILE *stream;
	51	{
	52	unsigned long ins;
	53	register struct opcode *op;
	54	register char *p;
	55	register int i, c;
	56	int s, e, val;
	57
	58	ins = read_memory_integer(memaddr, 4);
	59	for (i = 0, op = opcodes; i < N_OPCODES; i++, op++)
	60	if ((ins & op->mask) == op->value) break;
	61	assert(i != N_OPCODES);
	62
	63	for (p = op->assembler; *p;) {
	64	c = *p++;
	65	if (c == '%') {
	66	s = e = 0;
	67	while (isdigit(*p))
	68	s = s10 + (p++ - '0');
	69	if (*p == '-') {
	70	p++;
	71	while (isdigit(*p))
	72	e = e10 + (p++ - '0');
	73	} else
	74	e = s;
	75	assert(s >= 0 && s <= 31 && e >= 0 && e <= 31);
	76	val = (ins >> s) & ((1 << (e + 1 - s)) - 1);
	77	switch (*p++) {
	78	case '%' :
	79	putc('%', stream);
	80	break;
	81	case 'd' :
	82	fprintf(stream, "%d", val);
	83	break;
	84	case 'x' :
	85	fprintf(stream, "%x", val);
	86	break;
	87	case 'r' :
	88	assert(val >= 0 && val <= 15);
	89	fprintf(stream, "%s", reg_names[val]);
	90	break;
91	case 'c' :
92	fprintf(stream, "%s", cond_names[ins >> 28]);
93	break;
94	case '\'' :
95	assert(*p);
96	c = *p++;
97	if (val)
98	putc(c, stream);
99	break;
100	case '`' :
101	assert(*p);
102	c = *p++;
103	if (!val)
104	putc(c, stream);
105	break;
106	case '?' :
107	assert(*p);
108	c = *p++;
109	assert(*p);
110	if (val)
111	p++;
112	else
113	c = *p++;
114	putc(c, stream);
115	break;
116	case 'p' :
117	if (((ins >> 12) & 0xf) == 0xf)
118	putc('p', stream);
119	break;
120	case 'o' :
121	if (ins & (1<<25)) {
122	int immed = immediate_value(ins & 0xfff);
123	fprintf (stream, "#%d (0x%x)", immed, immed);
124	} else {
125	int operand2 = ins & 0xfff;
126	/* in operand2 :
127	bits 0-3 are the base register
128	bits 5-6 are the shift (0=lsl, 1=lsr, 2=asr, 3=ror)
129	if bit 4 is zero then bits 7-11 are an immediate shift count
130	else bit 7 must be zero and bits 8-11 are the register
131	to be used as a shift count.
132	Note: no shift at all is encoded as "reg lsl #0" */
133	fprintf (stream, "%s", reg_names[operand2 & 0xf]);
134	if (operand2 & 0xff0) {
135	/* ror #0 is really rrx (rotate right extend) */
136	if ((operand2 & 0xff0) == 0x060)
137	fprintf (stream, ", rrx");
138	else {
139	fprintf (stream, ", %s ",
140	shift_names[(operand2 >> 5) & 3]);
141	if (operand2 & (1<<4)) /* register shift */
142	fprintf (stream, "%s",
143	reg_names[operand2 >> 8]);
144	else /* immediate shift */
145	fprintf (stream, "#%d",
146	operand2 >> 7);
147	}
148	}
149	}
150	break;
151	case 'a' :
152	fprintf (stream, "[%s", reg_names[(ins >> 16) & 0xf]);
153	if (ins & (1<<24)) {
154	fprintf (stream, ", ");
155	print_ldr_str_offset (ins, stream);
156	putc (']', stream);
157	if (ins & (1<<21)) putc('!', stream);
158	/* If it is a pc relative load, then it is probably
159	a constant so print it */
160	if (((ins >> 16) & 0xf) == 15 &&
161	(ins & (1<<25)) == 0 &&
162	(ins & (1<<20))) {
163	int addr = memaddr + 8 +
164	(ins & 0xfff) * ((ins & (1<<23)) ? 1 : -1);
165	fprintf (stream, " (contents=");
166	print_address (read_memory_integer(addr, 4), stream);
167	fprintf (stream, ")");
168	}
169	} else {
170	fprintf (stream, "]," );
171	print_ldr_str_offset (ins, stream);
172	}
173	break;
174	case 'b' :
175	print_address (memaddr + 8 + (((int)ins << 8) >> 6), stream);
176	break;
177	case 'A' :
178	fprintf (stream, "[%s", reg_names[(ins >> 16) & 0xf]);
179	if (ins & (1<<24)) {
180	fprintf (stream, ", ");
181	print_ldc_stc_offset (ins, stream);
182	putc(']', stream);
183	if (ins & (1<<21))
184	putc('!', stream);
185	} else {
186	fprintf (stream, "], ");
187	print_ldc_stc_offset (ins, stream);
188	}
189	break;
190	case 'm' :
191	{
192	int regnum, first = 1;
193	putc('{', stream);
194	for (regnum = 0; regnum < 16; regnum++)
195	if (ins & (1<<regnum)) {
196	if (!first)
197	putc (',', stream);
198	first = 0;
199	fprintf (stream, "%s", reg_names[regnum]);
200	}
201	putc('}', stream);
202	}
203	break;
204	case 'P' :
205	val = ((ins >> 18) & 2) \| ((ins >> 7) & 1);
206	putc(float_precision[val], stream);
207	break;
208	case 'Q' :
209	val = ((ins >> 21) & 2) \| ((ins >> 15) & 1);
210	putc(float_precision[val], stream);
211	break;
212	case 'R' :
213	val = ((ins >> 5) & 3);
214	if (val) putc(float_rounding[val], stream);
215	break;
216	case 'f' :
217	assert(val >= 0 && val <= 15);
218	if (val > 7)
219	fprintf (stream, "#%3.1f", float_immed[val - 8]);
220	else
221	fprintf (stream, "f%d", val);
222	break;
223	default:
224	abort();
225	}
226	} else
227	putc(c, stream);
228	}
229	return 4;
230	}
231
232	static long
233	immediate_value(operand)
234	int operand;
235	{
236	int val = operand & 0xff;
237	int shift = 2*(operand >> 8);
238	/* immediate value is (val ror shift) */
239	return (val >> shift) \| (val << (32 - shift));
240	}
241
242	static void
243	print_ldr_str_offset(ins, stream)
244	unsigned long ins;
245	FILE *stream;
246	{
247	if ((ins & (1<<25)) == 0)
248	fprintf (stream, "#%d",
249	(ins & 0xfff) * ((ins & (1<<23)) ? 1 : -1));
250	else {
251	fprintf (stream, "%s%s", reg_names[ins & 0xf],
252	(ins & (1<<23)) ? "" : "-");
253	if (ins & 0xff0)
254	fprintf (stream, ", %s #%d",
255	shift_names[(ins >> 5) & 3],
256	(ins >> 7) & 0x1f);
257	}
258	}
259
260	static void
261	print_ldc_stc_offset(ins, stream)
262	unsigned long ins;
263	FILE *stream;
264	{
265	fprintf (stream, "#%d",
266	4 * (ins & 0xff) * ((ins & (1<<23)) ? 1 : -1));
267	}