Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
c3b4394c | 3 | 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
e8b09175 | 31 | #include "dis-asm.h" /* For register flavors. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
34e8f22d RE |
37 | |
38 | #include "arm-tdep.h" | |
26216b98 | 39 | #include "gdb/sim-arm.h" |
34e8f22d | 40 | |
082fc60d RE |
41 | #include "elf-bfd.h" |
42 | #include "coff/internal.h" | |
97e03143 | 43 | #include "elf/arm.h" |
c906108c | 44 | |
26216b98 AC |
45 | #include "gdb_assert.h" |
46 | ||
6529d2dd AC |
47 | static int arm_debug; |
48 | ||
2a451106 KB |
49 | /* Each OS has a different mechanism for accessing the various |
50 | registers stored in the sigcontext structure. | |
51 | ||
52 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
53 | function pointer) which may be used to determine the addresses | |
54 | of the various saved registers in the sigcontext structure. | |
55 | ||
56 | For the ARM target, there are three parameters to this function. | |
57 | The first is the pc value of the frame under consideration, the | |
58 | second the stack pointer of this frame, and the last is the | |
59 | register number to fetch. | |
60 | ||
61 | If the tm.h file does not define this macro, then it's assumed that | |
62 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
63 | be 0. | |
64 | ||
65 | When it comes time to multi-arching this code, see the identically | |
66 | named machinery in ia64-tdep.c for an example of how it could be | |
67 | done. It should not be necessary to modify the code below where | |
68 | this macro is used. */ | |
69 | ||
3bb04bdd AC |
70 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
71 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
72 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
73 | #endif | |
74 | #else | |
75 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
76 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
77 | #endif |
78 | ||
082fc60d RE |
79 | /* Macros for setting and testing a bit in a minimal symbol that marks |
80 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
81 | is used for this purpose. This field is already being used to store | |
82 | the symbol size, so the assumption is that the symbol size cannot | |
83 | exceed 2^31. | |
84 | ||
85 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
86 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
87 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
88 | i.e. the "info" field with the "special" bit | |
89 | masked out. */ | |
90 | ||
91 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
92 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
93 | | 0x80000000) | |
94 | ||
95 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
96 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
97 | ||
98 | #define MSYMBOL_SIZE(msym) \ | |
99 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 100 | |
94c30b78 | 101 | /* Number of different reg name sets (options). */ |
bc90b915 FN |
102 | static int num_flavor_options; |
103 | ||
104 | /* We have more registers than the disassembler as gdb can print the value | |
105 | of special registers as well. | |
106 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 107 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 108 | |
94c30b78 | 109 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 110 | static char * arm_register_name_strings[] = |
da59e081 JM |
111 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
112 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
113 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
114 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
115 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
116 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 117 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 118 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 119 | |
bc90b915 | 120 | /* Valid register name flavors. */ |
53904c9e | 121 | static const char **valid_flavors; |
ed9a39eb | 122 | |
94c30b78 | 123 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 124 | static const char *disassembly_flavor; |
94c30b78 | 125 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 126 | static int current_option; |
96baa820 | 127 | |
ed9a39eb JM |
128 | /* This is used to keep the bfd arch_info in sync with the disassembly |
129 | flavor. */ | |
130 | static void set_disassembly_flavor_sfunc(char *, int, | |
131 | struct cmd_list_element *); | |
132 | static void set_disassembly_flavor (void); | |
133 | ||
134 | static void convert_from_extended (void *ptr, void *dbl); | |
135 | ||
136 | /* Define other aspects of the stack frame. We keep the offsets of | |
137 | all saved registers, 'cause we need 'em a lot! We also keep the | |
138 | current size of the stack frame, and the offset of the frame | |
139 | pointer from the stack pointer (for frameless functions, and when | |
94c30b78 | 140 | we're still in the prologue of a function with a frame). */ |
ed9a39eb JM |
141 | |
142 | struct frame_extra_info | |
c3b4394c RE |
143 | { |
144 | int framesize; | |
145 | int frameoffset; | |
146 | int framereg; | |
147 | }; | |
ed9a39eb | 148 | |
bc90b915 FN |
149 | /* Addresses for calling Thumb functions have the bit 0 set. |
150 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
151 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
152 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
153 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
154 | ||
39bbf761 | 155 | static int |
ed9a39eb | 156 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 157 | { |
c906108c SS |
158 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
159 | } | |
160 | ||
94c30b78 | 161 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
162 | |
163 | int arm_apcs_32 = 1; | |
164 | ||
ed9a39eb JM |
165 | /* Flag set by arm_fix_call_dummy that tells whether the target |
166 | function is a Thumb function. This flag is checked by | |
167 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
168 | its use in valops.c) to pass the function address as an additional | |
169 | parameter. */ | |
c906108c SS |
170 | |
171 | static int target_is_thumb; | |
172 | ||
ed9a39eb JM |
173 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
174 | function is a Thumb function. This flag is checked by | |
175 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
176 | |
177 | static int caller_is_thumb; | |
178 | ||
ed9a39eb JM |
179 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
180 | function. */ | |
c906108c | 181 | |
34e8f22d | 182 | int |
2a451106 | 183 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 184 | { |
c5aa993b | 185 | struct minimal_symbol *sym; |
c906108c | 186 | |
ed9a39eb | 187 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
188 | if (IS_THUMB_ADDR (memaddr)) |
189 | return 1; | |
190 | ||
ed9a39eb | 191 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
192 | sym = lookup_minimal_symbol_by_pc (memaddr); |
193 | if (sym) | |
194 | { | |
c5aa993b | 195 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
196 | } |
197 | else | |
ed9a39eb JM |
198 | { |
199 | return 0; | |
200 | } | |
c906108c SS |
201 | } |
202 | ||
ed9a39eb JM |
203 | /* Determine if the program counter specified in MEMADDR is in a call |
204 | dummy being called from a Thumb function. */ | |
c906108c | 205 | |
34e8f22d | 206 | int |
2a451106 | 207 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 208 | { |
c5aa993b | 209 | CORE_ADDR sp = read_sp (); |
c906108c | 210 | |
dfcd3bfb JM |
211 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
212 | is the best we can do. We are trying to determine if the pc is on | |
213 | the stack, which (hopefully) will only happen in a call dummy. | |
214 | We hope the current stack pointer is not so far alway from the dummy | |
215 | frame location (true if we have not pushed large data structures or | |
216 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 217 | code regions as part of the stack (true for most practical purposes). */ |
ae45cd16 | 218 | if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
219 | return caller_is_thumb; |
220 | else | |
221 | return 0; | |
222 | } | |
223 | ||
181c1381 | 224 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 225 | static CORE_ADDR |
ed9a39eb | 226 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 227 | { |
a3a2ee65 JT |
228 | if (arm_apcs_32) |
229 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 230 | else |
a3a2ee65 | 231 | return (val & 0x03fffffc); |
c906108c SS |
232 | } |
233 | ||
181c1381 RE |
234 | /* When reading symbols, we need to zap the low bit of the address, |
235 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 236 | static CORE_ADDR |
181c1381 RE |
237 | arm_smash_text_address (CORE_ADDR val) |
238 | { | |
239 | return val & ~1; | |
240 | } | |
241 | ||
34e8f22d RE |
242 | /* Immediately after a function call, return the saved pc. Can't |
243 | always go through the frames for this because on some machines the | |
244 | new frame is not set up until the new function executes some | |
245 | instructions. */ | |
246 | ||
247 | static CORE_ADDR | |
ed9a39eb | 248 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 249 | { |
34e8f22d | 250 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
251 | } |
252 | ||
0defa245 RE |
253 | /* Determine whether the function invocation represented by FI has a |
254 | frame on the stack associated with it. If it does return zero, | |
255 | otherwise return 1. */ | |
256 | ||
148754e5 | 257 | static int |
ed9a39eb | 258 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 259 | { |
392a587b | 260 | CORE_ADDR func_start, after_prologue; |
96baa820 | 261 | int frameless; |
ed9a39eb | 262 | |
0defa245 RE |
263 | /* Sometimes we have functions that do a little setup (like saving the |
264 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
265 | The symbol table will report this as a prologue. However, it is | |
266 | important not to try to parse these partial frames as frames, or we | |
267 | will get really confused. | |
268 | ||
269 | So I will demand 3 instructions between the start & end of the | |
270 | prologue before I call it a real prologue, i.e. at least | |
271 | mov ip, sp, | |
272 | stmdb sp!, {} | |
273 | sub sp, ip, #4. */ | |
274 | ||
392a587b | 275 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 276 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 277 | |
96baa820 | 278 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 279 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 280 | be func_start + 8. */ |
ed9a39eb | 281 | |
96baa820 | 282 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
283 | return frameless; |
284 | } | |
285 | ||
0defa245 | 286 | /* The address of the arguments in the frame. */ |
148754e5 | 287 | static CORE_ADDR |
0defa245 RE |
288 | arm_frame_args_address (struct frame_info *fi) |
289 | { | |
290 | return fi->frame; | |
291 | } | |
292 | ||
293 | /* The address of the local variables in the frame. */ | |
148754e5 | 294 | static CORE_ADDR |
0defa245 RE |
295 | arm_frame_locals_address (struct frame_info *fi) |
296 | { | |
297 | return fi->frame; | |
298 | } | |
299 | ||
300 | /* The number of arguments being passed in the frame. */ | |
148754e5 | 301 | static int |
0defa245 RE |
302 | arm_frame_num_args (struct frame_info *fi) |
303 | { | |
304 | /* We have no way of knowing. */ | |
305 | return -1; | |
306 | } | |
307 | ||
c906108c | 308 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
309 | push {r7, lr} |
310 | add sp, sp, #-28 | |
311 | add r7, sp, #12 | |
c906108c | 312 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
313 | mov r7, sp |
314 | ||
315 | or like this: | |
316 | push {r7, lr} | |
317 | mov r7, sp | |
318 | sub sp, #12 | |
319 | ||
320 | or, on tpcs, like this: | |
321 | sub sp,#16 | |
322 | push {r7, lr} | |
323 | (many instructions) | |
324 | mov r7, sp | |
325 | sub sp, #12 | |
326 | ||
327 | There is always one instruction of three classes: | |
328 | 1 - push | |
329 | 2 - setting of r7 | |
330 | 3 - adjusting of sp | |
331 | ||
332 | When we have found at least one of each class we are done with the prolog. | |
333 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 334 | */ |
c906108c SS |
335 | |
336 | static CORE_ADDR | |
c7885828 | 337 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
338 | { |
339 | CORE_ADDR current_pc; | |
da3c6d4a MS |
340 | /* findmask: |
341 | bit 0 - push { rlist } | |
342 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
343 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
344 | */ | |
345 | int findmask = 0; | |
346 | ||
94c30b78 MS |
347 | for (current_pc = pc; |
348 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 349 | current_pc += 2) |
c906108c SS |
350 | { |
351 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
352 | ||
94c30b78 | 353 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 354 | { |
94c30b78 | 355 | findmask |= 1; /* push found */ |
da59e081 | 356 | } |
da3c6d4a MS |
357 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
358 | sub sp, #simm */ | |
da59e081 | 359 | { |
94c30b78 | 360 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
361 | continue; |
362 | else | |
94c30b78 | 363 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
364 | } |
365 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
366 | { | |
94c30b78 | 367 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
368 | } |
369 | else if (insn == 0x466f) /* mov r7, sp */ | |
370 | { | |
94c30b78 | 371 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 372 | } |
3d74b771 FF |
373 | else if (findmask == (4+2+1)) |
374 | { | |
da3c6d4a MS |
375 | /* We have found one of each type of prologue instruction */ |
376 | break; | |
3d74b771 | 377 | } |
da59e081 | 378 | else |
94c30b78 | 379 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 380 | instruction from outside the prolog scheduled here for |
94c30b78 | 381 | optimization. */ |
da3c6d4a | 382 | continue; |
c906108c SS |
383 | } |
384 | ||
385 | return current_pc; | |
386 | } | |
387 | ||
da3c6d4a MS |
388 | /* Advance the PC across any function entry prologue instructions to |
389 | reach some "real" code. | |
34e8f22d RE |
390 | |
391 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 392 | prologue: |
c906108c | 393 | |
c5aa993b JM |
394 | mov ip, sp |
395 | [stmfd sp!, {a1,a2,a3,a4}] | |
396 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
397 | [stfe f7, [sp, #-12]!] |
398 | [stfe f6, [sp, #-12]!] | |
399 | [stfe f5, [sp, #-12]!] | |
400 | [stfe f4, [sp, #-12]!] | |
401 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 402 | |
34e8f22d | 403 | static CORE_ADDR |
ed9a39eb | 404 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
405 | { |
406 | unsigned long inst; | |
407 | CORE_ADDR skip_pc; | |
b8d5e71d | 408 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 409 | char *func_name; |
c906108c SS |
410 | struct symtab_and_line sal; |
411 | ||
848cfffb | 412 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
ae45cd16 | 413 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
848cfffb AC |
414 | return pc; |
415 | ||
96baa820 | 416 | /* See what the symbol table says. */ |
ed9a39eb | 417 | |
50f6fb4b | 418 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 419 | { |
50f6fb4b CV |
420 | struct symbol *sym; |
421 | ||
422 | /* Found a function. */ | |
423 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
424 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
425 | { | |
94c30b78 | 426 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
427 | sal = find_pc_line (func_addr, 0); |
428 | if ((sal.line != 0) && (sal.end < func_end)) | |
429 | return sal.end; | |
430 | } | |
c906108c SS |
431 | } |
432 | ||
433 | /* Check if this is Thumb code. */ | |
434 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 435 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
436 | |
437 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 438 | by disassembling the instructions. */ |
c906108c | 439 | |
b8d5e71d MS |
440 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
441 | if (func_end == 0 || func_end > pc + 64) | |
442 | func_end = pc + 64; | |
c906108c | 443 | |
b8d5e71d | 444 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 445 | { |
f43845b3 | 446 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 447 | |
b8d5e71d MS |
448 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
449 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
450 | continue; | |
c906108c | 451 | |
b8d5e71d MS |
452 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
453 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
454 | continue; | |
c906108c | 455 | |
b8d5e71d MS |
456 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
457 | continue; | |
c906108c | 458 | |
b8d5e71d MS |
459 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
460 | continue; | |
11d3b27d | 461 | |
b8d5e71d MS |
462 | /* Any insns after this point may float into the code, if it makes |
463 | for better instruction scheduling, so we skip them only if we | |
464 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 465 | |
b8d5e71d MS |
466 | /* We may have either one sfmfd instruction here, or several stfe |
467 | insns, depending on the version of floating point code we | |
468 | support. */ | |
469 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
470 | continue; | |
471 | ||
472 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
473 | continue; | |
474 | ||
475 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
476 | continue; | |
477 | ||
478 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
479 | continue; | |
480 | ||
481 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
482 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
483 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
484 | continue; | |
485 | ||
486 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
487 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
488 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
489 | continue; | |
490 | ||
491 | /* Un-recognized instruction; stop scanning. */ | |
492 | break; | |
f43845b3 | 493 | } |
c906108c | 494 | |
b8d5e71d | 495 | return skip_pc; /* End of prologue */ |
c906108c | 496 | } |
94c30b78 | 497 | |
c5aa993b | 498 | /* *INDENT-OFF* */ |
c906108c SS |
499 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
500 | This function decodes a Thumb function prologue to determine: | |
501 | 1) the size of the stack frame | |
502 | 2) which registers are saved on it | |
503 | 3) the offsets of saved regs | |
504 | 4) the offset from the stack pointer to the frame pointer | |
505 | This information is stored in the "extra" fields of the frame_info. | |
506 | ||
da59e081 JM |
507 | A typical Thumb function prologue would create this stack frame |
508 | (offsets relative to FP) | |
c906108c SS |
509 | old SP -> 24 stack parameters |
510 | 20 LR | |
511 | 16 R7 | |
512 | R7 -> 0 local variables (16 bytes) | |
513 | SP -> -12 additional stack space (12 bytes) | |
514 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
515 | 12 bytes. The frame register is R7. |
516 | ||
da3c6d4a MS |
517 | The comments for thumb_skip_prolog() describe the algorithm we use |
518 | to detect the end of the prolog. */ | |
c5aa993b JM |
519 | /* *INDENT-ON* */ |
520 | ||
c906108c | 521 | static void |
ed9a39eb | 522 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
523 | { |
524 | CORE_ADDR prologue_start; | |
525 | CORE_ADDR prologue_end; | |
526 | CORE_ADDR current_pc; | |
94c30b78 | 527 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
528 | int saved_reg[16]; |
529 | /* findmask: | |
530 | bit 0 - push { rlist } | |
531 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
532 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
533 | */ | |
534 | int findmask = 0; | |
c5aa993b | 535 | int i; |
c906108c | 536 | |
848cfffb | 537 | /* Don't try to scan dummy frames. */ |
07555a72 | 538 | if (fi != NULL |
ae45cd16 | 539 | && DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
848cfffb AC |
540 | return; |
541 | ||
c5aa993b | 542 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
543 | { |
544 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
545 | ||
94c30b78 | 546 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
547 | prologue_end = fi->pc; |
548 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
94c30b78 | 549 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
550 | } |
551 | else | |
da3c6d4a MS |
552 | /* We're in the boondocks: allow for |
553 | 16 pushes, an add, and "mv fp,sp". */ | |
554 | prologue_end = prologue_start + 40; | |
c906108c SS |
555 | |
556 | prologue_end = min (prologue_end, fi->pc); | |
557 | ||
558 | /* Initialize the saved register map. When register H is copied to | |
559 | register L, we will put H in saved_reg[L]. */ | |
560 | for (i = 0; i < 16; i++) | |
561 | saved_reg[i] = i; | |
562 | ||
563 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
564 | frame pointer, adjust the stack pointer, and save registers. |
565 | Do this until all basic prolog instructions are found. */ | |
c906108c | 566 | |
c3b4394c | 567 | fi->extra_info->framesize = 0; |
da59e081 JM |
568 | for (current_pc = prologue_start; |
569 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
570 | current_pc += 2) | |
c906108c SS |
571 | { |
572 | unsigned short insn; | |
573 | int regno; | |
574 | int offset; | |
575 | ||
576 | insn = read_memory_unsigned_integer (current_pc, 2); | |
577 | ||
c5aa993b | 578 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 579 | { |
da59e081 | 580 | int mask; |
94c30b78 | 581 | findmask |= 1; /* push found */ |
c906108c SS |
582 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
583 | whether to save LR (R14). */ | |
da59e081 | 584 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 585 | |
b8d5e71d | 586 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 587 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 588 | if (mask & (1 << regno)) |
c5aa993b | 589 | { |
c3b4394c RE |
590 | fi->extra_info->framesize += 4; |
591 | fi->saved_regs[saved_reg[regno]] = | |
592 | -(fi->extra_info->framesize); | |
da3c6d4a MS |
593 | /* Reset saved register map. */ |
594 | saved_reg[regno] = regno; | |
c906108c SS |
595 | } |
596 | } | |
da3c6d4a MS |
597 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
598 | sub sp, #simm */ | |
c906108c | 599 | { |
b8d5e71d | 600 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
601 | continue; |
602 | else | |
94c30b78 | 603 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 604 | |
94c30b78 MS |
605 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
606 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 607 | { |
c3b4394c | 608 | fi->extra_info->frameoffset += offset; |
da59e081 JM |
609 | offset = -offset; |
610 | } | |
c3b4394c | 611 | fi->extra_info->framesize -= offset; |
c906108c SS |
612 | } |
613 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
614 | { | |
94c30b78 | 615 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
616 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
617 | /* get scaled offset */ | |
618 | fi->extra_info->frameoffset = (insn & 0xff) << 2; | |
c906108c | 619 | } |
da59e081 | 620 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 621 | { |
94c30b78 | 622 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
623 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
624 | fi->extra_info->frameoffset = 0; | |
34e8f22d | 625 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
626 | } |
627 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
628 | { | |
da3c6d4a | 629 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 630 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 631 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
632 | } |
633 | else | |
da3c6d4a MS |
634 | /* Something in the prolog that we don't care about or some |
635 | instruction from outside the prolog scheduled here for | |
636 | optimization. */ | |
637 | continue; | |
c906108c SS |
638 | } |
639 | } | |
640 | ||
ed9a39eb JM |
641 | /* Check if prologue for this frame's PC has already been scanned. If |
642 | it has, copy the relevant information about that prologue and | |
c906108c SS |
643 | return non-zero. Otherwise do not copy anything and return zero. |
644 | ||
645 | The information saved in the cache includes: | |
c5aa993b JM |
646 | * the frame register number; |
647 | * the size of the stack frame; | |
648 | * the offsets of saved regs (relative to the old SP); and | |
649 | * the offset from the stack pointer to the frame pointer | |
c906108c | 650 | |
ed9a39eb JM |
651 | The cache contains only one entry, since this is adequate for the |
652 | typical sequence of prologue scan requests we get. When performing | |
653 | a backtrace, GDB will usually ask to scan the same function twice | |
654 | in a row (once to get the frame chain, and once to fill in the | |
655 | extra frame information). */ | |
c906108c SS |
656 | |
657 | static struct frame_info prologue_cache; | |
658 | ||
659 | static int | |
ed9a39eb | 660 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
661 | { |
662 | int i; | |
663 | ||
664 | if (fi->pc == prologue_cache.pc) | |
665 | { | |
c3b4394c RE |
666 | fi->extra_info->framereg = prologue_cache.extra_info->framereg; |
667 | fi->extra_info->framesize = prologue_cache.extra_info->framesize; | |
668 | fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset; | |
669 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) | |
670 | fi->saved_regs[i] = prologue_cache.saved_regs[i]; | |
c906108c SS |
671 | return 1; |
672 | } | |
673 | else | |
674 | return 0; | |
675 | } | |
676 | ||
677 | ||
ed9a39eb | 678 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
679 | |
680 | static void | |
ed9a39eb | 681 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
682 | { |
683 | int i; | |
684 | ||
c5aa993b | 685 | prologue_cache.pc = fi->pc; |
c3b4394c RE |
686 | prologue_cache.extra_info->framereg = fi->extra_info->framereg; |
687 | prologue_cache.extra_info->framesize = fi->extra_info->framesize; | |
688 | prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset; | |
c5aa993b | 689 | |
c3b4394c RE |
690 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
691 | prologue_cache.saved_regs[i] = fi->saved_regs[i]; | |
c906108c SS |
692 | } |
693 | ||
694 | ||
ed9a39eb | 695 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
696 | 1) the size of the stack frame |
697 | 2) which registers are saved on it | |
698 | 3) the offsets of saved regs | |
699 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
700 | This information is stored in the "extra" fields of the frame_info. |
701 | ||
96baa820 JM |
702 | There are two basic forms for the ARM prologue. The fixed argument |
703 | function call will look like: | |
ed9a39eb JM |
704 | |
705 | mov ip, sp | |
706 | stmfd sp!, {fp, ip, lr, pc} | |
707 | sub fp, ip, #4 | |
708 | [sub sp, sp, #4] | |
96baa820 | 709 | |
c906108c | 710 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
711 | IP -> 4 (caller's stack) |
712 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
713 | -4 LR (return address in caller) | |
714 | -8 IP (copy of caller's SP) | |
715 | -12 FP (caller's FP) | |
716 | SP -> -28 Local variables | |
717 | ||
c906108c | 718 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
719 | 28 bytes. The stmfd call can also save any of the vN registers it |
720 | plans to use, which increases the frame size accordingly. | |
721 | ||
722 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
723 | because the ARM Store instructions always store PC + 8 when you read | |
724 | the PC register. | |
ed9a39eb | 725 | |
96baa820 JM |
726 | A variable argument function call will look like: |
727 | ||
ed9a39eb JM |
728 | mov ip, sp |
729 | stmfd sp!, {a1, a2, a3, a4} | |
730 | stmfd sp!, {fp, ip, lr, pc} | |
731 | sub fp, ip, #20 | |
732 | ||
96baa820 | 733 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
734 | IP -> 20 (caller's stack) |
735 | 16 A4 | |
736 | 12 A3 | |
737 | 8 A2 | |
738 | 4 A1 | |
739 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
740 | -4 LR (return address in caller) | |
741 | -8 IP (copy of caller's SP) | |
742 | -12 FP (caller's FP) | |
743 | SP -> -28 Local variables | |
96baa820 JM |
744 | |
745 | The frame size would thus be 48 bytes, and the frame offset would be | |
746 | 28 bytes. | |
747 | ||
748 | There is another potential complication, which is that the optimizer | |
749 | will try to separate the store of fp in the "stmfd" instruction from | |
750 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
751 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
752 | ||
753 | Also, note, the original version of the ARM toolchain claimed that there | |
754 | should be an | |
755 | ||
756 | instruction at the end of the prologue. I have never seen GCC produce | |
757 | this, and the ARM docs don't mention it. We still test for it below in | |
758 | case it happens... | |
ed9a39eb JM |
759 | |
760 | */ | |
c906108c SS |
761 | |
762 | static void | |
ed9a39eb | 763 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
764 | { |
765 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 766 | LONGEST return_value; |
c906108c SS |
767 | CORE_ADDR prologue_start, prologue_end, current_pc; |
768 | ||
94c30b78 | 769 | /* Check if this function is already in the cache of frame information. */ |
c906108c SS |
770 | if (check_prologue_cache (fi)) |
771 | return; | |
772 | ||
773 | /* Assume there is no frame until proven otherwise. */ | |
34e8f22d | 774 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
775 | fi->extra_info->framesize = 0; |
776 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
777 | |
778 | /* Check for Thumb prologue. */ | |
779 | if (arm_pc_is_thumb (fi->pc)) | |
780 | { | |
781 | thumb_scan_prologue (fi); | |
782 | save_prologue_cache (fi); | |
783 | return; | |
784 | } | |
785 | ||
786 | /* Find the function prologue. If we can't find the function in | |
787 | the symbol table, peek in the stack frame to find the PC. */ | |
788 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
789 | { | |
2a451106 KB |
790 | /* One way to find the end of the prologue (which works well |
791 | for unoptimized code) is to do the following: | |
792 | ||
793 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
794 | ||
795 | if (sal.line == 0) | |
796 | prologue_end = fi->pc; | |
797 | else if (sal.end < prologue_end) | |
798 | prologue_end = sal.end; | |
799 | ||
800 | This mechanism is very accurate so long as the optimizer | |
801 | doesn't move any instructions from the function body into the | |
802 | prologue. If this happens, sal.end will be the last | |
803 | instruction in the first hunk of prologue code just before | |
804 | the first instruction that the scheduler has moved from | |
805 | the body to the prologue. | |
806 | ||
807 | In order to make sure that we scan all of the prologue | |
808 | instructions, we use a slightly less accurate mechanism which | |
809 | may scan more than necessary. To help compensate for this | |
810 | lack of accuracy, the prologue scanning loop below contains | |
811 | several clauses which'll cause the loop to terminate early if | |
812 | an implausible prologue instruction is encountered. | |
813 | ||
814 | The expression | |
815 | ||
816 | prologue_start + 64 | |
817 | ||
818 | is a suitable endpoint since it accounts for the largest | |
819 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 820 | the scheduler. */ |
2a451106 KB |
821 | |
822 | if (prologue_end > prologue_start + 64) | |
823 | { | |
94c30b78 | 824 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 825 | } |
c906108c SS |
826 | } |
827 | else | |
828 | { | |
94c30b78 MS |
829 | /* Get address of the stmfd in the prologue of the callee; |
830 | the saved PC is the address of the stmfd + 8. */ | |
16a0f3e7 EZ |
831 | if (!safe_read_memory_integer (fi->frame, 4, &return_value)) |
832 | return; | |
833 | else | |
834 | { | |
835 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 836 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 837 | } |
c906108c SS |
838 | } |
839 | ||
840 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 841 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 842 | |
96baa820 JM |
843 | Be careful, however, and if it doesn't look like a prologue, |
844 | don't try to scan it. If, for instance, a frameless function | |
845 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 846 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
847 | and other operations that rely on a knowledge of the stack |
848 | traceback. | |
849 | ||
850 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 851 | if we don't see this as the first insn, we will stop. |
c906108c | 852 | |
f43845b3 MS |
853 | [Note: This doesn't seem to be true any longer, so it's now an |
854 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 855 | |
f43845b3 MS |
856 | [Note further: The "mov ip,sp" only seems to be missing in |
857 | frameless functions at optimization level "-O2" or above, | |
858 | in which case it is often (but not always) replaced by | |
b8d5e71d | 859 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 860 | |
f43845b3 MS |
861 | sp_offset = fp_offset = 0; |
862 | ||
94c30b78 MS |
863 | for (current_pc = prologue_start; |
864 | current_pc < prologue_end; | |
f43845b3 | 865 | current_pc += 4) |
96baa820 | 866 | { |
d4473757 KB |
867 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
868 | ||
94c30b78 | 869 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
870 | { |
871 | continue; | |
872 | } | |
94c30b78 | 873 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
874 | { |
875 | /* Function is frameless: extra_info defaults OK? */ | |
876 | continue; | |
877 | } | |
878 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
879 | /* stmfd sp!, {..., fp, ip, lr, pc} |
880 | or | |
881 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 882 | { |
d4473757 | 883 | int mask = insn & 0xffff; |
ed9a39eb | 884 | |
94c30b78 | 885 | /* Calculate offsets of saved registers. */ |
34e8f22d | 886 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
887 | if (mask & (1 << regno)) |
888 | { | |
889 | sp_offset -= 4; | |
c3b4394c | 890 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
891 | } |
892 | } | |
b8d5e71d MS |
893 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
894 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
895 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
896 | { | |
897 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
898 | continue; | |
899 | } | |
900 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
901 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
902 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
903 | { |
904 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
905 | continue; | |
906 | } | |
d4473757 KB |
907 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
908 | { | |
94c30b78 MS |
909 | unsigned imm = insn & 0xff; /* immediate value */ |
910 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
911 | imm = (imm >> rot) | (imm << (32 - rot)); |
912 | fp_offset = -imm; | |
34e8f22d | 913 | fi->extra_info->framereg = ARM_FP_REGNUM; |
d4473757 KB |
914 | } |
915 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
916 | { | |
94c30b78 MS |
917 | unsigned imm = insn & 0xff; /* immediate value */ |
918 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
919 | imm = (imm >> rot) | (imm << (32 - rot)); |
920 | sp_offset -= imm; | |
921 | } | |
922 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
923 | { | |
924 | sp_offset -= 12; | |
34e8f22d | 925 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
c3b4394c | 926 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
927 | } |
928 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
929 | { | |
930 | int n_saved_fp_regs; | |
931 | unsigned int fp_start_reg, fp_bound_reg; | |
932 | ||
94c30b78 | 933 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 934 | { |
d4473757 KB |
935 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
936 | n_saved_fp_regs = 3; | |
937 | else | |
938 | n_saved_fp_regs = 1; | |
96baa820 | 939 | } |
d4473757 | 940 | else |
96baa820 | 941 | { |
d4473757 KB |
942 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
943 | n_saved_fp_regs = 2; | |
944 | else | |
945 | n_saved_fp_regs = 4; | |
96baa820 | 946 | } |
d4473757 | 947 | |
34e8f22d | 948 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
949 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
950 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
951 | { |
952 | sp_offset -= 12; | |
c3b4394c | 953 | fi->saved_regs[fp_start_reg++] = sp_offset; |
96baa820 | 954 | } |
c906108c | 955 | } |
d4473757 | 956 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 957 | break; /* Condition not true, exit early */ |
b8d5e71d | 958 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 959 | break; /* Don't scan past a block load */ |
d4473757 KB |
960 | else |
961 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 962 | so we just skip what we don't recognize. */ |
d4473757 | 963 | continue; |
c906108c SS |
964 | } |
965 | ||
94c30b78 MS |
966 | /* The frame size is just the negative of the offset (from the |
967 | original SP) of the last thing thing we pushed on the stack. | |
968 | The frame offset is [new FP] - [new SP]. */ | |
c3b4394c | 969 | fi->extra_info->framesize = -sp_offset; |
34e8f22d | 970 | if (fi->extra_info->framereg == ARM_FP_REGNUM) |
c3b4394c | 971 | fi->extra_info->frameoffset = fp_offset - sp_offset; |
d4473757 | 972 | else |
c3b4394c | 973 | fi->extra_info->frameoffset = 0; |
ed9a39eb | 974 | |
c906108c SS |
975 | save_prologue_cache (fi); |
976 | } | |
977 | ||
ed9a39eb JM |
978 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
979 | One thing we might want to do here is to check REGNUM against the | |
980 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
981 | the stack somewhere. This would provide a graceful failure mode | |
982 | when trying to get the value of caller-saves registers for an inner | |
983 | frame. */ | |
c906108c SS |
984 | |
985 | static CORE_ADDR | |
ed9a39eb | 986 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 987 | { |
848cfffb AC |
988 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
989 | needed. Instead the (still being written) register unwind | |
990 | function could be called directly. */ | |
c906108c | 991 | for (; fi; fi = fi->next) |
848cfffb | 992 | { |
ae45cd16 | 993 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
848cfffb | 994 | { |
135c175f | 995 | return deprecated_read_register_dummy (fi->pc, fi->frame, regnum); |
848cfffb AC |
996 | } |
997 | else if (fi->saved_regs[regnum] != 0) | |
998 | { | |
999 | /* NOTE: cagney/2002-05-03: This would normally need to | |
1000 | handle ARM_SP_REGNUM as a special case as, according to | |
1001 | the frame.h comments, saved_regs[SP_REGNUM] contains the | |
1002 | SP value not its address. It appears that the ARM isn't | |
1003 | doing this though. */ | |
1004 | return read_memory_integer (fi->saved_regs[regnum], | |
1005 | REGISTER_RAW_SIZE (regnum)); | |
1006 | } | |
1007 | } | |
c906108c SS |
1008 | return read_register (regnum); |
1009 | } | |
148754e5 RE |
1010 | /* Function: frame_chain Given a GDB frame, determine the address of |
1011 | the calling function's frame. This will be used to create a new | |
1012 | GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC | |
1013 | will be called for the new frame. For ARM, we save the frame size | |
1014 | when we initialize the frame_info. */ | |
c5aa993b | 1015 | |
148754e5 | 1016 | static CORE_ADDR |
ed9a39eb | 1017 | arm_frame_chain (struct frame_info *fi) |
c906108c | 1018 | { |
848cfffb | 1019 | CORE_ADDR caller_pc; |
c3b4394c | 1020 | int framereg = fi->extra_info->framereg; |
c906108c | 1021 | |
ae45cd16 | 1022 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
848cfffb AC |
1023 | /* A generic call dummy's frame is the same as caller's. */ |
1024 | return fi->frame; | |
1025 | ||
c906108c SS |
1026 | if (fi->pc < LOWEST_PC) |
1027 | return 0; | |
1028 | ||
1029 | /* If the caller is the startup code, we're at the end of the chain. */ | |
1030 | caller_pc = FRAME_SAVED_PC (fi); | |
c906108c SS |
1031 | |
1032 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
1033 | the frame register of the caller is different from ours. | |
1034 | So we must scan the prologue of the caller to determine its | |
94c30b78 | 1035 | frame register number. */ |
c3b4394c RE |
1036 | /* XXX Fixme, we should try to do this without creating a temporary |
1037 | caller_fi. */ | |
c906108c SS |
1038 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
1039 | { | |
c3b4394c RE |
1040 | struct frame_info caller_fi; |
1041 | struct cleanup *old_chain; | |
1042 | ||
1043 | /* Create a temporary frame suitable for scanning the caller's | |
1044 | prologue. (Ugh.) */ | |
c5aa993b | 1045 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c3b4394c RE |
1046 | caller_fi.extra_info = (struct frame_extra_info *) |
1047 | xcalloc (1, sizeof (struct frame_extra_info)); | |
1048 | old_chain = make_cleanup (xfree, caller_fi.extra_info); | |
1049 | caller_fi.saved_regs = (CORE_ADDR *) | |
1050 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
1051 | make_cleanup (xfree, caller_fi.saved_regs); | |
1052 | ||
1053 | /* Now, scan the prologue and obtain the frame register. */ | |
c906108c | 1054 | caller_fi.pc = caller_pc; |
c5aa993b | 1055 | arm_scan_prologue (&caller_fi); |
c3b4394c RE |
1056 | framereg = caller_fi.extra_info->framereg; |
1057 | ||
1058 | /* Deallocate the storage associated with the temporary frame | |
1059 | created above. */ | |
1060 | do_cleanups (old_chain); | |
c906108c SS |
1061 | } |
1062 | ||
1063 | /* If the caller used a frame register, return its value. | |
1064 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 1065 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
1066 | return arm_find_callers_reg (fi, framereg); |
1067 | else | |
c3b4394c | 1068 | return fi->frame + fi->extra_info->framesize; |
c906108c SS |
1069 | } |
1070 | ||
ed9a39eb JM |
1071 | /* This function actually figures out the frame address for a given pc |
1072 | and sp. This is tricky because we sometimes don't use an explicit | |
1073 | frame pointer, and the previous stack pointer isn't necessarily | |
1074 | recorded on the stack. The only reliable way to get this info is | |
1075 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1076 | this is the next frame up the chain AFTER a frameless function. If | |
1077 | this is true, then the frame value for this frame is still in the | |
1078 | fp register. */ | |
c906108c | 1079 | |
148754e5 | 1080 | static void |
ed9a39eb | 1081 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1082 | { |
1083 | int reg; | |
f079148d | 1084 | CORE_ADDR sp; |
c906108c | 1085 | |
c3b4394c RE |
1086 | if (fi->saved_regs == NULL) |
1087 | frame_saved_regs_zalloc (fi); | |
1088 | ||
1089 | fi->extra_info = (struct frame_extra_info *) | |
1090 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1091 | ||
1092 | fi->extra_info->framesize = 0; | |
1093 | fi->extra_info->frameoffset = 0; | |
1094 | fi->extra_info->framereg = 0; | |
1095 | ||
c906108c SS |
1096 | if (fi->next) |
1097 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1098 | ||
c3b4394c | 1099 | memset (fi->saved_regs, '\000', sizeof fi->saved_regs); |
c906108c | 1100 | |
da3c6d4a MS |
1101 | /* Compute stack pointer for this frame. We use this value for both |
1102 | the sigtramp and call dummy cases. */ | |
f079148d KB |
1103 | if (!fi->next) |
1104 | sp = read_sp(); | |
ae45cd16 | 1105 | else if (DEPRECATED_PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) |
848cfffb AC |
1106 | /* For generic dummy frames, pull the value direct from the frame. |
1107 | Having an unwind function to do this would be nice. */ | |
135c175f AC |
1108 | sp = deprecated_read_register_dummy (fi->next->pc, fi->next->frame, |
1109 | ARM_SP_REGNUM); | |
f079148d | 1110 | else |
c3b4394c RE |
1111 | sp = (fi->next->frame - fi->next->extra_info->frameoffset |
1112 | + fi->next->extra_info->framesize); | |
f079148d | 1113 | |
d7bd68ca | 1114 | /* Determine whether or not we're in a sigtramp frame. |
5a203e44 AC |
1115 | Unfortunately, it isn't sufficient to test (get_frame_type (fi) |
1116 | == SIGTRAMP_FRAME) because this value is sometimes set after | |
1117 | invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
1118 | (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to | |
1119 | determine if we need to use the sigcontext addresses for the | |
1120 | saved registers. | |
2a451106 | 1121 | |
d7bd68ca AC |
1122 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1123 | against the name of the function, the code below will have to be | |
1124 | changed to first fetch the name of the function and then pass | |
1125 | this name to PC_IN_SIGTRAMP. */ | |
2a451106 | 1126 | |
5a203e44 AC |
1127 | /* FIXME: cagney/2002-11-18: This problem will go away once |
1128 | frame.c:get_prev_frame() is modified to set the frame's type | |
1129 | before calling functions like this. */ | |
1130 | ||
3bb04bdd | 1131 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
5a203e44 | 1132 | && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (fi->pc, (char *)0))) |
2a451106 | 1133 | { |
2a451106 | 1134 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c | 1135 | fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
2a451106 | 1136 | |
94c30b78 | 1137 | /* FIXME: What about thumb mode? */ |
34e8f22d | 1138 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
1139 | fi->frame = |
1140 | read_memory_integer (fi->saved_regs[fi->extra_info->framereg], | |
1141 | REGISTER_RAW_SIZE (fi->extra_info->framereg)); | |
1142 | fi->extra_info->framesize = 0; | |
1143 | fi->extra_info->frameoffset = 0; | |
2a451106 KB |
1144 | |
1145 | } | |
1146 | else | |
c906108c SS |
1147 | { |
1148 | arm_scan_prologue (fi); | |
1149 | ||
104c1213 | 1150 | if (!fi->next) |
94c30b78 | 1151 | /* This is the innermost frame? */ |
c3b4394c | 1152 | fi->frame = read_register (fi->extra_info->framereg); |
ae45cd16 | 1153 | else if (DEPRECATED_PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) |
848cfffb AC |
1154 | /* Next inner most frame is a dummy, just grab its frame. |
1155 | Dummy frames always have the same FP as their caller. */ | |
1156 | fi->frame = fi->next->frame; | |
34e8f22d | 1157 | else if (fi->extra_info->framereg == ARM_FP_REGNUM |
c3b4394c | 1158 | || fi->extra_info->framereg == THUMB_FP_REGNUM) |
ed9a39eb JM |
1159 | { |
1160 | /* not the innermost frame */ | |
94c30b78 | 1161 | /* If we have an FP, the callee saved it. */ |
c3b4394c | 1162 | if (fi->next->saved_regs[fi->extra_info->framereg] != 0) |
ed9a39eb | 1163 | fi->frame = |
c3b4394c RE |
1164 | read_memory_integer (fi->next |
1165 | ->saved_regs[fi->extra_info->framereg], 4); | |
ed9a39eb JM |
1166 | else if (fromleaf) |
1167 | /* If we were called by a frameless fn. then our frame is | |
94c30b78 | 1168 | still in the frame pointer register on the board... */ |
ed9a39eb JM |
1169 | fi->frame = read_fp (); |
1170 | } | |
c906108c | 1171 | |
ed9a39eb JM |
1172 | /* Calculate actual addresses of saved registers using offsets |
1173 | determined by arm_scan_prologue. */ | |
c906108c | 1174 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c RE |
1175 | if (fi->saved_regs[reg] != 0) |
1176 | fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize | |
1177 | - fi->extra_info->frameoffset); | |
c906108c SS |
1178 | } |
1179 | } | |
1180 | ||
1181 | ||
34e8f22d | 1182 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1183 | is saved in the stack anywhere, otherwise we get it from the |
1184 | registers. | |
c906108c SS |
1185 | |
1186 | The old definition of this function was a macro: | |
c5aa993b | 1187 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1188 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1189 | |
148754e5 | 1190 | static CORE_ADDR |
ed9a39eb | 1191 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1192 | { |
848cfffb | 1193 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
ae45cd16 | 1194 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
135c175f | 1195 | return deprecated_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM); |
848cfffb | 1196 | |
ae45cd16 | 1197 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset, |
c3b4394c | 1198 | fi->frame)) |
f079148d | 1199 | { |
34e8f22d RE |
1200 | return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM], |
1201 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); | |
f079148d KB |
1202 | } |
1203 | else | |
c906108c | 1204 | { |
34e8f22d | 1205 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1206 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1207 | } | |
1208 | } | |
1209 | ||
c906108c SS |
1210 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1211 | Examine the Program Status Register to decide which state we're in. */ | |
1212 | ||
148754e5 RE |
1213 | static CORE_ADDR |
1214 | arm_read_fp (void) | |
c906108c | 1215 | { |
34e8f22d | 1216 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1217 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1218 | else | |
34e8f22d | 1219 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1220 | } |
1221 | ||
148754e5 RE |
1222 | /* Store into a struct frame_saved_regs the addresses of the saved |
1223 | registers of frame described by FRAME_INFO. This includes special | |
1224 | registers such as PC and FP saved in special ways in the stack | |
1225 | frame. SP is even more special: the address we return for it IS | |
1226 | the sp for the next frame. */ | |
c906108c | 1227 | |
148754e5 | 1228 | static void |
c3b4394c | 1229 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1230 | { |
c3b4394c RE |
1231 | |
1232 | if (fip->saved_regs) | |
1233 | return; | |
1234 | ||
1235 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1236 | } |
1237 | ||
848cfffb AC |
1238 | /* Set the return address for a generic dummy frame. ARM uses the |
1239 | entry point. */ | |
1240 | ||
1241 | static CORE_ADDR | |
1242 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1243 | { | |
1244 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1245 | return sp; | |
1246 | } | |
1247 | ||
148754e5 RE |
1248 | /* Push an empty stack frame, to record the current PC, etc. */ |
1249 | ||
1250 | static void | |
ed9a39eb | 1251 | arm_push_dummy_frame (void) |
c906108c | 1252 | { |
34e8f22d | 1253 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1254 | CORE_ADDR sp = old_sp; |
1255 | CORE_ADDR fp, prologue_start; | |
1256 | int regnum; | |
1257 | ||
1258 | /* Push the two dummy prologue instructions in reverse order, | |
1259 | so that they'll be in the correct low-to-high order in memory. */ | |
1260 | /* sub fp, ip, #4 */ | |
1261 | sp = push_word (sp, 0xe24cb004); | |
1262 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1263 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1264 | ||
ed9a39eb JM |
1265 | /* Push a pointer to the dummy prologue + 12, because when stm |
1266 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1267 | instruction itself plus 12. */ |
1268 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1269 | |
f079148d | 1270 | /* Push the processor status. */ |
34e8f22d | 1271 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1272 | |
1273 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1274 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1275 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1276 | |
f079148d | 1277 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1278 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1279 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1280 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1281 | } |
1282 | ||
6eb69eab RE |
1283 | /* CALL_DUMMY_WORDS: |
1284 | This sequence of words is the instructions | |
1285 | ||
1286 | mov lr,pc | |
1287 | mov pc,r4 | |
1288 | illegal | |
1289 | ||
1290 | Note this is 12 bytes. */ | |
1291 | ||
34e8f22d | 1292 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1293 | { |
1294 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1295 | }; | |
1296 | ||
3fb4b924 RE |
1297 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1298 | breakpoint to the proper address in the call dummy, so that | |
1299 | `finish' after a stop in a call dummy works. | |
1300 | ||
d7b486e7 RE |
1301 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1302 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
1303 | followed by a call to run_stack_dummy, which is the only function | |
1304 | where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1305 | |
1306 | ||
1307 | static void | |
1308 | arm_set_call_dummy_breakpoint_offset (void) | |
1309 | { | |
1310 | if (caller_is_thumb) | |
1311 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); | |
1312 | else | |
1313 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); | |
1314 | } | |
1315 | ||
c906108c | 1316 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1317 | in Thumb or ARM mode, and whether the target function is Thumb or |
1318 | ARM. There are three different situations requiring three | |
c906108c SS |
1319 | different dummies: |
1320 | ||
1321 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1322 | been copied into the dummy parameter to this function. |
c906108c | 1323 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1324 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1325 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1326 | works for calling both ARM and Thumb functions. |
c906108c | 1327 | |
ed9a39eb JM |
1328 | All three call dummies expect to receive the target function |
1329 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1330 | |
34e8f22d | 1331 | static void |
ed9a39eb | 1332 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1333 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1334 | { |
1335 | static short thumb_dummy[4] = | |
1336 | { | |
c5aa993b JM |
1337 | 0xf000, 0xf801, /* bl label */ |
1338 | 0xdf18, /* swi 24 */ | |
1339 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1340 | }; |
1341 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1342 | ||
94c30b78 | 1343 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1344 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1345 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1346 | |
ed9a39eb JM |
1347 | /* If the target function is Thumb, set the low bit of the function |
1348 | address. And if the CPU is currently in ARM mode, patch the | |
1349 | second instruction of call dummy to use a BX instruction to | |
1350 | switch to Thumb mode. */ | |
c906108c SS |
1351 | target_is_thumb = arm_pc_is_thumb (fun); |
1352 | if (target_is_thumb) | |
1353 | { | |
1354 | fun |= 1; | |
1355 | if (!caller_is_thumb) | |
1356 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1357 | } | |
1358 | ||
1359 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1360 | instead of the ARM one that's already been copied. This will | |
1361 | work for both Thumb and ARM target functions. */ | |
1362 | if (caller_is_thumb) | |
1363 | { | |
1364 | int i; | |
1365 | char *p = dummy; | |
1366 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1367 | ||
1368 | for (i = 0; i < len; i++) | |
1369 | { | |
1370 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1371 | p += sizeof (thumb_dummy[0]); | |
1372 | } | |
1373 | } | |
1374 | ||
ed9a39eb | 1375 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1376 | the PC. */ |
c906108c SS |
1377 | write_register (4, fun); |
1378 | } | |
1379 | ||
ed9a39eb JM |
1380 | /* Note: ScottB |
1381 | ||
1382 | This function does not support passing parameters using the FPA | |
1383 | variant of the APCS. It passes any floating point arguments in the | |
1384 | general registers and/or on the stack. */ | |
c906108c | 1385 | |
39bbf761 | 1386 | static CORE_ADDR |
ea7c478f | 1387 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1388 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1389 | { |
6529d2dd AC |
1390 | CORE_ADDR fp; |
1391 | int argnum; | |
1392 | int argreg; | |
1393 | int nstack; | |
1394 | int simd_argreg; | |
1395 | int second_pass; | |
1396 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
ed9a39eb JM |
1397 | |
1398 | /* Walk through the list of args and determine how large a temporary | |
1399 | stack is required. Need to take care here as structs may be | |
6529d2dd AC |
1400 | passed on the stack, and we have to to push them. On the second |
1401 | pass, do the store. */ | |
1402 | nstack = 0; | |
1403 | fp = sp; | |
1404 | for (second_pass = 0; second_pass < 2; second_pass++) | |
c906108c | 1405 | { |
6529d2dd AC |
1406 | /* Compute the FP using the information computed during the |
1407 | first pass. */ | |
1408 | if (second_pass) | |
1409 | fp = sp - nstack; | |
1410 | ||
1411 | simd_argreg = 0; | |
1412 | argreg = ARM_A1_REGNUM; | |
1413 | nstack = 0; | |
1414 | ||
1415 | /* The struct_return pointer occupies the first parameter | |
1416 | passing register. */ | |
1417 | if (struct_return) | |
c906108c | 1418 | { |
6529d2dd AC |
1419 | if (second_pass) |
1420 | { | |
1421 | if (arm_debug) | |
1422 | fprintf_unfiltered (gdb_stdlog, | |
1423 | "struct return in %s = 0x%s\n", | |
1424 | REGISTER_NAME (argreg), | |
1425 | paddr (struct_addr)); | |
1426 | write_register (argreg, struct_addr); | |
1427 | } | |
1428 | argreg++; | |
c906108c | 1429 | } |
ed9a39eb | 1430 | |
6529d2dd AC |
1431 | for (argnum = 0; argnum < nargs; argnum++) |
1432 | { | |
1433 | int len; | |
1434 | struct type *arg_type; | |
1435 | struct type *target_type; | |
1436 | enum type_code typecode; | |
1437 | char *val; | |
1438 | ||
1439 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1440 | len = TYPE_LENGTH (arg_type); | |
1441 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1442 | typecode = TYPE_CODE (arg_type); | |
1443 | val = VALUE_CONTENTS (args[argnum]); | |
1444 | ||
1445 | /* If the argument is a pointer to a function, and it is a | |
1446 | Thumb function, create a LOCAL copy of the value and set | |
1447 | the THUMB bit in it. */ | |
1448 | if (second_pass | |
1449 | && TYPE_CODE_PTR == typecode | |
1450 | && target_type != NULL | |
1451 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1452 | { |
6529d2dd AC |
1453 | CORE_ADDR regval = extract_address (val, len); |
1454 | if (arm_pc_is_thumb (regval)) | |
1455 | { | |
1456 | val = alloca (len); | |
1457 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1458 | } | |
c906108c | 1459 | } |
6529d2dd AC |
1460 | |
1461 | /* Copy the argument to general registers or the stack in | |
1462 | register-sized pieces. Large arguments are split between | |
1463 | registers and stack. */ | |
1464 | while (len > 0) | |
ed9a39eb | 1465 | { |
6529d2dd AC |
1466 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1467 | ||
1468 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1469 | { | |
1470 | /* The argument is being passed in a general purpose | |
1471 | register. */ | |
1472 | if (second_pass) | |
1473 | { | |
1474 | CORE_ADDR regval = extract_address (val, | |
1475 | partial_len); | |
1476 | if (arm_debug) | |
1477 | fprintf_unfiltered (gdb_stdlog, | |
1478 | "arg %d in %s = 0x%s\n", | |
1479 | argnum, | |
1480 | REGISTER_NAME (argreg), | |
1481 | phex (regval, REGISTER_SIZE)); | |
1482 | write_register (argreg, regval); | |
1483 | } | |
1484 | argreg++; | |
1485 | } | |
1486 | else | |
1487 | { | |
1488 | if (second_pass) | |
1489 | { | |
1490 | /* Push the arguments onto the stack. */ | |
1491 | if (arm_debug) | |
1492 | fprintf_unfiltered (gdb_stdlog, | |
1493 | "arg %d @ 0x%s + %d\n", | |
1494 | argnum, paddr (fp), nstack); | |
1495 | write_memory (fp + nstack, val, REGISTER_SIZE); | |
1496 | } | |
1497 | nstack += REGISTER_SIZE; | |
1498 | } | |
1499 | ||
1500 | len -= partial_len; | |
1501 | val += partial_len; | |
ed9a39eb JM |
1502 | } |
1503 | ||
c906108c SS |
1504 | } |
1505 | } | |
c906108c | 1506 | |
6529d2dd AC |
1507 | /* Return the botom of the argument list (pointed to by fp). */ |
1508 | return fp; | |
c906108c SS |
1509 | } |
1510 | ||
da3c6d4a MS |
1511 | /* Pop the current frame. So long as the frame info has been |
1512 | initialized properly (see arm_init_extra_frame_info), this code | |
1513 | works for dummy frames as well as regular frames. I.e, there's no | |
1514 | need to have a special case for dummy frames. */ | |
148754e5 | 1515 | static void |
ed9a39eb | 1516 | arm_pop_frame (void) |
c906108c | 1517 | { |
c906108c | 1518 | int regnum; |
8b93c638 | 1519 | struct frame_info *frame = get_current_frame (); |
c3b4394c RE |
1520 | CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset |
1521 | + frame->extra_info->framesize); | |
c906108c | 1522 | |
ae45cd16 | 1523 | if (DEPRECATED_PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) |
848cfffb AC |
1524 | { |
1525 | generic_pop_dummy_frame (); | |
1526 | flush_cached_frames (); | |
1527 | return; | |
1528 | } | |
1529 | ||
f079148d | 1530 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c3b4394c | 1531 | if (frame->saved_regs[regnum] != 0) |
f079148d | 1532 | write_register (regnum, |
c3b4394c | 1533 | read_memory_integer (frame->saved_regs[regnum], |
f079148d | 1534 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1535 | |
34e8f22d RE |
1536 | write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame)); |
1537 | write_register (ARM_SP_REGNUM, old_SP); | |
c906108c SS |
1538 | |
1539 | flush_cached_frames (); | |
1540 | } | |
1541 | ||
1542 | static void | |
ed9a39eb | 1543 | print_fpu_flags (int flags) |
c906108c | 1544 | { |
c5aa993b JM |
1545 | if (flags & (1 << 0)) |
1546 | fputs ("IVO ", stdout); | |
1547 | if (flags & (1 << 1)) | |
1548 | fputs ("DVZ ", stdout); | |
1549 | if (flags & (1 << 2)) | |
1550 | fputs ("OFL ", stdout); | |
1551 | if (flags & (1 << 3)) | |
1552 | fputs ("UFL ", stdout); | |
1553 | if (flags & (1 << 4)) | |
1554 | fputs ("INX ", stdout); | |
1555 | putchar ('\n'); | |
c906108c SS |
1556 | } |
1557 | ||
5e74b15c RE |
1558 | /* Print interesting information about the floating point processor |
1559 | (if present) or emulator. */ | |
34e8f22d | 1560 | static void |
d855c300 | 1561 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1562 | struct frame_info *frame, const char *args) |
c906108c | 1563 | { |
34e8f22d | 1564 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1565 | int type; |
1566 | ||
1567 | type = (status >> 24) & 127; | |
1568 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1569 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1570 | type); |
1571 | fputs ("mask: ", stdout); | |
1572 | print_fpu_flags (status >> 16); | |
1573 | fputs ("flags: ", stdout); | |
1574 | print_fpu_flags (status); | |
c906108c SS |
1575 | } |
1576 | ||
34e8f22d RE |
1577 | /* Return the GDB type object for the "standard" data type of data in |
1578 | register N. */ | |
1579 | ||
1580 | static struct type * | |
032758dc AC |
1581 | arm_register_type (int regnum) |
1582 | { | |
34e8f22d | 1583 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1584 | { |
d7449b42 | 1585 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1586 | return builtin_type_arm_ext_big; |
1587 | else | |
1588 | return builtin_type_arm_ext_littlebyte_bigword; | |
1589 | } | |
1590 | else | |
1591 | return builtin_type_int32; | |
1592 | } | |
1593 | ||
34e8f22d RE |
1594 | /* Index within `registers' of the first byte of the space for |
1595 | register N. */ | |
1596 | ||
1597 | static int | |
1598 | arm_register_byte (int regnum) | |
1599 | { | |
1600 | if (regnum < ARM_F0_REGNUM) | |
1601 | return regnum * INT_REGISTER_RAW_SIZE; | |
1602 | else if (regnum < ARM_PS_REGNUM) | |
1603 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1604 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1605 | else | |
1606 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1607 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1608 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1609 | } | |
1610 | ||
1611 | /* Number of bytes of storage in the actual machine representation for | |
1612 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1613 | 12 bytes in length. */ | |
1614 | ||
1615 | static int | |
1616 | arm_register_raw_size (int regnum) | |
1617 | { | |
1618 | if (regnum < ARM_F0_REGNUM) | |
1619 | return INT_REGISTER_RAW_SIZE; | |
1620 | else if (regnum < ARM_FPS_REGNUM) | |
1621 | return FP_REGISTER_RAW_SIZE; | |
1622 | else | |
1623 | return STATUS_REGISTER_SIZE; | |
1624 | } | |
1625 | ||
1626 | /* Number of bytes of storage in a program's representation | |
1627 | for register N. */ | |
1628 | static int | |
1629 | arm_register_virtual_size (int regnum) | |
1630 | { | |
1631 | if (regnum < ARM_F0_REGNUM) | |
1632 | return INT_REGISTER_VIRTUAL_SIZE; | |
1633 | else if (regnum < ARM_FPS_REGNUM) | |
1634 | return FP_REGISTER_VIRTUAL_SIZE; | |
1635 | else | |
1636 | return STATUS_REGISTER_SIZE; | |
1637 | } | |
1638 | ||
26216b98 AC |
1639 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1640 | static int | |
1641 | arm_register_sim_regno (int regnum) | |
1642 | { | |
1643 | int reg = regnum; | |
1644 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1645 | ||
1646 | if (reg < NUM_GREGS) | |
1647 | return SIM_ARM_R0_REGNUM + reg; | |
1648 | reg -= NUM_GREGS; | |
1649 | ||
1650 | if (reg < NUM_FREGS) | |
1651 | return SIM_ARM_FP0_REGNUM + reg; | |
1652 | reg -= NUM_FREGS; | |
1653 | ||
1654 | if (reg < NUM_SREGS) | |
1655 | return SIM_ARM_FPS_REGNUM + reg; | |
1656 | reg -= NUM_SREGS; | |
1657 | ||
1658 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1659 | } | |
34e8f22d | 1660 | |
a37b3cc0 AC |
1661 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1662 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1663 | It is thought that this is is the floating-point register format on | |
1664 | little-endian systems. */ | |
c906108c | 1665 | |
ed9a39eb JM |
1666 | static void |
1667 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1668 | { |
a37b3cc0 | 1669 | DOUBLEST d; |
d7449b42 | 1670 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1671 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1672 | else | |
1673 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1674 | ptr, &d); | |
1675 | floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl); | |
c906108c SS |
1676 | } |
1677 | ||
34e8f22d | 1678 | static void |
ed9a39eb | 1679 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1680 | { |
a37b3cc0 AC |
1681 | DOUBLEST d; |
1682 | floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d); | |
d7449b42 | 1683 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1684 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1685 | else | |
1686 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1687 | &d, dbl); | |
c906108c | 1688 | } |
ed9a39eb | 1689 | |
c906108c | 1690 | static int |
ed9a39eb | 1691 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1692 | { |
1693 | if (cond == INST_AL || cond == INST_NV) | |
1694 | return 1; | |
1695 | ||
1696 | switch (cond) | |
1697 | { | |
1698 | case INST_EQ: | |
1699 | return ((status_reg & FLAG_Z) != 0); | |
1700 | case INST_NE: | |
1701 | return ((status_reg & FLAG_Z) == 0); | |
1702 | case INST_CS: | |
1703 | return ((status_reg & FLAG_C) != 0); | |
1704 | case INST_CC: | |
1705 | return ((status_reg & FLAG_C) == 0); | |
1706 | case INST_MI: | |
1707 | return ((status_reg & FLAG_N) != 0); | |
1708 | case INST_PL: | |
1709 | return ((status_reg & FLAG_N) == 0); | |
1710 | case INST_VS: | |
1711 | return ((status_reg & FLAG_V) != 0); | |
1712 | case INST_VC: | |
1713 | return ((status_reg & FLAG_V) == 0); | |
1714 | case INST_HI: | |
1715 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1716 | case INST_LS: | |
1717 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1718 | case INST_GE: | |
1719 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1720 | case INST_LT: | |
1721 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1722 | case INST_GT: | |
1723 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1724 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1725 | case INST_LE: |
1726 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1727 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1728 | } |
1729 | return 1; | |
1730 | } | |
1731 | ||
9512d7fd | 1732 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1733 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1734 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1735 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1736 | #define sbits(obj,st,fn) \ | |
1737 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1738 | #define BranchDest(addr,instr) \ | |
1739 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1740 | #define ARM_PC_32 1 | |
1741 | ||
1742 | static unsigned long | |
ed9a39eb JM |
1743 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1744 | unsigned long status_reg) | |
c906108c SS |
1745 | { |
1746 | unsigned long res, shift; | |
1747 | int rm = bits (inst, 0, 3); | |
1748 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1749 | |
1750 | if (bit (inst, 4)) | |
c906108c SS |
1751 | { |
1752 | int rs = bits (inst, 8, 11); | |
1753 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1754 | } | |
1755 | else | |
1756 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1757 | |
1758 | res = (rm == 15 | |
c906108c | 1759 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1760 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1761 | : read_register (rm)); |
1762 | ||
1763 | switch (shifttype) | |
1764 | { | |
c5aa993b | 1765 | case 0: /* LSL */ |
c906108c SS |
1766 | res = shift >= 32 ? 0 : res << shift; |
1767 | break; | |
c5aa993b JM |
1768 | |
1769 | case 1: /* LSR */ | |
c906108c SS |
1770 | res = shift >= 32 ? 0 : res >> shift; |
1771 | break; | |
1772 | ||
c5aa993b JM |
1773 | case 2: /* ASR */ |
1774 | if (shift >= 32) | |
1775 | shift = 31; | |
c906108c SS |
1776 | res = ((res & 0x80000000L) |
1777 | ? ~((~res) >> shift) : res >> shift); | |
1778 | break; | |
1779 | ||
c5aa993b | 1780 | case 3: /* ROR/RRX */ |
c906108c SS |
1781 | shift &= 31; |
1782 | if (shift == 0) | |
1783 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1784 | else | |
c5aa993b | 1785 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1786 | break; |
1787 | } | |
1788 | ||
1789 | return res & 0xffffffff; | |
1790 | } | |
1791 | ||
c906108c SS |
1792 | /* Return number of 1-bits in VAL. */ |
1793 | ||
1794 | static int | |
ed9a39eb | 1795 | bitcount (unsigned long val) |
c906108c SS |
1796 | { |
1797 | int nbits; | |
1798 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1799 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1800 | return nbits; |
1801 | } | |
1802 | ||
34e8f22d | 1803 | CORE_ADDR |
ed9a39eb | 1804 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1805 | { |
c5aa993b | 1806 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1807 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1808 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1809 | unsigned long offset; |
1810 | ||
1811 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1812 | { | |
1813 | CORE_ADDR sp; | |
1814 | ||
1815 | /* Fetch the saved PC from the stack. It's stored above | |
1816 | all of the other registers. */ | |
1817 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
34e8f22d | 1818 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1819 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1820 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1821 | if (nextpc == pc) | |
1822 | error ("Infinite loop detected"); | |
1823 | } | |
1824 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1825 | { | |
34e8f22d | 1826 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1827 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1828 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1829 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1830 | } | |
1831 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1832 | { | |
1833 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1834 | } | |
1835 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1836 | { | |
1837 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1838 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1839 | nextpc = pc_val + offset; |
1840 | } | |
1841 | ||
1842 | return nextpc; | |
1843 | } | |
1844 | ||
34e8f22d | 1845 | CORE_ADDR |
ed9a39eb | 1846 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1847 | { |
1848 | unsigned long pc_val; | |
1849 | unsigned long this_instr; | |
1850 | unsigned long status; | |
1851 | CORE_ADDR nextpc; | |
1852 | ||
1853 | if (arm_pc_is_thumb (pc)) | |
1854 | return thumb_get_next_pc (pc); | |
1855 | ||
1856 | pc_val = (unsigned long) pc; | |
1857 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1858 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1859 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1860 | |
1861 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1862 | { | |
1863 | switch (bits (this_instr, 24, 27)) | |
1864 | { | |
c5aa993b | 1865 | case 0x0: |
94c30b78 | 1866 | case 0x1: /* data processing */ |
c5aa993b JM |
1867 | case 0x2: |
1868 | case 0x3: | |
c906108c SS |
1869 | { |
1870 | unsigned long operand1, operand2, result = 0; | |
1871 | unsigned long rn; | |
1872 | int c; | |
c5aa993b | 1873 | |
c906108c SS |
1874 | if (bits (this_instr, 12, 15) != 15) |
1875 | break; | |
1876 | ||
1877 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1878 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1879 | error ("Illegal update to pc in instruction"); |
1880 | ||
1881 | /* Multiply into PC */ | |
1882 | c = (status & FLAG_C) ? 1 : 0; | |
1883 | rn = bits (this_instr, 16, 19); | |
1884 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1885 | |
c906108c SS |
1886 | if (bit (this_instr, 25)) |
1887 | { | |
1888 | unsigned long immval = bits (this_instr, 0, 7); | |
1889 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1890 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1891 | & 0xffffffff; | |
c906108c | 1892 | } |
c5aa993b | 1893 | else /* operand 2 is a shifted register */ |
c906108c | 1894 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1895 | |
c906108c SS |
1896 | switch (bits (this_instr, 21, 24)) |
1897 | { | |
c5aa993b | 1898 | case 0x0: /*and */ |
c906108c SS |
1899 | result = operand1 & operand2; |
1900 | break; | |
1901 | ||
c5aa993b | 1902 | case 0x1: /*eor */ |
c906108c SS |
1903 | result = operand1 ^ operand2; |
1904 | break; | |
1905 | ||
c5aa993b | 1906 | case 0x2: /*sub */ |
c906108c SS |
1907 | result = operand1 - operand2; |
1908 | break; | |
1909 | ||
c5aa993b | 1910 | case 0x3: /*rsb */ |
c906108c SS |
1911 | result = operand2 - operand1; |
1912 | break; | |
1913 | ||
c5aa993b | 1914 | case 0x4: /*add */ |
c906108c SS |
1915 | result = operand1 + operand2; |
1916 | break; | |
1917 | ||
c5aa993b | 1918 | case 0x5: /*adc */ |
c906108c SS |
1919 | result = operand1 + operand2 + c; |
1920 | break; | |
1921 | ||
c5aa993b | 1922 | case 0x6: /*sbc */ |
c906108c SS |
1923 | result = operand1 - operand2 + c; |
1924 | break; | |
1925 | ||
c5aa993b | 1926 | case 0x7: /*rsc */ |
c906108c SS |
1927 | result = operand2 - operand1 + c; |
1928 | break; | |
1929 | ||
c5aa993b JM |
1930 | case 0x8: |
1931 | case 0x9: | |
1932 | case 0xa: | |
1933 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1934 | result = (unsigned long) nextpc; |
1935 | break; | |
1936 | ||
c5aa993b | 1937 | case 0xc: /*orr */ |
c906108c SS |
1938 | result = operand1 | operand2; |
1939 | break; | |
1940 | ||
c5aa993b | 1941 | case 0xd: /*mov */ |
c906108c SS |
1942 | /* Always step into a function. */ |
1943 | result = operand2; | |
c5aa993b | 1944 | break; |
c906108c | 1945 | |
c5aa993b | 1946 | case 0xe: /*bic */ |
c906108c SS |
1947 | result = operand1 & ~operand2; |
1948 | break; | |
1949 | ||
c5aa993b | 1950 | case 0xf: /*mvn */ |
c906108c SS |
1951 | result = ~operand2; |
1952 | break; | |
1953 | } | |
1954 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1955 | ||
1956 | if (nextpc == pc) | |
1957 | error ("Infinite loop detected"); | |
1958 | break; | |
1959 | } | |
c5aa993b JM |
1960 | |
1961 | case 0x4: | |
1962 | case 0x5: /* data transfer */ | |
1963 | case 0x6: | |
1964 | case 0x7: | |
c906108c SS |
1965 | if (bit (this_instr, 20)) |
1966 | { | |
1967 | /* load */ | |
1968 | if (bits (this_instr, 12, 15) == 15) | |
1969 | { | |
1970 | /* rd == pc */ | |
c5aa993b | 1971 | unsigned long rn; |
c906108c | 1972 | unsigned long base; |
c5aa993b | 1973 | |
c906108c SS |
1974 | if (bit (this_instr, 22)) |
1975 | error ("Illegal update to pc in instruction"); | |
1976 | ||
1977 | /* byte write to PC */ | |
1978 | rn = bits (this_instr, 16, 19); | |
1979 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1980 | if (bit (this_instr, 24)) | |
1981 | { | |
1982 | /* pre-indexed */ | |
1983 | int c = (status & FLAG_C) ? 1 : 0; | |
1984 | unsigned long offset = | |
c5aa993b | 1985 | (bit (this_instr, 25) |
ed9a39eb | 1986 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1987 | : bits (this_instr, 0, 11)); |
c906108c SS |
1988 | |
1989 | if (bit (this_instr, 23)) | |
1990 | base += offset; | |
1991 | else | |
1992 | base -= offset; | |
1993 | } | |
c5aa993b | 1994 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1995 | 4); |
c5aa993b | 1996 | |
c906108c SS |
1997 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1998 | ||
1999 | if (nextpc == pc) | |
2000 | error ("Infinite loop detected"); | |
2001 | } | |
2002 | } | |
2003 | break; | |
c5aa993b JM |
2004 | |
2005 | case 0x8: | |
2006 | case 0x9: /* block transfer */ | |
c906108c SS |
2007 | if (bit (this_instr, 20)) |
2008 | { | |
2009 | /* LDM */ | |
2010 | if (bit (this_instr, 15)) | |
2011 | { | |
2012 | /* loading pc */ | |
2013 | int offset = 0; | |
2014 | ||
2015 | if (bit (this_instr, 23)) | |
2016 | { | |
2017 | /* up */ | |
2018 | unsigned long reglist = bits (this_instr, 0, 14); | |
2019 | offset = bitcount (reglist) * 4; | |
c5aa993b | 2020 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
2021 | offset += 4; |
2022 | } | |
2023 | else if (bit (this_instr, 24)) | |
2024 | offset = -4; | |
c5aa993b | 2025 | |
c906108c | 2026 | { |
c5aa993b JM |
2027 | unsigned long rn_val = |
2028 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
2029 | nextpc = |
2030 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2031 | + offset), |
c906108c SS |
2032 | 4); |
2033 | } | |
2034 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2035 | if (nextpc == pc) | |
2036 | error ("Infinite loop detected"); | |
2037 | } | |
2038 | } | |
2039 | break; | |
c5aa993b JM |
2040 | |
2041 | case 0xb: /* branch & link */ | |
2042 | case 0xa: /* branch */ | |
c906108c SS |
2043 | { |
2044 | nextpc = BranchDest (pc, this_instr); | |
2045 | ||
2046 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2047 | if (nextpc == pc) | |
2048 | error ("Infinite loop detected"); | |
2049 | break; | |
2050 | } | |
c5aa993b JM |
2051 | |
2052 | case 0xc: | |
2053 | case 0xd: | |
2054 | case 0xe: /* coproc ops */ | |
2055 | case 0xf: /* SWI */ | |
c906108c SS |
2056 | break; |
2057 | ||
2058 | default: | |
97e03143 | 2059 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
2060 | return (pc); |
2061 | } | |
2062 | } | |
2063 | ||
2064 | return nextpc; | |
2065 | } | |
2066 | ||
9512d7fd FN |
2067 | /* single_step() is called just before we want to resume the inferior, |
2068 | if we want to single-step it but there is no hardware or kernel | |
2069 | single-step support. We find the target of the coming instruction | |
2070 | and breakpoint it. | |
2071 | ||
94c30b78 MS |
2072 | single_step() is also called just after the inferior stops. If we |
2073 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2074 | |
34e8f22d RE |
2075 | static void |
2076 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2077 | { |
b8d5e71d | 2078 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2079 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2080 | ||
2081 | if (insert_bpt) | |
2082 | { | |
34e8f22d | 2083 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2084 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2085 | } |
2086 | else | |
80fcf3f0 | 2087 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2088 | } |
9512d7fd | 2089 | |
c906108c SS |
2090 | #include "bfd-in2.h" |
2091 | #include "libcoff.h" | |
2092 | ||
2093 | static int | |
ed9a39eb | 2094 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2095 | { |
2096 | if (arm_pc_is_thumb (memaddr)) | |
2097 | { | |
c5aa993b JM |
2098 | static asymbol *asym; |
2099 | static combined_entry_type ce; | |
2100 | static struct coff_symbol_struct csym; | |
2101 | static struct _bfd fake_bfd; | |
2102 | static bfd_target fake_target; | |
c906108c SS |
2103 | |
2104 | if (csym.native == NULL) | |
2105 | { | |
da3c6d4a MS |
2106 | /* Create a fake symbol vector containing a Thumb symbol. |
2107 | This is solely so that the code in print_insn_little_arm() | |
2108 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2109 | the presence of a Thumb symbol and switch to decoding | |
2110 | Thumb instructions. */ | |
c5aa993b JM |
2111 | |
2112 | fake_target.flavour = bfd_target_coff_flavour; | |
2113 | fake_bfd.xvec = &fake_target; | |
c906108c | 2114 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2115 | csym.native = &ce; |
2116 | csym.symbol.the_bfd = &fake_bfd; | |
2117 | csym.symbol.name = "fake"; | |
2118 | asym = (asymbol *) & csym; | |
c906108c | 2119 | } |
c5aa993b | 2120 | |
c906108c | 2121 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2122 | info->symbols = &asym; |
c906108c SS |
2123 | } |
2124 | else | |
2125 | info->symbols = NULL; | |
c5aa993b | 2126 | |
d7449b42 | 2127 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2128 | return print_insn_big_arm (memaddr, info); |
2129 | else | |
2130 | return print_insn_little_arm (memaddr, info); | |
2131 | } | |
2132 | ||
66e810cd RE |
2133 | /* The following define instruction sequences that will cause ARM |
2134 | cpu's to take an undefined instruction trap. These are used to | |
2135 | signal a breakpoint to GDB. | |
2136 | ||
2137 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2138 | modes. A different instruction is required for each mode. The ARM | |
2139 | cpu's can also be big or little endian. Thus four different | |
2140 | instructions are needed to support all cases. | |
2141 | ||
2142 | Note: ARMv4 defines several new instructions that will take the | |
2143 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2144 | not in fact add the new instructions. The new undefined | |
2145 | instructions in ARMv4 are all instructions that had no defined | |
2146 | behaviour in earlier chips. There is no guarantee that they will | |
2147 | raise an exception, but may be treated as NOP's. In practice, it | |
2148 | may only safe to rely on instructions matching: | |
2149 | ||
2150 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2151 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2152 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2153 | ||
2154 | Even this may only true if the condition predicate is true. The | |
2155 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2156 | ||
2157 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2158 | and NetBSD all use a software interrupt rather than an undefined | |
2159 | instruction to force a trap. This can be handled by by the | |
2160 | abi-specific code during establishment of the gdbarch vector. */ | |
2161 | ||
2162 | ||
d7b486e7 RE |
2163 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2164 | override these definitions. */ | |
66e810cd RE |
2165 | #ifndef ARM_LE_BREAKPOINT |
2166 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2167 | #endif | |
2168 | #ifndef ARM_BE_BREAKPOINT | |
2169 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2170 | #endif | |
2171 | #ifndef THUMB_LE_BREAKPOINT | |
2172 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2173 | #endif | |
2174 | #ifndef THUMB_BE_BREAKPOINT | |
2175 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2176 | #endif | |
2177 | ||
2178 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2179 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2180 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2181 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2182 | ||
34e8f22d RE |
2183 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2184 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2185 | breakpoint should be used. It returns a pointer to a string of |
2186 | bytes that encode a breakpoint instruction, stores the length of | |
2187 | the string to *lenptr, and adjusts the program counter (if | |
2188 | necessary) to point to the actual memory location where the | |
c906108c SS |
2189 | breakpoint should be inserted. */ |
2190 | ||
34e8f22d RE |
2191 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2192 | breakpoints and storing their handles instread of what was in | |
2193 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2194 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2195 | |
ab89facf | 2196 | static const unsigned char * |
ed9a39eb | 2197 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2198 | { |
66e810cd RE |
2199 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2200 | ||
c906108c SS |
2201 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2202 | { | |
66e810cd RE |
2203 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2204 | *lenptr = tdep->thumb_breakpoint_size; | |
2205 | return tdep->thumb_breakpoint; | |
c906108c SS |
2206 | } |
2207 | else | |
2208 | { | |
66e810cd RE |
2209 | *lenptr = tdep->arm_breakpoint_size; |
2210 | return tdep->arm_breakpoint; | |
c906108c SS |
2211 | } |
2212 | } | |
ed9a39eb JM |
2213 | |
2214 | /* Extract from an array REGBUF containing the (raw) register state a | |
2215 | function return value of type TYPE, and copy that, in virtual | |
2216 | format, into VALBUF. */ | |
2217 | ||
34e8f22d | 2218 | static void |
ed9a39eb JM |
2219 | arm_extract_return_value (struct type *type, |
2220 | char regbuf[REGISTER_BYTES], | |
2221 | char *valbuf) | |
2222 | { | |
2223 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 RE |
2224 | { |
2225 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2226 | ||
2227 | switch (tdep->fp_model) | |
2228 | { | |
2229 | case ARM_FLOAT_FPA: | |
2230 | convert_from_extended (®buf[REGISTER_BYTE (ARM_F0_REGNUM)], | |
2231 | valbuf); | |
2232 | break; | |
2233 | ||
2234 | case ARM_FLOAT_SOFT: | |
2235 | case ARM_FLOAT_SOFT_VFP: | |
2236 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], | |
2237 | TYPE_LENGTH (type)); | |
2238 | break; | |
2239 | ||
2240 | default: | |
2241 | internal_error | |
2242 | (__FILE__, __LINE__, | |
2243 | "arm_extract_return_value: Floating point model not supported"); | |
2244 | break; | |
2245 | } | |
2246 | } | |
ed9a39eb | 2247 | else |
34e8f22d RE |
2248 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], |
2249 | TYPE_LENGTH (type)); | |
2250 | } | |
2251 | ||
67255d04 RE |
2252 | /* Extract from an array REGBUF containing the (raw) register state |
2253 | the address in which a function should return its structure value. */ | |
2254 | ||
2255 | static CORE_ADDR | |
95f95911 | 2256 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2257 | { |
95f95911 MS |
2258 | ULONGEST ret; |
2259 | ||
2260 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2261 | return ret; | |
67255d04 RE |
2262 | } |
2263 | ||
2264 | /* Will a function return an aggregate type in memory or in a | |
2265 | register? Return 0 if an aggregate type can be returned in a | |
2266 | register, 1 if it must be returned in memory. */ | |
2267 | ||
2268 | static int | |
2269 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2270 | { | |
2271 | int nRc; | |
2272 | register enum type_code code; | |
2273 | ||
2274 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2275 | registers. For an aggregate type to be integer like, its size | |
2276 | must be less than or equal to REGISTER_SIZE and the offset of | |
2277 | each addressable subfield must be zero. Note that bit fields are | |
2278 | not addressable, and all addressable subfields of unions always | |
2279 | start at offset zero. | |
2280 | ||
2281 | This function is based on the behaviour of GCC 2.95.1. | |
2282 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2283 | ||
2284 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2285 | parameters correctly for a function returning the following | |
2286 | structure: struct { float f;}; This should be returned in memory, | |
2287 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2288 | know of any way to detect if a function like the above has been | |
2289 | compiled with the correct calling convention. */ | |
2290 | ||
2291 | /* All aggregate types that won't fit in a register must be returned | |
2292 | in memory. */ | |
2293 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
2294 | { | |
2295 | return 1; | |
2296 | } | |
2297 | ||
2298 | /* The only aggregate types that can be returned in a register are | |
2299 | structs and unions. Arrays must be returned in memory. */ | |
2300 | code = TYPE_CODE (type); | |
2301 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2302 | { | |
2303 | return 1; | |
2304 | } | |
2305 | ||
2306 | /* Assume all other aggregate types can be returned in a register. | |
2307 | Run a check for structures, unions and arrays. */ | |
2308 | nRc = 0; | |
2309 | ||
2310 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2311 | { | |
2312 | int i; | |
2313 | /* Need to check if this struct/union is "integer" like. For | |
2314 | this to be true, its size must be less than or equal to | |
2315 | REGISTER_SIZE and the offset of each addressable subfield | |
2316 | must be zero. Note that bit fields are not addressable, and | |
2317 | unions always start at offset zero. If any of the subfields | |
2318 | is a floating point type, the struct/union cannot be an | |
2319 | integer type. */ | |
2320 | ||
2321 | /* For each field in the object, check: | |
2322 | 1) Is it FP? --> yes, nRc = 1; | |
2323 | 2) Is it addressable (bitpos != 0) and | |
2324 | not packed (bitsize == 0)? | |
2325 | --> yes, nRc = 1 | |
2326 | */ | |
2327 | ||
2328 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2329 | { | |
2330 | enum type_code field_type_code; | |
2331 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2332 | ||
2333 | /* Is it a floating point type field? */ | |
2334 | if (field_type_code == TYPE_CODE_FLT) | |
2335 | { | |
2336 | nRc = 1; | |
2337 | break; | |
2338 | } | |
2339 | ||
2340 | /* If bitpos != 0, then we have to care about it. */ | |
2341 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2342 | { | |
2343 | /* Bitfields are not addressable. If the field bitsize is | |
2344 | zero, then the field is not packed. Hence it cannot be | |
2345 | a bitfield or any other packed type. */ | |
2346 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2347 | { | |
2348 | nRc = 1; | |
2349 | break; | |
2350 | } | |
2351 | } | |
2352 | } | |
2353 | } | |
2354 | ||
2355 | return nRc; | |
2356 | } | |
2357 | ||
34e8f22d RE |
2358 | /* Write into appropriate registers a function return value of type |
2359 | TYPE, given in virtual format. */ | |
2360 | ||
2361 | static void | |
2362 | arm_store_return_value (struct type *type, char *valbuf) | |
2363 | { | |
2364 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2365 | { | |
08216dd7 | 2366 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7bbcf283 | 2367 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2368 | |
08216dd7 RE |
2369 | switch (tdep->fp_model) |
2370 | { | |
2371 | case ARM_FLOAT_FPA: | |
2372 | ||
2373 | convert_to_extended (valbuf, buf); | |
73937e03 AC |
2374 | deprecated_write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM), buf, |
2375 | FP_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2376 | break; |
2377 | ||
2378 | case ARM_FLOAT_SOFT: | |
2379 | case ARM_FLOAT_SOFT_VFP: | |
73937e03 AC |
2380 | deprecated_write_register_bytes (ARM_A1_REGNUM, valbuf, |
2381 | TYPE_LENGTH (type)); | |
08216dd7 RE |
2382 | break; |
2383 | ||
2384 | default: | |
2385 | internal_error | |
2386 | (__FILE__, __LINE__, | |
2387 | "arm_store_return_value: Floating point model not supported"); | |
2388 | break; | |
2389 | } | |
34e8f22d RE |
2390 | } |
2391 | else | |
73937e03 AC |
2392 | deprecated_write_register_bytes (ARM_A1_REGNUM, valbuf, |
2393 | TYPE_LENGTH (type)); | |
34e8f22d RE |
2394 | } |
2395 | ||
2396 | /* Store the address of the place in which to copy the structure the | |
94c30b78 | 2397 | subroutine will return. This is called from call_function. */ |
34e8f22d RE |
2398 | |
2399 | static void | |
2400 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2401 | { | |
2402 | write_register (ARM_A1_REGNUM, addr); | |
ed9a39eb JM |
2403 | } |
2404 | ||
9df628e0 RE |
2405 | static int |
2406 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2407 | { | |
2408 | CORE_ADDR jb_addr; | |
2409 | char buf[INT_REGISTER_RAW_SIZE]; | |
2410 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2411 | ||
2412 | jb_addr = read_register (ARM_A1_REGNUM); | |
2413 | ||
2414 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2415 | INT_REGISTER_RAW_SIZE)) | |
2416 | return 0; | |
2417 | ||
2418 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); | |
2419 | return 1; | |
2420 | } | |
2421 | ||
ed9a39eb | 2422 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2423 | |
2424 | int | |
ed9a39eb | 2425 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2426 | { |
2427 | CORE_ADDR start_addr; | |
2428 | ||
ed9a39eb JM |
2429 | /* Find the starting address of the function containing the PC. If |
2430 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2431 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2432 | &start_addr, NULL)) | |
c906108c SS |
2433 | return 0; |
2434 | ||
2435 | return strncmp (name, "_call_via_r", 11) == 0; | |
2436 | } | |
2437 | ||
ed9a39eb JM |
2438 | /* If PC is in a Thumb call or return stub, return the address of the |
2439 | target PC, which is in a register. The thunk functions are called | |
2440 | _called_via_xx, where x is the register name. The possible names | |
2441 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2442 | |
2443 | CORE_ADDR | |
ed9a39eb | 2444 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2445 | { |
c5aa993b | 2446 | char *name; |
c906108c SS |
2447 | CORE_ADDR start_addr; |
2448 | ||
2449 | /* Find the starting address and name of the function containing the PC. */ | |
2450 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2451 | return 0; | |
2452 | ||
2453 | /* Call thunks always start with "_call_via_". */ | |
2454 | if (strncmp (name, "_call_via_", 10) == 0) | |
2455 | { | |
ed9a39eb JM |
2456 | /* Use the name suffix to determine which register contains the |
2457 | target PC. */ | |
c5aa993b JM |
2458 | static char *table[15] = |
2459 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2460 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2461 | }; | |
c906108c SS |
2462 | int regno; |
2463 | ||
2464 | for (regno = 0; regno <= 14; regno++) | |
2465 | if (strcmp (&name[10], table[regno]) == 0) | |
2466 | return read_register (regno); | |
2467 | } | |
ed9a39eb | 2468 | |
c5aa993b | 2469 | return 0; /* not a stub */ |
c906108c SS |
2470 | } |
2471 | ||
da3c6d4a MS |
2472 | /* If the user changes the register disassembly flavor used for info |
2473 | register and other commands, we have to also switch the flavor used | |
2474 | in opcodes for disassembly output. This function is run in the set | |
94c30b78 | 2475 | disassembly_flavor command, and does that. */ |
bc90b915 FN |
2476 | |
2477 | static void | |
2478 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2479 | struct cmd_list_element *c) | |
2480 | { | |
2481 | set_disassembly_flavor (); | |
2482 | } | |
2483 | \f | |
966fbf70 | 2484 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2485 | static const char * |
34e8f22d | 2486 | arm_register_name (int i) |
966fbf70 RE |
2487 | { |
2488 | return arm_register_names[i]; | |
2489 | } | |
2490 | ||
bc90b915 FN |
2491 | static void |
2492 | set_disassembly_flavor (void) | |
2493 | { | |
2494 | const char *setname, *setdesc, **regnames; | |
2495 | int numregs, j; | |
2496 | ||
94c30b78 | 2497 | /* Find the flavor that the user wants in the opcodes table. */ |
bc90b915 FN |
2498 | int current = 0; |
2499 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2500 | while ((disassembly_flavor != setname) | |
2501 | && (current < num_flavor_options)) | |
2502 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2503 | current_option = current; | |
2504 | ||
94c30b78 | 2505 | /* Fill our copy. */ |
bc90b915 FN |
2506 | for (j = 0; j < numregs; j++) |
2507 | arm_register_names[j] = (char *) regnames[j]; | |
2508 | ||
94c30b78 | 2509 | /* Adjust case. */ |
34e8f22d | 2510 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2511 | { |
34e8f22d RE |
2512 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2513 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2514 | } |
2515 | else | |
2516 | { | |
34e8f22d RE |
2517 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2518 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2519 | } |
2520 | ||
94c30b78 | 2521 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2522 | set_arm_regname_option (current); |
2523 | } | |
2524 | ||
2525 | /* arm_othernames implements the "othernames" command. This is kind | |
2526 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2527 | also used for the x86 gdb. I will keep this around, however, in | |
94c30b78 | 2528 | case anyone is actually using it. */ |
bc90b915 FN |
2529 | |
2530 | static void | |
2531 | arm_othernames (char *names, int n) | |
2532 | { | |
94c30b78 | 2533 | /* Circle through the various flavors. */ |
bc90b915 FN |
2534 | current_option = (current_option + 1) % num_flavor_options; |
2535 | ||
2536 | disassembly_flavor = valid_flavors[current_option]; | |
94c30b78 | 2537 | set_disassembly_flavor (); |
bc90b915 FN |
2538 | } |
2539 | ||
a42dd537 KB |
2540 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2541 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2542 | Note, however, that link.h is not actually referred to in this file. | |
2543 | Instead, the relevant structs offsets were obtained from examining | |
2544 | link.h. (We can't refer to link.h from this file because the host | |
2545 | system won't necessarily have it, or if it does, the structs which | |
94c30b78 | 2546 | it defines will refer to the host system, not the target). */ |
a42dd537 KB |
2547 | |
2548 | struct link_map_offsets * | |
2549 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2550 | { | |
2551 | static struct link_map_offsets lmo; | |
2552 | static struct link_map_offsets *lmp = 0; | |
2553 | ||
2554 | if (lmp == 0) | |
2555 | { | |
2556 | lmp = &lmo; | |
2557 | ||
2558 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
94c30b78 | 2559 | need. */ |
a42dd537 KB |
2560 | |
2561 | lmo.r_map_offset = 4; | |
2562 | lmo.r_map_size = 4; | |
2563 | ||
2564 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
94c30b78 | 2565 | need. */ |
a42dd537 KB |
2566 | |
2567 | lmo.l_addr_offset = 0; | |
2568 | lmo.l_addr_size = 4; | |
2569 | ||
2570 | lmo.l_name_offset = 4; | |
2571 | lmo.l_name_size = 4; | |
2572 | ||
2573 | lmo.l_next_offset = 12; | |
2574 | lmo.l_next_size = 4; | |
2575 | ||
2576 | lmo.l_prev_offset = 16; | |
2577 | lmo.l_prev_size = 4; | |
2578 | } | |
2579 | ||
2580 | return lmp; | |
2581 | } | |
2582 | ||
082fc60d RE |
2583 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2584 | function. */ | |
2585 | ||
2586 | static int | |
2587 | coff_sym_is_thumb (int val) | |
2588 | { | |
2589 | return (val == C_THUMBEXT || | |
2590 | val == C_THUMBSTAT || | |
2591 | val == C_THUMBEXTFUNC || | |
2592 | val == C_THUMBSTATFUNC || | |
2593 | val == C_THUMBLABEL); | |
2594 | } | |
2595 | ||
2596 | /* arm_coff_make_msymbol_special() | |
2597 | arm_elf_make_msymbol_special() | |
2598 | ||
2599 | These functions test whether the COFF or ELF symbol corresponds to | |
2600 | an address in thumb code, and set a "special" bit in a minimal | |
2601 | symbol to indicate that it does. */ | |
2602 | ||
34e8f22d | 2603 | static void |
082fc60d RE |
2604 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2605 | { | |
2606 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2607 | STT_ARM_TFUNC). */ | |
2608 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2609 | == STT_LOPROC) | |
2610 | MSYMBOL_SET_SPECIAL (msym); | |
2611 | } | |
2612 | ||
34e8f22d | 2613 | static void |
082fc60d RE |
2614 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2615 | { | |
2616 | if (coff_sym_is_thumb (val)) | |
2617 | MSYMBOL_SET_SPECIAL (msym); | |
2618 | } | |
2619 | ||
97e03143 | 2620 | \f |
70f80edf JT |
2621 | static enum gdb_osabi |
2622 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2623 | { |
70f80edf JT |
2624 | unsigned int elfosabi, eflags; |
2625 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2626 | |
70f80edf | 2627 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2628 | |
70f80edf | 2629 | switch (elfosabi) |
97e03143 | 2630 | { |
70f80edf JT |
2631 | case ELFOSABI_NONE: |
2632 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2633 | file are conforming to the base specification for that machine | |
2634 | (there are no OS-specific extensions). In order to determine the | |
2635 | real OS in use we must look for OS notes that have been added. */ | |
2636 | bfd_map_over_sections (abfd, | |
2637 | generic_elf_osabi_sniff_abi_tag_sections, | |
2638 | &osabi); | |
2639 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2640 | { |
70f80edf JT |
2641 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2642 | field for more information. */ | |
2643 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2644 | switch (eflags) | |
97e03143 | 2645 | { |
70f80edf JT |
2646 | case EF_ARM_EABI_VER1: |
2647 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2648 | break; |
2649 | ||
70f80edf JT |
2650 | case EF_ARM_EABI_VER2: |
2651 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2652 | break; |
2653 | ||
70f80edf JT |
2654 | case EF_ARM_EABI_UNKNOWN: |
2655 | /* Assume GNU tools. */ | |
2656 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2657 | break; |
2658 | ||
70f80edf JT |
2659 | default: |
2660 | internal_error (__FILE__, __LINE__, | |
2661 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2662 | "version 0x%x", eflags); | |
97e03143 RE |
2663 | } |
2664 | } | |
70f80edf | 2665 | break; |
97e03143 | 2666 | |
70f80edf JT |
2667 | case ELFOSABI_ARM: |
2668 | /* GNU tools use this value. Check note sections in this case, | |
2669 | as well. */ | |
97e03143 | 2670 | bfd_map_over_sections (abfd, |
70f80edf JT |
2671 | generic_elf_osabi_sniff_abi_tag_sections, |
2672 | &osabi); | |
2673 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2674 | { |
70f80edf JT |
2675 | /* Assume APCS ABI. */ |
2676 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2677 | } |
2678 | break; | |
2679 | ||
97e03143 | 2680 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2681 | osabi = GDB_OSABI_FREEBSD_ELF; |
2682 | break; | |
97e03143 | 2683 | |
70f80edf JT |
2684 | case ELFOSABI_NETBSD: |
2685 | osabi = GDB_OSABI_NETBSD_ELF; | |
2686 | break; | |
97e03143 | 2687 | |
70f80edf JT |
2688 | case ELFOSABI_LINUX: |
2689 | osabi = GDB_OSABI_LINUX; | |
2690 | break; | |
97e03143 RE |
2691 | } |
2692 | ||
70f80edf | 2693 | return osabi; |
97e03143 RE |
2694 | } |
2695 | ||
70f80edf | 2696 | \f |
da3c6d4a MS |
2697 | /* Initialize the current architecture based on INFO. If possible, |
2698 | re-use an architecture from ARCHES, which is a list of | |
2699 | architectures already created during this debugging session. | |
97e03143 | 2700 | |
da3c6d4a MS |
2701 | Called e.g. at program startup, when reading a core file, and when |
2702 | reading a binary file. */ | |
97e03143 | 2703 | |
39bbf761 RE |
2704 | static struct gdbarch * |
2705 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2706 | { | |
97e03143 | 2707 | struct gdbarch_tdep *tdep; |
39bbf761 | 2708 | struct gdbarch *gdbarch; |
70f80edf | 2709 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
39bbf761 | 2710 | |
97e03143 | 2711 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2712 | |
97e03143 RE |
2713 | if (info.abfd != NULL) |
2714 | { | |
70f80edf JT |
2715 | osabi = gdbarch_lookup_osabi (info.abfd); |
2716 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2717 | { |
70f80edf JT |
2718 | switch (bfd_get_flavour (info.abfd)) |
2719 | { | |
2720 | case bfd_target_aout_flavour: | |
2721 | /* Assume it's an old APCS-style ABI. */ | |
2722 | osabi = GDB_OSABI_ARM_APCS; | |
2723 | break; | |
97e03143 | 2724 | |
70f80edf JT |
2725 | case bfd_target_coff_flavour: |
2726 | /* Assume it's an old APCS-style ABI. */ | |
2727 | /* XXX WinCE? */ | |
2728 | osabi = GDB_OSABI_ARM_APCS; | |
2729 | break; | |
97e03143 | 2730 | |
70f80edf JT |
2731 | default: |
2732 | /* Leave it as "unknown". */ | |
2733 | } | |
97e03143 RE |
2734 | } |
2735 | } | |
2736 | ||
d7afb4c9 | 2737 | /* Find a candidate among extant architectures. */ |
97e03143 RE |
2738 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2739 | arches != NULL; | |
2740 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2741 | { | |
2742 | /* Make sure the ABI selection matches. */ | |
2743 | tdep = gdbarch_tdep (arches->gdbarch); | |
70f80edf | 2744 | if (tdep && tdep->osabi == osabi) |
97e03143 RE |
2745 | return arches->gdbarch; |
2746 | } | |
2747 | ||
2748 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2749 | gdbarch = gdbarch_alloc (&info, tdep); | |
2750 | ||
70f80edf | 2751 | tdep->osabi = osabi; |
39bbf761 | 2752 | |
08216dd7 RE |
2753 | /* This is the way it has always defaulted. */ |
2754 | tdep->fp_model = ARM_FLOAT_FPA; | |
2755 | ||
2756 | /* Breakpoints. */ | |
67255d04 RE |
2757 | switch (info.byte_order) |
2758 | { | |
2759 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2760 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2761 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2762 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2763 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2764 | ||
67255d04 RE |
2765 | break; |
2766 | ||
2767 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2768 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2769 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2770 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2771 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2772 | ||
67255d04 RE |
2773 | break; |
2774 | ||
2775 | default: | |
2776 | internal_error (__FILE__, __LINE__, | |
2777 | "arm_gdbarch_init: bad byte order for float format"); | |
2778 | } | |
2779 | ||
d7b486e7 RE |
2780 | /* On ARM targets char defaults to unsigned. */ |
2781 | set_gdbarch_char_signed (gdbarch, 0); | |
2782 | ||
9df628e0 | 2783 | /* This should be low enough for everything. */ |
97e03143 | 2784 | tdep->lowest_pc = 0x20; |
94c30b78 | 2785 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2786 | |
848cfffb AC |
2787 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
2788 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2789 | ||
2790 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
2791 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2792 | ||
2793 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); | |
2794 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
2795 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
2796 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
2797 | ||
2798 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
848cfffb AC |
2799 | |
2800 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
2801 | set_gdbarch_push_return_address (gdbarch, arm_push_return_address); | |
39bbf761 | 2802 | |
39bbf761 | 2803 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); |
d7afb4c9 RE |
2804 | set_gdbarch_coerce_float_to_double (gdbarch, |
2805 | standard_coerce_float_to_double); | |
39bbf761 | 2806 | |
148754e5 | 2807 | /* Frame handling. */ |
39bbf761 | 2808 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
148754e5 RE |
2809 | set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
2810 | set_gdbarch_read_fp (gdbarch, arm_read_fp); | |
2811 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); | |
2812 | set_gdbarch_frameless_function_invocation | |
2813 | (gdbarch, arm_frameless_function_invocation); | |
2814 | set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc); | |
2815 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); | |
2816 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); | |
2817 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); | |
2818 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2819 | set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); | |
848cfffb | 2820 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); |
148754e5 RE |
2821 | set_gdbarch_pop_frame (gdbarch, arm_pop_frame); |
2822 | ||
34e8f22d RE |
2823 | /* Address manipulation. */ |
2824 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2825 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2826 | ||
2827 | /* Offset from address of function to start of its code. */ | |
2828 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2829 | ||
2830 | /* Advance PC across function entry code. */ | |
2831 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2832 | ||
2833 | /* Get the PC when a frame might not be available. */ | |
2834 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); | |
2835 | ||
2836 | /* The stack grows downward. */ | |
2837 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2838 | ||
2839 | /* Breakpoint manipulation. */ | |
2840 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2841 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2842 | ||
2843 | /* Information about registers, etc. */ | |
2844 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
94c30b78 | 2845 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2846 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2847 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
2848 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
2849 | set_gdbarch_register_bytes (gdbarch, | |
2850 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2851 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2852 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
2853 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); | |
2854 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
2855 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
2856 | set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); | |
2857 | set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
2858 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); | |
2859 | ||
26216b98 AC |
2860 | /* Internal <-> external register number maps. */ |
2861 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2862 | ||
34e8f22d RE |
2863 | /* Integer registers are 4 bytes. */ |
2864 | set_gdbarch_register_size (gdbarch, 4); | |
2865 | set_gdbarch_register_name (gdbarch, arm_register_name); | |
2866 | ||
2867 | /* Returning results. */ | |
26e9b323 | 2868 | set_gdbarch_deprecated_extract_return_value (gdbarch, arm_extract_return_value); |
ebba8386 | 2869 | set_gdbarch_deprecated_store_return_value (gdbarch, arm_store_return_value); |
34e8f22d | 2870 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); |
67255d04 | 2871 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
95f95911 | 2872 | set_gdbarch_extract_struct_value_address (gdbarch, |
67255d04 | 2873 | arm_extract_struct_value_address); |
34e8f22d RE |
2874 | |
2875 | /* Single stepping. */ | |
2876 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2877 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2878 | ||
2879 | /* Minsymbol frobbing. */ | |
2880 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2881 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2882 | arm_coff_make_msymbol_special); | |
2883 | ||
97e03143 | 2884 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
70f80edf | 2885 | gdbarch_init_osabi (info, gdbarch, osabi); |
97e03143 RE |
2886 | |
2887 | /* Now we have tuned the configuration, set a few final things, | |
2888 | based on what the OS ABI has told us. */ | |
2889 | ||
9df628e0 RE |
2890 | if (tdep->jb_pc >= 0) |
2891 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2892 | ||
08216dd7 RE |
2893 | /* Floating point sizes and format. */ |
2894 | switch (info.byte_order) | |
2895 | { | |
2896 | case BFD_ENDIAN_BIG: | |
2897 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2898 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2899 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2900 | ||
2901 | break; | |
2902 | ||
2903 | case BFD_ENDIAN_LITTLE: | |
2904 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
2905 | if (tdep->fp_model == ARM_FLOAT_VFP | |
2906 | || tdep->fp_model == ARM_FLOAT_SOFT_VFP) | |
2907 | { | |
2908 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2909 | set_gdbarch_long_double_format (gdbarch, | |
2910 | &floatformat_ieee_double_little); | |
2911 | } | |
2912 | else | |
2913 | { | |
2914 | set_gdbarch_double_format | |
2915 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2916 | set_gdbarch_long_double_format | |
2917 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2918 | } | |
2919 | break; | |
2920 | ||
2921 | default: | |
2922 | internal_error (__FILE__, __LINE__, | |
2923 | "arm_gdbarch_init: bad byte order for float format"); | |
2924 | } | |
2925 | ||
97e03143 | 2926 | /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still |
34e8f22d RE |
2927 | references the old architecture vector, not the one we are |
2928 | building here. */ | |
2929 | if (prologue_cache.saved_regs != NULL) | |
2930 | xfree (prologue_cache.saved_regs); | |
2931 | ||
a0abec03 AC |
2932 | /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still |
2933 | references the old architecture vector, not the one we are | |
2934 | building here. */ | |
34e8f22d RE |
2935 | prologue_cache.saved_regs = (CORE_ADDR *) |
2936 | xcalloc (1, (sizeof (CORE_ADDR) | |
29673b29 AC |
2937 | * (gdbarch_num_regs (gdbarch) |
2938 | + gdbarch_num_pseudo_regs (gdbarch)))); | |
39bbf761 RE |
2939 | |
2940 | return gdbarch; | |
2941 | } | |
2942 | ||
97e03143 RE |
2943 | static void |
2944 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2945 | { | |
2946 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2947 | ||
2948 | if (tdep == NULL) | |
2949 | return; | |
2950 | ||
70f80edf JT |
2951 | fprintf_unfiltered (file, "arm_dump_tdep: OS ABI = %s\n", |
2952 | gdbarch_osabi_name (tdep->osabi)); | |
97e03143 RE |
2953 | |
2954 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", | |
2955 | (unsigned long) tdep->lowest_pc); | |
2956 | } | |
2957 | ||
2958 | static void | |
2959 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2960 | struct gdbarch *gdbarch) | |
2961 | { | |
2962 | /* Place-holder. */ | |
2963 | } | |
2964 | ||
2965 | static void | |
2966 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
2967 | struct gdbarch *gdbarch) | |
2968 | { | |
2969 | /* Place-holder. */ | |
2970 | } | |
2971 | ||
2972 | static void | |
2973 | arm_init_abi_apcs (struct gdbarch_info info, | |
2974 | struct gdbarch *gdbarch) | |
2975 | { | |
2976 | /* Place-holder. */ | |
2977 | } | |
2978 | ||
c906108c | 2979 | void |
ed9a39eb | 2980 | _initialize_arm_tdep (void) |
c906108c | 2981 | { |
bc90b915 FN |
2982 | struct ui_file *stb; |
2983 | long length; | |
96baa820 | 2984 | struct cmd_list_element *new_cmd; |
53904c9e AC |
2985 | const char *setname; |
2986 | const char *setdesc; | |
2987 | const char **regnames; | |
bc90b915 FN |
2988 | int numregs, i, j; |
2989 | static char *helptext; | |
085dd6e6 | 2990 | |
39bbf761 | 2991 | if (GDB_MULTI_ARCH) |
97e03143 RE |
2992 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
2993 | ||
70f80edf JT |
2994 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
2995 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
2996 | bfd_target_elf_flavour, | |
2997 | arm_elf_osabi_sniffer); | |
2998 | ||
97e03143 | 2999 | /* Register some ABI variants for embedded systems. */ |
70f80edf JT |
3000 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V1, |
3001 | arm_init_abi_eabi_v1); | |
3002 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V2, | |
3003 | arm_init_abi_eabi_v2); | |
3004 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_APCS, | |
3005 | arm_init_abi_apcs); | |
39bbf761 | 3006 | |
c906108c | 3007 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 3008 | |
94c30b78 | 3009 | /* Get the number of possible sets of register names defined in opcodes. */ |
bc90b915 FN |
3010 | num_flavor_options = get_arm_regname_num_options (); |
3011 | ||
94c30b78 | 3012 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3013 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3014 | |
94c30b78 | 3015 | /* Begin creating the help text. */ |
bc90b915 FN |
3016 | stb = mem_fileopen (); |
3017 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
3018 | The valid values are:\n"); | |
ed9a39eb | 3019 | |
94c30b78 | 3020 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
bc90b915 FN |
3021 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); |
3022 | for (i = 0; i < num_flavor_options; i++) | |
3023 | { | |
3024 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 3025 | valid_flavors[i] = setname; |
bc90b915 FN |
3026 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3027 | setdesc); | |
94c30b78 | 3028 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3029 | if (!strcmp (setname, "std")) |
3030 | { | |
53904c9e | 3031 | disassembly_flavor = setname; |
bc90b915 FN |
3032 | current_option = i; |
3033 | for (j = 0; j < numregs; j++) | |
3034 | arm_register_names[j] = (char *) regnames[j]; | |
3035 | set_arm_regname_option (i); | |
3036 | } | |
3037 | } | |
94c30b78 | 3038 | /* Mark the end of valid options. */ |
bc90b915 | 3039 | valid_flavors[num_flavor_options] = NULL; |
c906108c | 3040 | |
94c30b78 | 3041 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3042 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3043 | helptext = ui_file_xstrdup (stb, &length); | |
3044 | ui_file_delete (stb); | |
ed9a39eb | 3045 | |
94c30b78 | 3046 | /* Add the disassembly-flavor command. */ |
96baa820 | 3047 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 3048 | valid_flavors, |
1ed2a135 | 3049 | &disassembly_flavor, |
bc90b915 | 3050 | helptext, |
ed9a39eb | 3051 | &setlist); |
9f60d481 | 3052 | set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc); |
ed9a39eb JM |
3053 | add_show_from_set (new_cmd, &showlist); |
3054 | ||
c906108c SS |
3055 | /* ??? Maybe this should be a boolean. */ |
3056 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 3057 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 3058 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 3059 | &showlist); |
c906108c | 3060 | |
94c30b78 | 3061 | /* Add the deprecated "othernames" command. */ |
bc90b915 FN |
3062 | |
3063 | add_com ("othernames", class_obscure, arm_othernames, | |
3064 | "Switch to the next set of register names."); | |
c3b4394c RE |
3065 | |
3066 | /* Fill in the prologue_cache fields. */ | |
34e8f22d | 3067 | prologue_cache.saved_regs = NULL; |
c3b4394c RE |
3068 | prologue_cache.extra_info = (struct frame_extra_info *) |
3069 | xcalloc (1, sizeof (struct frame_extra_info)); | |
6529d2dd AC |
3070 | |
3071 | /* Debugging flag. */ | |
3072 | add_show_from_set (add_set_cmd ("arm", class_maintenance, var_zinteger, | |
3073 | &arm_debug, "Set arm debugging.\n\ | |
3074 | When non-zero, arm specific debugging is enabled.", &setdebuglist), | |
3075 | &showdebuglist); | |
c906108c | 3076 | } |