Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. | |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
c906108c | 22 | |
34e8f22d RE |
23 | #include <ctype.h> /* XXX for isupper () */ |
24 | ||
c906108c SS |
25 | #include "defs.h" |
26 | #include "frame.h" | |
27 | #include "inferior.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
c906108c | 30 | #include "gdb_string.h" |
afd7eef0 | 31 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
4be87837 | 36 | #include "osabi.h" |
eb5492fa DJ |
37 | #include "frame-unwind.h" |
38 | #include "frame-base.h" | |
39 | #include "trad-frame.h" | |
842e1f1e DJ |
40 | #include "objfiles.h" |
41 | #include "dwarf2-frame.h" | |
e4c16157 | 42 | #include "gdbtypes.h" |
29d73ae4 | 43 | #include "prologue-value.h" |
123dc839 DJ |
44 | #include "target-descriptions.h" |
45 | #include "user-regs.h" | |
34e8f22d RE |
46 | |
47 | #include "arm-tdep.h" | |
26216b98 | 48 | #include "gdb/sim-arm.h" |
34e8f22d | 49 | |
082fc60d RE |
50 | #include "elf-bfd.h" |
51 | #include "coff/internal.h" | |
97e03143 | 52 | #include "elf/arm.h" |
c906108c | 53 | |
26216b98 AC |
54 | #include "gdb_assert.h" |
55 | ||
6529d2dd AC |
56 | static int arm_debug; |
57 | ||
082fc60d RE |
58 | /* Macros for setting and testing a bit in a minimal symbol that marks |
59 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 60 | is used for this purpose. |
082fc60d RE |
61 | |
62 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 63 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
64 | |
65 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
66 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
67 | | 0x80000000) | |
68 | ||
69 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
70 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
71 | ||
afd7eef0 RE |
72 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
73 | static struct cmd_list_element *setarmcmdlist = NULL; | |
74 | static struct cmd_list_element *showarmcmdlist = NULL; | |
75 | ||
fd50bc42 RE |
76 | /* The type of floating-point to use. Keep this in sync with enum |
77 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
78 | static const char *fp_model_strings[] = | |
79 | { | |
80 | "auto", | |
81 | "softfpa", | |
82 | "fpa", | |
83 | "softvfp", | |
28e97307 DJ |
84 | "vfp", |
85 | NULL | |
fd50bc42 RE |
86 | }; |
87 | ||
88 | /* A variable that can be configured by the user. */ | |
89 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
90 | static const char *current_fp_model = "auto"; | |
91 | ||
28e97307 DJ |
92 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
93 | static const char *arm_abi_strings[] = | |
94 | { | |
95 | "auto", | |
96 | "APCS", | |
97 | "AAPCS", | |
98 | NULL | |
99 | }; | |
100 | ||
101 | /* A variable that can be configured by the user. */ | |
102 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
103 | static const char *arm_abi_string = "auto"; | |
104 | ||
94c30b78 | 105 | /* Number of different reg name sets (options). */ |
afd7eef0 | 106 | static int num_disassembly_options; |
bc90b915 | 107 | |
123dc839 DJ |
108 | /* The standard register names, and all the valid aliases for them. */ |
109 | static const struct | |
110 | { | |
111 | const char *name; | |
112 | int regnum; | |
113 | } arm_register_aliases[] = { | |
114 | /* Basic register numbers. */ | |
115 | { "r0", 0 }, | |
116 | { "r1", 1 }, | |
117 | { "r2", 2 }, | |
118 | { "r3", 3 }, | |
119 | { "r4", 4 }, | |
120 | { "r5", 5 }, | |
121 | { "r6", 6 }, | |
122 | { "r7", 7 }, | |
123 | { "r8", 8 }, | |
124 | { "r9", 9 }, | |
125 | { "r10", 10 }, | |
126 | { "r11", 11 }, | |
127 | { "r12", 12 }, | |
128 | { "r13", 13 }, | |
129 | { "r14", 14 }, | |
130 | { "r15", 15 }, | |
131 | /* Synonyms (argument and variable registers). */ | |
132 | { "a1", 0 }, | |
133 | { "a2", 1 }, | |
134 | { "a3", 2 }, | |
135 | { "a4", 3 }, | |
136 | { "v1", 4 }, | |
137 | { "v2", 5 }, | |
138 | { "v3", 6 }, | |
139 | { "v4", 7 }, | |
140 | { "v5", 8 }, | |
141 | { "v6", 9 }, | |
142 | { "v7", 10 }, | |
143 | { "v8", 11 }, | |
144 | /* Other platform-specific names for r9. */ | |
145 | { "sb", 9 }, | |
146 | { "tr", 9 }, | |
147 | /* Special names. */ | |
148 | { "ip", 12 }, | |
149 | { "sp", 13 }, | |
150 | { "lr", 14 }, | |
151 | { "pc", 15 }, | |
152 | /* Names used by GCC (not listed in the ARM EABI). */ | |
153 | { "sl", 10 }, | |
154 | { "fp", 11 }, | |
155 | /* A special name from the older ATPCS. */ | |
156 | { "wr", 7 }, | |
157 | }; | |
bc90b915 | 158 | |
123dc839 | 159 | static const char *const arm_register_names[] = |
da59e081 JM |
160 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
161 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
162 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
163 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
164 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
165 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 166 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 167 | |
afd7eef0 RE |
168 | /* Valid register name styles. */ |
169 | static const char **valid_disassembly_styles; | |
ed9a39eb | 170 | |
afd7eef0 RE |
171 | /* Disassembly style to use. Default to "std" register names. */ |
172 | static const char *disassembly_style; | |
96baa820 | 173 | |
ed9a39eb | 174 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
175 | style. */ |
176 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 177 | struct cmd_list_element *); |
afd7eef0 | 178 | static void set_disassembly_style (void); |
ed9a39eb | 179 | |
b508a996 RE |
180 | static void convert_from_extended (const struct floatformat *, const void *, |
181 | void *); | |
182 | static void convert_to_extended (const struct floatformat *, void *, | |
183 | const void *); | |
ed9a39eb | 184 | |
9b8d791a | 185 | struct arm_prologue_cache |
c3b4394c | 186 | { |
eb5492fa DJ |
187 | /* The stack pointer at the time this frame was created; i.e. the |
188 | caller's stack pointer when this function was called. It is used | |
189 | to identify this frame. */ | |
190 | CORE_ADDR prev_sp; | |
191 | ||
192 | /* The frame base for this frame is just prev_sp + frame offset - | |
193 | frame size. FRAMESIZE is the size of this stack frame, and | |
194 | FRAMEOFFSET if the initial offset from the stack pointer (this | |
195 | frame's stack pointer, not PREV_SP) to the frame base. */ | |
196 | ||
c3b4394c RE |
197 | int framesize; |
198 | int frameoffset; | |
eb5492fa DJ |
199 | |
200 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 201 | int framereg; |
eb5492fa DJ |
202 | |
203 | /* Saved register offsets. */ | |
204 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 205 | }; |
ed9a39eb | 206 | |
bc90b915 FN |
207 | /* Addresses for calling Thumb functions have the bit 0 set. |
208 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
209 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
210 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
211 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
212 | ||
94c30b78 | 213 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
214 | |
215 | int arm_apcs_32 = 1; | |
216 | ||
ed9a39eb JM |
217 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
218 | function. */ | |
c906108c | 219 | |
34e8f22d | 220 | int |
2a451106 | 221 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 222 | { |
c5aa993b | 223 | struct minimal_symbol *sym; |
c906108c | 224 | |
ed9a39eb | 225 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
226 | if (IS_THUMB_ADDR (memaddr)) |
227 | return 1; | |
228 | ||
ed9a39eb | 229 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
230 | sym = lookup_minimal_symbol_by_pc (memaddr); |
231 | if (sym) | |
232 | { | |
c5aa993b | 233 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
234 | } |
235 | else | |
ed9a39eb JM |
236 | { |
237 | return 0; | |
238 | } | |
c906108c SS |
239 | } |
240 | ||
181c1381 | 241 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 242 | static CORE_ADDR |
ed9a39eb | 243 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 244 | { |
a3a2ee65 JT |
245 | if (arm_apcs_32) |
246 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 247 | else |
a3a2ee65 | 248 | return (val & 0x03fffffc); |
c906108c SS |
249 | } |
250 | ||
181c1381 RE |
251 | /* When reading symbols, we need to zap the low bit of the address, |
252 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 253 | static CORE_ADDR |
181c1381 RE |
254 | arm_smash_text_address (CORE_ADDR val) |
255 | { | |
256 | return val & ~1; | |
257 | } | |
258 | ||
29d73ae4 DJ |
259 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
260 | and frame pointer. Scan until we encounter a store that could | |
261 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
c906108c SS |
262 | |
263 | static CORE_ADDR | |
29d73ae4 DJ |
264 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
265 | CORE_ADDR start, CORE_ADDR limit, | |
266 | struct arm_prologue_cache *cache) | |
c906108c | 267 | { |
29d73ae4 DJ |
268 | int i; |
269 | pv_t regs[16]; | |
270 | struct pv_area *stack; | |
271 | struct cleanup *back_to; | |
272 | CORE_ADDR offset; | |
da3c6d4a | 273 | |
29d73ae4 DJ |
274 | for (i = 0; i < 16; i++) |
275 | regs[i] = pv_register (i, 0); | |
276 | stack = make_pv_area (ARM_SP_REGNUM); | |
277 | back_to = make_cleanup_free_pv_area (stack); | |
278 | ||
279 | /* The call instruction saved PC in LR, and the current PC is not | |
280 | interesting. Due to this file's conventions, we want the value | |
281 | of LR at this function's entry, not at the call site, so we do | |
282 | not record the save of the PC - when the ARM prologue analyzer | |
283 | has also been converted to the pv mechanism, we could record the | |
284 | save here and remove the hack in prev_register. */ | |
285 | regs[ARM_PC_REGNUM] = pv_unknown (); | |
286 | ||
287 | while (start < limit) | |
c906108c | 288 | { |
29d73ae4 DJ |
289 | unsigned short insn; |
290 | ||
291 | insn = read_memory_unsigned_integer (start, 2); | |
c906108c | 292 | |
94c30b78 | 293 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 294 | { |
29d73ae4 DJ |
295 | int regno; |
296 | int mask; | |
297 | int stop = 0; | |
298 | ||
299 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
300 | whether to save LR (R14). */ | |
301 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
302 | ||
303 | /* Calculate offsets of saved R0-R7 and LR. */ | |
304 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
305 | if (mask & (1 << regno)) | |
306 | { | |
307 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
308 | { | |
309 | stop = 1; | |
310 | break; | |
311 | } | |
312 | ||
313 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
314 | -4); | |
315 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
316 | } | |
317 | ||
318 | if (stop) | |
319 | break; | |
da59e081 | 320 | } |
da3c6d4a MS |
321 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
322 | sub sp, #simm */ | |
da59e081 | 323 | { |
29d73ae4 DJ |
324 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
325 | if (insn & 0x80) /* Check for SUB. */ | |
326 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
327 | -offset); | |
da59e081 | 328 | else |
29d73ae4 DJ |
329 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
330 | offset); | |
da59e081 JM |
331 | } |
332 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
29d73ae4 DJ |
333 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
334 | (insn & 0xff) << 2); | |
335 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ | |
da59e081 | 336 | { |
29d73ae4 DJ |
337 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
338 | int src_reg = (insn & 0x78) >> 3; | |
339 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 340 | } |
29d73ae4 | 341 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 342 | { |
29d73ae4 DJ |
343 | /* Handle stores to the stack. Normally pushes are used, |
344 | but with GCC -mtpcs-frame, there may be other stores | |
345 | in the prologue to create the frame. */ | |
346 | int regno = (insn >> 8) & 0x7; | |
347 | pv_t addr; | |
348 | ||
349 | offset = (insn & 0xff) << 2; | |
350 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
351 | ||
352 | if (pv_area_store_would_trash (stack, addr)) | |
353 | break; | |
354 | ||
355 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 356 | } |
29d73ae4 | 357 | else |
3d74b771 | 358 | { |
29d73ae4 DJ |
359 | /* We don't know what this instruction is. We're finished |
360 | scanning. NOTE: Recognizing more safe-to-ignore | |
361 | instructions here will improve support for optimized | |
362 | code. */ | |
da3c6d4a | 363 | break; |
3d74b771 | 364 | } |
29d73ae4 DJ |
365 | |
366 | start += 2; | |
c906108c SS |
367 | } |
368 | ||
29d73ae4 DJ |
369 | if (cache == NULL) |
370 | { | |
371 | do_cleanups (back_to); | |
372 | return start; | |
373 | } | |
374 | ||
375 | /* frameoffset is unused for this unwinder. */ | |
376 | cache->frameoffset = 0; | |
377 | ||
378 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
379 | { | |
380 | /* Frame pointer is fp. Frame size is constant. */ | |
381 | cache->framereg = ARM_FP_REGNUM; | |
382 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
383 | } | |
384 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
385 | { | |
386 | /* Frame pointer is r7. Frame size is constant. */ | |
387 | cache->framereg = THUMB_FP_REGNUM; | |
388 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
389 | } | |
390 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
391 | { | |
392 | /* Try the stack pointer... this is a bit desperate. */ | |
393 | cache->framereg = ARM_SP_REGNUM; | |
394 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
395 | } | |
396 | else | |
397 | { | |
398 | /* We're just out of luck. We don't know where the frame is. */ | |
399 | cache->framereg = -1; | |
400 | cache->framesize = 0; | |
401 | } | |
402 | ||
403 | for (i = 0; i < 16; i++) | |
404 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
405 | cache->saved_regs[i].addr = offset; | |
406 | ||
407 | do_cleanups (back_to); | |
408 | return start; | |
c906108c SS |
409 | } |
410 | ||
da3c6d4a MS |
411 | /* Advance the PC across any function entry prologue instructions to |
412 | reach some "real" code. | |
34e8f22d RE |
413 | |
414 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 415 | prologue: |
c906108c | 416 | |
c5aa993b JM |
417 | mov ip, sp |
418 | [stmfd sp!, {a1,a2,a3,a4}] | |
419 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
420 | [stfe f7, [sp, #-12]!] |
421 | [stfe f6, [sp, #-12]!] | |
422 | [stfe f5, [sp, #-12]!] | |
423 | [stfe f4, [sp, #-12]!] | |
424 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 425 | |
34e8f22d | 426 | static CORE_ADDR |
ed9a39eb | 427 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
428 | { |
429 | unsigned long inst; | |
430 | CORE_ADDR skip_pc; | |
b8d5e71d | 431 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 432 | char *func_name; |
c906108c SS |
433 | struct symtab_and_line sal; |
434 | ||
848cfffb | 435 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 436 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
437 | return pc; |
438 | ||
96baa820 | 439 | /* See what the symbol table says. */ |
ed9a39eb | 440 | |
50f6fb4b | 441 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 442 | { |
50f6fb4b CV |
443 | struct symbol *sym; |
444 | ||
445 | /* Found a function. */ | |
176620f1 | 446 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
447 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
448 | { | |
94c30b78 | 449 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
450 | sal = find_pc_line (func_addr, 0); |
451 | if ((sal.line != 0) && (sal.end < func_end)) | |
452 | return sal.end; | |
453 | } | |
c906108c SS |
454 | } |
455 | ||
c906108c | 456 | /* Can't find the prologue end in the symbol table, try it the hard way |
94c30b78 | 457 | by disassembling the instructions. */ |
c906108c | 458 | |
b8d5e71d MS |
459 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
460 | if (func_end == 0 || func_end > pc + 64) | |
461 | func_end = pc + 64; | |
c906108c | 462 | |
29d73ae4 DJ |
463 | /* Check if this is Thumb code. */ |
464 | if (arm_pc_is_thumb (pc)) | |
465 | return thumb_analyze_prologue (current_gdbarch, pc, func_end, NULL); | |
466 | ||
b8d5e71d | 467 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 468 | { |
1c5bada0 | 469 | inst = read_memory_unsigned_integer (skip_pc, 4); |
f43845b3 | 470 | |
b8d5e71d MS |
471 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
472 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
473 | continue; | |
c906108c | 474 | |
28cd8767 JG |
475 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
476 | continue; | |
477 | ||
478 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
479 | continue; | |
480 | ||
b8d5e71d MS |
481 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
482 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
483 | continue; | |
c906108c | 484 | |
b8d5e71d MS |
485 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
486 | continue; | |
c906108c | 487 | |
b8d5e71d MS |
488 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
489 | continue; | |
11d3b27d | 490 | |
b8d5e71d MS |
491 | /* Any insns after this point may float into the code, if it makes |
492 | for better instruction scheduling, so we skip them only if we | |
493 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 494 | |
b8d5e71d MS |
495 | /* We may have either one sfmfd instruction here, or several stfe |
496 | insns, depending on the version of floating point code we | |
497 | support. */ | |
498 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
499 | continue; | |
500 | ||
501 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
502 | continue; | |
503 | ||
504 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
505 | continue; | |
506 | ||
507 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
508 | continue; | |
509 | ||
510 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
511 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
512 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
513 | continue; | |
514 | ||
515 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
516 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
517 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
518 | continue; | |
519 | ||
520 | /* Un-recognized instruction; stop scanning. */ | |
521 | break; | |
f43845b3 | 522 | } |
c906108c | 523 | |
b8d5e71d | 524 | return skip_pc; /* End of prologue */ |
c906108c | 525 | } |
94c30b78 | 526 | |
c5aa993b | 527 | /* *INDENT-OFF* */ |
c906108c SS |
528 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
529 | This function decodes a Thumb function prologue to determine: | |
530 | 1) the size of the stack frame | |
531 | 2) which registers are saved on it | |
532 | 3) the offsets of saved regs | |
533 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 534 | |
da59e081 JM |
535 | A typical Thumb function prologue would create this stack frame |
536 | (offsets relative to FP) | |
c906108c SS |
537 | old SP -> 24 stack parameters |
538 | 20 LR | |
539 | 16 R7 | |
540 | R7 -> 0 local variables (16 bytes) | |
541 | SP -> -12 additional stack space (12 bytes) | |
542 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
543 | 12 bytes. The frame register is R7. |
544 | ||
da3c6d4a MS |
545 | The comments for thumb_skip_prolog() describe the algorithm we use |
546 | to detect the end of the prolog. */ | |
c5aa993b JM |
547 | /* *INDENT-ON* */ |
548 | ||
c906108c | 549 | static void |
eb5492fa | 550 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
c906108c SS |
551 | { |
552 | CORE_ADDR prologue_start; | |
553 | CORE_ADDR prologue_end; | |
554 | CORE_ADDR current_pc; | |
94c30b78 | 555 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
556 | int saved_reg[16]; |
557 | /* findmask: | |
558 | bit 0 - push { rlist } | |
559 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
560 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
561 | */ | |
562 | int findmask = 0; | |
c5aa993b | 563 | int i; |
c906108c | 564 | |
eb5492fa | 565 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
566 | { |
567 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
568 | ||
94c30b78 | 569 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 570 | prologue_end = prev_pc; |
c906108c | 571 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 572 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
573 | } |
574 | else | |
f7060f85 DJ |
575 | /* We're in the boondocks: we have no idea where the start of the |
576 | function is. */ | |
577 | return; | |
c906108c | 578 | |
eb5492fa | 579 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 580 | |
29d73ae4 DJ |
581 | thumb_analyze_prologue (current_gdbarch, prologue_start, prologue_end, |
582 | cache); | |
c906108c SS |
583 | } |
584 | ||
ed9a39eb | 585 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
586 | 1) the size of the stack frame |
587 | 2) which registers are saved on it | |
588 | 3) the offsets of saved regs | |
589 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
590 | This information is stored in the "extra" fields of the frame_info. |
591 | ||
96baa820 JM |
592 | There are two basic forms for the ARM prologue. The fixed argument |
593 | function call will look like: | |
ed9a39eb JM |
594 | |
595 | mov ip, sp | |
596 | stmfd sp!, {fp, ip, lr, pc} | |
597 | sub fp, ip, #4 | |
598 | [sub sp, sp, #4] | |
96baa820 | 599 | |
c906108c | 600 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
601 | IP -> 4 (caller's stack) |
602 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
603 | -4 LR (return address in caller) | |
604 | -8 IP (copy of caller's SP) | |
605 | -12 FP (caller's FP) | |
606 | SP -> -28 Local variables | |
607 | ||
c906108c | 608 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
609 | 28 bytes. The stmfd call can also save any of the vN registers it |
610 | plans to use, which increases the frame size accordingly. | |
611 | ||
612 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
613 | because the ARM Store instructions always store PC + 8 when you read | |
614 | the PC register. | |
ed9a39eb | 615 | |
96baa820 JM |
616 | A variable argument function call will look like: |
617 | ||
ed9a39eb JM |
618 | mov ip, sp |
619 | stmfd sp!, {a1, a2, a3, a4} | |
620 | stmfd sp!, {fp, ip, lr, pc} | |
621 | sub fp, ip, #20 | |
622 | ||
96baa820 | 623 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
624 | IP -> 20 (caller's stack) |
625 | 16 A4 | |
626 | 12 A3 | |
627 | 8 A2 | |
628 | 4 A1 | |
629 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
630 | -4 LR (return address in caller) | |
631 | -8 IP (copy of caller's SP) | |
632 | -12 FP (caller's FP) | |
633 | SP -> -28 Local variables | |
96baa820 JM |
634 | |
635 | The frame size would thus be 48 bytes, and the frame offset would be | |
636 | 28 bytes. | |
637 | ||
638 | There is another potential complication, which is that the optimizer | |
639 | will try to separate the store of fp in the "stmfd" instruction from | |
640 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
641 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
642 | ||
643 | Also, note, the original version of the ARM toolchain claimed that there | |
644 | should be an | |
645 | ||
646 | instruction at the end of the prologue. I have never seen GCC produce | |
647 | this, and the ARM docs don't mention it. We still test for it below in | |
648 | case it happens... | |
ed9a39eb JM |
649 | |
650 | */ | |
c906108c SS |
651 | |
652 | static void | |
eb5492fa | 653 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
c906108c | 654 | { |
28cd8767 | 655 | int regno, sp_offset, fp_offset, ip_offset; |
c906108c | 656 | CORE_ADDR prologue_start, prologue_end, current_pc; |
eb5492fa | 657 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
c906108c | 658 | |
c906108c | 659 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
660 | cache->framereg = ARM_SP_REGNUM; |
661 | cache->framesize = 0; | |
662 | cache->frameoffset = 0; | |
c906108c SS |
663 | |
664 | /* Check for Thumb prologue. */ | |
eb5492fa | 665 | if (arm_pc_is_thumb (prev_pc)) |
c906108c | 666 | { |
eb5492fa | 667 | thumb_scan_prologue (prev_pc, cache); |
c906108c SS |
668 | return; |
669 | } | |
670 | ||
671 | /* Find the function prologue. If we can't find the function in | |
672 | the symbol table, peek in the stack frame to find the PC. */ | |
eb5492fa | 673 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
c906108c | 674 | { |
2a451106 KB |
675 | /* One way to find the end of the prologue (which works well |
676 | for unoptimized code) is to do the following: | |
677 | ||
678 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
679 | ||
680 | if (sal.line == 0) | |
eb5492fa | 681 | prologue_end = prev_pc; |
2a451106 KB |
682 | else if (sal.end < prologue_end) |
683 | prologue_end = sal.end; | |
684 | ||
685 | This mechanism is very accurate so long as the optimizer | |
686 | doesn't move any instructions from the function body into the | |
687 | prologue. If this happens, sal.end will be the last | |
688 | instruction in the first hunk of prologue code just before | |
689 | the first instruction that the scheduler has moved from | |
690 | the body to the prologue. | |
691 | ||
692 | In order to make sure that we scan all of the prologue | |
693 | instructions, we use a slightly less accurate mechanism which | |
694 | may scan more than necessary. To help compensate for this | |
695 | lack of accuracy, the prologue scanning loop below contains | |
696 | several clauses which'll cause the loop to terminate early if | |
697 | an implausible prologue instruction is encountered. | |
698 | ||
699 | The expression | |
700 | ||
701 | prologue_start + 64 | |
702 | ||
703 | is a suitable endpoint since it accounts for the largest | |
704 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 705 | the scheduler. */ |
2a451106 KB |
706 | |
707 | if (prologue_end > prologue_start + 64) | |
708 | { | |
94c30b78 | 709 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 710 | } |
c906108c SS |
711 | } |
712 | else | |
713 | { | |
eb5492fa DJ |
714 | /* We have no symbol information. Our only option is to assume this |
715 | function has a standard stack frame and the normal frame register. | |
716 | Then, we can find the value of our frame pointer on entrance to | |
717 | the callee (or at the present moment if this is the innermost frame). | |
718 | The value stored there should be the address of the stmfd + 8. */ | |
719 | CORE_ADDR frame_loc; | |
720 | LONGEST return_value; | |
721 | ||
722 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); | |
723 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) | |
16a0f3e7 EZ |
724 | return; |
725 | else | |
726 | { | |
727 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 728 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 729 | } |
c906108c SS |
730 | } |
731 | ||
eb5492fa DJ |
732 | if (prev_pc < prologue_end) |
733 | prologue_end = prev_pc; | |
734 | ||
c906108c | 735 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 736 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 737 | |
96baa820 JM |
738 | Be careful, however, and if it doesn't look like a prologue, |
739 | don't try to scan it. If, for instance, a frameless function | |
740 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 741 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
742 | and other operations that rely on a knowledge of the stack |
743 | traceback. | |
744 | ||
745 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 746 | if we don't see this as the first insn, we will stop. |
c906108c | 747 | |
f43845b3 MS |
748 | [Note: This doesn't seem to be true any longer, so it's now an |
749 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 750 | |
f43845b3 MS |
751 | [Note further: The "mov ip,sp" only seems to be missing in |
752 | frameless functions at optimization level "-O2" or above, | |
753 | in which case it is often (but not always) replaced by | |
b8d5e71d | 754 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 755 | |
28cd8767 | 756 | sp_offset = fp_offset = ip_offset = 0; |
f43845b3 | 757 | |
94c30b78 MS |
758 | for (current_pc = prologue_start; |
759 | current_pc < prologue_end; | |
f43845b3 | 760 | current_pc += 4) |
96baa820 | 761 | { |
d4473757 KB |
762 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
763 | ||
94c30b78 | 764 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 765 | { |
28cd8767 JG |
766 | ip_offset = 0; |
767 | continue; | |
768 | } | |
769 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
770 | { | |
771 | unsigned imm = insn & 0xff; /* immediate value */ | |
772 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
773 | imm = (imm >> rot) | (imm << (32 - rot)); | |
774 | ip_offset = imm; | |
775 | continue; | |
776 | } | |
777 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
778 | { | |
779 | unsigned imm = insn & 0xff; /* immediate value */ | |
780 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
781 | imm = (imm >> rot) | (imm << (32 - rot)); | |
782 | ip_offset = -imm; | |
f43845b3 MS |
783 | continue; |
784 | } | |
94c30b78 | 785 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 786 | { |
e28a332c JG |
787 | sp_offset -= 4; |
788 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; | |
f43845b3 MS |
789 | continue; |
790 | } | |
791 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
792 | /* stmfd sp!, {..., fp, ip, lr, pc} |
793 | or | |
794 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 795 | { |
d4473757 | 796 | int mask = insn & 0xffff; |
ed9a39eb | 797 | |
94c30b78 | 798 | /* Calculate offsets of saved registers. */ |
34e8f22d | 799 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
800 | if (mask & (1 << regno)) |
801 | { | |
802 | sp_offset -= 4; | |
eb5492fa | 803 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 KB |
804 | } |
805 | } | |
b8d5e71d MS |
806 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
807 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
808 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
809 | { | |
810 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
811 | continue; | |
812 | } | |
813 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
814 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
815 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
816 | { |
817 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
818 | continue; | |
819 | } | |
d4473757 KB |
820 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
821 | { | |
94c30b78 MS |
822 | unsigned imm = insn & 0xff; /* immediate value */ |
823 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 824 | imm = (imm >> rot) | (imm << (32 - rot)); |
28cd8767 | 825 | fp_offset = -imm + ip_offset; |
9b8d791a | 826 | cache->framereg = ARM_FP_REGNUM; |
d4473757 KB |
827 | } |
828 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
829 | { | |
94c30b78 MS |
830 | unsigned imm = insn & 0xff; /* immediate value */ |
831 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
832 | imm = (imm >> rot) | (imm << (32 - rot)); |
833 | sp_offset -= imm; | |
834 | } | |
ff6f572f DJ |
835 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
836 | && gdbarch_tdep (current_gdbarch)->have_fpa_registers) | |
d4473757 KB |
837 | { |
838 | sp_offset -= 12; | |
34e8f22d | 839 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
eb5492fa | 840 | cache->saved_regs[regno].addr = sp_offset; |
d4473757 | 841 | } |
ff6f572f DJ |
842 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
843 | && gdbarch_tdep (current_gdbarch)->have_fpa_registers) | |
d4473757 KB |
844 | { |
845 | int n_saved_fp_regs; | |
846 | unsigned int fp_start_reg, fp_bound_reg; | |
847 | ||
94c30b78 | 848 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 849 | { |
d4473757 KB |
850 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
851 | n_saved_fp_regs = 3; | |
852 | else | |
853 | n_saved_fp_regs = 1; | |
96baa820 | 854 | } |
d4473757 | 855 | else |
96baa820 | 856 | { |
d4473757 KB |
857 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
858 | n_saved_fp_regs = 2; | |
859 | else | |
860 | n_saved_fp_regs = 4; | |
96baa820 | 861 | } |
d4473757 | 862 | |
34e8f22d | 863 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
864 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
865 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
866 | { |
867 | sp_offset -= 12; | |
eb5492fa | 868 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
96baa820 | 869 | } |
c906108c | 870 | } |
d4473757 | 871 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 872 | break; /* Condition not true, exit early */ |
b8d5e71d | 873 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 874 | break; /* Don't scan past a block load */ |
d4473757 KB |
875 | else |
876 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 877 | so we just skip what we don't recognize. */ |
d4473757 | 878 | continue; |
c906108c SS |
879 | } |
880 | ||
94c30b78 MS |
881 | /* The frame size is just the negative of the offset (from the |
882 | original SP) of the last thing thing we pushed on the stack. | |
883 | The frame offset is [new FP] - [new SP]. */ | |
9b8d791a DJ |
884 | cache->framesize = -sp_offset; |
885 | if (cache->framereg == ARM_FP_REGNUM) | |
886 | cache->frameoffset = fp_offset - sp_offset; | |
d4473757 | 887 | else |
9b8d791a | 888 | cache->frameoffset = 0; |
c906108c SS |
889 | } |
890 | ||
eb5492fa DJ |
891 | static struct arm_prologue_cache * |
892 | arm_make_prologue_cache (struct frame_info *next_frame) | |
c906108c | 893 | { |
eb5492fa DJ |
894 | int reg; |
895 | struct arm_prologue_cache *cache; | |
896 | CORE_ADDR unwound_fp; | |
c5aa993b | 897 | |
35d5d4ee | 898 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
eb5492fa | 899 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
c906108c | 900 | |
eb5492fa | 901 | arm_scan_prologue (next_frame, cache); |
848cfffb | 902 | |
eb5492fa DJ |
903 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
904 | if (unwound_fp == 0) | |
905 | return cache; | |
c906108c | 906 | |
eb5492fa | 907 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
c906108c | 908 | |
eb5492fa DJ |
909 | /* Calculate actual addresses of saved registers using offsets |
910 | determined by arm_scan_prologue. */ | |
911 | for (reg = 0; reg < NUM_REGS; reg++) | |
e28a332c | 912 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
913 | cache->saved_regs[reg].addr += cache->prev_sp; |
914 | ||
915 | return cache; | |
c906108c SS |
916 | } |
917 | ||
eb5492fa DJ |
918 | /* Our frame ID for a normal frame is the current function's starting PC |
919 | and the caller's SP when we were called. */ | |
c906108c | 920 | |
148754e5 | 921 | static void |
eb5492fa DJ |
922 | arm_prologue_this_id (struct frame_info *next_frame, |
923 | void **this_cache, | |
924 | struct frame_id *this_id) | |
c906108c | 925 | { |
eb5492fa DJ |
926 | struct arm_prologue_cache *cache; |
927 | struct frame_id id; | |
928 | CORE_ADDR func; | |
f079148d | 929 | |
eb5492fa DJ |
930 | if (*this_cache == NULL) |
931 | *this_cache = arm_make_prologue_cache (next_frame); | |
932 | cache = *this_cache; | |
2a451106 | 933 | |
eb5492fa | 934 | func = frame_func_unwind (next_frame); |
2a451106 | 935 | |
eb5492fa DJ |
936 | /* This is meant to halt the backtrace at "_start". Make sure we |
937 | don't halt it at a generic dummy frame. */ | |
9e815ec2 | 938 | if (func <= LOWEST_PC) |
eb5492fa | 939 | return; |
5a203e44 | 940 | |
eb5492fa DJ |
941 | /* If we've hit a wall, stop. */ |
942 | if (cache->prev_sp == 0) | |
943 | return; | |
24de872b | 944 | |
eb5492fa | 945 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 946 | *this_id = id; |
c906108c SS |
947 | } |
948 | ||
eb5492fa DJ |
949 | static void |
950 | arm_prologue_prev_register (struct frame_info *next_frame, | |
951 | void **this_cache, | |
952 | int prev_regnum, | |
953 | int *optimized, | |
954 | enum lval_type *lvalp, | |
955 | CORE_ADDR *addrp, | |
956 | int *realnump, | |
9af75ef6 | 957 | gdb_byte *valuep) |
24de872b DJ |
958 | { |
959 | struct arm_prologue_cache *cache; | |
960 | ||
eb5492fa DJ |
961 | if (*this_cache == NULL) |
962 | *this_cache = arm_make_prologue_cache (next_frame); | |
963 | cache = *this_cache; | |
24de872b | 964 | |
eb5492fa DJ |
965 | /* If we are asked to unwind the PC, then we need to return the LR |
966 | instead. The saved value of PC points into this frame's | |
967 | prologue, not the next frame's resume location. */ | |
968 | if (prev_regnum == ARM_PC_REGNUM) | |
969 | prev_regnum = ARM_LR_REGNUM; | |
24de872b | 970 | |
eb5492fa DJ |
971 | /* SP is generally not saved to the stack, but this frame is |
972 | identified by NEXT_FRAME's stack pointer at the time of the call. | |
973 | The value was already reconstructed into PREV_SP. */ | |
974 | if (prev_regnum == ARM_SP_REGNUM) | |
975 | { | |
976 | *lvalp = not_lval; | |
977 | if (valuep) | |
978 | store_unsigned_integer (valuep, 4, cache->prev_sp); | |
979 | return; | |
980 | } | |
981 | ||
1f67027d AC |
982 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
983 | optimized, lvalp, addrp, realnump, valuep); | |
eb5492fa DJ |
984 | } |
985 | ||
986 | struct frame_unwind arm_prologue_unwind = { | |
987 | NORMAL_FRAME, | |
988 | arm_prologue_this_id, | |
989 | arm_prologue_prev_register | |
990 | }; | |
991 | ||
992 | static const struct frame_unwind * | |
993 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) | |
994 | { | |
995 | return &arm_prologue_unwind; | |
24de872b DJ |
996 | } |
997 | ||
909cf6ea DJ |
998 | static struct arm_prologue_cache * |
999 | arm_make_stub_cache (struct frame_info *next_frame) | |
1000 | { | |
1001 | int reg; | |
1002 | struct arm_prologue_cache *cache; | |
1003 | CORE_ADDR unwound_fp; | |
1004 | ||
35d5d4ee | 1005 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
909cf6ea DJ |
1006 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
1007 | ||
1008 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); | |
1009 | ||
1010 | return cache; | |
1011 | } | |
1012 | ||
1013 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1014 | ||
1015 | static void | |
1016 | arm_stub_this_id (struct frame_info *next_frame, | |
1017 | void **this_cache, | |
1018 | struct frame_id *this_id) | |
1019 | { | |
1020 | struct arm_prologue_cache *cache; | |
1021 | ||
1022 | if (*this_cache == NULL) | |
1023 | *this_cache = arm_make_stub_cache (next_frame); | |
1024 | cache = *this_cache; | |
1025 | ||
1026 | *this_id = frame_id_build (cache->prev_sp, | |
1027 | frame_pc_unwind (next_frame)); | |
1028 | } | |
1029 | ||
1030 | struct frame_unwind arm_stub_unwind = { | |
1031 | NORMAL_FRAME, | |
1032 | arm_stub_this_id, | |
1033 | arm_prologue_prev_register | |
1034 | }; | |
1035 | ||
1036 | static const struct frame_unwind * | |
1037 | arm_stub_unwind_sniffer (struct frame_info *next_frame) | |
1038 | { | |
1039 | char dummy[4]; | |
1040 | ||
1041 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) | |
1042 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
1043 | return &arm_stub_unwind; | |
1044 | ||
1045 | return NULL; | |
1046 | } | |
1047 | ||
24de872b | 1048 | static CORE_ADDR |
eb5492fa | 1049 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
24de872b DJ |
1050 | { |
1051 | struct arm_prologue_cache *cache; | |
1052 | ||
eb5492fa DJ |
1053 | if (*this_cache == NULL) |
1054 | *this_cache = arm_make_prologue_cache (next_frame); | |
1055 | cache = *this_cache; | |
1056 | ||
1057 | return cache->prev_sp + cache->frameoffset - cache->framesize; | |
24de872b DJ |
1058 | } |
1059 | ||
eb5492fa DJ |
1060 | struct frame_base arm_normal_base = { |
1061 | &arm_prologue_unwind, | |
1062 | arm_normal_frame_base, | |
1063 | arm_normal_frame_base, | |
1064 | arm_normal_frame_base | |
1065 | }; | |
1066 | ||
eb5492fa DJ |
1067 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1068 | dummy frame. The frame ID's base needs to match the TOS value | |
1069 | saved by save_dummy_frame_tos() and returned from | |
1070 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1071 | breakpoint. */ | |
c906108c | 1072 | |
eb5492fa DJ |
1073 | static struct frame_id |
1074 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
c906108c | 1075 | { |
eb5492fa DJ |
1076 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
1077 | frame_pc_unwind (next_frame)); | |
1078 | } | |
c3b4394c | 1079 | |
eb5492fa DJ |
1080 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1081 | be used to construct the previous frame's ID, after looking up the | |
1082 | containing function). */ | |
c3b4394c | 1083 | |
eb5492fa DJ |
1084 | static CORE_ADDR |
1085 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1086 | { | |
1087 | CORE_ADDR pc; | |
1088 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
59ea4f70 | 1089 | return arm_addr_bits_remove (pc); |
eb5492fa DJ |
1090 | } |
1091 | ||
1092 | static CORE_ADDR | |
1093 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1094 | { | |
1095 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1096 | } |
1097 | ||
2dd604e7 RE |
1098 | /* When arguments must be pushed onto the stack, they go on in reverse |
1099 | order. The code below implements a FILO (stack) to do this. */ | |
1100 | ||
1101 | struct stack_item | |
1102 | { | |
1103 | int len; | |
1104 | struct stack_item *prev; | |
1105 | void *data; | |
1106 | }; | |
1107 | ||
1108 | static struct stack_item * | |
1109 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1110 | { | |
1111 | struct stack_item *si; | |
1112 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1113 | si->data = xmalloc (len); |
2dd604e7 RE |
1114 | si->len = len; |
1115 | si->prev = prev; | |
1116 | memcpy (si->data, contents, len); | |
1117 | return si; | |
1118 | } | |
1119 | ||
1120 | static struct stack_item * | |
1121 | pop_stack_item (struct stack_item *si) | |
1122 | { | |
1123 | struct stack_item *dead = si; | |
1124 | si = si->prev; | |
1125 | xfree (dead->data); | |
1126 | xfree (dead); | |
1127 | return si; | |
1128 | } | |
1129 | ||
2af48f68 PB |
1130 | |
1131 | /* Return the alignment (in bytes) of the given type. */ | |
1132 | ||
1133 | static int | |
1134 | arm_type_align (struct type *t) | |
1135 | { | |
1136 | int n; | |
1137 | int align; | |
1138 | int falign; | |
1139 | ||
1140 | t = check_typedef (t); | |
1141 | switch (TYPE_CODE (t)) | |
1142 | { | |
1143 | default: | |
1144 | /* Should never happen. */ | |
1145 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1146 | return 4; | |
1147 | ||
1148 | case TYPE_CODE_PTR: | |
1149 | case TYPE_CODE_ENUM: | |
1150 | case TYPE_CODE_INT: | |
1151 | case TYPE_CODE_FLT: | |
1152 | case TYPE_CODE_SET: | |
1153 | case TYPE_CODE_RANGE: | |
1154 | case TYPE_CODE_BITSTRING: | |
1155 | case TYPE_CODE_REF: | |
1156 | case TYPE_CODE_CHAR: | |
1157 | case TYPE_CODE_BOOL: | |
1158 | return TYPE_LENGTH (t); | |
1159 | ||
1160 | case TYPE_CODE_ARRAY: | |
1161 | case TYPE_CODE_COMPLEX: | |
1162 | /* TODO: What about vector types? */ | |
1163 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1164 | ||
1165 | case TYPE_CODE_STRUCT: | |
1166 | case TYPE_CODE_UNION: | |
1167 | align = 1; | |
1168 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1169 | { | |
1170 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1171 | if (falign > align) | |
1172 | align = falign; | |
1173 | } | |
1174 | return align; | |
1175 | } | |
1176 | } | |
1177 | ||
2dd604e7 RE |
1178 | /* We currently only support passing parameters in integer registers. This |
1179 | conforms with GCC's default model. Several other variants exist and | |
1180 | we should probably support some of them based on the selected ABI. */ | |
1181 | ||
1182 | static CORE_ADDR | |
7d9b040b | 1183 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1184 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1185 | struct value **args, CORE_ADDR sp, int struct_return, | |
1186 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1187 | { |
1188 | int argnum; | |
1189 | int argreg; | |
1190 | int nstack; | |
1191 | struct stack_item *si = NULL; | |
1192 | ||
6a65450a AC |
1193 | /* Set the return address. For the ARM, the return breakpoint is |
1194 | always at BP_ADDR. */ | |
2dd604e7 | 1195 | /* XXX Fix for Thumb. */ |
6a65450a | 1196 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1197 | |
1198 | /* Walk through the list of args and determine how large a temporary | |
1199 | stack is required. Need to take care here as structs may be | |
1200 | passed on the stack, and we have to to push them. */ | |
1201 | nstack = 0; | |
1202 | ||
1203 | argreg = ARM_A1_REGNUM; | |
1204 | nstack = 0; | |
1205 | ||
2dd604e7 RE |
1206 | /* The struct_return pointer occupies the first parameter |
1207 | passing register. */ | |
1208 | if (struct_return) | |
1209 | { | |
1210 | if (arm_debug) | |
1211 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1212 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1213 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1214 | argreg++; | |
1215 | } | |
1216 | ||
1217 | for (argnum = 0; argnum < nargs; argnum++) | |
1218 | { | |
1219 | int len; | |
1220 | struct type *arg_type; | |
1221 | struct type *target_type; | |
1222 | enum type_code typecode; | |
0fd88904 | 1223 | bfd_byte *val; |
2af48f68 | 1224 | int align; |
2dd604e7 | 1225 | |
df407dfe | 1226 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1227 | len = TYPE_LENGTH (arg_type); |
1228 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1229 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1230 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1231 | |
2af48f68 PB |
1232 | align = arm_type_align (arg_type); |
1233 | /* Round alignment up to a whole number of words. */ | |
1234 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1235 | /* Different ABIs have different maximum alignments. */ | |
1236 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1237 | { | |
1238 | /* The APCS ABI only requires word alignment. */ | |
1239 | align = INT_REGISTER_SIZE; | |
1240 | } | |
1241 | else | |
1242 | { | |
1243 | /* The AAPCS requires at most doubleword alignment. */ | |
1244 | if (align > INT_REGISTER_SIZE * 2) | |
1245 | align = INT_REGISTER_SIZE * 2; | |
1246 | } | |
1247 | ||
1248 | /* Push stack padding for dowubleword alignment. */ | |
1249 | if (nstack & (align - 1)) | |
1250 | { | |
1251 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1252 | nstack += INT_REGISTER_SIZE; | |
1253 | } | |
1254 | ||
1255 | /* Doubleword aligned quantities must go in even register pairs. */ | |
1256 | if (argreg <= ARM_LAST_ARG_REGNUM | |
1257 | && align > INT_REGISTER_SIZE | |
1258 | && argreg & 1) | |
1259 | argreg++; | |
1260 | ||
2dd604e7 RE |
1261 | /* If the argument is a pointer to a function, and it is a |
1262 | Thumb function, create a LOCAL copy of the value and set | |
1263 | the THUMB bit in it. */ | |
1264 | if (TYPE_CODE_PTR == typecode | |
1265 | && target_type != NULL | |
1266 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1267 | { | |
7c0b4a20 | 1268 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1269 | if (arm_pc_is_thumb (regval)) |
1270 | { | |
1271 | val = alloca (len); | |
fbd9dcd3 | 1272 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1273 | } |
1274 | } | |
1275 | ||
1276 | /* Copy the argument to general registers or the stack in | |
1277 | register-sized pieces. Large arguments are split between | |
1278 | registers and stack. */ | |
1279 | while (len > 0) | |
1280 | { | |
b1e29e33 | 1281 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1282 | |
1283 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1284 | { | |
1285 | /* The argument is being passed in a general purpose | |
1286 | register. */ | |
7c0b4a20 | 1287 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1288 | if (arm_debug) |
1289 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1290 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1291 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1292 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1293 | argreg++; | |
1294 | } | |
1295 | else | |
1296 | { | |
1297 | /* Push the arguments onto the stack. */ | |
1298 | if (arm_debug) | |
1299 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1300 | argnum, nstack); | |
b1e29e33 AC |
1301 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1302 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1303 | } |
1304 | ||
1305 | len -= partial_len; | |
1306 | val += partial_len; | |
1307 | } | |
1308 | } | |
1309 | /* If we have an odd number of words to push, then decrement the stack | |
1310 | by one word now, so first stack argument will be dword aligned. */ | |
1311 | if (nstack & 4) | |
1312 | sp -= 4; | |
1313 | ||
1314 | while (si) | |
1315 | { | |
1316 | sp -= si->len; | |
1317 | write_memory (sp, si->data, si->len); | |
1318 | si = pop_stack_item (si); | |
1319 | } | |
1320 | ||
1321 | /* Finally, update teh SP register. */ | |
1322 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1323 | ||
1324 | return sp; | |
1325 | } | |
1326 | ||
f53f0d0b PB |
1327 | |
1328 | /* Always align the frame to an 8-byte boundary. This is required on | |
1329 | some platforms and harmless on the rest. */ | |
1330 | ||
1331 | static CORE_ADDR | |
1332 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1333 | { | |
1334 | /* Align the stack to eight bytes. */ | |
1335 | return sp & ~ (CORE_ADDR) 7; | |
1336 | } | |
1337 | ||
c906108c | 1338 | static void |
ed9a39eb | 1339 | print_fpu_flags (int flags) |
c906108c | 1340 | { |
c5aa993b JM |
1341 | if (flags & (1 << 0)) |
1342 | fputs ("IVO ", stdout); | |
1343 | if (flags & (1 << 1)) | |
1344 | fputs ("DVZ ", stdout); | |
1345 | if (flags & (1 << 2)) | |
1346 | fputs ("OFL ", stdout); | |
1347 | if (flags & (1 << 3)) | |
1348 | fputs ("UFL ", stdout); | |
1349 | if (flags & (1 << 4)) | |
1350 | fputs ("INX ", stdout); | |
1351 | putchar ('\n'); | |
c906108c SS |
1352 | } |
1353 | ||
5e74b15c RE |
1354 | /* Print interesting information about the floating point processor |
1355 | (if present) or emulator. */ | |
34e8f22d | 1356 | static void |
d855c300 | 1357 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1358 | struct frame_info *frame, const char *args) |
c906108c | 1359 | { |
52f0bd74 | 1360 | unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1361 | int type; |
1362 | ||
1363 | type = (status >> 24) & 127; | |
edefbb7c AC |
1364 | if (status & (1 << 31)) |
1365 | printf (_("Hardware FPU type %d\n"), type); | |
1366 | else | |
1367 | printf (_("Software FPU type %d\n"), type); | |
1368 | /* i18n: [floating point unit] mask */ | |
1369 | fputs (_("mask: "), stdout); | |
c5aa993b | 1370 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1371 | /* i18n: [floating point unit] flags */ |
1372 | fputs (_("flags: "), stdout); | |
c5aa993b | 1373 | print_fpu_flags (status); |
c906108c SS |
1374 | } |
1375 | ||
34e8f22d RE |
1376 | /* Return the GDB type object for the "standard" data type of data in |
1377 | register N. */ | |
1378 | ||
1379 | static struct type * | |
7a5ea0d4 | 1380 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1381 | { |
34e8f22d | 1382 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
8da61cc4 | 1383 | return builtin_type_arm_ext; |
e4c16157 DJ |
1384 | else if (regnum == ARM_SP_REGNUM) |
1385 | return builtin_type_void_data_ptr; | |
1386 | else if (regnum == ARM_PC_REGNUM) | |
1387 | return builtin_type_void_func_ptr; | |
ff6f572f DJ |
1388 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
1389 | /* These registers are only supported on targets which supply | |
1390 | an XML description. */ | |
1391 | return builtin_type_int0; | |
032758dc | 1392 | else |
e4c16157 | 1393 | return builtin_type_uint32; |
032758dc AC |
1394 | } |
1395 | ||
ff6f572f DJ |
1396 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
1397 | number. */ | |
1398 | ||
1399 | static int | |
1400 | arm_dwarf_reg_to_regnum (int reg) | |
1401 | { | |
1402 | /* Core integer regs. */ | |
1403 | if (reg >= 0 && reg <= 15) | |
1404 | return reg; | |
1405 | ||
1406 | /* Legacy FPA encoding. These were once used in a way which | |
1407 | overlapped with VFP register numbering, so their use is | |
1408 | discouraged, but GDB doesn't support the ARM toolchain | |
1409 | which used them for VFP. */ | |
1410 | if (reg >= 16 && reg <= 23) | |
1411 | return ARM_F0_REGNUM + reg - 16; | |
1412 | ||
1413 | /* New assignments for the FPA registers. */ | |
1414 | if (reg >= 96 && reg <= 103) | |
1415 | return ARM_F0_REGNUM + reg - 96; | |
1416 | ||
1417 | /* WMMX register assignments. */ | |
1418 | if (reg >= 104 && reg <= 111) | |
1419 | return ARM_WCGR0_REGNUM + reg - 104; | |
1420 | ||
1421 | if (reg >= 112 && reg <= 127) | |
1422 | return ARM_WR0_REGNUM + reg - 112; | |
1423 | ||
1424 | if (reg >= 192 && reg <= 199) | |
1425 | return ARM_WC0_REGNUM + reg - 192; | |
1426 | ||
1427 | return -1; | |
1428 | } | |
1429 | ||
26216b98 AC |
1430 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1431 | static int | |
1432 | arm_register_sim_regno (int regnum) | |
1433 | { | |
1434 | int reg = regnum; | |
1435 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1436 | ||
ff6f572f DJ |
1437 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
1438 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
1439 | ||
1440 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
1441 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
1442 | ||
1443 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
1444 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
1445 | ||
26216b98 AC |
1446 | if (reg < NUM_GREGS) |
1447 | return SIM_ARM_R0_REGNUM + reg; | |
1448 | reg -= NUM_GREGS; | |
1449 | ||
1450 | if (reg < NUM_FREGS) | |
1451 | return SIM_ARM_FP0_REGNUM + reg; | |
1452 | reg -= NUM_FREGS; | |
1453 | ||
1454 | if (reg < NUM_SREGS) | |
1455 | return SIM_ARM_FPS_REGNUM + reg; | |
1456 | reg -= NUM_SREGS; | |
1457 | ||
edefbb7c | 1458 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1459 | } |
34e8f22d | 1460 | |
a37b3cc0 AC |
1461 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1462 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1463 | It is thought that this is is the floating-point register format on | |
1464 | little-endian systems. */ | |
c906108c | 1465 | |
ed9a39eb | 1466 | static void |
b508a996 RE |
1467 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1468 | void *dbl) | |
c906108c | 1469 | { |
a37b3cc0 | 1470 | DOUBLEST d; |
d7449b42 | 1471 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1472 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1473 | else | |
1474 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1475 | ptr, &d); | |
b508a996 | 1476 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1477 | } |
1478 | ||
34e8f22d | 1479 | static void |
b508a996 | 1480 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1481 | { |
a37b3cc0 | 1482 | DOUBLEST d; |
b508a996 | 1483 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1484 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1485 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1486 | else | |
1487 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1488 | &d, dbl); | |
c906108c | 1489 | } |
ed9a39eb | 1490 | |
c906108c | 1491 | static int |
ed9a39eb | 1492 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1493 | { |
1494 | if (cond == INST_AL || cond == INST_NV) | |
1495 | return 1; | |
1496 | ||
1497 | switch (cond) | |
1498 | { | |
1499 | case INST_EQ: | |
1500 | return ((status_reg & FLAG_Z) != 0); | |
1501 | case INST_NE: | |
1502 | return ((status_reg & FLAG_Z) == 0); | |
1503 | case INST_CS: | |
1504 | return ((status_reg & FLAG_C) != 0); | |
1505 | case INST_CC: | |
1506 | return ((status_reg & FLAG_C) == 0); | |
1507 | case INST_MI: | |
1508 | return ((status_reg & FLAG_N) != 0); | |
1509 | case INST_PL: | |
1510 | return ((status_reg & FLAG_N) == 0); | |
1511 | case INST_VS: | |
1512 | return ((status_reg & FLAG_V) != 0); | |
1513 | case INST_VC: | |
1514 | return ((status_reg & FLAG_V) == 0); | |
1515 | case INST_HI: | |
1516 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1517 | case INST_LS: | |
1518 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1519 | case INST_GE: | |
1520 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1521 | case INST_LT: | |
1522 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1523 | case INST_GT: | |
1524 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1525 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1526 | case INST_LE: |
1527 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1528 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1529 | } |
1530 | return 1; | |
1531 | } | |
1532 | ||
9512d7fd | 1533 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1534 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1535 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1536 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1537 | #define sbits(obj,st,fn) \ | |
1538 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1539 | #define BranchDest(addr,instr) \ | |
1540 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1541 | #define ARM_PC_32 1 | |
1542 | ||
1543 | static unsigned long | |
ed9a39eb JM |
1544 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1545 | unsigned long status_reg) | |
c906108c SS |
1546 | { |
1547 | unsigned long res, shift; | |
1548 | int rm = bits (inst, 0, 3); | |
1549 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1550 | |
1551 | if (bit (inst, 4)) | |
c906108c SS |
1552 | { |
1553 | int rs = bits (inst, 8, 11); | |
1554 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1555 | } | |
1556 | else | |
1557 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1558 | |
1559 | res = (rm == 15 | |
c906108c | 1560 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1561 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1562 | : read_register (rm)); |
1563 | ||
1564 | switch (shifttype) | |
1565 | { | |
c5aa993b | 1566 | case 0: /* LSL */ |
c906108c SS |
1567 | res = shift >= 32 ? 0 : res << shift; |
1568 | break; | |
c5aa993b JM |
1569 | |
1570 | case 1: /* LSR */ | |
c906108c SS |
1571 | res = shift >= 32 ? 0 : res >> shift; |
1572 | break; | |
1573 | ||
c5aa993b JM |
1574 | case 2: /* ASR */ |
1575 | if (shift >= 32) | |
1576 | shift = 31; | |
c906108c SS |
1577 | res = ((res & 0x80000000L) |
1578 | ? ~((~res) >> shift) : res >> shift); | |
1579 | break; | |
1580 | ||
c5aa993b | 1581 | case 3: /* ROR/RRX */ |
c906108c SS |
1582 | shift &= 31; |
1583 | if (shift == 0) | |
1584 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1585 | else | |
c5aa993b | 1586 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1587 | break; |
1588 | } | |
1589 | ||
1590 | return res & 0xffffffff; | |
1591 | } | |
1592 | ||
c906108c SS |
1593 | /* Return number of 1-bits in VAL. */ |
1594 | ||
1595 | static int | |
ed9a39eb | 1596 | bitcount (unsigned long val) |
c906108c SS |
1597 | { |
1598 | int nbits; | |
1599 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1600 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1601 | return nbits; |
1602 | } | |
1603 | ||
34e8f22d | 1604 | CORE_ADDR |
ed9a39eb | 1605 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1606 | { |
c5aa993b | 1607 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
1c5bada0 | 1608 | unsigned short inst1 = read_memory_unsigned_integer (pc, 2); |
94c30b78 | 1609 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1610 | unsigned long offset; |
1611 | ||
1612 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1613 | { | |
1614 | CORE_ADDR sp; | |
1615 | ||
1616 | /* Fetch the saved PC from the stack. It's stored above | |
1617 | all of the other registers. */ | |
b1e29e33 | 1618 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1619 | sp = read_register (ARM_SP_REGNUM); |
1c5bada0 | 1620 | nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4); |
c906108c SS |
1621 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1622 | if (nextpc == pc) | |
edefbb7c | 1623 | error (_("Infinite loop detected")); |
c906108c SS |
1624 | } |
1625 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1626 | { | |
34e8f22d | 1627 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1628 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1629 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1630 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1631 | } | |
1632 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1633 | { | |
1634 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1635 | } | |
aa17d93e | 1636 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c | 1637 | { |
1c5bada0 | 1638 | unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2); |
c5aa993b | 1639 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1640 | nextpc = pc_val + offset; |
aa17d93e DJ |
1641 | /* For BLX make sure to clear the low bits. */ |
1642 | if (bits (inst2, 11, 12) == 1) | |
1643 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1644 | } |
aa17d93e | 1645 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1646 | { |
1647 | if (bits (inst1, 3, 6) == 0x0f) | |
1648 | nextpc = pc_val; | |
1649 | else | |
1650 | nextpc = read_register (bits (inst1, 3, 6)); | |
1651 | ||
1652 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1653 | if (nextpc == pc) | |
edefbb7c | 1654 | error (_("Infinite loop detected")); |
9498281f | 1655 | } |
c906108c SS |
1656 | |
1657 | return nextpc; | |
1658 | } | |
1659 | ||
34e8f22d | 1660 | CORE_ADDR |
ed9a39eb | 1661 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1662 | { |
1663 | unsigned long pc_val; | |
1664 | unsigned long this_instr; | |
1665 | unsigned long status; | |
1666 | CORE_ADDR nextpc; | |
1667 | ||
1668 | if (arm_pc_is_thumb (pc)) | |
1669 | return thumb_get_next_pc (pc); | |
1670 | ||
1671 | pc_val = (unsigned long) pc; | |
1c5bada0 | 1672 | this_instr = read_memory_unsigned_integer (pc, 4); |
34e8f22d | 1673 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1674 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1675 | |
1676 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1677 | { | |
1678 | switch (bits (this_instr, 24, 27)) | |
1679 | { | |
c5aa993b | 1680 | case 0x0: |
94c30b78 | 1681 | case 0x1: /* data processing */ |
c5aa993b JM |
1682 | case 0x2: |
1683 | case 0x3: | |
c906108c SS |
1684 | { |
1685 | unsigned long operand1, operand2, result = 0; | |
1686 | unsigned long rn; | |
1687 | int c; | |
c5aa993b | 1688 | |
c906108c SS |
1689 | if (bits (this_instr, 12, 15) != 15) |
1690 | break; | |
1691 | ||
1692 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1693 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1694 | error (_("Invalid update to pc in instruction")); |
c906108c | 1695 | |
9498281f | 1696 | /* BX <reg>, BLX <reg> */ |
e150acc7 PB |
1697 | if (bits (this_instr, 4, 27) == 0x12fff1 |
1698 | || bits (this_instr, 4, 27) == 0x12fff3) | |
9498281f DJ |
1699 | { |
1700 | rn = bits (this_instr, 0, 3); | |
1701 | result = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1702 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1703 | ||
1704 | if (nextpc == pc) | |
edefbb7c | 1705 | error (_("Infinite loop detected")); |
9498281f DJ |
1706 | |
1707 | return nextpc; | |
1708 | } | |
1709 | ||
c906108c SS |
1710 | /* Multiply into PC */ |
1711 | c = (status & FLAG_C) ? 1 : 0; | |
1712 | rn = bits (this_instr, 16, 19); | |
1713 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1714 | |
c906108c SS |
1715 | if (bit (this_instr, 25)) |
1716 | { | |
1717 | unsigned long immval = bits (this_instr, 0, 7); | |
1718 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1719 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1720 | & 0xffffffff; | |
c906108c | 1721 | } |
c5aa993b | 1722 | else /* operand 2 is a shifted register */ |
c906108c | 1723 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1724 | |
c906108c SS |
1725 | switch (bits (this_instr, 21, 24)) |
1726 | { | |
c5aa993b | 1727 | case 0x0: /*and */ |
c906108c SS |
1728 | result = operand1 & operand2; |
1729 | break; | |
1730 | ||
c5aa993b | 1731 | case 0x1: /*eor */ |
c906108c SS |
1732 | result = operand1 ^ operand2; |
1733 | break; | |
1734 | ||
c5aa993b | 1735 | case 0x2: /*sub */ |
c906108c SS |
1736 | result = operand1 - operand2; |
1737 | break; | |
1738 | ||
c5aa993b | 1739 | case 0x3: /*rsb */ |
c906108c SS |
1740 | result = operand2 - operand1; |
1741 | break; | |
1742 | ||
c5aa993b | 1743 | case 0x4: /*add */ |
c906108c SS |
1744 | result = operand1 + operand2; |
1745 | break; | |
1746 | ||
c5aa993b | 1747 | case 0x5: /*adc */ |
c906108c SS |
1748 | result = operand1 + operand2 + c; |
1749 | break; | |
1750 | ||
c5aa993b | 1751 | case 0x6: /*sbc */ |
c906108c SS |
1752 | result = operand1 - operand2 + c; |
1753 | break; | |
1754 | ||
c5aa993b | 1755 | case 0x7: /*rsc */ |
c906108c SS |
1756 | result = operand2 - operand1 + c; |
1757 | break; | |
1758 | ||
c5aa993b JM |
1759 | case 0x8: |
1760 | case 0x9: | |
1761 | case 0xa: | |
1762 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1763 | result = (unsigned long) nextpc; |
1764 | break; | |
1765 | ||
c5aa993b | 1766 | case 0xc: /*orr */ |
c906108c SS |
1767 | result = operand1 | operand2; |
1768 | break; | |
1769 | ||
c5aa993b | 1770 | case 0xd: /*mov */ |
c906108c SS |
1771 | /* Always step into a function. */ |
1772 | result = operand2; | |
c5aa993b | 1773 | break; |
c906108c | 1774 | |
c5aa993b | 1775 | case 0xe: /*bic */ |
c906108c SS |
1776 | result = operand1 & ~operand2; |
1777 | break; | |
1778 | ||
c5aa993b | 1779 | case 0xf: /*mvn */ |
c906108c SS |
1780 | result = ~operand2; |
1781 | break; | |
1782 | } | |
1783 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1784 | ||
1785 | if (nextpc == pc) | |
edefbb7c | 1786 | error (_("Infinite loop detected")); |
c906108c SS |
1787 | break; |
1788 | } | |
c5aa993b JM |
1789 | |
1790 | case 0x4: | |
1791 | case 0x5: /* data transfer */ | |
1792 | case 0x6: | |
1793 | case 0x7: | |
c906108c SS |
1794 | if (bit (this_instr, 20)) |
1795 | { | |
1796 | /* load */ | |
1797 | if (bits (this_instr, 12, 15) == 15) | |
1798 | { | |
1799 | /* rd == pc */ | |
c5aa993b | 1800 | unsigned long rn; |
c906108c | 1801 | unsigned long base; |
c5aa993b | 1802 | |
c906108c | 1803 | if (bit (this_instr, 22)) |
edefbb7c | 1804 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1805 | |
1806 | /* byte write to PC */ | |
1807 | rn = bits (this_instr, 16, 19); | |
1808 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1809 | if (bit (this_instr, 24)) | |
1810 | { | |
1811 | /* pre-indexed */ | |
1812 | int c = (status & FLAG_C) ? 1 : 0; | |
1813 | unsigned long offset = | |
c5aa993b | 1814 | (bit (this_instr, 25) |
ed9a39eb | 1815 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1816 | : bits (this_instr, 0, 11)); |
c906108c SS |
1817 | |
1818 | if (bit (this_instr, 23)) | |
1819 | base += offset; | |
1820 | else | |
1821 | base -= offset; | |
1822 | } | |
c5aa993b | 1823 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1824 | 4); |
c5aa993b | 1825 | |
c906108c SS |
1826 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1827 | ||
1828 | if (nextpc == pc) | |
edefbb7c | 1829 | error (_("Infinite loop detected")); |
c906108c SS |
1830 | } |
1831 | } | |
1832 | break; | |
c5aa993b JM |
1833 | |
1834 | case 0x8: | |
1835 | case 0x9: /* block transfer */ | |
c906108c SS |
1836 | if (bit (this_instr, 20)) |
1837 | { | |
1838 | /* LDM */ | |
1839 | if (bit (this_instr, 15)) | |
1840 | { | |
1841 | /* loading pc */ | |
1842 | int offset = 0; | |
1843 | ||
1844 | if (bit (this_instr, 23)) | |
1845 | { | |
1846 | /* up */ | |
1847 | unsigned long reglist = bits (this_instr, 0, 14); | |
1848 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1849 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1850 | offset += 4; |
1851 | } | |
1852 | else if (bit (this_instr, 24)) | |
1853 | offset = -4; | |
c5aa993b | 1854 | |
c906108c | 1855 | { |
c5aa993b JM |
1856 | unsigned long rn_val = |
1857 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1858 | nextpc = |
1859 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1860 | + offset), |
c906108c SS |
1861 | 4); |
1862 | } | |
1863 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1864 | if (nextpc == pc) | |
edefbb7c | 1865 | error (_("Infinite loop detected")); |
c906108c SS |
1866 | } |
1867 | } | |
1868 | break; | |
c5aa993b JM |
1869 | |
1870 | case 0xb: /* branch & link */ | |
1871 | case 0xa: /* branch */ | |
c906108c SS |
1872 | { |
1873 | nextpc = BranchDest (pc, this_instr); | |
1874 | ||
9498281f DJ |
1875 | /* BLX */ |
1876 | if (bits (this_instr, 28, 31) == INST_NV) | |
1877 | nextpc |= bit (this_instr, 24) << 1; | |
1878 | ||
c906108c SS |
1879 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1880 | if (nextpc == pc) | |
edefbb7c | 1881 | error (_("Infinite loop detected")); |
c906108c SS |
1882 | break; |
1883 | } | |
c5aa993b JM |
1884 | |
1885 | case 0xc: | |
1886 | case 0xd: | |
1887 | case 0xe: /* coproc ops */ | |
1888 | case 0xf: /* SWI */ | |
c906108c SS |
1889 | break; |
1890 | ||
1891 | default: | |
edefbb7c | 1892 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
1893 | return (pc); |
1894 | } | |
1895 | } | |
1896 | ||
1897 | return nextpc; | |
1898 | } | |
1899 | ||
9512d7fd FN |
1900 | /* single_step() is called just before we want to resume the inferior, |
1901 | if we want to single-step it but there is no hardware or kernel | |
1902 | single-step support. We find the target of the coming instruction | |
1903 | and breakpoint it. | |
1904 | ||
94c30b78 MS |
1905 | single_step() is also called just after the inferior stops. If we |
1906 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 1907 | |
34e8f22d RE |
1908 | static void |
1909 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 1910 | { |
8181d85f DJ |
1911 | /* NOTE: This may insert the wrong breakpoint instruction when |
1912 | single-stepping over a mode-changing instruction, if the | |
1913 | CPSR heuristics are used. */ | |
9512d7fd FN |
1914 | |
1915 | if (insert_bpt) | |
1916 | { | |
8181d85f DJ |
1917 | CORE_ADDR next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
1918 | ||
1919 | insert_single_step_breakpoint (next_pc); | |
9512d7fd FN |
1920 | } |
1921 | else | |
8181d85f | 1922 | remove_single_step_breakpoints (); |
9512d7fd | 1923 | } |
9512d7fd | 1924 | |
c906108c SS |
1925 | #include "bfd-in2.h" |
1926 | #include "libcoff.h" | |
1927 | ||
1928 | static int | |
ed9a39eb | 1929 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1930 | { |
1931 | if (arm_pc_is_thumb (memaddr)) | |
1932 | { | |
c5aa993b JM |
1933 | static asymbol *asym; |
1934 | static combined_entry_type ce; | |
1935 | static struct coff_symbol_struct csym; | |
27cddce2 | 1936 | static struct bfd fake_bfd; |
c5aa993b | 1937 | static bfd_target fake_target; |
c906108c SS |
1938 | |
1939 | if (csym.native == NULL) | |
1940 | { | |
da3c6d4a MS |
1941 | /* Create a fake symbol vector containing a Thumb symbol. |
1942 | This is solely so that the code in print_insn_little_arm() | |
1943 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
1944 | the presence of a Thumb symbol and switch to decoding | |
1945 | Thumb instructions. */ | |
c5aa993b JM |
1946 | |
1947 | fake_target.flavour = bfd_target_coff_flavour; | |
1948 | fake_bfd.xvec = &fake_target; | |
c906108c | 1949 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1950 | csym.native = &ce; |
1951 | csym.symbol.the_bfd = &fake_bfd; | |
1952 | csym.symbol.name = "fake"; | |
1953 | asym = (asymbol *) & csym; | |
c906108c | 1954 | } |
c5aa993b | 1955 | |
c906108c | 1956 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1957 | info->symbols = &asym; |
c906108c SS |
1958 | } |
1959 | else | |
1960 | info->symbols = NULL; | |
c5aa993b | 1961 | |
d7449b42 | 1962 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1963 | return print_insn_big_arm (memaddr, info); |
1964 | else | |
1965 | return print_insn_little_arm (memaddr, info); | |
1966 | } | |
1967 | ||
66e810cd RE |
1968 | /* The following define instruction sequences that will cause ARM |
1969 | cpu's to take an undefined instruction trap. These are used to | |
1970 | signal a breakpoint to GDB. | |
1971 | ||
1972 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
1973 | modes. A different instruction is required for each mode. The ARM | |
1974 | cpu's can also be big or little endian. Thus four different | |
1975 | instructions are needed to support all cases. | |
1976 | ||
1977 | Note: ARMv4 defines several new instructions that will take the | |
1978 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
1979 | not in fact add the new instructions. The new undefined | |
1980 | instructions in ARMv4 are all instructions that had no defined | |
1981 | behaviour in earlier chips. There is no guarantee that they will | |
1982 | raise an exception, but may be treated as NOP's. In practice, it | |
1983 | may only safe to rely on instructions matching: | |
1984 | ||
1985 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
1986 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
1987 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
1988 | ||
1989 | Even this may only true if the condition predicate is true. The | |
1990 | following use a condition predicate of ALWAYS so it is always TRUE. | |
1991 | ||
1992 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
1993 | and NetBSD all use a software interrupt rather than an undefined | |
1994 | instruction to force a trap. This can be handled by by the | |
1995 | abi-specific code during establishment of the gdbarch vector. */ | |
1996 | ||
1997 | ||
d7b486e7 RE |
1998 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
1999 | override these definitions. */ | |
66e810cd RE |
2000 | #ifndef ARM_LE_BREAKPOINT |
2001 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2002 | #endif | |
2003 | #ifndef ARM_BE_BREAKPOINT | |
2004 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2005 | #endif | |
2006 | #ifndef THUMB_LE_BREAKPOINT | |
2007 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2008 | #endif | |
2009 | #ifndef THUMB_BE_BREAKPOINT | |
2010 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2011 | #endif | |
2012 | ||
2013 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2014 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2015 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2016 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2017 | ||
34e8f22d RE |
2018 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2019 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2020 | breakpoint should be used. It returns a pointer to a string of |
2021 | bytes that encode a breakpoint instruction, stores the length of | |
2022 | the string to *lenptr, and adjusts the program counter (if | |
2023 | necessary) to point to the actual memory location where the | |
c906108c SS |
2024 | breakpoint should be inserted. */ |
2025 | ||
ab89facf | 2026 | static const unsigned char * |
ed9a39eb | 2027 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2028 | { |
66e810cd RE |
2029 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2030 | ||
4bf7064c | 2031 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 2032 | { |
66e810cd RE |
2033 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2034 | *lenptr = tdep->thumb_breakpoint_size; | |
2035 | return tdep->thumb_breakpoint; | |
c906108c SS |
2036 | } |
2037 | else | |
2038 | { | |
66e810cd RE |
2039 | *lenptr = tdep->arm_breakpoint_size; |
2040 | return tdep->arm_breakpoint; | |
c906108c SS |
2041 | } |
2042 | } | |
ed9a39eb JM |
2043 | |
2044 | /* Extract from an array REGBUF containing the (raw) register state a | |
2045 | function return value of type TYPE, and copy that, in virtual | |
2046 | format, into VALBUF. */ | |
2047 | ||
34e8f22d | 2048 | static void |
5238cf52 MK |
2049 | arm_extract_return_value (struct type *type, struct regcache *regs, |
2050 | gdb_byte *valbuf) | |
ed9a39eb JM |
2051 | { |
2052 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 | 2053 | { |
28e97307 | 2054 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2055 | { |
2056 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2057 | { |
2058 | /* The value is in register F0 in internal format. We need to | |
2059 | extract the raw value and then convert it to the desired | |
2060 | internal type. */ | |
7a5ea0d4 | 2061 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2062 | |
2063 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2064 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2065 | valbuf); | |
2066 | } | |
08216dd7 RE |
2067 | break; |
2068 | ||
fd50bc42 | 2069 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2070 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2071 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2072 | if (TYPE_LENGTH (type) > 4) | |
2073 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2074 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2075 | break; |
2076 | ||
2077 | default: | |
2078 | internal_error | |
2079 | (__FILE__, __LINE__, | |
edefbb7c | 2080 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2081 | break; |
2082 | } | |
2083 | } | |
b508a996 RE |
2084 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2085 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2086 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2087 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2088 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2089 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2090 | { | |
2091 | /* If the the type is a plain integer, then the access is | |
2092 | straight-forward. Otherwise we have to play around a bit more. */ | |
2093 | int len = TYPE_LENGTH (type); | |
2094 | int regno = ARM_A1_REGNUM; | |
2095 | ULONGEST tmp; | |
2096 | ||
2097 | while (len > 0) | |
2098 | { | |
2099 | /* By using store_unsigned_integer we avoid having to do | |
2100 | anything special for small big-endian values. */ | |
2101 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2102 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2103 | (len > INT_REGISTER_SIZE |
2104 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2105 | tmp); |
7a5ea0d4 DJ |
2106 | len -= INT_REGISTER_SIZE; |
2107 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2108 | } |
2109 | } | |
ed9a39eb | 2110 | else |
b508a996 RE |
2111 | { |
2112 | /* For a structure or union the behaviour is as if the value had | |
2113 | been stored to word-aligned memory and then loaded into | |
2114 | registers with 32-bit load instruction(s). */ | |
2115 | int len = TYPE_LENGTH (type); | |
2116 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2117 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2118 | |
2119 | while (len > 0) | |
2120 | { | |
2121 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2122 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2123 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2124 | len -= INT_REGISTER_SIZE; | |
2125 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2126 | } |
2127 | } | |
34e8f22d RE |
2128 | } |
2129 | ||
67255d04 RE |
2130 | |
2131 | /* Will a function return an aggregate type in memory or in a | |
2132 | register? Return 0 if an aggregate type can be returned in a | |
2133 | register, 1 if it must be returned in memory. */ | |
2134 | ||
2135 | static int | |
2af48f68 | 2136 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2137 | { |
2138 | int nRc; | |
52f0bd74 | 2139 | enum type_code code; |
67255d04 | 2140 | |
44e1a9eb DJ |
2141 | CHECK_TYPEDEF (type); |
2142 | ||
67255d04 RE |
2143 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2144 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2145 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2146 | offset of each addressable subfield must be zero. Note that bit | |
2147 | fields are not addressable, and all addressable subfields of | |
2148 | unions always start at offset zero. | |
67255d04 RE |
2149 | |
2150 | This function is based on the behaviour of GCC 2.95.1. | |
2151 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2152 | ||
2153 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2154 | parameters correctly for a function returning the following | |
2155 | structure: struct { float f;}; This should be returned in memory, | |
2156 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2157 | know of any way to detect if a function like the above has been | |
2158 | compiled with the correct calling convention. */ | |
2159 | ||
2160 | /* All aggregate types that won't fit in a register must be returned | |
2161 | in memory. */ | |
b1e29e33 | 2162 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2163 | { |
2164 | return 1; | |
2165 | } | |
2166 | ||
2af48f68 PB |
2167 | /* The AAPCS says all aggregates not larger than a word are returned |
2168 | in a register. */ | |
2169 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2170 | return 0; | |
2171 | ||
67255d04 RE |
2172 | /* The only aggregate types that can be returned in a register are |
2173 | structs and unions. Arrays must be returned in memory. */ | |
2174 | code = TYPE_CODE (type); | |
2175 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2176 | { | |
2177 | return 1; | |
2178 | } | |
2179 | ||
2180 | /* Assume all other aggregate types can be returned in a register. | |
2181 | Run a check for structures, unions and arrays. */ | |
2182 | nRc = 0; | |
2183 | ||
2184 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2185 | { | |
2186 | int i; | |
2187 | /* Need to check if this struct/union is "integer" like. For | |
2188 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2189 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2190 | subfield must be zero. Note that bit fields are not | |
2191 | addressable, and unions always start at offset zero. If any | |
2192 | of the subfields is a floating point type, the struct/union | |
2193 | cannot be an integer type. */ | |
67255d04 RE |
2194 | |
2195 | /* For each field in the object, check: | |
2196 | 1) Is it FP? --> yes, nRc = 1; | |
2197 | 2) Is it addressable (bitpos != 0) and | |
2198 | not packed (bitsize == 0)? | |
2199 | --> yes, nRc = 1 | |
2200 | */ | |
2201 | ||
2202 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2203 | { | |
2204 | enum type_code field_type_code; | |
44e1a9eb | 2205 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2206 | |
2207 | /* Is it a floating point type field? */ | |
2208 | if (field_type_code == TYPE_CODE_FLT) | |
2209 | { | |
2210 | nRc = 1; | |
2211 | break; | |
2212 | } | |
2213 | ||
2214 | /* If bitpos != 0, then we have to care about it. */ | |
2215 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2216 | { | |
2217 | /* Bitfields are not addressable. If the field bitsize is | |
2218 | zero, then the field is not packed. Hence it cannot be | |
2219 | a bitfield or any other packed type. */ | |
2220 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2221 | { | |
2222 | nRc = 1; | |
2223 | break; | |
2224 | } | |
2225 | } | |
2226 | } | |
2227 | } | |
2228 | ||
2229 | return nRc; | |
2230 | } | |
2231 | ||
34e8f22d RE |
2232 | /* Write into appropriate registers a function return value of type |
2233 | TYPE, given in virtual format. */ | |
2234 | ||
2235 | static void | |
b508a996 | 2236 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2237 | const gdb_byte *valbuf) |
34e8f22d RE |
2238 | { |
2239 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2240 | { | |
7a5ea0d4 | 2241 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2242 | |
28e97307 | 2243 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
08216dd7 RE |
2244 | { |
2245 | case ARM_FLOAT_FPA: | |
2246 | ||
b508a996 RE |
2247 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2248 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2249 | break; |
2250 | ||
fd50bc42 | 2251 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2252 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2253 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2254 | if (TYPE_LENGTH (type) > 4) | |
2255 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2256 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2257 | break; |
2258 | ||
2259 | default: | |
2260 | internal_error | |
2261 | (__FILE__, __LINE__, | |
edefbb7c | 2262 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2263 | break; |
2264 | } | |
34e8f22d | 2265 | } |
b508a996 RE |
2266 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2267 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2268 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2269 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2270 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2271 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2272 | { | |
2273 | if (TYPE_LENGTH (type) <= 4) | |
2274 | { | |
2275 | /* Values of one word or less are zero/sign-extended and | |
2276 | returned in r0. */ | |
7a5ea0d4 | 2277 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2278 | LONGEST val = unpack_long (type, valbuf); |
2279 | ||
7a5ea0d4 | 2280 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2281 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2282 | } | |
2283 | else | |
2284 | { | |
2285 | /* Integral values greater than one word are stored in consecutive | |
2286 | registers starting with r0. This will always be a multiple of | |
2287 | the regiser size. */ | |
2288 | int len = TYPE_LENGTH (type); | |
2289 | int regno = ARM_A1_REGNUM; | |
2290 | ||
2291 | while (len > 0) | |
2292 | { | |
2293 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2294 | len -= INT_REGISTER_SIZE; |
2295 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2296 | } |
2297 | } | |
2298 | } | |
34e8f22d | 2299 | else |
b508a996 RE |
2300 | { |
2301 | /* For a structure or union the behaviour is as if the value had | |
2302 | been stored to word-aligned memory and then loaded into | |
2303 | registers with 32-bit load instruction(s). */ | |
2304 | int len = TYPE_LENGTH (type); | |
2305 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2306 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2307 | |
2308 | while (len > 0) | |
2309 | { | |
2310 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2311 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2312 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2313 | len -= INT_REGISTER_SIZE; |
2314 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2315 | } |
2316 | } | |
34e8f22d RE |
2317 | } |
2318 | ||
2af48f68 PB |
2319 | |
2320 | /* Handle function return values. */ | |
2321 | ||
2322 | static enum return_value_convention | |
2323 | arm_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
25224166 MK |
2324 | struct regcache *regcache, gdb_byte *readbuf, |
2325 | const gdb_byte *writebuf) | |
2af48f68 | 2326 | { |
7c00367c MK |
2327 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2328 | ||
2af48f68 PB |
2329 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
2330 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2331 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2332 | { | |
7c00367c MK |
2333 | if (tdep->struct_return == pcc_struct_return |
2334 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
2335 | return RETURN_VALUE_STRUCT_CONVENTION; |
2336 | } | |
2337 | ||
2338 | if (writebuf) | |
2339 | arm_store_return_value (valtype, regcache, writebuf); | |
2340 | ||
2341 | if (readbuf) | |
2342 | arm_extract_return_value (valtype, regcache, readbuf); | |
2343 | ||
2344 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2345 | } | |
2346 | ||
2347 | ||
9df628e0 RE |
2348 | static int |
2349 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2350 | { | |
2351 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2352 | char buf[INT_REGISTER_SIZE]; |
9df628e0 RE |
2353 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2354 | ||
2355 | jb_addr = read_register (ARM_A1_REGNUM); | |
2356 | ||
2357 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2358 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2359 | return 0; |
2360 | ||
7a5ea0d4 | 2361 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2362 | return 1; |
2363 | } | |
2364 | ||
ed9a39eb | 2365 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2366 | |
2367 | int | |
ed9a39eb | 2368 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2369 | { |
2370 | CORE_ADDR start_addr; | |
2371 | ||
ed9a39eb JM |
2372 | /* Find the starting address of the function containing the PC. If |
2373 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2374 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2375 | &start_addr, NULL)) | |
c906108c SS |
2376 | return 0; |
2377 | ||
2378 | return strncmp (name, "_call_via_r", 11) == 0; | |
2379 | } | |
2380 | ||
ed9a39eb JM |
2381 | /* If PC is in a Thumb call or return stub, return the address of the |
2382 | target PC, which is in a register. The thunk functions are called | |
2383 | _called_via_xx, where x is the register name. The possible names | |
2384 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2385 | |
2386 | CORE_ADDR | |
ed9a39eb | 2387 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2388 | { |
c5aa993b | 2389 | char *name; |
c906108c SS |
2390 | CORE_ADDR start_addr; |
2391 | ||
2392 | /* Find the starting address and name of the function containing the PC. */ | |
2393 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2394 | return 0; | |
2395 | ||
2396 | /* Call thunks always start with "_call_via_". */ | |
2397 | if (strncmp (name, "_call_via_", 10) == 0) | |
2398 | { | |
ed9a39eb JM |
2399 | /* Use the name suffix to determine which register contains the |
2400 | target PC. */ | |
c5aa993b JM |
2401 | static char *table[15] = |
2402 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2403 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2404 | }; | |
c906108c SS |
2405 | int regno; |
2406 | ||
2407 | for (regno = 0; regno <= 14; regno++) | |
2408 | if (strcmp (&name[10], table[regno]) == 0) | |
2409 | return read_register (regno); | |
2410 | } | |
ed9a39eb | 2411 | |
c5aa993b | 2412 | return 0; /* not a stub */ |
c906108c SS |
2413 | } |
2414 | ||
afd7eef0 RE |
2415 | static void |
2416 | set_arm_command (char *args, int from_tty) | |
2417 | { | |
edefbb7c AC |
2418 | printf_unfiltered (_("\ |
2419 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2420 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2421 | } | |
2422 | ||
2423 | static void | |
2424 | show_arm_command (char *args, int from_tty) | |
2425 | { | |
26304000 | 2426 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2427 | } |
2428 | ||
28e97307 DJ |
2429 | static void |
2430 | arm_update_current_architecture (void) | |
fd50bc42 | 2431 | { |
28e97307 | 2432 | struct gdbarch_info info; |
fd50bc42 | 2433 | |
28e97307 DJ |
2434 | /* If the current architecture is not ARM, we have nothing to do. */ |
2435 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) | |
2436 | return; | |
fd50bc42 | 2437 | |
28e97307 DJ |
2438 | /* Update the architecture. */ |
2439 | gdbarch_info_init (&info); | |
fd50bc42 | 2440 | |
28e97307 DJ |
2441 | if (!gdbarch_update_p (info)) |
2442 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2443 | } |
2444 | ||
2445 | static void | |
2446 | set_fp_model_sfunc (char *args, int from_tty, | |
2447 | struct cmd_list_element *c) | |
2448 | { | |
2449 | enum arm_float_model fp_model; | |
2450 | ||
2451 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2452 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2453 | { | |
2454 | arm_fp_model = fp_model; | |
2455 | break; | |
2456 | } | |
2457 | ||
2458 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2459 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2460 | current_fp_model); |
2461 | ||
28e97307 | 2462 | arm_update_current_architecture (); |
fd50bc42 RE |
2463 | } |
2464 | ||
2465 | static void | |
08546159 AC |
2466 | show_fp_model (struct ui_file *file, int from_tty, |
2467 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2468 | { |
2469 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2470 | ||
28e97307 | 2471 | if (arm_fp_model == ARM_FLOAT_AUTO |
fd50bc42 | 2472 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2473 | fprintf_filtered (file, _("\ |
2474 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2475 | fp_model_strings[tdep->fp_model]); | |
2476 | else | |
2477 | fprintf_filtered (file, _("\ | |
2478 | The current ARM floating point model is \"%s\".\n"), | |
2479 | fp_model_strings[arm_fp_model]); | |
2480 | } | |
2481 | ||
2482 | static void | |
2483 | arm_set_abi (char *args, int from_tty, | |
2484 | struct cmd_list_element *c) | |
2485 | { | |
2486 | enum arm_abi_kind arm_abi; | |
2487 | ||
2488 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2489 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2490 | { | |
2491 | arm_abi_global = arm_abi; | |
2492 | break; | |
2493 | } | |
2494 | ||
2495 | if (arm_abi == ARM_ABI_LAST) | |
2496 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2497 | arm_abi_string); | |
2498 | ||
2499 | arm_update_current_architecture (); | |
2500 | } | |
2501 | ||
2502 | static void | |
2503 | arm_show_abi (struct ui_file *file, int from_tty, | |
2504 | struct cmd_list_element *c, const char *value) | |
2505 | { | |
2506 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2507 | ||
2508 | if (arm_abi_global == ARM_ABI_AUTO | |
2509 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2510 | fprintf_filtered (file, _("\ | |
2511 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2512 | arm_abi_strings[tdep->arm_abi]); | |
2513 | else | |
2514 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2515 | arm_abi_string); | |
fd50bc42 RE |
2516 | } |
2517 | ||
afd7eef0 RE |
2518 | /* If the user changes the register disassembly style used for info |
2519 | register and other commands, we have to also switch the style used | |
2520 | in opcodes for disassembly output. This function is run in the "set | |
2521 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2522 | |
2523 | static void | |
afd7eef0 | 2524 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2525 | struct cmd_list_element *c) |
2526 | { | |
afd7eef0 | 2527 | set_disassembly_style (); |
bc90b915 FN |
2528 | } |
2529 | \f | |
966fbf70 | 2530 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2531 | static const char * |
34e8f22d | 2532 | arm_register_name (int i) |
966fbf70 | 2533 | { |
ff6f572f DJ |
2534 | if (i >= ARRAY_SIZE (arm_register_names)) |
2535 | /* These registers are only supported on targets which supply | |
2536 | an XML description. */ | |
2537 | return ""; | |
2538 | ||
966fbf70 RE |
2539 | return arm_register_names[i]; |
2540 | } | |
2541 | ||
bc90b915 | 2542 | static void |
afd7eef0 | 2543 | set_disassembly_style (void) |
bc90b915 | 2544 | { |
123dc839 | 2545 | int current; |
bc90b915 | 2546 | |
123dc839 DJ |
2547 | /* Find the style that the user wants. */ |
2548 | for (current = 0; current < num_disassembly_options; current++) | |
2549 | if (disassembly_style == valid_disassembly_styles[current]) | |
2550 | break; | |
2551 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 2552 | |
94c30b78 | 2553 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2554 | set_arm_regname_option (current); |
2555 | } | |
2556 | ||
082fc60d RE |
2557 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2558 | function. */ | |
2559 | ||
2560 | static int | |
2561 | coff_sym_is_thumb (int val) | |
2562 | { | |
2563 | return (val == C_THUMBEXT || | |
2564 | val == C_THUMBSTAT || | |
2565 | val == C_THUMBEXTFUNC || | |
2566 | val == C_THUMBSTATFUNC || | |
2567 | val == C_THUMBLABEL); | |
2568 | } | |
2569 | ||
2570 | /* arm_coff_make_msymbol_special() | |
2571 | arm_elf_make_msymbol_special() | |
2572 | ||
2573 | These functions test whether the COFF or ELF symbol corresponds to | |
2574 | an address in thumb code, and set a "special" bit in a minimal | |
2575 | symbol to indicate that it does. */ | |
2576 | ||
34e8f22d | 2577 | static void |
082fc60d RE |
2578 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2579 | { | |
2580 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2581 | STT_ARM_TFUNC). */ | |
2582 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2583 | == STT_LOPROC) | |
2584 | MSYMBOL_SET_SPECIAL (msym); | |
2585 | } | |
2586 | ||
34e8f22d | 2587 | static void |
082fc60d RE |
2588 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2589 | { | |
2590 | if (coff_sym_is_thumb (val)) | |
2591 | MSYMBOL_SET_SPECIAL (msym); | |
2592 | } | |
2593 | ||
756fe439 DJ |
2594 | static void |
2595 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) | |
2596 | { | |
2597 | write_register_pid (ARM_PC_REGNUM, pc, ptid); | |
2598 | ||
2599 | /* If necessary, set the T bit. */ | |
2600 | if (arm_apcs_32) | |
2601 | { | |
2602 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); | |
2603 | if (arm_pc_is_thumb (pc)) | |
2604 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); | |
2605 | else | |
2606 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); | |
2607 | } | |
2608 | } | |
123dc839 DJ |
2609 | |
2610 | static struct value * | |
2611 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
2612 | { | |
2613 | const int *reg_p = baton; | |
2614 | return value_of_register (*reg_p, frame); | |
2615 | } | |
97e03143 | 2616 | \f |
70f80edf JT |
2617 | static enum gdb_osabi |
2618 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2619 | { |
2af48f68 | 2620 | unsigned int elfosabi; |
70f80edf | 2621 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 2622 | |
70f80edf | 2623 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2624 | |
28e97307 DJ |
2625 | if (elfosabi == ELFOSABI_ARM) |
2626 | /* GNU tools use this value. Check note sections in this case, | |
2627 | as well. */ | |
2628 | bfd_map_over_sections (abfd, | |
2629 | generic_elf_osabi_sniff_abi_tag_sections, | |
2630 | &osabi); | |
97e03143 | 2631 | |
28e97307 | 2632 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2633 | return osabi; |
97e03143 RE |
2634 | } |
2635 | ||
70f80edf | 2636 | \f |
da3c6d4a MS |
2637 | /* Initialize the current architecture based on INFO. If possible, |
2638 | re-use an architecture from ARCHES, which is a list of | |
2639 | architectures already created during this debugging session. | |
97e03143 | 2640 | |
da3c6d4a MS |
2641 | Called e.g. at program startup, when reading a core file, and when |
2642 | reading a binary file. */ | |
97e03143 | 2643 | |
39bbf761 RE |
2644 | static struct gdbarch * |
2645 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2646 | { | |
97e03143 | 2647 | struct gdbarch_tdep *tdep; |
39bbf761 | 2648 | struct gdbarch *gdbarch; |
28e97307 DJ |
2649 | struct gdbarch_list *best_arch; |
2650 | enum arm_abi_kind arm_abi = arm_abi_global; | |
2651 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 DJ |
2652 | struct tdesc_arch_data *tdesc_data = NULL; |
2653 | int i; | |
ff6f572f | 2654 | int have_fpa_registers = 1; |
123dc839 DJ |
2655 | |
2656 | /* Check any target description for validity. */ | |
2657 | if (tdesc_has_registers (info.target_desc)) | |
2658 | { | |
2659 | /* For most registers we require GDB's default names; but also allow | |
2660 | the numeric names for sp / lr / pc, as a convenience. */ | |
2661 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
2662 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
2663 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
2664 | ||
2665 | const struct tdesc_feature *feature; | |
2666 | int i, valid_p; | |
2667 | ||
2668 | feature = tdesc_find_feature (info.target_desc, | |
2669 | "org.gnu.gdb.arm.core"); | |
2670 | if (feature == NULL) | |
2671 | return NULL; | |
2672 | ||
2673 | tdesc_data = tdesc_data_alloc (); | |
2674 | ||
2675 | valid_p = 1; | |
2676 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
2677 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
2678 | arm_register_names[i]); | |
2679 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2680 | ARM_SP_REGNUM, | |
2681 | arm_sp_names); | |
2682 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2683 | ARM_LR_REGNUM, | |
2684 | arm_lr_names); | |
2685 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2686 | ARM_PC_REGNUM, | |
2687 | arm_pc_names); | |
2688 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
2689 | ARM_PS_REGNUM, "cpsr"); | |
2690 | ||
2691 | if (!valid_p) | |
2692 | { | |
2693 | tdesc_data_cleanup (tdesc_data); | |
2694 | return NULL; | |
2695 | } | |
2696 | ||
2697 | feature = tdesc_find_feature (info.target_desc, | |
2698 | "org.gnu.gdb.arm.fpa"); | |
2699 | if (feature != NULL) | |
2700 | { | |
2701 | valid_p = 1; | |
2702 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
2703 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
2704 | arm_register_names[i]); | |
2705 | if (!valid_p) | |
2706 | { | |
2707 | tdesc_data_cleanup (tdesc_data); | |
2708 | return NULL; | |
2709 | } | |
2710 | } | |
ff6f572f DJ |
2711 | else |
2712 | have_fpa_registers = 0; | |
2713 | ||
2714 | feature = tdesc_find_feature (info.target_desc, | |
2715 | "org.gnu.gdb.xscale.iwmmxt"); | |
2716 | if (feature != NULL) | |
2717 | { | |
2718 | static const char *const iwmmxt_names[] = { | |
2719 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
2720 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
2721 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
2722 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
2723 | }; | |
2724 | ||
2725 | valid_p = 1; | |
2726 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
2727 | valid_p | |
2728 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
2729 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2730 | ||
2731 | /* Check for the control registers, but do not fail if they | |
2732 | are missing. */ | |
2733 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
2734 | tdesc_numbered_register (feature, tdesc_data, i, | |
2735 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2736 | ||
2737 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
2738 | valid_p | |
2739 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
2740 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2741 | ||
2742 | if (!valid_p) | |
2743 | { | |
2744 | tdesc_data_cleanup (tdesc_data); | |
2745 | return NULL; | |
2746 | } | |
2747 | } | |
123dc839 | 2748 | } |
39bbf761 | 2749 | |
28e97307 DJ |
2750 | /* If we have an object to base this architecture on, try to determine |
2751 | its ABI. */ | |
39bbf761 | 2752 | |
28e97307 | 2753 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 2754 | { |
6b26d61a | 2755 | int ei_osabi, e_flags; |
28e97307 | 2756 | |
4be87837 | 2757 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2758 | { |
4be87837 DJ |
2759 | case bfd_target_aout_flavour: |
2760 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 2761 | arm_abi = ARM_ABI_APCS; |
4be87837 | 2762 | break; |
97e03143 | 2763 | |
4be87837 DJ |
2764 | case bfd_target_coff_flavour: |
2765 | /* Assume it's an old APCS-style ABI. */ | |
2766 | /* XXX WinCE? */ | |
28e97307 DJ |
2767 | arm_abi = ARM_ABI_APCS; |
2768 | break; | |
2769 | ||
2770 | case bfd_target_elf_flavour: | |
2771 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
6b26d61a MK |
2772 | e_flags = elf_elfheader (info.abfd)->e_flags; |
2773 | ||
28e97307 DJ |
2774 | if (ei_osabi == ELFOSABI_ARM) |
2775 | { | |
2776 | /* GNU tools used to use this value, but do not for EABI | |
6b26d61a MK |
2777 | objects. There's nowhere to tag an EABI version |
2778 | anyway, so assume APCS. */ | |
28e97307 DJ |
2779 | arm_abi = ARM_ABI_APCS; |
2780 | } | |
2781 | else if (ei_osabi == ELFOSABI_NONE) | |
2782 | { | |
6b26d61a | 2783 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
28e97307 DJ |
2784 | |
2785 | switch (eabi_ver) | |
2786 | { | |
2787 | case EF_ARM_EABI_UNKNOWN: | |
2788 | /* Assume GNU tools. */ | |
2789 | arm_abi = ARM_ABI_APCS; | |
2790 | break; | |
2791 | ||
2792 | case EF_ARM_EABI_VER4: | |
625b5003 | 2793 | case EF_ARM_EABI_VER5: |
28e97307 | 2794 | arm_abi = ARM_ABI_AAPCS; |
2af48f68 PB |
2795 | /* EABI binaries default to VFP float ordering. */ |
2796 | if (fp_model == ARM_FLOAT_AUTO) | |
2797 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2798 | break; |
2799 | ||
2800 | default: | |
6b26d61a | 2801 | /* Leave it as "auto". */ |
28e97307 | 2802 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
6b26d61a MK |
2803 | break; |
2804 | } | |
2805 | } | |
2806 | ||
2807 | if (fp_model == ARM_FLOAT_AUTO) | |
2808 | { | |
2809 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2810 | ||
2811 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
2812 | { | |
2813 | case 0: | |
2814 | /* Leave it as "auto". Strictly speaking this case | |
2815 | means FPA, but almost nobody uses that now, and | |
2816 | many toolchains fail to set the appropriate bits | |
2817 | for the floating-point model they use. */ | |
2818 | break; | |
2819 | case EF_ARM_SOFT_FLOAT: | |
2820 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2821 | break; | |
2822 | case EF_ARM_VFP_FLOAT: | |
2823 | fp_model = ARM_FLOAT_VFP; | |
2824 | break; | |
2825 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
2826 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2827 | break; |
2828 | } | |
2829 | } | |
4be87837 | 2830 | break; |
97e03143 | 2831 | |
4be87837 | 2832 | default: |
28e97307 | 2833 | /* Leave it as "auto". */ |
50ceaba5 | 2834 | break; |
97e03143 RE |
2835 | } |
2836 | } | |
2837 | ||
28e97307 DJ |
2838 | /* Now that we have inferred any architecture settings that we |
2839 | can, try to inherit from the last ARM ABI. */ | |
4be87837 | 2840 | if (arches != NULL) |
28e97307 DJ |
2841 | { |
2842 | if (arm_abi == ARM_ABI_AUTO) | |
2843 | arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi; | |
2844 | ||
2845 | if (fp_model == ARM_FLOAT_AUTO) | |
2846 | fp_model = gdbarch_tdep (arches->gdbarch)->fp_model; | |
2847 | } | |
2848 | else | |
2849 | { | |
2850 | /* There was no prior ARM architecture; fill in default values. */ | |
2851 | ||
2852 | if (arm_abi == ARM_ABI_AUTO) | |
2853 | arm_abi = ARM_ABI_APCS; | |
2854 | ||
2855 | /* We used to default to FPA for generic ARM, but almost nobody | |
2856 | uses that now, and we now provide a way for the user to force | |
2857 | the model. So default to the most useful variant. */ | |
2858 | if (fp_model == ARM_FLOAT_AUTO) | |
2859 | fp_model = ARM_FLOAT_SOFT_FPA; | |
2860 | } | |
2861 | ||
2862 | /* If there is already a candidate, use it. */ | |
2863 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2864 | best_arch != NULL; | |
2865 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2866 | { | |
2867 | if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
2868 | continue; | |
2869 | ||
2870 | if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
2871 | continue; | |
2872 | ||
2873 | /* Found a match. */ | |
2874 | break; | |
2875 | } | |
97e03143 | 2876 | |
28e97307 | 2877 | if (best_arch != NULL) |
123dc839 DJ |
2878 | { |
2879 | if (tdesc_data != NULL) | |
2880 | tdesc_data_cleanup (tdesc_data); | |
2881 | return best_arch->gdbarch; | |
2882 | } | |
28e97307 DJ |
2883 | |
2884 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
2885 | gdbarch = gdbarch_alloc (&info, tdep); |
2886 | ||
28e97307 DJ |
2887 | /* Record additional information about the architecture we are defining. |
2888 | These are gdbarch discriminators, like the OSABI. */ | |
2889 | tdep->arm_abi = arm_abi; | |
2890 | tdep->fp_model = fp_model; | |
ff6f572f | 2891 | tdep->have_fpa_registers = have_fpa_registers; |
08216dd7 RE |
2892 | |
2893 | /* Breakpoints. */ | |
67255d04 RE |
2894 | switch (info.byte_order) |
2895 | { | |
2896 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2897 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2898 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2899 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2900 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2901 | ||
67255d04 RE |
2902 | break; |
2903 | ||
2904 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2905 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2906 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2907 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2908 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2909 | ||
67255d04 RE |
2910 | break; |
2911 | ||
2912 | default: | |
2913 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 2914 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
2915 | } |
2916 | ||
d7b486e7 RE |
2917 | /* On ARM targets char defaults to unsigned. */ |
2918 | set_gdbarch_char_signed (gdbarch, 0); | |
2919 | ||
9df628e0 | 2920 | /* This should be low enough for everything. */ |
97e03143 | 2921 | tdep->lowest_pc = 0x20; |
94c30b78 | 2922 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2923 | |
7c00367c MK |
2924 | /* The default, for both APCS and AAPCS, is to return small |
2925 | structures in registers. */ | |
2926 | tdep->struct_return = reg_struct_return; | |
2927 | ||
2dd604e7 | 2928 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 2929 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 2930 | |
756fe439 DJ |
2931 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
2932 | ||
148754e5 | 2933 | /* Frame handling. */ |
eb5492fa DJ |
2934 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
2935 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); | |
2936 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
2937 | ||
eb5492fa | 2938 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 2939 | |
34e8f22d RE |
2940 | /* Address manipulation. */ |
2941 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2942 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2943 | ||
34e8f22d RE |
2944 | /* Advance PC across function entry code. */ |
2945 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2946 | ||
34e8f22d RE |
2947 | /* The stack grows downward. */ |
2948 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2949 | ||
2950 | /* Breakpoint manipulation. */ | |
2951 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
2952 | |
2953 | /* Information about registers, etc. */ | |
0ba6dca9 | 2954 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2955 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2956 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 2957 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 2958 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 2959 | |
ff6f572f DJ |
2960 | /* This "info float" is FPA-specific. Use the generic version if we |
2961 | do not have FPA. */ | |
2962 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
2963 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
2964 | ||
26216b98 | 2965 | /* Internal <-> external register number maps. */ |
ff6f572f DJ |
2966 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
2967 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); | |
26216b98 AC |
2968 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
2969 | ||
34e8f22d | 2970 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2971 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2972 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2973 | ||
2974 | /* Returning results. */ | |
2af48f68 | 2975 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d RE |
2976 | |
2977 | /* Single stepping. */ | |
2978 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2979 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2980 | ||
03d48a7d RE |
2981 | /* Disassembly. */ |
2982 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2983 | ||
34e8f22d RE |
2984 | /* Minsymbol frobbing. */ |
2985 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2986 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2987 | arm_coff_make_msymbol_special); | |
2988 | ||
0d5de010 DJ |
2989 | /* Virtual tables. */ |
2990 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
2991 | ||
97e03143 | 2992 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2993 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 2994 | |
eb5492fa | 2995 | /* Add some default predicates. */ |
909cf6ea | 2996 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
842e1f1e | 2997 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eb5492fa DJ |
2998 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
2999 | ||
97e03143 RE |
3000 | /* Now we have tuned the configuration, set a few final things, |
3001 | based on what the OS ABI has told us. */ | |
3002 | ||
9df628e0 RE |
3003 | if (tdep->jb_pc >= 0) |
3004 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
3005 | ||
08216dd7 | 3006 | /* Floating point sizes and format. */ |
8da61cc4 DJ |
3007 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
3008 | if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA) | |
08216dd7 | 3009 | { |
8da61cc4 DJ |
3010 | set_gdbarch_double_format |
3011 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3012 | set_gdbarch_long_double_format | |
3013 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3014 | } | |
3015 | else | |
3016 | { | |
3017 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
3018 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
3019 | } |
3020 | ||
123dc839 DJ |
3021 | if (tdesc_data) |
3022 | tdesc_use_registers (gdbarch, tdesc_data); | |
3023 | ||
3024 | /* Add standard register aliases. We add aliases even for those | |
3025 | nanes which are used by the current architecture - it's simpler, | |
3026 | and does no harm, since nothing ever lists user registers. */ | |
3027 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
3028 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
3029 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
3030 | ||
39bbf761 RE |
3031 | return gdbarch; |
3032 | } | |
3033 | ||
97e03143 RE |
3034 | static void |
3035 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3036 | { | |
3037 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3038 | ||
3039 | if (tdep == NULL) | |
3040 | return; | |
3041 | ||
edefbb7c | 3042 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
3043 | (unsigned long) tdep->lowest_pc); |
3044 | } | |
3045 | ||
a78f21af AC |
3046 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
3047 | ||
c906108c | 3048 | void |
ed9a39eb | 3049 | _initialize_arm_tdep (void) |
c906108c | 3050 | { |
bc90b915 FN |
3051 | struct ui_file *stb; |
3052 | long length; | |
26304000 | 3053 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
3054 | const char *setname; |
3055 | const char *setdesc; | |
4bd7b427 | 3056 | const char *const *regnames; |
bc90b915 FN |
3057 | int numregs, i, j; |
3058 | static char *helptext; | |
edefbb7c AC |
3059 | char regdesc[1024], *rdptr = regdesc; |
3060 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 3061 | |
42cf1509 | 3062 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 3063 | |
70f80edf JT |
3064 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3065 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3066 | bfd_target_elf_flavour, | |
3067 | arm_elf_osabi_sniffer); | |
3068 | ||
94c30b78 | 3069 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
3070 | num_disassembly_options = get_arm_regname_num_options (); |
3071 | ||
3072 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
3073 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 3074 | _("Various ARM-specific commands."), |
afd7eef0 RE |
3075 | &setarmcmdlist, "set arm ", 0, &setlist); |
3076 | ||
3077 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 3078 | _("Various ARM-specific commands."), |
afd7eef0 | 3079 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 3080 | |
94c30b78 | 3081 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3082 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3083 | |
eefe576e AC |
3084 | /* Initialize the array that will be passed to |
3085 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
3086 | valid_disassembly_styles |
3087 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
3088 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
3089 | { |
3090 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 3091 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
3092 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
3093 | rdptr += length; | |
3094 | rest -= length; | |
123dc839 DJ |
3095 | /* When we find the default names, tell the disassembler to use |
3096 | them. */ | |
bc90b915 FN |
3097 | if (!strcmp (setname, "std")) |
3098 | { | |
afd7eef0 | 3099 | disassembly_style = setname; |
bc90b915 FN |
3100 | set_arm_regname_option (i); |
3101 | } | |
3102 | } | |
94c30b78 | 3103 | /* Mark the end of valid options. */ |
afd7eef0 | 3104 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 3105 | |
edefbb7c AC |
3106 | /* Create the help text. */ |
3107 | stb = mem_fileopen (); | |
3108 | fprintf_unfiltered (stb, "%s%s%s", | |
3109 | _("The valid values are:\n"), | |
3110 | regdesc, | |
3111 | _("The default is \"std\".")); | |
bc90b915 FN |
3112 | helptext = ui_file_xstrdup (stb, &length); |
3113 | ui_file_delete (stb); | |
ed9a39eb | 3114 | |
edefbb7c AC |
3115 | add_setshow_enum_cmd("disassembler", no_class, |
3116 | valid_disassembly_styles, &disassembly_style, | |
3117 | _("Set the disassembly style."), | |
3118 | _("Show the disassembly style."), | |
3119 | helptext, | |
2c5b56ce | 3120 | set_disassembly_style_sfunc, |
7915a72c | 3121 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 3122 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
3123 | |
3124 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
3125 | _("Set usage of ARM 32-bit mode."), | |
3126 | _("Show usage of ARM 32-bit mode."), | |
3127 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 3128 | NULL, |
7915a72c | 3129 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 3130 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 3131 | |
fd50bc42 | 3132 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
3133 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
3134 | _("Set the floating point type."), | |
3135 | _("Show the floating point type."), | |
3136 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
3137 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
3138 | fpa - FPA co-processor (GCC compiled).\n\ | |
3139 | softvfp - Software FP with pure-endian doubles.\n\ | |
3140 | vfp - VFP co-processor."), | |
edefbb7c | 3141 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 3142 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 3143 | |
28e97307 DJ |
3144 | /* Add a command to allow the user to force the ABI. */ |
3145 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
3146 | _("Set the ABI."), | |
3147 | _("Show the ABI."), | |
3148 | NULL, arm_set_abi, arm_show_abi, | |
3149 | &setarmcmdlist, &showarmcmdlist); | |
3150 | ||
6529d2dd | 3151 | /* Debugging flag. */ |
edefbb7c AC |
3152 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
3153 | _("Set ARM debugging."), | |
3154 | _("Show ARM debugging."), | |
3155 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 3156 | NULL, |
7915a72c | 3157 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 3158 | &setdebuglist, &showdebuglist); |
c906108c | 3159 | } |