* frame.h (frame_unwind_arch): New.
[deliverable/binutils-gdb.git] / gdb / arm-tdep.c
CommitLineData
ed9a39eb 1/* Common target dependent code for GDB on ARM systems.
0fd88904 2
6aba47ca 3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
0fb0cc75 4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
9b254dd1 5 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c 21
34e8f22d
RE
22#include <ctype.h> /* XXX for isupper () */
23
c906108c
SS
24#include "defs.h"
25#include "frame.h"
26#include "inferior.h"
27#include "gdbcmd.h"
28#include "gdbcore.h"
c906108c 29#include "gdb_string.h"
afd7eef0 30#include "dis-asm.h" /* For register styles. */
4e052eda 31#include "regcache.h"
d16aafd8 32#include "doublest.h"
fd0407d6 33#include "value.h"
34e8f22d 34#include "arch-utils.h"
4be87837 35#include "osabi.h"
eb5492fa
DJ
36#include "frame-unwind.h"
37#include "frame-base.h"
38#include "trad-frame.h"
842e1f1e
DJ
39#include "objfiles.h"
40#include "dwarf2-frame.h"
e4c16157 41#include "gdbtypes.h"
29d73ae4 42#include "prologue-value.h"
123dc839
DJ
43#include "target-descriptions.h"
44#include "user-regs.h"
34e8f22d
RE
45
46#include "arm-tdep.h"
26216b98 47#include "gdb/sim-arm.h"
34e8f22d 48
082fc60d
RE
49#include "elf-bfd.h"
50#include "coff/internal.h"
97e03143 51#include "elf/arm.h"
c906108c 52
26216b98 53#include "gdb_assert.h"
60c5725c 54#include "vec.h"
26216b98 55
6529d2dd
AC
56static int arm_debug;
57
082fc60d
RE
58/* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
f594e5e9 60 is used for this purpose.
082fc60d
RE
61
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
f594e5e9 63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
082fc60d
RE
64
65#define MSYMBOL_SET_SPECIAL(msym) \
b887350f 66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
082fc60d
RE
67
68#define MSYMBOL_IS_SPECIAL(msym) \
b887350f 69 MSYMBOL_TARGET_FLAG_1 (msym)
082fc60d 70
9d4fde75
SS
71/* Macros for swapping shorts and ints. In the unlikely case that anybody else needs these,
72 move to a general header. (A better solution might be to define memory read routines that
73 know whether they are reading code or data.) */
74
75#define SWAP_SHORT(x) \
76 ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
77
78#define SWAP_INT(x) \
79 ( ((x & 0xff000000) >> 24) \
80 | ((x & 0x00ff0000) >> 8) \
81 | ((x & 0x0000ff00) << 8) \
82 | ((x & 0x000000ff) << 24))
83
60c5725c
DJ
84/* Per-objfile data used for mapping symbols. */
85static const struct objfile_data *arm_objfile_data_key;
86
87struct arm_mapping_symbol
88{
89 bfd_vma value;
90 char type;
91};
92typedef struct arm_mapping_symbol arm_mapping_symbol_s;
93DEF_VEC_O(arm_mapping_symbol_s);
94
95struct arm_per_objfile
96{
97 VEC(arm_mapping_symbol_s) **section_maps;
98};
99
afd7eef0
RE
100/* The list of available "set arm ..." and "show arm ..." commands. */
101static struct cmd_list_element *setarmcmdlist = NULL;
102static struct cmd_list_element *showarmcmdlist = NULL;
103
fd50bc42
RE
104/* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106static const char *fp_model_strings[] =
107{
108 "auto",
109 "softfpa",
110 "fpa",
111 "softvfp",
28e97307
DJ
112 "vfp",
113 NULL
fd50bc42
RE
114};
115
116/* A variable that can be configured by the user. */
117static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
118static const char *current_fp_model = "auto";
119
28e97307
DJ
120/* The ABI to use. Keep this in sync with arm_abi_kind. */
121static const char *arm_abi_strings[] =
122{
123 "auto",
124 "APCS",
125 "AAPCS",
126 NULL
127};
128
129/* A variable that can be configured by the user. */
130static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
131static const char *arm_abi_string = "auto";
132
0428b8f5
DJ
133/* The execution mode to assume. */
134static const char *arm_mode_strings[] =
135 {
136 "auto",
137 "arm",
138 "thumb"
139 };
140
141static const char *arm_fallback_mode_string = "auto";
142static const char *arm_force_mode_string = "auto";
143
94c30b78 144/* Number of different reg name sets (options). */
afd7eef0 145static int num_disassembly_options;
bc90b915 146
123dc839
DJ
147/* The standard register names, and all the valid aliases for them. */
148static const struct
149{
150 const char *name;
151 int regnum;
152} arm_register_aliases[] = {
153 /* Basic register numbers. */
154 { "r0", 0 },
155 { "r1", 1 },
156 { "r2", 2 },
157 { "r3", 3 },
158 { "r4", 4 },
159 { "r5", 5 },
160 { "r6", 6 },
161 { "r7", 7 },
162 { "r8", 8 },
163 { "r9", 9 },
164 { "r10", 10 },
165 { "r11", 11 },
166 { "r12", 12 },
167 { "r13", 13 },
168 { "r14", 14 },
169 { "r15", 15 },
170 /* Synonyms (argument and variable registers). */
171 { "a1", 0 },
172 { "a2", 1 },
173 { "a3", 2 },
174 { "a4", 3 },
175 { "v1", 4 },
176 { "v2", 5 },
177 { "v3", 6 },
178 { "v4", 7 },
179 { "v5", 8 },
180 { "v6", 9 },
181 { "v7", 10 },
182 { "v8", 11 },
183 /* Other platform-specific names for r9. */
184 { "sb", 9 },
185 { "tr", 9 },
186 /* Special names. */
187 { "ip", 12 },
188 { "sp", 13 },
189 { "lr", 14 },
190 { "pc", 15 },
191 /* Names used by GCC (not listed in the ARM EABI). */
192 { "sl", 10 },
193 { "fp", 11 },
194 /* A special name from the older ATPCS. */
195 { "wr", 7 },
196};
bc90b915 197
123dc839 198static const char *const arm_register_names[] =
da59e081
JM
199{"r0", "r1", "r2", "r3", /* 0 1 2 3 */
200 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
201 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
202 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
203 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
204 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
94c30b78 205 "fps", "cpsr" }; /* 24 25 */
ed9a39eb 206
afd7eef0
RE
207/* Valid register name styles. */
208static const char **valid_disassembly_styles;
ed9a39eb 209
afd7eef0
RE
210/* Disassembly style to use. Default to "std" register names. */
211static const char *disassembly_style;
96baa820 212
ed9a39eb 213/* This is used to keep the bfd arch_info in sync with the disassembly
afd7eef0
RE
214 style. */
215static void set_disassembly_style_sfunc(char *, int,
ed9a39eb 216 struct cmd_list_element *);
afd7eef0 217static void set_disassembly_style (void);
ed9a39eb 218
b508a996 219static void convert_from_extended (const struct floatformat *, const void *,
be8626e0 220 void *, int);
b508a996 221static void convert_to_extended (const struct floatformat *, void *,
be8626e0 222 const void *, int);
ed9a39eb 223
9b8d791a 224struct arm_prologue_cache
c3b4394c 225{
eb5492fa
DJ
226 /* The stack pointer at the time this frame was created; i.e. the
227 caller's stack pointer when this function was called. It is used
228 to identify this frame. */
229 CORE_ADDR prev_sp;
230
4be43953
DJ
231 /* The frame base for this frame is just prev_sp - frame size.
232 FRAMESIZE is the distance from the frame pointer to the
233 initial stack pointer. */
eb5492fa 234
c3b4394c 235 int framesize;
eb5492fa
DJ
236
237 /* The register used to hold the frame pointer for this frame. */
c3b4394c 238 int framereg;
eb5492fa
DJ
239
240 /* Saved register offsets. */
241 struct trad_frame_saved_reg *saved_regs;
c3b4394c 242};
ed9a39eb 243
bc90b915
FN
244/* Addresses for calling Thumb functions have the bit 0 set.
245 Here are some macros to test, set, or clear bit 0 of addresses. */
246#define IS_THUMB_ADDR(addr) ((addr) & 1)
247#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
248#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
249
94c30b78 250/* Set to true if the 32-bit mode is in use. */
c906108c
SS
251
252int arm_apcs_32 = 1;
253
b39cc962
DJ
254/* Determine if FRAME is executing in Thumb mode. */
255
256static int
257arm_frame_is_thumb (struct frame_info *frame)
258{
259 CORE_ADDR cpsr;
260
261 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
262 directly (from a signal frame or dummy frame) or by interpreting
263 the saved LR (from a prologue or DWARF frame). So consult it and
264 trust the unwinders. */
265 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
266
267 return (cpsr & CPSR_T) != 0;
268}
269
60c5725c
DJ
270/* Callback for VEC_lower_bound. */
271
272static inline int
273arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
274 const struct arm_mapping_symbol *rhs)
275{
276 return lhs->value < rhs->value;
277}
278
ed9a39eb 279/* Determine if the program counter specified in MEMADDR is in a Thumb
b39cc962
DJ
280 function. This function should be called for addresses unrelated to
281 any executing frame; otherwise, prefer arm_frame_is_thumb. */
c906108c 282
ad527d2e 283static int
2a451106 284arm_pc_is_thumb (CORE_ADDR memaddr)
c906108c 285{
60c5725c 286 struct obj_section *sec;
c5aa993b 287 struct minimal_symbol *sym;
c906108c 288
ed9a39eb 289 /* If bit 0 of the address is set, assume this is a Thumb address. */
c906108c
SS
290 if (IS_THUMB_ADDR (memaddr))
291 return 1;
292
0428b8f5
DJ
293 /* If the user wants to override the symbol table, let him. */
294 if (strcmp (arm_force_mode_string, "arm") == 0)
295 return 0;
296 if (strcmp (arm_force_mode_string, "thumb") == 0)
297 return 1;
298
60c5725c
DJ
299 /* If there are mapping symbols, consult them. */
300 sec = find_pc_section (memaddr);
301 if (sec != NULL)
302 {
303 struct arm_per_objfile *data;
304 VEC(arm_mapping_symbol_s) *map;
aded6f54
PA
305 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
306 0 };
60c5725c
DJ
307 unsigned int idx;
308
309 data = objfile_data (sec->objfile, arm_objfile_data_key);
310 if (data != NULL)
311 {
312 map = data->section_maps[sec->the_bfd_section->index];
313 if (!VEC_empty (arm_mapping_symbol_s, map))
314 {
315 struct arm_mapping_symbol *map_sym;
316
317 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
318 arm_compare_mapping_symbols);
319
320 /* VEC_lower_bound finds the earliest ordered insertion
321 point. If the following symbol starts at this exact
322 address, we use that; otherwise, the preceding
323 mapping symbol covers this address. */
324 if (idx < VEC_length (arm_mapping_symbol_s, map))
325 {
326 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
327 if (map_sym->value == map_key.value)
328 return map_sym->type == 't';
329 }
330
331 if (idx > 0)
332 {
333 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
334 return map_sym->type == 't';
335 }
336 }
337 }
338 }
339
ed9a39eb 340 /* Thumb functions have a "special" bit set in minimal symbols. */
c906108c
SS
341 sym = lookup_minimal_symbol_by_pc (memaddr);
342 if (sym)
0428b8f5
DJ
343 return (MSYMBOL_IS_SPECIAL (sym));
344
345 /* If the user wants to override the fallback mode, let them. */
346 if (strcmp (arm_fallback_mode_string, "arm") == 0)
347 return 0;
348 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
349 return 1;
350
351 /* If we couldn't find any symbol, but we're talking to a running
352 target, then trust the current value of $cpsr. This lets
353 "display/i $pc" always show the correct mode (though if there is
354 a symbol table we will not reach here, so it still may not be
355 displayed in the mode it will be executed). */
356 if (target_has_registers)
357 return arm_frame_is_thumb (get_current_frame ());
358
359 /* Otherwise we're out of luck; we assume ARM. */
360 return 0;
c906108c
SS
361}
362
181c1381 363/* Remove useless bits from addresses in a running program. */
34e8f22d 364static CORE_ADDR
24568a2c 365arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
c906108c 366{
a3a2ee65 367 if (arm_apcs_32)
dd6be234 368 return UNMAKE_THUMB_ADDR (val);
c906108c 369 else
a3a2ee65 370 return (val & 0x03fffffc);
c906108c
SS
371}
372
181c1381
RE
373/* When reading symbols, we need to zap the low bit of the address,
374 which may be set to 1 for Thumb functions. */
34e8f22d 375static CORE_ADDR
24568a2c 376arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
181c1381
RE
377{
378 return val & ~1;
379}
380
29d73ae4
DJ
381/* Analyze a Thumb prologue, looking for a recognizable stack frame
382 and frame pointer. Scan until we encounter a store that could
383 clobber the stack frame unexpectedly, or an unknown instruction. */
c906108c
SS
384
385static CORE_ADDR
29d73ae4
DJ
386thumb_analyze_prologue (struct gdbarch *gdbarch,
387 CORE_ADDR start, CORE_ADDR limit,
388 struct arm_prologue_cache *cache)
c906108c 389{
29d73ae4
DJ
390 int i;
391 pv_t regs[16];
392 struct pv_area *stack;
393 struct cleanup *back_to;
394 CORE_ADDR offset;
da3c6d4a 395
29d73ae4
DJ
396 for (i = 0; i < 16; i++)
397 regs[i] = pv_register (i, 0);
55f960e1 398 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
29d73ae4
DJ
399 back_to = make_cleanup_free_pv_area (stack);
400
29d73ae4 401 while (start < limit)
c906108c 402 {
29d73ae4
DJ
403 unsigned short insn;
404
405 insn = read_memory_unsigned_integer (start, 2);
c906108c 406
9d4fde75
SS
407 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
408 insn = SWAP_SHORT (insn);
409
94c30b78 410 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
da59e081 411 {
29d73ae4
DJ
412 int regno;
413 int mask;
4be43953
DJ
414
415 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
416 break;
29d73ae4
DJ
417
418 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
419 whether to save LR (R14). */
420 mask = (insn & 0xff) | ((insn & 0x100) << 6);
421
422 /* Calculate offsets of saved R0-R7 and LR. */
423 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
424 if (mask & (1 << regno))
425 {
29d73ae4
DJ
426 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
427 -4);
428 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
429 }
da59e081 430 }
da3c6d4a
MS
431 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
432 sub sp, #simm */
da59e081 433 {
29d73ae4
DJ
434 offset = (insn & 0x7f) << 2; /* get scaled offset */
435 if (insn & 0x80) /* Check for SUB. */
436 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
437 -offset);
da59e081 438 else
29d73ae4
DJ
439 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
440 offset);
da59e081
JM
441 }
442 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
29d73ae4
DJ
443 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
444 (insn & 0xff) << 2);
445 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
da59e081 446 {
29d73ae4
DJ
447 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
448 int src_reg = (insn & 0x78) >> 3;
449 regs[dst_reg] = regs[src_reg];
da59e081 450 }
29d73ae4 451 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
da59e081 452 {
29d73ae4
DJ
453 /* Handle stores to the stack. Normally pushes are used,
454 but with GCC -mtpcs-frame, there may be other stores
455 in the prologue to create the frame. */
456 int regno = (insn >> 8) & 0x7;
457 pv_t addr;
458
459 offset = (insn & 0xff) << 2;
460 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
461
462 if (pv_area_store_would_trash (stack, addr))
463 break;
464
465 pv_area_store (stack, addr, 4, regs[regno]);
da59e081 466 }
29d73ae4 467 else
3d74b771 468 {
29d73ae4
DJ
469 /* We don't know what this instruction is. We're finished
470 scanning. NOTE: Recognizing more safe-to-ignore
471 instructions here will improve support for optimized
472 code. */
da3c6d4a 473 break;
3d74b771 474 }
29d73ae4
DJ
475
476 start += 2;
c906108c
SS
477 }
478
29d73ae4
DJ
479 if (cache == NULL)
480 {
481 do_cleanups (back_to);
482 return start;
483 }
484
29d73ae4
DJ
485 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
486 {
487 /* Frame pointer is fp. Frame size is constant. */
488 cache->framereg = ARM_FP_REGNUM;
489 cache->framesize = -regs[ARM_FP_REGNUM].k;
490 }
491 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
492 {
493 /* Frame pointer is r7. Frame size is constant. */
494 cache->framereg = THUMB_FP_REGNUM;
495 cache->framesize = -regs[THUMB_FP_REGNUM].k;
496 }
497 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
498 {
499 /* Try the stack pointer... this is a bit desperate. */
500 cache->framereg = ARM_SP_REGNUM;
501 cache->framesize = -regs[ARM_SP_REGNUM].k;
502 }
503 else
504 {
505 /* We're just out of luck. We don't know where the frame is. */
506 cache->framereg = -1;
507 cache->framesize = 0;
508 }
509
510 for (i = 0; i < 16; i++)
511 if (pv_area_find_reg (stack, gdbarch, i, &offset))
512 cache->saved_regs[i].addr = offset;
513
514 do_cleanups (back_to);
515 return start;
c906108c
SS
516}
517
da3c6d4a
MS
518/* Advance the PC across any function entry prologue instructions to
519 reach some "real" code.
34e8f22d
RE
520
521 The APCS (ARM Procedure Call Standard) defines the following
ed9a39eb 522 prologue:
c906108c 523
c5aa993b
JM
524 mov ip, sp
525 [stmfd sp!, {a1,a2,a3,a4}]
526 stmfd sp!, {...,fp,ip,lr,pc}
ed9a39eb
JM
527 [stfe f7, [sp, #-12]!]
528 [stfe f6, [sp, #-12]!]
529 [stfe f5, [sp, #-12]!]
530 [stfe f4, [sp, #-12]!]
531 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
c906108c 532
34e8f22d 533static CORE_ADDR
6093d2eb 534arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c
SS
535{
536 unsigned long inst;
537 CORE_ADDR skip_pc;
a89fea3c 538 CORE_ADDR func_addr, limit_pc;
c906108c
SS
539 struct symtab_and_line sal;
540
848cfffb 541 /* If we're in a dummy frame, don't even try to skip the prologue. */
d80b854b 542 if (deprecated_pc_in_call_dummy (gdbarch, pc))
848cfffb
AC
543 return pc;
544
a89fea3c
JL
545 /* See if we can determine the end of the prologue via the symbol table.
546 If so, then return either PC, or the PC after the prologue, whichever
547 is greater. */
548 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
c906108c 549 {
d80b854b
UW
550 CORE_ADDR post_prologue_pc
551 = skip_prologue_using_sal (gdbarch, func_addr);
a89fea3c
JL
552 if (post_prologue_pc != 0)
553 return max (pc, post_prologue_pc);
c906108c
SS
554 }
555
a89fea3c
JL
556 /* Can't determine prologue from the symbol table, need to examine
557 instructions. */
c906108c 558
a89fea3c
JL
559 /* Find an upper limit on the function prologue using the debug
560 information. If the debug information could not be used to provide
561 that bound, then use an arbitrary large number as the upper bound. */
b8d5e71d 562 /* Like arm_scan_prologue, stop no later than pc + 64. */
d80b854b 563 limit_pc = skip_prologue_using_sal (gdbarch, pc);
a89fea3c
JL
564 if (limit_pc == 0)
565 limit_pc = pc + 64; /* Magic. */
566
c906108c 567
29d73ae4
DJ
568 /* Check if this is Thumb code. */
569 if (arm_pc_is_thumb (pc))
a89fea3c 570 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
29d73ae4 571
a89fea3c 572 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
f43845b3 573 {
1c5bada0 574 inst = read_memory_unsigned_integer (skip_pc, 4);
f43845b3 575
9d4fde75
SS
576 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
577 inst = SWAP_INT (inst);
578
b8d5e71d
MS
579 /* "mov ip, sp" is no longer a required part of the prologue. */
580 if (inst == 0xe1a0c00d) /* mov ip, sp */
581 continue;
c906108c 582
28cd8767
JG
583 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
584 continue;
585
586 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
587 continue;
588
b8d5e71d
MS
589 /* Some prologues begin with "str lr, [sp, #-4]!". */
590 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
591 continue;
c906108c 592
b8d5e71d
MS
593 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
594 continue;
c906108c 595
b8d5e71d
MS
596 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
597 continue;
11d3b27d 598
b8d5e71d
MS
599 /* Any insns after this point may float into the code, if it makes
600 for better instruction scheduling, so we skip them only if we
601 find them, but still consider the function to be frame-ful. */
f43845b3 602
b8d5e71d
MS
603 /* We may have either one sfmfd instruction here, or several stfe
604 insns, depending on the version of floating point code we
605 support. */
606 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
607 continue;
608
609 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
610 continue;
611
612 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
613 continue;
614
615 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
616 continue;
617
618 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
619 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
620 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
621 continue;
622
623 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
624 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
625 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
626 continue;
627
628 /* Un-recognized instruction; stop scanning. */
629 break;
f43845b3 630 }
c906108c 631
b8d5e71d 632 return skip_pc; /* End of prologue */
c906108c 633}
94c30b78 634
c5aa993b 635/* *INDENT-OFF* */
c906108c
SS
636/* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
637 This function decodes a Thumb function prologue to determine:
638 1) the size of the stack frame
639 2) which registers are saved on it
640 3) the offsets of saved regs
641 4) the offset from the stack pointer to the frame pointer
c906108c 642
da59e081
JM
643 A typical Thumb function prologue would create this stack frame
644 (offsets relative to FP)
c906108c
SS
645 old SP -> 24 stack parameters
646 20 LR
647 16 R7
648 R7 -> 0 local variables (16 bytes)
649 SP -> -12 additional stack space (12 bytes)
650 The frame size would thus be 36 bytes, and the frame offset would be
da59e081
JM
651 12 bytes. The frame register is R7.
652
da3c6d4a
MS
653 The comments for thumb_skip_prolog() describe the algorithm we use
654 to detect the end of the prolog. */
c5aa993b
JM
655/* *INDENT-ON* */
656
c906108c 657static void
be8626e0 658thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
b39cc962 659 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
c906108c
SS
660{
661 CORE_ADDR prologue_start;
662 CORE_ADDR prologue_end;
663 CORE_ADDR current_pc;
c906108c 664
b39cc962
DJ
665 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
666 &prologue_end))
c906108c
SS
667 {
668 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
669
94c30b78 670 if (sal.line == 0) /* no line info, use current PC */
eb5492fa 671 prologue_end = prev_pc;
c906108c 672 else if (sal.end < prologue_end) /* next line begins after fn end */
94c30b78 673 prologue_end = sal.end; /* (probably means no prologue) */
c906108c
SS
674 }
675 else
f7060f85
DJ
676 /* We're in the boondocks: we have no idea where the start of the
677 function is. */
678 return;
c906108c 679
eb5492fa 680 prologue_end = min (prologue_end, prev_pc);
c906108c 681
be8626e0 682 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
c906108c
SS
683}
684
ed9a39eb 685/* This function decodes an ARM function prologue to determine:
c5aa993b
JM
686 1) the size of the stack frame
687 2) which registers are saved on it
688 3) the offsets of saved regs
689 4) the offset from the stack pointer to the frame pointer
c906108c
SS
690 This information is stored in the "extra" fields of the frame_info.
691
96baa820
JM
692 There are two basic forms for the ARM prologue. The fixed argument
693 function call will look like:
ed9a39eb
JM
694
695 mov ip, sp
696 stmfd sp!, {fp, ip, lr, pc}
697 sub fp, ip, #4
698 [sub sp, sp, #4]
96baa820 699
c906108c 700 Which would create this stack frame (offsets relative to FP):
ed9a39eb
JM
701 IP -> 4 (caller's stack)
702 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
703 -4 LR (return address in caller)
704 -8 IP (copy of caller's SP)
705 -12 FP (caller's FP)
706 SP -> -28 Local variables
707
c906108c 708 The frame size would thus be 32 bytes, and the frame offset would be
96baa820
JM
709 28 bytes. The stmfd call can also save any of the vN registers it
710 plans to use, which increases the frame size accordingly.
711
712 Note: The stored PC is 8 off of the STMFD instruction that stored it
713 because the ARM Store instructions always store PC + 8 when you read
714 the PC register.
ed9a39eb 715
96baa820
JM
716 A variable argument function call will look like:
717
ed9a39eb
JM
718 mov ip, sp
719 stmfd sp!, {a1, a2, a3, a4}
720 stmfd sp!, {fp, ip, lr, pc}
721 sub fp, ip, #20
722
96baa820 723 Which would create this stack frame (offsets relative to FP):
ed9a39eb
JM
724 IP -> 20 (caller's stack)
725 16 A4
726 12 A3
727 8 A2
728 4 A1
729 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
730 -4 LR (return address in caller)
731 -8 IP (copy of caller's SP)
732 -12 FP (caller's FP)
733 SP -> -28 Local variables
96baa820
JM
734
735 The frame size would thus be 48 bytes, and the frame offset would be
736 28 bytes.
737
738 There is another potential complication, which is that the optimizer
739 will try to separate the store of fp in the "stmfd" instruction from
740 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
741 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
742
743 Also, note, the original version of the ARM toolchain claimed that there
744 should be an
745
746 instruction at the end of the prologue. I have never seen GCC produce
747 this, and the ARM docs don't mention it. We still test for it below in
748 case it happens...
ed9a39eb
JM
749
750 */
c906108c
SS
751
752static void
a262aec2 753arm_scan_prologue (struct frame_info *this_frame,
2af46ca0 754 struct arm_prologue_cache *cache)
c906108c 755{
a262aec2 756 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4be43953 757 int regno;
c906108c 758 CORE_ADDR prologue_start, prologue_end, current_pc;
a262aec2 759 CORE_ADDR prev_pc = get_frame_pc (this_frame);
b39cc962 760 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
4be43953
DJ
761 pv_t regs[ARM_FPS_REGNUM];
762 struct pv_area *stack;
763 struct cleanup *back_to;
764 CORE_ADDR offset;
c906108c 765
c906108c 766 /* Assume there is no frame until proven otherwise. */
9b8d791a
DJ
767 cache->framereg = ARM_SP_REGNUM;
768 cache->framesize = 0;
c906108c
SS
769
770 /* Check for Thumb prologue. */
b39cc962 771 if (arm_frame_is_thumb (this_frame))
c906108c 772 {
b39cc962 773 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
c906108c
SS
774 return;
775 }
776
777 /* Find the function prologue. If we can't find the function in
778 the symbol table, peek in the stack frame to find the PC. */
b39cc962
DJ
779 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
780 &prologue_end))
c906108c 781 {
2a451106
KB
782 /* One way to find the end of the prologue (which works well
783 for unoptimized code) is to do the following:
784
785 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
786
787 if (sal.line == 0)
eb5492fa 788 prologue_end = prev_pc;
2a451106
KB
789 else if (sal.end < prologue_end)
790 prologue_end = sal.end;
791
792 This mechanism is very accurate so long as the optimizer
793 doesn't move any instructions from the function body into the
794 prologue. If this happens, sal.end will be the last
795 instruction in the first hunk of prologue code just before
796 the first instruction that the scheduler has moved from
797 the body to the prologue.
798
799 In order to make sure that we scan all of the prologue
800 instructions, we use a slightly less accurate mechanism which
801 may scan more than necessary. To help compensate for this
802 lack of accuracy, the prologue scanning loop below contains
803 several clauses which'll cause the loop to terminate early if
804 an implausible prologue instruction is encountered.
805
806 The expression
807
808 prologue_start + 64
809
810 is a suitable endpoint since it accounts for the largest
811 possible prologue plus up to five instructions inserted by
94c30b78 812 the scheduler. */
2a451106
KB
813
814 if (prologue_end > prologue_start + 64)
815 {
94c30b78 816 prologue_end = prologue_start + 64; /* See above. */
2a451106 817 }
c906108c
SS
818 }
819 else
820 {
eb5492fa
DJ
821 /* We have no symbol information. Our only option is to assume this
822 function has a standard stack frame and the normal frame register.
823 Then, we can find the value of our frame pointer on entrance to
824 the callee (or at the present moment if this is the innermost frame).
825 The value stored there should be the address of the stmfd + 8. */
826 CORE_ADDR frame_loc;
827 LONGEST return_value;
828
a262aec2 829 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
eb5492fa 830 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
16a0f3e7
EZ
831 return;
832 else
833 {
bf6ae464 834 prologue_start = gdbarch_addr_bits_remove
2af46ca0 835 (gdbarch, return_value) - 8;
94c30b78 836 prologue_end = prologue_start + 64; /* See above. */
16a0f3e7 837 }
c906108c
SS
838 }
839
eb5492fa
DJ
840 if (prev_pc < prologue_end)
841 prologue_end = prev_pc;
842
c906108c 843 /* Now search the prologue looking for instructions that set up the
96baa820 844 frame pointer, adjust the stack pointer, and save registers.
ed9a39eb 845
96baa820
JM
846 Be careful, however, and if it doesn't look like a prologue,
847 don't try to scan it. If, for instance, a frameless function
848 begins with stmfd sp!, then we will tell ourselves there is
b8d5e71d 849 a frame, which will confuse stack traceback, as well as "finish"
96baa820
JM
850 and other operations that rely on a knowledge of the stack
851 traceback.
852
853 In the APCS, the prologue should start with "mov ip, sp" so
f43845b3 854 if we don't see this as the first insn, we will stop.
c906108c 855
f43845b3
MS
856 [Note: This doesn't seem to be true any longer, so it's now an
857 optional part of the prologue. - Kevin Buettner, 2001-11-20]
c906108c 858
f43845b3
MS
859 [Note further: The "mov ip,sp" only seems to be missing in
860 frameless functions at optimization level "-O2" or above,
861 in which case it is often (but not always) replaced by
b8d5e71d 862 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
d4473757 863
4be43953
DJ
864 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
865 regs[regno] = pv_register (regno, 0);
55f960e1 866 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
4be43953
DJ
867 back_to = make_cleanup_free_pv_area (stack);
868
94c30b78
MS
869 for (current_pc = prologue_start;
870 current_pc < prologue_end;
f43845b3 871 current_pc += 4)
96baa820 872 {
d4473757
KB
873 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
874
9d4fde75
SS
875 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
876 insn = SWAP_INT (insn);
877
94c30b78 878 if (insn == 0xe1a0c00d) /* mov ip, sp */
f43845b3 879 {
4be43953 880 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
28cd8767
JG
881 continue;
882 }
883 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
884 {
885 unsigned imm = insn & 0xff; /* immediate value */
886 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
887 imm = (imm >> rot) | (imm << (32 - rot));
4be43953 888 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
28cd8767
JG
889 continue;
890 }
891 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
892 {
893 unsigned imm = insn & 0xff; /* immediate value */
894 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
895 imm = (imm >> rot) | (imm << (32 - rot));
4be43953 896 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
f43845b3
MS
897 continue;
898 }
94c30b78 899 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
f43845b3 900 {
4be43953
DJ
901 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
902 break;
903 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
904 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
f43845b3
MS
905 continue;
906 }
907 else if ((insn & 0xffff0000) == 0xe92d0000)
d4473757
KB
908 /* stmfd sp!, {..., fp, ip, lr, pc}
909 or
910 stmfd sp!, {a1, a2, a3, a4} */
c906108c 911 {
d4473757 912 int mask = insn & 0xffff;
ed9a39eb 913
4be43953
DJ
914 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
915 break;
916
94c30b78 917 /* Calculate offsets of saved registers. */
34e8f22d 918 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
d4473757
KB
919 if (mask & (1 << regno))
920 {
4be43953
DJ
921 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
922 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
d4473757
KB
923 }
924 }
b8d5e71d
MS
925 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
926 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
927 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
928 {
929 /* No need to add this to saved_regs -- it's just an arg reg. */
930 continue;
931 }
932 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
933 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
934 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
f43845b3
MS
935 {
936 /* No need to add this to saved_regs -- it's just an arg reg. */
937 continue;
938 }
d4473757
KB
939 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
940 {
94c30b78
MS
941 unsigned imm = insn & 0xff; /* immediate value */
942 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
d4473757 943 imm = (imm >> rot) | (imm << (32 - rot));
4be43953 944 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
d4473757
KB
945 }
946 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
947 {
94c30b78
MS
948 unsigned imm = insn & 0xff; /* immediate value */
949 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
d4473757 950 imm = (imm >> rot) | (imm << (32 - rot));
4be43953 951 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
d4473757 952 }
ff6f572f 953 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
2af46ca0 954 && gdbarch_tdep (gdbarch)->have_fpa_registers)
d4473757 955 {
4be43953
DJ
956 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
957 break;
958
959 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
34e8f22d 960 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
4be43953 961 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
d4473757 962 }
ff6f572f 963 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
2af46ca0 964 && gdbarch_tdep (gdbarch)->have_fpa_registers)
d4473757
KB
965 {
966 int n_saved_fp_regs;
967 unsigned int fp_start_reg, fp_bound_reg;
968
4be43953
DJ
969 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
970 break;
971
94c30b78 972 if ((insn & 0x800) == 0x800) /* N0 is set */
96baa820 973 {
d4473757
KB
974 if ((insn & 0x40000) == 0x40000) /* N1 is set */
975 n_saved_fp_regs = 3;
976 else
977 n_saved_fp_regs = 1;
96baa820 978 }
d4473757 979 else
96baa820 980 {
d4473757
KB
981 if ((insn & 0x40000) == 0x40000) /* N1 is set */
982 n_saved_fp_regs = 2;
983 else
984 n_saved_fp_regs = 4;
96baa820 985 }
d4473757 986
34e8f22d 987 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
d4473757
KB
988 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
989 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
96baa820 990 {
4be43953
DJ
991 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
992 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
993 regs[fp_start_reg++]);
96baa820 994 }
c906108c 995 }
d4473757 996 else if ((insn & 0xf0000000) != 0xe0000000)
94c30b78 997 break; /* Condition not true, exit early */
b8d5e71d 998 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
94c30b78 999 break; /* Don't scan past a block load */
d4473757
KB
1000 else
1001 /* The optimizer might shove anything into the prologue,
94c30b78 1002 so we just skip what we don't recognize. */
d4473757 1003 continue;
c906108c
SS
1004 }
1005
4be43953
DJ
1006 /* The frame size is just the distance from the frame register
1007 to the original stack pointer. */
1008 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1009 {
1010 /* Frame pointer is fp. */
1011 cache->framereg = ARM_FP_REGNUM;
1012 cache->framesize = -regs[ARM_FP_REGNUM].k;
1013 }
1014 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1015 {
1016 /* Try the stack pointer... this is a bit desperate. */
1017 cache->framereg = ARM_SP_REGNUM;
1018 cache->framesize = -regs[ARM_SP_REGNUM].k;
1019 }
d4473757 1020 else
4be43953
DJ
1021 {
1022 /* We're just out of luck. We don't know where the frame is. */
1023 cache->framereg = -1;
1024 cache->framesize = 0;
1025 }
1026
1027 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1028 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1029 cache->saved_regs[regno].addr = offset;
1030
1031 do_cleanups (back_to);
c906108c
SS
1032}
1033
eb5492fa 1034static struct arm_prologue_cache *
a262aec2 1035arm_make_prologue_cache (struct frame_info *this_frame)
c906108c 1036{
eb5492fa
DJ
1037 int reg;
1038 struct arm_prologue_cache *cache;
1039 CORE_ADDR unwound_fp;
c5aa993b 1040
35d5d4ee 1041 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
a262aec2 1042 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
c906108c 1043
a262aec2 1044 arm_scan_prologue (this_frame, cache);
848cfffb 1045
a262aec2 1046 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
eb5492fa
DJ
1047 if (unwound_fp == 0)
1048 return cache;
c906108c 1049
4be43953 1050 cache->prev_sp = unwound_fp + cache->framesize;
c906108c 1051
eb5492fa
DJ
1052 /* Calculate actual addresses of saved registers using offsets
1053 determined by arm_scan_prologue. */
a262aec2 1054 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
e28a332c 1055 if (trad_frame_addr_p (cache->saved_regs, reg))
eb5492fa
DJ
1056 cache->saved_regs[reg].addr += cache->prev_sp;
1057
1058 return cache;
c906108c
SS
1059}
1060
eb5492fa
DJ
1061/* Our frame ID for a normal frame is the current function's starting PC
1062 and the caller's SP when we were called. */
c906108c 1063
148754e5 1064static void
a262aec2 1065arm_prologue_this_id (struct frame_info *this_frame,
eb5492fa
DJ
1066 void **this_cache,
1067 struct frame_id *this_id)
c906108c 1068{
eb5492fa
DJ
1069 struct arm_prologue_cache *cache;
1070 struct frame_id id;
2c404490 1071 CORE_ADDR pc, func;
f079148d 1072
eb5492fa 1073 if (*this_cache == NULL)
a262aec2 1074 *this_cache = arm_make_prologue_cache (this_frame);
eb5492fa 1075 cache = *this_cache;
2a451106 1076
2c404490
DJ
1077 /* This is meant to halt the backtrace at "_start". */
1078 pc = get_frame_pc (this_frame);
1079 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
eb5492fa 1080 return;
5a203e44 1081
eb5492fa
DJ
1082 /* If we've hit a wall, stop. */
1083 if (cache->prev_sp == 0)
1084 return;
24de872b 1085
2c404490 1086 func = get_frame_func (this_frame);
eb5492fa 1087 id = frame_id_build (cache->prev_sp, func);
eb5492fa 1088 *this_id = id;
c906108c
SS
1089}
1090
a262aec2
DJ
1091static struct value *
1092arm_prologue_prev_register (struct frame_info *this_frame,
eb5492fa 1093 void **this_cache,
a262aec2 1094 int prev_regnum)
24de872b 1095{
24568a2c 1096 struct gdbarch *gdbarch = get_frame_arch (this_frame);
24de872b
DJ
1097 struct arm_prologue_cache *cache;
1098
eb5492fa 1099 if (*this_cache == NULL)
a262aec2 1100 *this_cache = arm_make_prologue_cache (this_frame);
eb5492fa 1101 cache = *this_cache;
24de872b 1102
eb5492fa 1103 /* If we are asked to unwind the PC, then we need to return the LR
b39cc962
DJ
1104 instead. The prologue may save PC, but it will point into this
1105 frame's prologue, not the next frame's resume location. Also
1106 strip the saved T bit. A valid LR may have the low bit set, but
1107 a valid PC never does. */
eb5492fa 1108 if (prev_regnum == ARM_PC_REGNUM)
b39cc962
DJ
1109 {
1110 CORE_ADDR lr;
1111
1112 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1113 return frame_unwind_got_constant (this_frame, prev_regnum,
24568a2c 1114 arm_addr_bits_remove (gdbarch, lr));
b39cc962 1115 }
24de872b 1116
eb5492fa 1117 /* SP is generally not saved to the stack, but this frame is
a262aec2 1118 identified by the next frame's stack pointer at the time of the call.
eb5492fa
DJ
1119 The value was already reconstructed into PREV_SP. */
1120 if (prev_regnum == ARM_SP_REGNUM)
a262aec2 1121 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
eb5492fa 1122
b39cc962
DJ
1123 /* The CPSR may have been changed by the call instruction and by the
1124 called function. The only bit we can reconstruct is the T bit,
1125 by checking the low bit of LR as of the call. This is a reliable
1126 indicator of Thumb-ness except for some ARM v4T pre-interworking
1127 Thumb code, which could get away with a clear low bit as long as
1128 the called function did not use bx. Guess that all other
1129 bits are unchanged; the condition flags are presumably lost,
1130 but the processor status is likely valid. */
1131 if (prev_regnum == ARM_PS_REGNUM)
1132 {
1133 CORE_ADDR lr, cpsr;
1134
1135 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1136 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1137 if (IS_THUMB_ADDR (lr))
1138 cpsr |= CPSR_T;
1139 else
1140 cpsr &= ~CPSR_T;
1141 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1142 }
1143
a262aec2
DJ
1144 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1145 prev_regnum);
eb5492fa
DJ
1146}
1147
1148struct frame_unwind arm_prologue_unwind = {
1149 NORMAL_FRAME,
1150 arm_prologue_this_id,
a262aec2
DJ
1151 arm_prologue_prev_register,
1152 NULL,
1153 default_frame_sniffer
eb5492fa
DJ
1154};
1155
909cf6ea 1156static struct arm_prologue_cache *
a262aec2 1157arm_make_stub_cache (struct frame_info *this_frame)
909cf6ea
DJ
1158{
1159 int reg;
1160 struct arm_prologue_cache *cache;
1161 CORE_ADDR unwound_fp;
1162
35d5d4ee 1163 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
a262aec2 1164 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
909cf6ea 1165
a262aec2 1166 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
909cf6ea
DJ
1167
1168 return cache;
1169}
1170
1171/* Our frame ID for a stub frame is the current SP and LR. */
1172
1173static void
a262aec2 1174arm_stub_this_id (struct frame_info *this_frame,
909cf6ea
DJ
1175 void **this_cache,
1176 struct frame_id *this_id)
1177{
1178 struct arm_prologue_cache *cache;
1179
1180 if (*this_cache == NULL)
a262aec2 1181 *this_cache = arm_make_stub_cache (this_frame);
909cf6ea
DJ
1182 cache = *this_cache;
1183
a262aec2 1184 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
909cf6ea
DJ
1185}
1186
a262aec2
DJ
1187static int
1188arm_stub_unwind_sniffer (const struct frame_unwind *self,
1189 struct frame_info *this_frame,
1190 void **this_prologue_cache)
909cf6ea 1191{
93d42b30 1192 CORE_ADDR addr_in_block;
909cf6ea
DJ
1193 char dummy[4];
1194
a262aec2 1195 addr_in_block = get_frame_address_in_block (this_frame);
93d42b30 1196 if (in_plt_section (addr_in_block, NULL)
a262aec2
DJ
1197 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1198 return 1;
909cf6ea 1199
a262aec2 1200 return 0;
909cf6ea
DJ
1201}
1202
a262aec2
DJ
1203struct frame_unwind arm_stub_unwind = {
1204 NORMAL_FRAME,
1205 arm_stub_this_id,
1206 arm_prologue_prev_register,
1207 NULL,
1208 arm_stub_unwind_sniffer
1209};
1210
24de872b 1211static CORE_ADDR
a262aec2 1212arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
24de872b
DJ
1213{
1214 struct arm_prologue_cache *cache;
1215
eb5492fa 1216 if (*this_cache == NULL)
a262aec2 1217 *this_cache = arm_make_prologue_cache (this_frame);
eb5492fa
DJ
1218 cache = *this_cache;
1219
4be43953 1220 return cache->prev_sp - cache->framesize;
24de872b
DJ
1221}
1222
eb5492fa
DJ
1223struct frame_base arm_normal_base = {
1224 &arm_prologue_unwind,
1225 arm_normal_frame_base,
1226 arm_normal_frame_base,
1227 arm_normal_frame_base
1228};
1229
a262aec2 1230/* Assuming THIS_FRAME is a dummy, return the frame ID of that
eb5492fa
DJ
1231 dummy frame. The frame ID's base needs to match the TOS value
1232 saved by save_dummy_frame_tos() and returned from
1233 arm_push_dummy_call, and the PC needs to match the dummy frame's
1234 breakpoint. */
c906108c 1235
eb5492fa 1236static struct frame_id
a262aec2 1237arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
c906108c 1238{
a262aec2
DJ
1239 return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
1240 get_frame_pc (this_frame));
eb5492fa 1241}
c3b4394c 1242
eb5492fa
DJ
1243/* Given THIS_FRAME, find the previous frame's resume PC (which will
1244 be used to construct the previous frame's ID, after looking up the
1245 containing function). */
c3b4394c 1246
eb5492fa
DJ
1247static CORE_ADDR
1248arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1249{
1250 CORE_ADDR pc;
1251 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
24568a2c 1252 return arm_addr_bits_remove (gdbarch, pc);
eb5492fa
DJ
1253}
1254
1255static CORE_ADDR
1256arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1257{
1258 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
c906108c
SS
1259}
1260
b39cc962
DJ
1261static struct value *
1262arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
1263 int regnum)
1264{
24568a2c 1265 struct gdbarch * gdbarch = get_frame_arch (this_frame);
b39cc962
DJ
1266 CORE_ADDR lr, cpsr;
1267
1268 switch (regnum)
1269 {
1270 case ARM_PC_REGNUM:
1271 /* The PC is normally copied from the return column, which
1272 describes saves of LR. However, that version may have an
1273 extra bit set to indicate Thumb state. The bit is not
1274 part of the PC. */
1275 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1276 return frame_unwind_got_constant (this_frame, regnum,
24568a2c 1277 arm_addr_bits_remove (gdbarch, lr));
b39cc962
DJ
1278
1279 case ARM_PS_REGNUM:
1280 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
ca38c58e 1281 cpsr = get_frame_register_unsigned (this_frame, regnum);
b39cc962
DJ
1282 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1283 if (IS_THUMB_ADDR (lr))
1284 cpsr |= CPSR_T;
1285 else
1286 cpsr &= ~CPSR_T;
ca38c58e 1287 return frame_unwind_got_constant (this_frame, regnum, cpsr);
b39cc962
DJ
1288
1289 default:
1290 internal_error (__FILE__, __LINE__,
1291 _("Unexpected register %d"), regnum);
1292 }
1293}
1294
1295static void
1296arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1297 struct dwarf2_frame_state_reg *reg,
1298 struct frame_info *this_frame)
1299{
1300 switch (regnum)
1301 {
1302 case ARM_PC_REGNUM:
1303 case ARM_PS_REGNUM:
1304 reg->how = DWARF2_FRAME_REG_FN;
1305 reg->loc.fn = arm_dwarf2_prev_register;
1306 break;
1307 case ARM_SP_REGNUM:
1308 reg->how = DWARF2_FRAME_REG_CFA;
1309 break;
1310 }
1311}
1312
2dd604e7
RE
1313/* When arguments must be pushed onto the stack, they go on in reverse
1314 order. The code below implements a FILO (stack) to do this. */
1315
1316struct stack_item
1317{
1318 int len;
1319 struct stack_item *prev;
1320 void *data;
1321};
1322
1323static struct stack_item *
1324push_stack_item (struct stack_item *prev, void *contents, int len)
1325{
1326 struct stack_item *si;
1327 si = xmalloc (sizeof (struct stack_item));
226c7fbc 1328 si->data = xmalloc (len);
2dd604e7
RE
1329 si->len = len;
1330 si->prev = prev;
1331 memcpy (si->data, contents, len);
1332 return si;
1333}
1334
1335static struct stack_item *
1336pop_stack_item (struct stack_item *si)
1337{
1338 struct stack_item *dead = si;
1339 si = si->prev;
1340 xfree (dead->data);
1341 xfree (dead);
1342 return si;
1343}
1344
2af48f68
PB
1345
1346/* Return the alignment (in bytes) of the given type. */
1347
1348static int
1349arm_type_align (struct type *t)
1350{
1351 int n;
1352 int align;
1353 int falign;
1354
1355 t = check_typedef (t);
1356 switch (TYPE_CODE (t))
1357 {
1358 default:
1359 /* Should never happen. */
1360 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1361 return 4;
1362
1363 case TYPE_CODE_PTR:
1364 case TYPE_CODE_ENUM:
1365 case TYPE_CODE_INT:
1366 case TYPE_CODE_FLT:
1367 case TYPE_CODE_SET:
1368 case TYPE_CODE_RANGE:
1369 case TYPE_CODE_BITSTRING:
1370 case TYPE_CODE_REF:
1371 case TYPE_CODE_CHAR:
1372 case TYPE_CODE_BOOL:
1373 return TYPE_LENGTH (t);
1374
1375 case TYPE_CODE_ARRAY:
1376 case TYPE_CODE_COMPLEX:
1377 /* TODO: What about vector types? */
1378 return arm_type_align (TYPE_TARGET_TYPE (t));
1379
1380 case TYPE_CODE_STRUCT:
1381 case TYPE_CODE_UNION:
1382 align = 1;
1383 for (n = 0; n < TYPE_NFIELDS (t); n++)
1384 {
1385 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1386 if (falign > align)
1387 align = falign;
1388 }
1389 return align;
1390 }
1391}
1392
2dd604e7
RE
1393/* We currently only support passing parameters in integer registers. This
1394 conforms with GCC's default model. Several other variants exist and
1395 we should probably support some of them based on the selected ABI. */
1396
1397static CORE_ADDR
7d9b040b 1398arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
6a65450a
AC
1399 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1400 struct value **args, CORE_ADDR sp, int struct_return,
1401 CORE_ADDR struct_addr)
2dd604e7
RE
1402{
1403 int argnum;
1404 int argreg;
1405 int nstack;
1406 struct stack_item *si = NULL;
1407
6a65450a
AC
1408 /* Set the return address. For the ARM, the return breakpoint is
1409 always at BP_ADDR. */
2dd604e7 1410 /* XXX Fix for Thumb. */
6a65450a 1411 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
2dd604e7
RE
1412
1413 /* Walk through the list of args and determine how large a temporary
1414 stack is required. Need to take care here as structs may be
1415 passed on the stack, and we have to to push them. */
1416 nstack = 0;
1417
1418 argreg = ARM_A1_REGNUM;
1419 nstack = 0;
1420
2dd604e7
RE
1421 /* The struct_return pointer occupies the first parameter
1422 passing register. */
1423 if (struct_return)
1424 {
1425 if (arm_debug)
1426 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
2af46ca0 1427 gdbarch_register_name (gdbarch, argreg),
c9f4d572 1428 paddr (struct_addr));
2dd604e7
RE
1429 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1430 argreg++;
1431 }
1432
1433 for (argnum = 0; argnum < nargs; argnum++)
1434 {
1435 int len;
1436 struct type *arg_type;
1437 struct type *target_type;
1438 enum type_code typecode;
0fd88904 1439 bfd_byte *val;
2af48f68 1440 int align;
2dd604e7 1441
df407dfe 1442 arg_type = check_typedef (value_type (args[argnum]));
2dd604e7
RE
1443 len = TYPE_LENGTH (arg_type);
1444 target_type = TYPE_TARGET_TYPE (arg_type);
1445 typecode = TYPE_CODE (arg_type);
0fd88904 1446 val = value_contents_writeable (args[argnum]);
2dd604e7 1447
2af48f68
PB
1448 align = arm_type_align (arg_type);
1449 /* Round alignment up to a whole number of words. */
1450 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1451 /* Different ABIs have different maximum alignments. */
1452 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1453 {
1454 /* The APCS ABI only requires word alignment. */
1455 align = INT_REGISTER_SIZE;
1456 }
1457 else
1458 {
1459 /* The AAPCS requires at most doubleword alignment. */
1460 if (align > INT_REGISTER_SIZE * 2)
1461 align = INT_REGISTER_SIZE * 2;
1462 }
1463
1464 /* Push stack padding for dowubleword alignment. */
1465 if (nstack & (align - 1))
1466 {
1467 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1468 nstack += INT_REGISTER_SIZE;
1469 }
1470
1471 /* Doubleword aligned quantities must go in even register pairs. */
1472 if (argreg <= ARM_LAST_ARG_REGNUM
1473 && align > INT_REGISTER_SIZE
1474 && argreg & 1)
1475 argreg++;
1476
2dd604e7
RE
1477 /* If the argument is a pointer to a function, and it is a
1478 Thumb function, create a LOCAL copy of the value and set
1479 the THUMB bit in it. */
1480 if (TYPE_CODE_PTR == typecode
1481 && target_type != NULL
1482 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1483 {
7c0b4a20 1484 CORE_ADDR regval = extract_unsigned_integer (val, len);
2dd604e7
RE
1485 if (arm_pc_is_thumb (regval))
1486 {
1487 val = alloca (len);
fbd9dcd3 1488 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
2dd604e7
RE
1489 }
1490 }
1491
1492 /* Copy the argument to general registers or the stack in
1493 register-sized pieces. Large arguments are split between
1494 registers and stack. */
1495 while (len > 0)
1496 {
f0c9063c 1497 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
2dd604e7
RE
1498
1499 if (argreg <= ARM_LAST_ARG_REGNUM)
1500 {
1501 /* The argument is being passed in a general purpose
1502 register. */
7c0b4a20 1503 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
2af46ca0 1504 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
8bf8793c 1505 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
2dd604e7
RE
1506 if (arm_debug)
1507 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
c9f4d572
UW
1508 argnum,
1509 gdbarch_register_name
2af46ca0 1510 (gdbarch, argreg),
f0c9063c 1511 phex (regval, INT_REGISTER_SIZE));
2dd604e7
RE
1512 regcache_cooked_write_unsigned (regcache, argreg, regval);
1513 argreg++;
1514 }
1515 else
1516 {
1517 /* Push the arguments onto the stack. */
1518 if (arm_debug)
1519 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1520 argnum, nstack);
f0c9063c
UW
1521 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1522 nstack += INT_REGISTER_SIZE;
2dd604e7
RE
1523 }
1524
1525 len -= partial_len;
1526 val += partial_len;
1527 }
1528 }
1529 /* If we have an odd number of words to push, then decrement the stack
1530 by one word now, so first stack argument will be dword aligned. */
1531 if (nstack & 4)
1532 sp -= 4;
1533
1534 while (si)
1535 {
1536 sp -= si->len;
1537 write_memory (sp, si->data, si->len);
1538 si = pop_stack_item (si);
1539 }
1540
1541 /* Finally, update teh SP register. */
1542 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1543
1544 return sp;
1545}
1546
f53f0d0b
PB
1547
1548/* Always align the frame to an 8-byte boundary. This is required on
1549 some platforms and harmless on the rest. */
1550
1551static CORE_ADDR
1552arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1553{
1554 /* Align the stack to eight bytes. */
1555 return sp & ~ (CORE_ADDR) 7;
1556}
1557
c906108c 1558static void
ed9a39eb 1559print_fpu_flags (int flags)
c906108c 1560{
c5aa993b
JM
1561 if (flags & (1 << 0))
1562 fputs ("IVO ", stdout);
1563 if (flags & (1 << 1))
1564 fputs ("DVZ ", stdout);
1565 if (flags & (1 << 2))
1566 fputs ("OFL ", stdout);
1567 if (flags & (1 << 3))
1568 fputs ("UFL ", stdout);
1569 if (flags & (1 << 4))
1570 fputs ("INX ", stdout);
1571 putchar ('\n');
c906108c
SS
1572}
1573
5e74b15c
RE
1574/* Print interesting information about the floating point processor
1575 (if present) or emulator. */
34e8f22d 1576static void
d855c300 1577arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
23e3a7ac 1578 struct frame_info *frame, const char *args)
c906108c 1579{
9c9acae0 1580 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
c5aa993b
JM
1581 int type;
1582
1583 type = (status >> 24) & 127;
edefbb7c
AC
1584 if (status & (1 << 31))
1585 printf (_("Hardware FPU type %d\n"), type);
1586 else
1587 printf (_("Software FPU type %d\n"), type);
1588 /* i18n: [floating point unit] mask */
1589 fputs (_("mask: "), stdout);
c5aa993b 1590 print_fpu_flags (status >> 16);
edefbb7c
AC
1591 /* i18n: [floating point unit] flags */
1592 fputs (_("flags: "), stdout);
c5aa993b 1593 print_fpu_flags (status);
c906108c
SS
1594}
1595
27067745
UW
1596/* Construct the ARM extended floating point type. */
1597static struct type *
1598arm_ext_type (struct gdbarch *gdbarch)
1599{
1600 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1601
1602 if (!tdep->arm_ext_type)
1603 tdep->arm_ext_type
e9bb382b 1604 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
27067745
UW
1605 floatformats_arm_ext);
1606
1607 return tdep->arm_ext_type;
1608}
1609
34e8f22d
RE
1610/* Return the GDB type object for the "standard" data type of data in
1611 register N. */
1612
1613static struct type *
7a5ea0d4 1614arm_register_type (struct gdbarch *gdbarch, int regnum)
032758dc 1615{
34e8f22d 1616 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
27067745 1617 return arm_ext_type (gdbarch);
e4c16157 1618 else if (regnum == ARM_SP_REGNUM)
0dfff4cb 1619 return builtin_type (gdbarch)->builtin_data_ptr;
e4c16157 1620 else if (regnum == ARM_PC_REGNUM)
0dfff4cb 1621 return builtin_type (gdbarch)->builtin_func_ptr;
ff6f572f
DJ
1622 else if (regnum >= ARRAY_SIZE (arm_register_names))
1623 /* These registers are only supported on targets which supply
1624 an XML description. */
df4df182 1625 return builtin_type (gdbarch)->builtin_int0;
032758dc 1626 else
df4df182 1627 return builtin_type (gdbarch)->builtin_uint32;
032758dc
AC
1628}
1629
ff6f572f
DJ
1630/* Map a DWARF register REGNUM onto the appropriate GDB register
1631 number. */
1632
1633static int
d3f73121 1634arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
ff6f572f
DJ
1635{
1636 /* Core integer regs. */
1637 if (reg >= 0 && reg <= 15)
1638 return reg;
1639
1640 /* Legacy FPA encoding. These were once used in a way which
1641 overlapped with VFP register numbering, so their use is
1642 discouraged, but GDB doesn't support the ARM toolchain
1643 which used them for VFP. */
1644 if (reg >= 16 && reg <= 23)
1645 return ARM_F0_REGNUM + reg - 16;
1646
1647 /* New assignments for the FPA registers. */
1648 if (reg >= 96 && reg <= 103)
1649 return ARM_F0_REGNUM + reg - 96;
1650
1651 /* WMMX register assignments. */
1652 if (reg >= 104 && reg <= 111)
1653 return ARM_WCGR0_REGNUM + reg - 104;
1654
1655 if (reg >= 112 && reg <= 127)
1656 return ARM_WR0_REGNUM + reg - 112;
1657
1658 if (reg >= 192 && reg <= 199)
1659 return ARM_WC0_REGNUM + reg - 192;
1660
1661 return -1;
1662}
1663
26216b98
AC
1664/* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1665static int
e7faf938 1666arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
26216b98
AC
1667{
1668 int reg = regnum;
e7faf938 1669 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
26216b98 1670
ff6f572f
DJ
1671 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1672 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1673
1674 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1675 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1676
1677 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1678 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1679
26216b98
AC
1680 if (reg < NUM_GREGS)
1681 return SIM_ARM_R0_REGNUM + reg;
1682 reg -= NUM_GREGS;
1683
1684 if (reg < NUM_FREGS)
1685 return SIM_ARM_FP0_REGNUM + reg;
1686 reg -= NUM_FREGS;
1687
1688 if (reg < NUM_SREGS)
1689 return SIM_ARM_FPS_REGNUM + reg;
1690 reg -= NUM_SREGS;
1691
edefbb7c 1692 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
26216b98 1693}
34e8f22d 1694
a37b3cc0
AC
1695/* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1696 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1697 It is thought that this is is the floating-point register format on
1698 little-endian systems. */
c906108c 1699
ed9a39eb 1700static void
b508a996 1701convert_from_extended (const struct floatformat *fmt, const void *ptr,
be8626e0 1702 void *dbl, int endianess)
c906108c 1703{
a37b3cc0 1704 DOUBLEST d;
be8626e0
MD
1705
1706 if (endianess == BFD_ENDIAN_BIG)
a37b3cc0
AC
1707 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1708 else
1709 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1710 ptr, &d);
b508a996 1711 floatformat_from_doublest (fmt, &d, dbl);
c906108c
SS
1712}
1713
34e8f22d 1714static void
be8626e0
MD
1715convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
1716 int endianess)
c906108c 1717{
a37b3cc0 1718 DOUBLEST d;
be8626e0 1719
b508a996 1720 floatformat_to_doublest (fmt, ptr, &d);
be8626e0 1721 if (endianess == BFD_ENDIAN_BIG)
a37b3cc0
AC
1722 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1723 else
1724 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1725 &d, dbl);
c906108c 1726}
ed9a39eb 1727
c906108c 1728static int
ed9a39eb 1729condition_true (unsigned long cond, unsigned long status_reg)
c906108c
SS
1730{
1731 if (cond == INST_AL || cond == INST_NV)
1732 return 1;
1733
1734 switch (cond)
1735 {
1736 case INST_EQ:
1737 return ((status_reg & FLAG_Z) != 0);
1738 case INST_NE:
1739 return ((status_reg & FLAG_Z) == 0);
1740 case INST_CS:
1741 return ((status_reg & FLAG_C) != 0);
1742 case INST_CC:
1743 return ((status_reg & FLAG_C) == 0);
1744 case INST_MI:
1745 return ((status_reg & FLAG_N) != 0);
1746 case INST_PL:
1747 return ((status_reg & FLAG_N) == 0);
1748 case INST_VS:
1749 return ((status_reg & FLAG_V) != 0);
1750 case INST_VC:
1751 return ((status_reg & FLAG_V) == 0);
1752 case INST_HI:
1753 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1754 case INST_LS:
1755 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1756 case INST_GE:
1757 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1758 case INST_LT:
1759 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1760 case INST_GT:
1761 return (((status_reg & FLAG_Z) == 0) &&
ed9a39eb 1762 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
c906108c
SS
1763 case INST_LE:
1764 return (((status_reg & FLAG_Z) != 0) ||
ed9a39eb 1765 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
c906108c
SS
1766 }
1767 return 1;
1768}
1769
9512d7fd 1770/* Support routines for single stepping. Calculate the next PC value. */
c906108c
SS
1771#define submask(x) ((1L << ((x) + 1)) - 1)
1772#define bit(obj,st) (((obj) >> (st)) & 1)
1773#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1774#define sbits(obj,st,fn) \
1775 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1776#define BranchDest(addr,instr) \
1777 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1778#define ARM_PC_32 1
1779
1780static unsigned long
0b1b3e42
UW
1781shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
1782 unsigned long pc_val, unsigned long status_reg)
c906108c
SS
1783{
1784 unsigned long res, shift;
1785 int rm = bits (inst, 0, 3);
1786 unsigned long shifttype = bits (inst, 5, 6);
c5aa993b
JM
1787
1788 if (bit (inst, 4))
c906108c
SS
1789 {
1790 int rs = bits (inst, 8, 11);
0b1b3e42
UW
1791 shift = (rs == 15 ? pc_val + 8
1792 : get_frame_register_unsigned (frame, rs)) & 0xFF;
c906108c
SS
1793 }
1794 else
1795 shift = bits (inst, 7, 11);
c5aa993b
JM
1796
1797 res = (rm == 15
c906108c 1798 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
c5aa993b 1799 + (bit (inst, 4) ? 12 : 8))
0b1b3e42 1800 : get_frame_register_unsigned (frame, rm));
c906108c
SS
1801
1802 switch (shifttype)
1803 {
c5aa993b 1804 case 0: /* LSL */
c906108c
SS
1805 res = shift >= 32 ? 0 : res << shift;
1806 break;
c5aa993b
JM
1807
1808 case 1: /* LSR */
c906108c
SS
1809 res = shift >= 32 ? 0 : res >> shift;
1810 break;
1811
c5aa993b
JM
1812 case 2: /* ASR */
1813 if (shift >= 32)
1814 shift = 31;
c906108c
SS
1815 res = ((res & 0x80000000L)
1816 ? ~((~res) >> shift) : res >> shift);
1817 break;
1818
c5aa993b 1819 case 3: /* ROR/RRX */
c906108c
SS
1820 shift &= 31;
1821 if (shift == 0)
1822 res = (res >> 1) | (carry ? 0x80000000L : 0);
1823 else
c5aa993b 1824 res = (res >> shift) | (res << (32 - shift));
c906108c
SS
1825 break;
1826 }
1827
1828 return res & 0xffffffff;
1829}
1830
c906108c
SS
1831/* Return number of 1-bits in VAL. */
1832
1833static int
ed9a39eb 1834bitcount (unsigned long val)
c906108c
SS
1835{
1836 int nbits;
1837 for (nbits = 0; val != 0; nbits++)
c5aa993b 1838 val &= val - 1; /* delete rightmost 1-bit in val */
c906108c
SS
1839 return nbits;
1840}
1841
ad527d2e 1842static CORE_ADDR
0b1b3e42 1843thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
c906108c 1844{
2af46ca0 1845 struct gdbarch *gdbarch = get_frame_arch (frame);
c5aa993b 1846 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1c5bada0 1847 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
94c30b78 1848 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
c906108c
SS
1849 unsigned long offset;
1850
9d4fde75
SS
1851 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
1852 inst1 = SWAP_SHORT (inst1);
1853
c906108c
SS
1854 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1855 {
1856 CORE_ADDR sp;
1857
1858 /* Fetch the saved PC from the stack. It's stored above
1859 all of the other registers. */
f0c9063c 1860 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
0b1b3e42 1861 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
1c5bada0 1862 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
2af46ca0 1863 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
c906108c 1864 if (nextpc == pc)
edefbb7c 1865 error (_("Infinite loop detected"));
c906108c
SS
1866 }
1867 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1868 {
0b1b3e42 1869 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
c5aa993b 1870 unsigned long cond = bits (inst1, 8, 11);
94c30b78 1871 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
c906108c
SS
1872 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1873 }
1874 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1875 {
1876 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1877 }
aa17d93e 1878 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
c906108c 1879 {
1c5bada0 1880 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
9d4fde75
SS
1881 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
1882 inst2 = SWAP_SHORT (inst2);
c5aa993b 1883 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
c906108c 1884 nextpc = pc_val + offset;
aa17d93e
DJ
1885 /* For BLX make sure to clear the low bits. */
1886 if (bits (inst2, 11, 12) == 1)
1887 nextpc = nextpc & 0xfffffffc;
c906108c 1888 }
aa17d93e 1889 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
9498281f
DJ
1890 {
1891 if (bits (inst1, 3, 6) == 0x0f)
1892 nextpc = pc_val;
1893 else
0b1b3e42 1894 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
9498281f 1895
2af46ca0 1896 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
9498281f 1897 if (nextpc == pc)
edefbb7c 1898 error (_("Infinite loop detected"));
9498281f 1899 }
c906108c
SS
1900
1901 return nextpc;
1902}
1903
daddc3c1 1904CORE_ADDR
0b1b3e42 1905arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
c906108c 1906{
2af46ca0 1907 struct gdbarch *gdbarch = get_frame_arch (frame);
c906108c
SS
1908 unsigned long pc_val;
1909 unsigned long this_instr;
1910 unsigned long status;
1911 CORE_ADDR nextpc;
1912
b39cc962 1913 if (arm_frame_is_thumb (frame))
0b1b3e42 1914 return thumb_get_next_pc (frame, pc);
c906108c
SS
1915
1916 pc_val = (unsigned long) pc;
1c5bada0 1917 this_instr = read_memory_unsigned_integer (pc, 4);
9d4fde75
SS
1918
1919 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
1920 this_instr = SWAP_INT (this_instr);
1921
0b1b3e42 1922 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
c5aa993b 1923 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
c906108c 1924
daddc3c1
DJ
1925 if (bits (this_instr, 28, 31) == INST_NV)
1926 switch (bits (this_instr, 24, 27))
1927 {
1928 case 0xa:
1929 case 0xb:
1930 {
1931 /* Branch with Link and change to Thumb. */
1932 nextpc = BranchDest (pc, this_instr);
1933 nextpc |= bit (this_instr, 24) << 1;
1934
e1e01acd 1935 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
daddc3c1
DJ
1936 if (nextpc == pc)
1937 error (_("Infinite loop detected"));
1938 break;
1939 }
1940 case 0xc:
1941 case 0xd:
1942 case 0xe:
1943 /* Coprocessor register transfer. */
1944 if (bits (this_instr, 12, 15) == 15)
1945 error (_("Invalid update to pc in instruction"));
1946 break;
1947 }
1948 else if (condition_true (bits (this_instr, 28, 31), status))
c906108c
SS
1949 {
1950 switch (bits (this_instr, 24, 27))
1951 {
c5aa993b 1952 case 0x0:
94c30b78 1953 case 0x1: /* data processing */
c5aa993b
JM
1954 case 0x2:
1955 case 0x3:
c906108c
SS
1956 {
1957 unsigned long operand1, operand2, result = 0;
1958 unsigned long rn;
1959 int c;
c5aa993b 1960
c906108c
SS
1961 if (bits (this_instr, 12, 15) != 15)
1962 break;
1963
1964 if (bits (this_instr, 22, 25) == 0
c5aa993b 1965 && bits (this_instr, 4, 7) == 9) /* multiply */
edefbb7c 1966 error (_("Invalid update to pc in instruction"));
c906108c 1967
9498281f 1968 /* BX <reg>, BLX <reg> */
e150acc7
PB
1969 if (bits (this_instr, 4, 27) == 0x12fff1
1970 || bits (this_instr, 4, 27) == 0x12fff3)
9498281f
DJ
1971 {
1972 rn = bits (this_instr, 0, 3);
0b1b3e42
UW
1973 result = (rn == 15) ? pc_val + 8
1974 : get_frame_register_unsigned (frame, rn);
bf6ae464 1975 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
2af46ca0 1976 (gdbarch, result);
9498281f
DJ
1977
1978 if (nextpc == pc)
edefbb7c 1979 error (_("Infinite loop detected"));
9498281f
DJ
1980
1981 return nextpc;
1982 }
1983
c906108c
SS
1984 /* Multiply into PC */
1985 c = (status & FLAG_C) ? 1 : 0;
1986 rn = bits (this_instr, 16, 19);
0b1b3e42
UW
1987 operand1 = (rn == 15) ? pc_val + 8
1988 : get_frame_register_unsigned (frame, rn);
c5aa993b 1989
c906108c
SS
1990 if (bit (this_instr, 25))
1991 {
1992 unsigned long immval = bits (this_instr, 0, 7);
1993 unsigned long rotate = 2 * bits (this_instr, 8, 11);
c5aa993b
JM
1994 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1995 & 0xffffffff;
c906108c 1996 }
c5aa993b 1997 else /* operand 2 is a shifted register */
0b1b3e42 1998 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
c5aa993b 1999
c906108c
SS
2000 switch (bits (this_instr, 21, 24))
2001 {
c5aa993b 2002 case 0x0: /*and */
c906108c
SS
2003 result = operand1 & operand2;
2004 break;
2005
c5aa993b 2006 case 0x1: /*eor */
c906108c
SS
2007 result = operand1 ^ operand2;
2008 break;
2009
c5aa993b 2010 case 0x2: /*sub */
c906108c
SS
2011 result = operand1 - operand2;
2012 break;
2013
c5aa993b 2014 case 0x3: /*rsb */
c906108c
SS
2015 result = operand2 - operand1;
2016 break;
2017
c5aa993b 2018 case 0x4: /*add */
c906108c
SS
2019 result = operand1 + operand2;
2020 break;
2021
c5aa993b 2022 case 0x5: /*adc */
c906108c
SS
2023 result = operand1 + operand2 + c;
2024 break;
2025
c5aa993b 2026 case 0x6: /*sbc */
c906108c
SS
2027 result = operand1 - operand2 + c;
2028 break;
2029
c5aa993b 2030 case 0x7: /*rsc */
c906108c
SS
2031 result = operand2 - operand1 + c;
2032 break;
2033
c5aa993b
JM
2034 case 0x8:
2035 case 0x9:
2036 case 0xa:
2037 case 0xb: /* tst, teq, cmp, cmn */
c906108c
SS
2038 result = (unsigned long) nextpc;
2039 break;
2040
c5aa993b 2041 case 0xc: /*orr */
c906108c
SS
2042 result = operand1 | operand2;
2043 break;
2044
c5aa993b 2045 case 0xd: /*mov */
c906108c
SS
2046 /* Always step into a function. */
2047 result = operand2;
c5aa993b 2048 break;
c906108c 2049
c5aa993b 2050 case 0xe: /*bic */
c906108c
SS
2051 result = operand1 & ~operand2;
2052 break;
2053
c5aa993b 2054 case 0xf: /*mvn */
c906108c
SS
2055 result = ~operand2;
2056 break;
2057 }
bf6ae464 2058 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
2af46ca0 2059 (gdbarch, result);
c906108c
SS
2060
2061 if (nextpc == pc)
edefbb7c 2062 error (_("Infinite loop detected"));
c906108c
SS
2063 break;
2064 }
c5aa993b
JM
2065
2066 case 0x4:
2067 case 0x5: /* data transfer */
2068 case 0x6:
2069 case 0x7:
c906108c
SS
2070 if (bit (this_instr, 20))
2071 {
2072 /* load */
2073 if (bits (this_instr, 12, 15) == 15)
2074 {
2075 /* rd == pc */
c5aa993b 2076 unsigned long rn;
c906108c 2077 unsigned long base;
c5aa993b 2078
c906108c 2079 if (bit (this_instr, 22))
edefbb7c 2080 error (_("Invalid update to pc in instruction"));
c906108c
SS
2081
2082 /* byte write to PC */
2083 rn = bits (this_instr, 16, 19);
0b1b3e42
UW
2084 base = (rn == 15) ? pc_val + 8
2085 : get_frame_register_unsigned (frame, rn);
c906108c
SS
2086 if (bit (this_instr, 24))
2087 {
2088 /* pre-indexed */
2089 int c = (status & FLAG_C) ? 1 : 0;
2090 unsigned long offset =
c5aa993b 2091 (bit (this_instr, 25)
0b1b3e42 2092 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
c5aa993b 2093 : bits (this_instr, 0, 11));
c906108c
SS
2094
2095 if (bit (this_instr, 23))
2096 base += offset;
2097 else
2098 base -= offset;
2099 }
c5aa993b 2100 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
c906108c 2101 4);
c5aa993b 2102
2af46ca0 2103 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
c906108c
SS
2104
2105 if (nextpc == pc)
edefbb7c 2106 error (_("Infinite loop detected"));
c906108c
SS
2107 }
2108 }
2109 break;
c5aa993b
JM
2110
2111 case 0x8:
2112 case 0x9: /* block transfer */
c906108c
SS
2113 if (bit (this_instr, 20))
2114 {
2115 /* LDM */
2116 if (bit (this_instr, 15))
2117 {
2118 /* loading pc */
2119 int offset = 0;
2120
2121 if (bit (this_instr, 23))
2122 {
2123 /* up */
2124 unsigned long reglist = bits (this_instr, 0, 14);
2125 offset = bitcount (reglist) * 4;
c5aa993b 2126 if (bit (this_instr, 24)) /* pre */
c906108c
SS
2127 offset += 4;
2128 }
2129 else if (bit (this_instr, 24))
2130 offset = -4;
c5aa993b 2131
c906108c 2132 {
c5aa993b 2133 unsigned long rn_val =
0b1b3e42
UW
2134 get_frame_register_unsigned (frame,
2135 bits (this_instr, 16, 19));
c906108c
SS
2136 nextpc =
2137 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
c5aa993b 2138 + offset),
c906108c
SS
2139 4);
2140 }
bf6ae464 2141 nextpc = gdbarch_addr_bits_remove
2af46ca0 2142 (gdbarch, nextpc);
c906108c 2143 if (nextpc == pc)
edefbb7c 2144 error (_("Infinite loop detected"));
c906108c
SS
2145 }
2146 }
2147 break;
c5aa993b
JM
2148
2149 case 0xb: /* branch & link */
2150 case 0xa: /* branch */
c906108c
SS
2151 {
2152 nextpc = BranchDest (pc, this_instr);
2153
2af46ca0 2154 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
c906108c 2155 if (nextpc == pc)
edefbb7c 2156 error (_("Infinite loop detected"));
c906108c
SS
2157 break;
2158 }
c5aa993b
JM
2159
2160 case 0xc:
2161 case 0xd:
2162 case 0xe: /* coproc ops */
2163 case 0xf: /* SWI */
c906108c
SS
2164 break;
2165
2166 default:
edefbb7c 2167 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
c906108c
SS
2168 return (pc);
2169 }
2170 }
2171
2172 return nextpc;
2173}
2174
9512d7fd
FN
2175/* single_step() is called just before we want to resume the inferior,
2176 if we want to single-step it but there is no hardware or kernel
2177 single-step support. We find the target of the coming instruction
e0cd558a 2178 and breakpoint it. */
9512d7fd 2179
190dce09 2180int
0b1b3e42 2181arm_software_single_step (struct frame_info *frame)
9512d7fd 2182{
8181d85f
DJ
2183 /* NOTE: This may insert the wrong breakpoint instruction when
2184 single-stepping over a mode-changing instruction, if the
2185 CPSR heuristics are used. */
9512d7fd 2186
0b1b3e42 2187 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
e0cd558a 2188 insert_single_step_breakpoint (next_pc);
e6590a1b
UW
2189
2190 return 1;
9512d7fd 2191}
9512d7fd 2192
c906108c
SS
2193#include "bfd-in2.h"
2194#include "libcoff.h"
2195
2196static int
ed9a39eb 2197gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
c906108c
SS
2198{
2199 if (arm_pc_is_thumb (memaddr))
2200 {
c5aa993b
JM
2201 static asymbol *asym;
2202 static combined_entry_type ce;
2203 static struct coff_symbol_struct csym;
27cddce2 2204 static struct bfd fake_bfd;
c5aa993b 2205 static bfd_target fake_target;
c906108c
SS
2206
2207 if (csym.native == NULL)
2208 {
da3c6d4a
MS
2209 /* Create a fake symbol vector containing a Thumb symbol.
2210 This is solely so that the code in print_insn_little_arm()
2211 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2212 the presence of a Thumb symbol and switch to decoding
2213 Thumb instructions. */
c5aa993b
JM
2214
2215 fake_target.flavour = bfd_target_coff_flavour;
2216 fake_bfd.xvec = &fake_target;
c906108c 2217 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
c5aa993b
JM
2218 csym.native = &ce;
2219 csym.symbol.the_bfd = &fake_bfd;
2220 csym.symbol.name = "fake";
2221 asym = (asymbol *) & csym;
c906108c 2222 }
c5aa993b 2223
c906108c 2224 memaddr = UNMAKE_THUMB_ADDR (memaddr);
c5aa993b 2225 info->symbols = &asym;
c906108c
SS
2226 }
2227 else
2228 info->symbols = NULL;
c5aa993b 2229
40887e1a 2230 if (info->endian == BFD_ENDIAN_BIG)
c906108c
SS
2231 return print_insn_big_arm (memaddr, info);
2232 else
2233 return print_insn_little_arm (memaddr, info);
2234}
2235
66e810cd
RE
2236/* The following define instruction sequences that will cause ARM
2237 cpu's to take an undefined instruction trap. These are used to
2238 signal a breakpoint to GDB.
2239
2240 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2241 modes. A different instruction is required for each mode. The ARM
2242 cpu's can also be big or little endian. Thus four different
2243 instructions are needed to support all cases.
2244
2245 Note: ARMv4 defines several new instructions that will take the
2246 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2247 not in fact add the new instructions. The new undefined
2248 instructions in ARMv4 are all instructions that had no defined
2249 behaviour in earlier chips. There is no guarantee that they will
2250 raise an exception, but may be treated as NOP's. In practice, it
2251 may only safe to rely on instructions matching:
2252
2253 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2254 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2255 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2256
2257 Even this may only true if the condition predicate is true. The
2258 following use a condition predicate of ALWAYS so it is always TRUE.
2259
2260 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2261 and NetBSD all use a software interrupt rather than an undefined
2262 instruction to force a trap. This can be handled by by the
2263 abi-specific code during establishment of the gdbarch vector. */
2264
66e810cd 2265#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
66e810cd 2266#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
190dce09
UW
2267#define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2268#define THUMB_BE_BREAKPOINT {0xbe,0xbe}
66e810cd
RE
2269
2270static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2271static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2272static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2273static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2274
34e8f22d
RE
2275/* Determine the type and size of breakpoint to insert at PCPTR. Uses
2276 the program counter value to determine whether a 16-bit or 32-bit
ed9a39eb
JM
2277 breakpoint should be used. It returns a pointer to a string of
2278 bytes that encode a breakpoint instruction, stores the length of
2279 the string to *lenptr, and adjusts the program counter (if
2280 necessary) to point to the actual memory location where the
c906108c
SS
2281 breakpoint should be inserted. */
2282
ab89facf 2283static const unsigned char *
67d57894 2284arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
c906108c 2285{
67d57894 2286 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
66e810cd 2287
4bf7064c 2288 if (arm_pc_is_thumb (*pcptr))
c906108c 2289 {
66e810cd
RE
2290 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2291 *lenptr = tdep->thumb_breakpoint_size;
2292 return tdep->thumb_breakpoint;
c906108c
SS
2293 }
2294 else
2295 {
66e810cd
RE
2296 *lenptr = tdep->arm_breakpoint_size;
2297 return tdep->arm_breakpoint;
c906108c
SS
2298 }
2299}
ed9a39eb
JM
2300
2301/* Extract from an array REGBUF containing the (raw) register state a
2302 function return value of type TYPE, and copy that, in virtual
2303 format, into VALBUF. */
2304
34e8f22d 2305static void
5238cf52
MK
2306arm_extract_return_value (struct type *type, struct regcache *regs,
2307 gdb_byte *valbuf)
ed9a39eb 2308{
be8626e0
MD
2309 struct gdbarch *gdbarch = get_regcache_arch (regs);
2310
ed9a39eb 2311 if (TYPE_CODE_FLT == TYPE_CODE (type))
08216dd7 2312 {
be8626e0 2313 switch (gdbarch_tdep (gdbarch)->fp_model)
08216dd7
RE
2314 {
2315 case ARM_FLOAT_FPA:
b508a996
RE
2316 {
2317 /* The value is in register F0 in internal format. We need to
2318 extract the raw value and then convert it to the desired
2319 internal type. */
7a5ea0d4 2320 bfd_byte tmpbuf[FP_REGISTER_SIZE];
b508a996
RE
2321
2322 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2323 convert_from_extended (floatformat_from_type (type), tmpbuf,
be8626e0 2324 valbuf, gdbarch_byte_order (gdbarch));
b508a996 2325 }
08216dd7
RE
2326 break;
2327
fd50bc42 2328 case ARM_FLOAT_SOFT_FPA:
08216dd7 2329 case ARM_FLOAT_SOFT_VFP:
b508a996
RE
2330 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2331 if (TYPE_LENGTH (type) > 4)
2332 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
7a5ea0d4 2333 valbuf + INT_REGISTER_SIZE);
08216dd7
RE
2334 break;
2335
2336 default:
2337 internal_error
2338 (__FILE__, __LINE__,
edefbb7c 2339 _("arm_extract_return_value: Floating point model not supported"));
08216dd7
RE
2340 break;
2341 }
2342 }
b508a996
RE
2343 else if (TYPE_CODE (type) == TYPE_CODE_INT
2344 || TYPE_CODE (type) == TYPE_CODE_CHAR
2345 || TYPE_CODE (type) == TYPE_CODE_BOOL
2346 || TYPE_CODE (type) == TYPE_CODE_PTR
2347 || TYPE_CODE (type) == TYPE_CODE_REF
2348 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2349 {
2350 /* If the the type is a plain integer, then the access is
2351 straight-forward. Otherwise we have to play around a bit more. */
2352 int len = TYPE_LENGTH (type);
2353 int regno = ARM_A1_REGNUM;
2354 ULONGEST tmp;
2355
2356 while (len > 0)
2357 {
2358 /* By using store_unsigned_integer we avoid having to do
2359 anything special for small big-endian values. */
2360 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2361 store_unsigned_integer (valbuf,
7a5ea0d4
DJ
2362 (len > INT_REGISTER_SIZE
2363 ? INT_REGISTER_SIZE : len),
b508a996 2364 tmp);
7a5ea0d4
DJ
2365 len -= INT_REGISTER_SIZE;
2366 valbuf += INT_REGISTER_SIZE;
b508a996
RE
2367 }
2368 }
ed9a39eb 2369 else
b508a996
RE
2370 {
2371 /* For a structure or union the behaviour is as if the value had
2372 been stored to word-aligned memory and then loaded into
2373 registers with 32-bit load instruction(s). */
2374 int len = TYPE_LENGTH (type);
2375 int regno = ARM_A1_REGNUM;
7a5ea0d4 2376 bfd_byte tmpbuf[INT_REGISTER_SIZE];
b508a996
RE
2377
2378 while (len > 0)
2379 {
2380 regcache_cooked_read (regs, regno++, tmpbuf);
2381 memcpy (valbuf, tmpbuf,
7a5ea0d4
DJ
2382 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2383 len -= INT_REGISTER_SIZE;
2384 valbuf += INT_REGISTER_SIZE;
b508a996
RE
2385 }
2386 }
34e8f22d
RE
2387}
2388
67255d04
RE
2389
2390/* Will a function return an aggregate type in memory or in a
2391 register? Return 0 if an aggregate type can be returned in a
2392 register, 1 if it must be returned in memory. */
2393
2394static int
2af48f68 2395arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
67255d04
RE
2396{
2397 int nRc;
52f0bd74 2398 enum type_code code;
67255d04 2399
44e1a9eb
DJ
2400 CHECK_TYPEDEF (type);
2401
67255d04
RE
2402 /* In the ARM ABI, "integer" like aggregate types are returned in
2403 registers. For an aggregate type to be integer like, its size
f0c9063c 2404 must be less than or equal to INT_REGISTER_SIZE and the
b1e29e33
AC
2405 offset of each addressable subfield must be zero. Note that bit
2406 fields are not addressable, and all addressable subfields of
2407 unions always start at offset zero.
67255d04
RE
2408
2409 This function is based on the behaviour of GCC 2.95.1.
2410 See: gcc/arm.c: arm_return_in_memory() for details.
2411
2412 Note: All versions of GCC before GCC 2.95.2 do not set up the
2413 parameters correctly for a function returning the following
2414 structure: struct { float f;}; This should be returned in memory,
2415 not a register. Richard Earnshaw sent me a patch, but I do not
2416 know of any way to detect if a function like the above has been
2417 compiled with the correct calling convention. */
2418
2419 /* All aggregate types that won't fit in a register must be returned
2420 in memory. */
f0c9063c 2421 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
67255d04
RE
2422 {
2423 return 1;
2424 }
2425
2af48f68
PB
2426 /* The AAPCS says all aggregates not larger than a word are returned
2427 in a register. */
2428 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2429 return 0;
2430
67255d04
RE
2431 /* The only aggregate types that can be returned in a register are
2432 structs and unions. Arrays must be returned in memory. */
2433 code = TYPE_CODE (type);
2434 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2435 {
2436 return 1;
2437 }
2438
2439 /* Assume all other aggregate types can be returned in a register.
2440 Run a check for structures, unions and arrays. */
2441 nRc = 0;
2442
2443 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2444 {
2445 int i;
2446 /* Need to check if this struct/union is "integer" like. For
2447 this to be true, its size must be less than or equal to
f0c9063c 2448 INT_REGISTER_SIZE and the offset of each addressable
b1e29e33
AC
2449 subfield must be zero. Note that bit fields are not
2450 addressable, and unions always start at offset zero. If any
2451 of the subfields is a floating point type, the struct/union
2452 cannot be an integer type. */
67255d04
RE
2453
2454 /* For each field in the object, check:
2455 1) Is it FP? --> yes, nRc = 1;
2456 2) Is it addressable (bitpos != 0) and
2457 not packed (bitsize == 0)?
2458 --> yes, nRc = 1
2459 */
2460
2461 for (i = 0; i < TYPE_NFIELDS (type); i++)
2462 {
2463 enum type_code field_type_code;
44e1a9eb 2464 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
67255d04
RE
2465
2466 /* Is it a floating point type field? */
2467 if (field_type_code == TYPE_CODE_FLT)
2468 {
2469 nRc = 1;
2470 break;
2471 }
2472
2473 /* If bitpos != 0, then we have to care about it. */
2474 if (TYPE_FIELD_BITPOS (type, i) != 0)
2475 {
2476 /* Bitfields are not addressable. If the field bitsize is
2477 zero, then the field is not packed. Hence it cannot be
2478 a bitfield or any other packed type. */
2479 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2480 {
2481 nRc = 1;
2482 break;
2483 }
2484 }
2485 }
2486 }
2487
2488 return nRc;
2489}
2490
34e8f22d
RE
2491/* Write into appropriate registers a function return value of type
2492 TYPE, given in virtual format. */
2493
2494static void
b508a996 2495arm_store_return_value (struct type *type, struct regcache *regs,
5238cf52 2496 const gdb_byte *valbuf)
34e8f22d 2497{
be8626e0
MD
2498 struct gdbarch *gdbarch = get_regcache_arch (regs);
2499
34e8f22d
RE
2500 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2501 {
7a5ea0d4 2502 char buf[MAX_REGISTER_SIZE];
34e8f22d 2503
be8626e0 2504 switch (gdbarch_tdep (gdbarch)->fp_model)
08216dd7
RE
2505 {
2506 case ARM_FLOAT_FPA:
2507
be8626e0
MD
2508 convert_to_extended (floatformat_from_type (type), buf, valbuf,
2509 gdbarch_byte_order (gdbarch));
b508a996 2510 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
08216dd7
RE
2511 break;
2512
fd50bc42 2513 case ARM_FLOAT_SOFT_FPA:
08216dd7 2514 case ARM_FLOAT_SOFT_VFP:
b508a996
RE
2515 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2516 if (TYPE_LENGTH (type) > 4)
2517 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
7a5ea0d4 2518 valbuf + INT_REGISTER_SIZE);
08216dd7
RE
2519 break;
2520
2521 default:
2522 internal_error
2523 (__FILE__, __LINE__,
edefbb7c 2524 _("arm_store_return_value: Floating point model not supported"));
08216dd7
RE
2525 break;
2526 }
34e8f22d 2527 }
b508a996
RE
2528 else if (TYPE_CODE (type) == TYPE_CODE_INT
2529 || TYPE_CODE (type) == TYPE_CODE_CHAR
2530 || TYPE_CODE (type) == TYPE_CODE_BOOL
2531 || TYPE_CODE (type) == TYPE_CODE_PTR
2532 || TYPE_CODE (type) == TYPE_CODE_REF
2533 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2534 {
2535 if (TYPE_LENGTH (type) <= 4)
2536 {
2537 /* Values of one word or less are zero/sign-extended and
2538 returned in r0. */
7a5ea0d4 2539 bfd_byte tmpbuf[INT_REGISTER_SIZE];
b508a996
RE
2540 LONGEST val = unpack_long (type, valbuf);
2541
7a5ea0d4 2542 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
b508a996
RE
2543 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2544 }
2545 else
2546 {
2547 /* Integral values greater than one word are stored in consecutive
2548 registers starting with r0. This will always be a multiple of
2549 the regiser size. */
2550 int len = TYPE_LENGTH (type);
2551 int regno = ARM_A1_REGNUM;
2552
2553 while (len > 0)
2554 {
2555 regcache_cooked_write (regs, regno++, valbuf);
7a5ea0d4
DJ
2556 len -= INT_REGISTER_SIZE;
2557 valbuf += INT_REGISTER_SIZE;
b508a996
RE
2558 }
2559 }
2560 }
34e8f22d 2561 else
b508a996
RE
2562 {
2563 /* For a structure or union the behaviour is as if the value had
2564 been stored to word-aligned memory and then loaded into
2565 registers with 32-bit load instruction(s). */
2566 int len = TYPE_LENGTH (type);
2567 int regno = ARM_A1_REGNUM;
7a5ea0d4 2568 bfd_byte tmpbuf[INT_REGISTER_SIZE];
b508a996
RE
2569
2570 while (len > 0)
2571 {
2572 memcpy (tmpbuf, valbuf,
7a5ea0d4 2573 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
b508a996 2574 regcache_cooked_write (regs, regno++, tmpbuf);
7a5ea0d4
DJ
2575 len -= INT_REGISTER_SIZE;
2576 valbuf += INT_REGISTER_SIZE;
b508a996
RE
2577 }
2578 }
34e8f22d
RE
2579}
2580
2af48f68
PB
2581
2582/* Handle function return values. */
2583
2584static enum return_value_convention
c055b101
CV
2585arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
2586 struct type *valtype, struct regcache *regcache,
2587 gdb_byte *readbuf, const gdb_byte *writebuf)
2af48f68 2588{
7c00367c
MK
2589 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2590
2af48f68
PB
2591 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2592 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2593 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2594 {
7c00367c
MK
2595 if (tdep->struct_return == pcc_struct_return
2596 || arm_return_in_memory (gdbarch, valtype))
2af48f68
PB
2597 return RETURN_VALUE_STRUCT_CONVENTION;
2598 }
2599
2600 if (writebuf)
2601 arm_store_return_value (valtype, regcache, writebuf);
2602
2603 if (readbuf)
2604 arm_extract_return_value (valtype, regcache, readbuf);
2605
2606 return RETURN_VALUE_REGISTER_CONVENTION;
2607}
2608
2609
9df628e0 2610static int
60ade65d 2611arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
9df628e0
RE
2612{
2613 CORE_ADDR jb_addr;
7a5ea0d4 2614 char buf[INT_REGISTER_SIZE];
60ade65d 2615 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
9df628e0 2616
60ade65d 2617 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
9df628e0
RE
2618
2619 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
7a5ea0d4 2620 INT_REGISTER_SIZE))
9df628e0
RE
2621 return 0;
2622
7a5ea0d4 2623 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
9df628e0
RE
2624 return 1;
2625}
2626
faa95490
DJ
2627/* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2628 return the target PC. Otherwise return 0. */
c906108c
SS
2629
2630CORE_ADDR
52f729a7 2631arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
c906108c 2632{
c5aa993b 2633 char *name;
faa95490 2634 int namelen;
c906108c
SS
2635 CORE_ADDR start_addr;
2636
2637 /* Find the starting address and name of the function containing the PC. */
2638 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2639 return 0;
2640
faa95490
DJ
2641 /* If PC is in a Thumb call or return stub, return the address of the
2642 target PC, which is in a register. The thunk functions are called
2643 _call_via_xx, where x is the register name. The possible names
2644 are r0-r9, sl, fp, ip, sp, and lr. */
c906108c
SS
2645 if (strncmp (name, "_call_via_", 10) == 0)
2646 {
ed9a39eb
JM
2647 /* Use the name suffix to determine which register contains the
2648 target PC. */
c5aa993b
JM
2649 static char *table[15] =
2650 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2651 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2652 };
c906108c 2653 int regno;
faa95490 2654 int offset = strlen (name) - 2;
c906108c
SS
2655
2656 for (regno = 0; regno <= 14; regno++)
faa95490 2657 if (strcmp (&name[offset], table[regno]) == 0)
52f729a7 2658 return get_frame_register_unsigned (frame, regno);
c906108c 2659 }
ed9a39eb 2660
faa95490
DJ
2661 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2662 non-interworking calls to foo. We could decode the stubs
2663 to find the target but it's easier to use the symbol table. */
2664 namelen = strlen (name);
2665 if (name[0] == '_' && name[1] == '_'
2666 && ((namelen > 2 + strlen ("_from_thumb")
2667 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2668 strlen ("_from_thumb")) == 0)
2669 || (namelen > 2 + strlen ("_from_arm")
2670 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2671 strlen ("_from_arm")) == 0)))
2672 {
2673 char *target_name;
2674 int target_len = namelen - 2;
2675 struct minimal_symbol *minsym;
2676 struct objfile *objfile;
2677 struct obj_section *sec;
2678
2679 if (name[namelen - 1] == 'b')
2680 target_len -= strlen ("_from_thumb");
2681 else
2682 target_len -= strlen ("_from_arm");
2683
2684 target_name = alloca (target_len + 1);
2685 memcpy (target_name, name + 2, target_len);
2686 target_name[target_len] = '\0';
2687
2688 sec = find_pc_section (pc);
2689 objfile = (sec == NULL) ? NULL : sec->objfile;
2690 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2691 if (minsym != NULL)
2692 return SYMBOL_VALUE_ADDRESS (minsym);
2693 else
2694 return 0;
2695 }
2696
c5aa993b 2697 return 0; /* not a stub */
c906108c
SS
2698}
2699
afd7eef0
RE
2700static void
2701set_arm_command (char *args, int from_tty)
2702{
edefbb7c
AC
2703 printf_unfiltered (_("\
2704\"set arm\" must be followed by an apporpriate subcommand.\n"));
afd7eef0
RE
2705 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2706}
2707
2708static void
2709show_arm_command (char *args, int from_tty)
2710{
26304000 2711 cmd_show_list (showarmcmdlist, from_tty, "");
afd7eef0
RE
2712}
2713
28e97307
DJ
2714static void
2715arm_update_current_architecture (void)
fd50bc42 2716{
28e97307 2717 struct gdbarch_info info;
fd50bc42 2718
28e97307 2719 /* If the current architecture is not ARM, we have nothing to do. */
1cf3db46 2720 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
28e97307 2721 return;
fd50bc42 2722
28e97307
DJ
2723 /* Update the architecture. */
2724 gdbarch_info_init (&info);
fd50bc42 2725
28e97307
DJ
2726 if (!gdbarch_update_p (info))
2727 internal_error (__FILE__, __LINE__, "could not update architecture");
fd50bc42
RE
2728}
2729
2730static void
2731set_fp_model_sfunc (char *args, int from_tty,
2732 struct cmd_list_element *c)
2733{
2734 enum arm_float_model fp_model;
2735
2736 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2737 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2738 {
2739 arm_fp_model = fp_model;
2740 break;
2741 }
2742
2743 if (fp_model == ARM_FLOAT_LAST)
edefbb7c 2744 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
fd50bc42
RE
2745 current_fp_model);
2746
28e97307 2747 arm_update_current_architecture ();
fd50bc42
RE
2748}
2749
2750static void
08546159
AC
2751show_fp_model (struct ui_file *file, int from_tty,
2752 struct cmd_list_element *c, const char *value)
fd50bc42 2753{
1cf3db46 2754 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
fd50bc42 2755
28e97307 2756 if (arm_fp_model == ARM_FLOAT_AUTO
1cf3db46 2757 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
28e97307
DJ
2758 fprintf_filtered (file, _("\
2759The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2760 fp_model_strings[tdep->fp_model]);
2761 else
2762 fprintf_filtered (file, _("\
2763The current ARM floating point model is \"%s\".\n"),
2764 fp_model_strings[arm_fp_model]);
2765}
2766
2767static void
2768arm_set_abi (char *args, int from_tty,
2769 struct cmd_list_element *c)
2770{
2771 enum arm_abi_kind arm_abi;
2772
2773 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2774 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2775 {
2776 arm_abi_global = arm_abi;
2777 break;
2778 }
2779
2780 if (arm_abi == ARM_ABI_LAST)
2781 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2782 arm_abi_string);
2783
2784 arm_update_current_architecture ();
2785}
2786
2787static void
2788arm_show_abi (struct ui_file *file, int from_tty,
2789 struct cmd_list_element *c, const char *value)
2790{
1cf3db46 2791 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
28e97307
DJ
2792
2793 if (arm_abi_global == ARM_ABI_AUTO
1cf3db46 2794 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
28e97307
DJ
2795 fprintf_filtered (file, _("\
2796The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2797 arm_abi_strings[tdep->arm_abi]);
2798 else
2799 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2800 arm_abi_string);
fd50bc42
RE
2801}
2802
0428b8f5
DJ
2803static void
2804arm_show_fallback_mode (struct ui_file *file, int from_tty,
2805 struct cmd_list_element *c, const char *value)
2806{
1cf3db46 2807 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
0428b8f5
DJ
2808
2809 fprintf_filtered (file, _("\
2810The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2811 arm_fallback_mode_string);
2812}
2813
2814static void
2815arm_show_force_mode (struct ui_file *file, int from_tty,
2816 struct cmd_list_element *c, const char *value)
2817{
1cf3db46 2818 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
0428b8f5
DJ
2819
2820 fprintf_filtered (file, _("\
2821The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2822 arm_force_mode_string);
2823}
2824
afd7eef0
RE
2825/* If the user changes the register disassembly style used for info
2826 register and other commands, we have to also switch the style used
2827 in opcodes for disassembly output. This function is run in the "set
2828 arm disassembly" command, and does that. */
bc90b915
FN
2829
2830static void
afd7eef0 2831set_disassembly_style_sfunc (char *args, int from_tty,
bc90b915
FN
2832 struct cmd_list_element *c)
2833{
afd7eef0 2834 set_disassembly_style ();
bc90b915
FN
2835}
2836\f
966fbf70 2837/* Return the ARM register name corresponding to register I. */
a208b0cb 2838static const char *
d93859e2 2839arm_register_name (struct gdbarch *gdbarch, int i)
966fbf70 2840{
ff6f572f
DJ
2841 if (i >= ARRAY_SIZE (arm_register_names))
2842 /* These registers are only supported on targets which supply
2843 an XML description. */
2844 return "";
2845
966fbf70
RE
2846 return arm_register_names[i];
2847}
2848
bc90b915 2849static void
afd7eef0 2850set_disassembly_style (void)
bc90b915 2851{
123dc839 2852 int current;
bc90b915 2853
123dc839
DJ
2854 /* Find the style that the user wants. */
2855 for (current = 0; current < num_disassembly_options; current++)
2856 if (disassembly_style == valid_disassembly_styles[current])
2857 break;
2858 gdb_assert (current < num_disassembly_options);
bc90b915 2859
94c30b78 2860 /* Synchronize the disassembler. */
bc90b915
FN
2861 set_arm_regname_option (current);
2862}
2863
082fc60d
RE
2864/* Test whether the coff symbol specific value corresponds to a Thumb
2865 function. */
2866
2867static int
2868coff_sym_is_thumb (int val)
2869{
2870 return (val == C_THUMBEXT ||
2871 val == C_THUMBSTAT ||
2872 val == C_THUMBEXTFUNC ||
2873 val == C_THUMBSTATFUNC ||
2874 val == C_THUMBLABEL);
2875}
2876
2877/* arm_coff_make_msymbol_special()
2878 arm_elf_make_msymbol_special()
2879
2880 These functions test whether the COFF or ELF symbol corresponds to
2881 an address in thumb code, and set a "special" bit in a minimal
2882 symbol to indicate that it does. */
2883
34e8f22d 2884static void
082fc60d
RE
2885arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2886{
2887 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2888 STT_ARM_TFUNC). */
2889 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2890 == STT_LOPROC)
2891 MSYMBOL_SET_SPECIAL (msym);
2892}
2893
34e8f22d 2894static void
082fc60d
RE
2895arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2896{
2897 if (coff_sym_is_thumb (val))
2898 MSYMBOL_SET_SPECIAL (msym);
2899}
2900
60c5725c
DJ
2901static void
2902arm_objfile_data_cleanup (struct objfile *objfile, void *arg)
2903{
2904 struct arm_per_objfile *data = arg;
2905 unsigned int i;
2906
2907 for (i = 0; i < objfile->obfd->section_count; i++)
2908 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
2909}
2910
2911static void
2912arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
2913 asymbol *sym)
2914{
2915 const char *name = bfd_asymbol_name (sym);
2916 struct arm_per_objfile *data;
2917 VEC(arm_mapping_symbol_s) **map_p;
2918 struct arm_mapping_symbol new_map_sym;
2919
2920 gdb_assert (name[0] == '$');
2921 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
2922 return;
2923
2924 data = objfile_data (objfile, arm_objfile_data_key);
2925 if (data == NULL)
2926 {
2927 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
2928 struct arm_per_objfile);
2929 set_objfile_data (objfile, arm_objfile_data_key, data);
2930 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2931 objfile->obfd->section_count,
2932 VEC(arm_mapping_symbol_s) *);
2933 }
2934 map_p = &data->section_maps[bfd_get_section (sym)->index];
2935
2936 new_map_sym.value = sym->value;
2937 new_map_sym.type = name[1];
2938
2939 /* Assume that most mapping symbols appear in order of increasing
2940 value. If they were randomly distributed, it would be faster to
2941 always push here and then sort at first use. */
2942 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
2943 {
2944 struct arm_mapping_symbol *prev_map_sym;
2945
2946 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
2947 if (prev_map_sym->value >= sym->value)
2948 {
2949 unsigned int idx;
2950 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
2951 arm_compare_mapping_symbols);
2952 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
2953 return;
2954 }
2955 }
2956
2957 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
2958}
2959
756fe439 2960static void
61a1198a 2961arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
756fe439 2962{
61a1198a 2963 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
756fe439
DJ
2964
2965 /* If necessary, set the T bit. */
2966 if (arm_apcs_32)
2967 {
61a1198a
UW
2968 ULONGEST val;
2969 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
756fe439 2970 if (arm_pc_is_thumb (pc))
b39cc962 2971 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T);
756fe439 2972 else
61a1198a 2973 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
b39cc962 2974 val & ~(ULONGEST) CPSR_T);
756fe439
DJ
2975 }
2976}
123dc839
DJ
2977
2978static struct value *
2979value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2980{
2981 const int *reg_p = baton;
2982 return value_of_register (*reg_p, frame);
2983}
97e03143 2984\f
70f80edf
JT
2985static enum gdb_osabi
2986arm_elf_osabi_sniffer (bfd *abfd)
97e03143 2987{
2af48f68 2988 unsigned int elfosabi;
70f80edf 2989 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
97e03143 2990
70f80edf 2991 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
97e03143 2992
28e97307
DJ
2993 if (elfosabi == ELFOSABI_ARM)
2994 /* GNU tools use this value. Check note sections in this case,
2995 as well. */
2996 bfd_map_over_sections (abfd,
2997 generic_elf_osabi_sniff_abi_tag_sections,
2998 &osabi);
97e03143 2999
28e97307 3000 /* Anything else will be handled by the generic ELF sniffer. */
70f80edf 3001 return osabi;
97e03143
RE
3002}
3003
70f80edf 3004\f
da3c6d4a
MS
3005/* Initialize the current architecture based on INFO. If possible,
3006 re-use an architecture from ARCHES, which is a list of
3007 architectures already created during this debugging session.
97e03143 3008
da3c6d4a
MS
3009 Called e.g. at program startup, when reading a core file, and when
3010 reading a binary file. */
97e03143 3011
39bbf761
RE
3012static struct gdbarch *
3013arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3014{
97e03143 3015 struct gdbarch_tdep *tdep;
39bbf761 3016 struct gdbarch *gdbarch;
28e97307
DJ
3017 struct gdbarch_list *best_arch;
3018 enum arm_abi_kind arm_abi = arm_abi_global;
3019 enum arm_float_model fp_model = arm_fp_model;
123dc839
DJ
3020 struct tdesc_arch_data *tdesc_data = NULL;
3021 int i;
ff6f572f 3022 int have_fpa_registers = 1;
123dc839
DJ
3023
3024 /* Check any target description for validity. */
3025 if (tdesc_has_registers (info.target_desc))
3026 {
3027 /* For most registers we require GDB's default names; but also allow
3028 the numeric names for sp / lr / pc, as a convenience. */
3029 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
3030 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
3031 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
3032
3033 const struct tdesc_feature *feature;
3034 int i, valid_p;
3035
3036 feature = tdesc_find_feature (info.target_desc,
3037 "org.gnu.gdb.arm.core");
3038 if (feature == NULL)
3039 return NULL;
3040
3041 tdesc_data = tdesc_data_alloc ();
3042
3043 valid_p = 1;
3044 for (i = 0; i < ARM_SP_REGNUM; i++)
3045 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3046 arm_register_names[i]);
3047 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3048 ARM_SP_REGNUM,
3049 arm_sp_names);
3050 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3051 ARM_LR_REGNUM,
3052 arm_lr_names);
3053 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3054 ARM_PC_REGNUM,
3055 arm_pc_names);
3056 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3057 ARM_PS_REGNUM, "cpsr");
3058
3059 if (!valid_p)
3060 {
3061 tdesc_data_cleanup (tdesc_data);
3062 return NULL;
3063 }
3064
3065 feature = tdesc_find_feature (info.target_desc,
3066 "org.gnu.gdb.arm.fpa");
3067 if (feature != NULL)
3068 {
3069 valid_p = 1;
3070 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
3071 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3072 arm_register_names[i]);
3073 if (!valid_p)
3074 {
3075 tdesc_data_cleanup (tdesc_data);
3076 return NULL;
3077 }
3078 }
ff6f572f
DJ
3079 else
3080 have_fpa_registers = 0;
3081
3082 feature = tdesc_find_feature (info.target_desc,
3083 "org.gnu.gdb.xscale.iwmmxt");
3084 if (feature != NULL)
3085 {
3086 static const char *const iwmmxt_names[] = {
3087 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
3088 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
3089 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
3090 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
3091 };
3092
3093 valid_p = 1;
3094 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
3095 valid_p
3096 &= tdesc_numbered_register (feature, tdesc_data, i,
3097 iwmmxt_names[i - ARM_WR0_REGNUM]);
3098
3099 /* Check for the control registers, but do not fail if they
3100 are missing. */
3101 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
3102 tdesc_numbered_register (feature, tdesc_data, i,
3103 iwmmxt_names[i - ARM_WR0_REGNUM]);
3104
3105 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
3106 valid_p
3107 &= tdesc_numbered_register (feature, tdesc_data, i,
3108 iwmmxt_names[i - ARM_WR0_REGNUM]);
3109
3110 if (!valid_p)
3111 {
3112 tdesc_data_cleanup (tdesc_data);
3113 return NULL;
3114 }
3115 }
123dc839 3116 }
39bbf761 3117
28e97307
DJ
3118 /* If we have an object to base this architecture on, try to determine
3119 its ABI. */
39bbf761 3120
28e97307 3121 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
97e03143 3122 {
6b26d61a 3123 int ei_osabi, e_flags;
28e97307 3124
4be87837 3125 switch (bfd_get_flavour (info.abfd))
97e03143 3126 {
4be87837
DJ
3127 case bfd_target_aout_flavour:
3128 /* Assume it's an old APCS-style ABI. */
28e97307 3129 arm_abi = ARM_ABI_APCS;
4be87837 3130 break;
97e03143 3131
4be87837
DJ
3132 case bfd_target_coff_flavour:
3133 /* Assume it's an old APCS-style ABI. */
3134 /* XXX WinCE? */
28e97307
DJ
3135 arm_abi = ARM_ABI_APCS;
3136 break;
3137
3138 case bfd_target_elf_flavour:
3139 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
6b26d61a
MK
3140 e_flags = elf_elfheader (info.abfd)->e_flags;
3141
28e97307
DJ
3142 if (ei_osabi == ELFOSABI_ARM)
3143 {
3144 /* GNU tools used to use this value, but do not for EABI
6b26d61a
MK
3145 objects. There's nowhere to tag an EABI version
3146 anyway, so assume APCS. */
28e97307
DJ
3147 arm_abi = ARM_ABI_APCS;
3148 }
3149 else if (ei_osabi == ELFOSABI_NONE)
3150 {
6b26d61a 3151 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
28e97307
DJ
3152
3153 switch (eabi_ver)
3154 {
3155 case EF_ARM_EABI_UNKNOWN:
3156 /* Assume GNU tools. */
3157 arm_abi = ARM_ABI_APCS;
3158 break;
3159
3160 case EF_ARM_EABI_VER4:
625b5003 3161 case EF_ARM_EABI_VER5:
28e97307 3162 arm_abi = ARM_ABI_AAPCS;
2af48f68
PB
3163 /* EABI binaries default to VFP float ordering. */
3164 if (fp_model == ARM_FLOAT_AUTO)
3165 fp_model = ARM_FLOAT_SOFT_VFP;
28e97307
DJ
3166 break;
3167
3168 default:
6b26d61a 3169 /* Leave it as "auto". */
28e97307 3170 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
6b26d61a
MK
3171 break;
3172 }
3173 }
3174
3175 if (fp_model == ARM_FLOAT_AUTO)
3176 {
3177 int e_flags = elf_elfheader (info.abfd)->e_flags;
3178
3179 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
3180 {
3181 case 0:
3182 /* Leave it as "auto". Strictly speaking this case
3183 means FPA, but almost nobody uses that now, and
3184 many toolchains fail to set the appropriate bits
3185 for the floating-point model they use. */
3186 break;
3187 case EF_ARM_SOFT_FLOAT:
3188 fp_model = ARM_FLOAT_SOFT_FPA;
3189 break;
3190 case EF_ARM_VFP_FLOAT:
3191 fp_model = ARM_FLOAT_VFP;
3192 break;
3193 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
3194 fp_model = ARM_FLOAT_SOFT_VFP;
28e97307
DJ
3195 break;
3196 }
3197 }
9d4fde75
SS
3198
3199 if (e_flags & EF_ARM_BE8)
3200 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3201
4be87837 3202 break;
97e03143 3203
4be87837 3204 default:
28e97307 3205 /* Leave it as "auto". */
50ceaba5 3206 break;
97e03143
RE
3207 }
3208 }
3209
28e97307
DJ
3210 /* If there is already a candidate, use it. */
3211 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3212 best_arch != NULL;
3213 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3214 {
b8926edc
DJ
3215 if (arm_abi != ARM_ABI_AUTO
3216 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
28e97307
DJ
3217 continue;
3218
b8926edc
DJ
3219 if (fp_model != ARM_FLOAT_AUTO
3220 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
28e97307
DJ
3221 continue;
3222
3223 /* Found a match. */
3224 break;
3225 }
97e03143 3226
28e97307 3227 if (best_arch != NULL)
123dc839
DJ
3228 {
3229 if (tdesc_data != NULL)
3230 tdesc_data_cleanup (tdesc_data);
3231 return best_arch->gdbarch;
3232 }
28e97307
DJ
3233
3234 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
97e03143
RE
3235 gdbarch = gdbarch_alloc (&info, tdep);
3236
28e97307
DJ
3237 /* Record additional information about the architecture we are defining.
3238 These are gdbarch discriminators, like the OSABI. */
3239 tdep->arm_abi = arm_abi;
3240 tdep->fp_model = fp_model;
ff6f572f 3241 tdep->have_fpa_registers = have_fpa_registers;
08216dd7
RE
3242
3243 /* Breakpoints. */
9d4fde75 3244 switch (info.byte_order_for_code)
67255d04
RE
3245 {
3246 case BFD_ENDIAN_BIG:
66e810cd
RE
3247 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
3248 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
3249 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
3250 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
3251
67255d04
RE
3252 break;
3253
3254 case BFD_ENDIAN_LITTLE:
66e810cd
RE
3255 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
3256 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
3257 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
3258 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
3259
67255d04
RE
3260 break;
3261
3262 default:
3263 internal_error (__FILE__, __LINE__,
edefbb7c 3264 _("arm_gdbarch_init: bad byte order for float format"));
67255d04
RE
3265 }
3266
d7b486e7
RE
3267 /* On ARM targets char defaults to unsigned. */
3268 set_gdbarch_char_signed (gdbarch, 0);
3269
9df628e0 3270 /* This should be low enough for everything. */
97e03143 3271 tdep->lowest_pc = 0x20;
94c30b78 3272 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
97e03143 3273
7c00367c
MK
3274 /* The default, for both APCS and AAPCS, is to return small
3275 structures in registers. */
3276 tdep->struct_return = reg_struct_return;
3277
2dd604e7 3278 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
f53f0d0b 3279 set_gdbarch_frame_align (gdbarch, arm_frame_align);
39bbf761 3280
756fe439
DJ
3281 set_gdbarch_write_pc (gdbarch, arm_write_pc);
3282
148754e5 3283 /* Frame handling. */
a262aec2 3284 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
eb5492fa
DJ
3285 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
3286 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
3287
eb5492fa 3288 frame_base_set_default (gdbarch, &arm_normal_base);
148754e5 3289
34e8f22d
RE
3290 /* Address manipulation. */
3291 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
3292 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
3293
34e8f22d
RE
3294 /* Advance PC across function entry code. */
3295 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
3296
190dce09
UW
3297 /* Skip trampolines. */
3298 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
3299
34e8f22d
RE
3300 /* The stack grows downward. */
3301 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3302
3303 /* Breakpoint manipulation. */
3304 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
34e8f22d
RE
3305
3306 /* Information about registers, etc. */
0ba6dca9 3307 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
34e8f22d
RE
3308 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
3309 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
ff6f572f 3310 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
7a5ea0d4 3311 set_gdbarch_register_type (gdbarch, arm_register_type);
34e8f22d 3312
ff6f572f
DJ
3313 /* This "info float" is FPA-specific. Use the generic version if we
3314 do not have FPA. */
3315 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
3316 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
3317
26216b98 3318 /* Internal <-> external register number maps. */
ff6f572f 3319 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
26216b98
AC
3320 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
3321
34e8f22d
RE
3322 set_gdbarch_register_name (gdbarch, arm_register_name);
3323
3324 /* Returning results. */
2af48f68 3325 set_gdbarch_return_value (gdbarch, arm_return_value);
34e8f22d 3326
03d48a7d
RE
3327 /* Disassembly. */
3328 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3329
34e8f22d
RE
3330 /* Minsymbol frobbing. */
3331 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3332 set_gdbarch_coff_make_msymbol_special (gdbarch,
3333 arm_coff_make_msymbol_special);
60c5725c 3334 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
34e8f22d 3335
0d5de010
DJ
3336 /* Virtual tables. */
3337 set_gdbarch_vbit_in_delta (gdbarch, 1);
3338
97e03143 3339 /* Hook in the ABI-specific overrides, if they have been registered. */
4be87837 3340 gdbarch_init_osabi (info, gdbarch);
97e03143 3341
b39cc962
DJ
3342 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
3343
eb5492fa 3344 /* Add some default predicates. */
a262aec2
DJ
3345 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
3346 dwarf2_append_unwinders (gdbarch);
3347 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
eb5492fa 3348
97e03143
RE
3349 /* Now we have tuned the configuration, set a few final things,
3350 based on what the OS ABI has told us. */
3351
b8926edc
DJ
3352 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3353 binaries are always marked. */
3354 if (tdep->arm_abi == ARM_ABI_AUTO)
3355 tdep->arm_abi = ARM_ABI_APCS;
3356
3357 /* We used to default to FPA for generic ARM, but almost nobody
3358 uses that now, and we now provide a way for the user to force
3359 the model. So default to the most useful variant. */
3360 if (tdep->fp_model == ARM_FLOAT_AUTO)
3361 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3362
9df628e0
RE
3363 if (tdep->jb_pc >= 0)
3364 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3365
08216dd7 3366 /* Floating point sizes and format. */
8da61cc4 3367 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
b8926edc 3368 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
08216dd7 3369 {
8da61cc4
DJ
3370 set_gdbarch_double_format
3371 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3372 set_gdbarch_long_double_format
3373 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3374 }
3375 else
3376 {
3377 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3378 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
08216dd7
RE
3379 }
3380
123dc839 3381 if (tdesc_data)
7cc46491 3382 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
123dc839
DJ
3383
3384 /* Add standard register aliases. We add aliases even for those
3385 nanes which are used by the current architecture - it's simpler,
3386 and does no harm, since nothing ever lists user registers. */
3387 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3388 user_reg_add (gdbarch, arm_register_aliases[i].name,
3389 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3390
39bbf761
RE
3391 return gdbarch;
3392}
3393
97e03143 3394static void
2af46ca0 3395arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
97e03143 3396{
2af46ca0 3397 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
97e03143
RE
3398
3399 if (tdep == NULL)
3400 return;
3401
edefbb7c 3402 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
97e03143
RE
3403 (unsigned long) tdep->lowest_pc);
3404}
3405
a78f21af
AC
3406extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3407
c906108c 3408void
ed9a39eb 3409_initialize_arm_tdep (void)
c906108c 3410{
bc90b915
FN
3411 struct ui_file *stb;
3412 long length;
26304000 3413 struct cmd_list_element *new_set, *new_show;
53904c9e
AC
3414 const char *setname;
3415 const char *setdesc;
4bd7b427 3416 const char *const *regnames;
bc90b915
FN
3417 int numregs, i, j;
3418 static char *helptext;
edefbb7c
AC
3419 char regdesc[1024], *rdptr = regdesc;
3420 size_t rest = sizeof (regdesc);
085dd6e6 3421
42cf1509 3422 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
97e03143 3423
60c5725c
DJ
3424 arm_objfile_data_key
3425 = register_objfile_data_with_cleanup (arm_objfile_data_cleanup);
3426
70f80edf
JT
3427 /* Register an ELF OS ABI sniffer for ARM binaries. */
3428 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3429 bfd_target_elf_flavour,
3430 arm_elf_osabi_sniffer);
3431
94c30b78 3432 /* Get the number of possible sets of register names defined in opcodes. */
afd7eef0
RE
3433 num_disassembly_options = get_arm_regname_num_options ();
3434
3435 /* Add root prefix command for all "set arm"/"show arm" commands. */
3436 add_prefix_cmd ("arm", no_class, set_arm_command,
edefbb7c 3437 _("Various ARM-specific commands."),
afd7eef0
RE
3438 &setarmcmdlist, "set arm ", 0, &setlist);
3439
3440 add_prefix_cmd ("arm", no_class, show_arm_command,
edefbb7c 3441 _("Various ARM-specific commands."),
afd7eef0 3442 &showarmcmdlist, "show arm ", 0, &showlist);
bc90b915 3443
94c30b78 3444 /* Sync the opcode insn printer with our register viewer. */
bc90b915 3445 parse_arm_disassembler_option ("reg-names-std");
c5aa993b 3446
eefe576e
AC
3447 /* Initialize the array that will be passed to
3448 add_setshow_enum_cmd(). */
afd7eef0
RE
3449 valid_disassembly_styles
3450 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3451 for (i = 0; i < num_disassembly_options; i++)
bc90b915
FN
3452 {
3453 numregs = get_arm_regnames (i, &setname, &setdesc, &regnames);
afd7eef0 3454 valid_disassembly_styles[i] = setname;
edefbb7c
AC
3455 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3456 rdptr += length;
3457 rest -= length;
123dc839
DJ
3458 /* When we find the default names, tell the disassembler to use
3459 them. */
bc90b915
FN
3460 if (!strcmp (setname, "std"))
3461 {
afd7eef0 3462 disassembly_style = setname;
bc90b915
FN
3463 set_arm_regname_option (i);
3464 }
3465 }
94c30b78 3466 /* Mark the end of valid options. */
afd7eef0 3467 valid_disassembly_styles[num_disassembly_options] = NULL;
c906108c 3468
edefbb7c
AC
3469 /* Create the help text. */
3470 stb = mem_fileopen ();
3471 fprintf_unfiltered (stb, "%s%s%s",
3472 _("The valid values are:\n"),
3473 regdesc,
3474 _("The default is \"std\"."));
bc90b915
FN
3475 helptext = ui_file_xstrdup (stb, &length);
3476 ui_file_delete (stb);
ed9a39eb 3477
edefbb7c
AC
3478 add_setshow_enum_cmd("disassembler", no_class,
3479 valid_disassembly_styles, &disassembly_style,
3480 _("Set the disassembly style."),
3481 _("Show the disassembly style."),
3482 helptext,
2c5b56ce 3483 set_disassembly_style_sfunc,
7915a72c 3484 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
7376b4c2 3485 &setarmcmdlist, &showarmcmdlist);
edefbb7c
AC
3486
3487 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3488 _("Set usage of ARM 32-bit mode."),
3489 _("Show usage of ARM 32-bit mode."),
3490 _("When off, a 26-bit PC will be used."),
2c5b56ce 3491 NULL,
7915a72c 3492 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
26304000 3493 &setarmcmdlist, &showarmcmdlist);
c906108c 3494
fd50bc42 3495 /* Add a command to allow the user to force the FPU model. */
edefbb7c
AC
3496 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, &current_fp_model,
3497 _("Set the floating point type."),
3498 _("Show the floating point type."),
3499 _("auto - Determine the FP typefrom the OS-ABI.\n\
3500softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3501fpa - FPA co-processor (GCC compiled).\n\
3502softvfp - Software FP with pure-endian doubles.\n\
3503vfp - VFP co-processor."),
edefbb7c 3504 set_fp_model_sfunc, show_fp_model,
7376b4c2 3505 &setarmcmdlist, &showarmcmdlist);
fd50bc42 3506
28e97307
DJ
3507 /* Add a command to allow the user to force the ABI. */
3508 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3509 _("Set the ABI."),
3510 _("Show the ABI."),
3511 NULL, arm_set_abi, arm_show_abi,
3512 &setarmcmdlist, &showarmcmdlist);
3513
0428b8f5
DJ
3514 /* Add two commands to allow the user to force the assumed
3515 execution mode. */
3516 add_setshow_enum_cmd ("fallback-mode", class_support,
3517 arm_mode_strings, &arm_fallback_mode_string,
3518 _("Set the mode assumed when symbols are unavailable."),
3519 _("Show the mode assumed when symbols are unavailable."),
3520 NULL, NULL, arm_show_fallback_mode,
3521 &setarmcmdlist, &showarmcmdlist);
3522 add_setshow_enum_cmd ("force-mode", class_support,
3523 arm_mode_strings, &arm_force_mode_string,
3524 _("Set the mode assumed even when symbols are available."),
3525 _("Show the mode assumed even when symbols are available."),
3526 NULL, NULL, arm_show_force_mode,
3527 &setarmcmdlist, &showarmcmdlist);
3528
6529d2dd 3529 /* Debugging flag. */
edefbb7c
AC
3530 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3531 _("Set ARM debugging."),
3532 _("Show ARM debugging."),
3533 _("When on, arm-specific debugging is enabled."),
2c5b56ce 3534 NULL,
7915a72c 3535 NULL, /* FIXME: i18n: "ARM debugging is %s. */
26304000 3536 &setdebuglist, &showdebuglist);
c906108c 3537}
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