Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
c3b4394c | 3 | 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
e8b09175 | 31 | #include "dis-asm.h" /* For register flavors. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
34e8f22d RE |
37 | |
38 | #include "arm-tdep.h" | |
26216b98 | 39 | #include "gdb/sim-arm.h" |
34e8f22d | 40 | |
082fc60d RE |
41 | #include "elf-bfd.h" |
42 | #include "coff/internal.h" | |
97e03143 | 43 | #include "elf/arm.h" |
c906108c | 44 | |
26216b98 AC |
45 | #include "gdb_assert.h" |
46 | ||
6529d2dd AC |
47 | static int arm_debug; |
48 | ||
2a451106 KB |
49 | /* Each OS has a different mechanism for accessing the various |
50 | registers stored in the sigcontext structure. | |
51 | ||
52 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
53 | function pointer) which may be used to determine the addresses | |
54 | of the various saved registers in the sigcontext structure. | |
55 | ||
56 | For the ARM target, there are three parameters to this function. | |
57 | The first is the pc value of the frame under consideration, the | |
58 | second the stack pointer of this frame, and the last is the | |
59 | register number to fetch. | |
60 | ||
61 | If the tm.h file does not define this macro, then it's assumed that | |
62 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
63 | be 0. | |
64 | ||
65 | When it comes time to multi-arching this code, see the identically | |
66 | named machinery in ia64-tdep.c for an example of how it could be | |
67 | done. It should not be necessary to modify the code below where | |
68 | this macro is used. */ | |
69 | ||
3bb04bdd AC |
70 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
71 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
72 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
73 | #endif | |
74 | #else | |
75 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
76 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
77 | #endif |
78 | ||
082fc60d RE |
79 | /* Macros for setting and testing a bit in a minimal symbol that marks |
80 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
81 | is used for this purpose. This field is already being used to store | |
82 | the symbol size, so the assumption is that the symbol size cannot | |
83 | exceed 2^31. | |
84 | ||
85 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
86 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
87 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
88 | i.e. the "info" field with the "special" bit | |
89 | masked out. */ | |
90 | ||
91 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
92 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
93 | | 0x80000000) | |
94 | ||
95 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
96 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
97 | ||
98 | #define MSYMBOL_SIZE(msym) \ | |
99 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 100 | |
94c30b78 | 101 | /* Number of different reg name sets (options). */ |
bc90b915 FN |
102 | static int num_flavor_options; |
103 | ||
104 | /* We have more registers than the disassembler as gdb can print the value | |
105 | of special registers as well. | |
106 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 107 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 108 | |
94c30b78 | 109 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 110 | static char * arm_register_name_strings[] = |
da59e081 JM |
111 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
112 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
113 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
114 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
115 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
116 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 117 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 118 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 119 | |
bc90b915 | 120 | /* Valid register name flavors. */ |
53904c9e | 121 | static const char **valid_flavors; |
ed9a39eb | 122 | |
94c30b78 | 123 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 124 | static const char *disassembly_flavor; |
94c30b78 | 125 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 126 | static int current_option; |
96baa820 | 127 | |
ed9a39eb JM |
128 | /* This is used to keep the bfd arch_info in sync with the disassembly |
129 | flavor. */ | |
130 | static void set_disassembly_flavor_sfunc(char *, int, | |
131 | struct cmd_list_element *); | |
132 | static void set_disassembly_flavor (void); | |
133 | ||
b508a996 RE |
134 | static void convert_from_extended (const struct floatformat *, const void *, |
135 | void *); | |
136 | static void convert_to_extended (const struct floatformat *, void *, | |
137 | const void *); | |
ed9a39eb JM |
138 | |
139 | /* Define other aspects of the stack frame. We keep the offsets of | |
140 | all saved registers, 'cause we need 'em a lot! We also keep the | |
141 | current size of the stack frame, and the offset of the frame | |
142 | pointer from the stack pointer (for frameless functions, and when | |
94c30b78 | 143 | we're still in the prologue of a function with a frame). */ |
ed9a39eb JM |
144 | |
145 | struct frame_extra_info | |
c3b4394c RE |
146 | { |
147 | int framesize; | |
148 | int frameoffset; | |
149 | int framereg; | |
150 | }; | |
ed9a39eb | 151 | |
bc90b915 FN |
152 | /* Addresses for calling Thumb functions have the bit 0 set. |
153 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
154 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
155 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
156 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
157 | ||
39bbf761 | 158 | static int |
ed9a39eb | 159 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 160 | { |
c906108c SS |
161 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
162 | } | |
163 | ||
94c30b78 | 164 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
165 | |
166 | int arm_apcs_32 = 1; | |
167 | ||
ed9a39eb JM |
168 | /* Flag set by arm_fix_call_dummy that tells whether the target |
169 | function is a Thumb function. This flag is checked by | |
170 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
171 | its use in valops.c) to pass the function address as an additional | |
172 | parameter. */ | |
c906108c SS |
173 | |
174 | static int target_is_thumb; | |
175 | ||
ed9a39eb JM |
176 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
177 | function is a Thumb function. This flag is checked by | |
178 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
179 | |
180 | static int caller_is_thumb; | |
181 | ||
ed9a39eb JM |
182 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
183 | function. */ | |
c906108c | 184 | |
34e8f22d | 185 | int |
2a451106 | 186 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 187 | { |
c5aa993b | 188 | struct minimal_symbol *sym; |
c906108c | 189 | |
ed9a39eb | 190 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
191 | if (IS_THUMB_ADDR (memaddr)) |
192 | return 1; | |
193 | ||
ed9a39eb | 194 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
195 | sym = lookup_minimal_symbol_by_pc (memaddr); |
196 | if (sym) | |
197 | { | |
c5aa993b | 198 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
199 | } |
200 | else | |
ed9a39eb JM |
201 | { |
202 | return 0; | |
203 | } | |
c906108c SS |
204 | } |
205 | ||
ed9a39eb JM |
206 | /* Determine if the program counter specified in MEMADDR is in a call |
207 | dummy being called from a Thumb function. */ | |
c906108c | 208 | |
34e8f22d | 209 | int |
2a451106 | 210 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 211 | { |
c5aa993b | 212 | CORE_ADDR sp = read_sp (); |
c906108c | 213 | |
dfcd3bfb JM |
214 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
215 | is the best we can do. We are trying to determine if the pc is on | |
216 | the stack, which (hopefully) will only happen in a call dummy. | |
217 | We hope the current stack pointer is not so far alway from the dummy | |
218 | frame location (true if we have not pushed large data structures or | |
219 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 220 | code regions as part of the stack (true for most practical purposes). */ |
ae45cd16 | 221 | if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
222 | return caller_is_thumb; |
223 | else | |
224 | return 0; | |
225 | } | |
226 | ||
181c1381 | 227 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 228 | static CORE_ADDR |
ed9a39eb | 229 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 230 | { |
a3a2ee65 JT |
231 | if (arm_apcs_32) |
232 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 233 | else |
a3a2ee65 | 234 | return (val & 0x03fffffc); |
c906108c SS |
235 | } |
236 | ||
181c1381 RE |
237 | /* When reading symbols, we need to zap the low bit of the address, |
238 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 239 | static CORE_ADDR |
181c1381 RE |
240 | arm_smash_text_address (CORE_ADDR val) |
241 | { | |
242 | return val & ~1; | |
243 | } | |
244 | ||
34e8f22d RE |
245 | /* Immediately after a function call, return the saved pc. Can't |
246 | always go through the frames for this because on some machines the | |
247 | new frame is not set up until the new function executes some | |
248 | instructions. */ | |
249 | ||
250 | static CORE_ADDR | |
ed9a39eb | 251 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 252 | { |
34e8f22d | 253 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
254 | } |
255 | ||
0defa245 RE |
256 | /* Determine whether the function invocation represented by FI has a |
257 | frame on the stack associated with it. If it does return zero, | |
258 | otherwise return 1. */ | |
259 | ||
148754e5 | 260 | static int |
ed9a39eb | 261 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 262 | { |
392a587b | 263 | CORE_ADDR func_start, after_prologue; |
96baa820 | 264 | int frameless; |
ed9a39eb | 265 | |
0defa245 RE |
266 | /* Sometimes we have functions that do a little setup (like saving the |
267 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
268 | The symbol table will report this as a prologue. However, it is | |
269 | important not to try to parse these partial frames as frames, or we | |
270 | will get really confused. | |
271 | ||
272 | So I will demand 3 instructions between the start & end of the | |
273 | prologue before I call it a real prologue, i.e. at least | |
274 | mov ip, sp, | |
275 | stmdb sp!, {} | |
276 | sub sp, ip, #4. */ | |
277 | ||
392a587b | 278 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 279 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 280 | |
96baa820 | 281 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 282 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 283 | be func_start + 8. */ |
ed9a39eb | 284 | |
96baa820 | 285 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
286 | return frameless; |
287 | } | |
288 | ||
0defa245 | 289 | /* The address of the arguments in the frame. */ |
148754e5 | 290 | static CORE_ADDR |
0defa245 RE |
291 | arm_frame_args_address (struct frame_info *fi) |
292 | { | |
293 | return fi->frame; | |
294 | } | |
295 | ||
296 | /* The address of the local variables in the frame. */ | |
148754e5 | 297 | static CORE_ADDR |
0defa245 RE |
298 | arm_frame_locals_address (struct frame_info *fi) |
299 | { | |
300 | return fi->frame; | |
301 | } | |
302 | ||
303 | /* The number of arguments being passed in the frame. */ | |
148754e5 | 304 | static int |
0defa245 RE |
305 | arm_frame_num_args (struct frame_info *fi) |
306 | { | |
307 | /* We have no way of knowing. */ | |
308 | return -1; | |
309 | } | |
310 | ||
c906108c | 311 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
312 | push {r7, lr} |
313 | add sp, sp, #-28 | |
314 | add r7, sp, #12 | |
c906108c | 315 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
316 | mov r7, sp |
317 | ||
318 | or like this: | |
319 | push {r7, lr} | |
320 | mov r7, sp | |
321 | sub sp, #12 | |
322 | ||
323 | or, on tpcs, like this: | |
324 | sub sp,#16 | |
325 | push {r7, lr} | |
326 | (many instructions) | |
327 | mov r7, sp | |
328 | sub sp, #12 | |
329 | ||
330 | There is always one instruction of three classes: | |
331 | 1 - push | |
332 | 2 - setting of r7 | |
333 | 3 - adjusting of sp | |
334 | ||
335 | When we have found at least one of each class we are done with the prolog. | |
336 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 337 | */ |
c906108c SS |
338 | |
339 | static CORE_ADDR | |
c7885828 | 340 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
341 | { |
342 | CORE_ADDR current_pc; | |
da3c6d4a MS |
343 | /* findmask: |
344 | bit 0 - push { rlist } | |
345 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
346 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
347 | */ | |
348 | int findmask = 0; | |
349 | ||
94c30b78 MS |
350 | for (current_pc = pc; |
351 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 352 | current_pc += 2) |
c906108c SS |
353 | { |
354 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
355 | ||
94c30b78 | 356 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 357 | { |
94c30b78 | 358 | findmask |= 1; /* push found */ |
da59e081 | 359 | } |
da3c6d4a MS |
360 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
361 | sub sp, #simm */ | |
da59e081 | 362 | { |
94c30b78 | 363 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
364 | continue; |
365 | else | |
94c30b78 | 366 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
367 | } |
368 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
369 | { | |
94c30b78 | 370 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
371 | } |
372 | else if (insn == 0x466f) /* mov r7, sp */ | |
373 | { | |
94c30b78 | 374 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 375 | } |
3d74b771 FF |
376 | else if (findmask == (4+2+1)) |
377 | { | |
da3c6d4a MS |
378 | /* We have found one of each type of prologue instruction */ |
379 | break; | |
3d74b771 | 380 | } |
da59e081 | 381 | else |
94c30b78 | 382 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 383 | instruction from outside the prolog scheduled here for |
94c30b78 | 384 | optimization. */ |
da3c6d4a | 385 | continue; |
c906108c SS |
386 | } |
387 | ||
388 | return current_pc; | |
389 | } | |
390 | ||
da3c6d4a MS |
391 | /* Advance the PC across any function entry prologue instructions to |
392 | reach some "real" code. | |
34e8f22d RE |
393 | |
394 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 395 | prologue: |
c906108c | 396 | |
c5aa993b JM |
397 | mov ip, sp |
398 | [stmfd sp!, {a1,a2,a3,a4}] | |
399 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
400 | [stfe f7, [sp, #-12]!] |
401 | [stfe f6, [sp, #-12]!] | |
402 | [stfe f5, [sp, #-12]!] | |
403 | [stfe f4, [sp, #-12]!] | |
404 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 405 | |
34e8f22d | 406 | static CORE_ADDR |
ed9a39eb | 407 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
408 | { |
409 | unsigned long inst; | |
410 | CORE_ADDR skip_pc; | |
b8d5e71d | 411 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 412 | char *func_name; |
c906108c SS |
413 | struct symtab_and_line sal; |
414 | ||
848cfffb | 415 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
ae45cd16 | 416 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
848cfffb AC |
417 | return pc; |
418 | ||
96baa820 | 419 | /* See what the symbol table says. */ |
ed9a39eb | 420 | |
50f6fb4b | 421 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 422 | { |
50f6fb4b CV |
423 | struct symbol *sym; |
424 | ||
425 | /* Found a function. */ | |
426 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
427 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
428 | { | |
94c30b78 | 429 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
430 | sal = find_pc_line (func_addr, 0); |
431 | if ((sal.line != 0) && (sal.end < func_end)) | |
432 | return sal.end; | |
433 | } | |
c906108c SS |
434 | } |
435 | ||
436 | /* Check if this is Thumb code. */ | |
437 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 438 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
439 | |
440 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 441 | by disassembling the instructions. */ |
c906108c | 442 | |
b8d5e71d MS |
443 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
444 | if (func_end == 0 || func_end > pc + 64) | |
445 | func_end = pc + 64; | |
c906108c | 446 | |
b8d5e71d | 447 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 448 | { |
f43845b3 | 449 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 450 | |
b8d5e71d MS |
451 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
452 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
453 | continue; | |
c906108c | 454 | |
b8d5e71d MS |
455 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
456 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
457 | continue; | |
c906108c | 458 | |
b8d5e71d MS |
459 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
460 | continue; | |
c906108c | 461 | |
b8d5e71d MS |
462 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
463 | continue; | |
11d3b27d | 464 | |
b8d5e71d MS |
465 | /* Any insns after this point may float into the code, if it makes |
466 | for better instruction scheduling, so we skip them only if we | |
467 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 468 | |
b8d5e71d MS |
469 | /* We may have either one sfmfd instruction here, or several stfe |
470 | insns, depending on the version of floating point code we | |
471 | support. */ | |
472 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
473 | continue; | |
474 | ||
475 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
476 | continue; | |
477 | ||
478 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
479 | continue; | |
480 | ||
481 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
482 | continue; | |
483 | ||
484 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
485 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
486 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
487 | continue; | |
488 | ||
489 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
490 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
491 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
492 | continue; | |
493 | ||
494 | /* Un-recognized instruction; stop scanning. */ | |
495 | break; | |
f43845b3 | 496 | } |
c906108c | 497 | |
b8d5e71d | 498 | return skip_pc; /* End of prologue */ |
c906108c | 499 | } |
94c30b78 | 500 | |
c5aa993b | 501 | /* *INDENT-OFF* */ |
c906108c SS |
502 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
503 | This function decodes a Thumb function prologue to determine: | |
504 | 1) the size of the stack frame | |
505 | 2) which registers are saved on it | |
506 | 3) the offsets of saved regs | |
507 | 4) the offset from the stack pointer to the frame pointer | |
508 | This information is stored in the "extra" fields of the frame_info. | |
509 | ||
da59e081 JM |
510 | A typical Thumb function prologue would create this stack frame |
511 | (offsets relative to FP) | |
c906108c SS |
512 | old SP -> 24 stack parameters |
513 | 20 LR | |
514 | 16 R7 | |
515 | R7 -> 0 local variables (16 bytes) | |
516 | SP -> -12 additional stack space (12 bytes) | |
517 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
518 | 12 bytes. The frame register is R7. |
519 | ||
da3c6d4a MS |
520 | The comments for thumb_skip_prolog() describe the algorithm we use |
521 | to detect the end of the prolog. */ | |
c5aa993b JM |
522 | /* *INDENT-ON* */ |
523 | ||
c906108c | 524 | static void |
ed9a39eb | 525 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
526 | { |
527 | CORE_ADDR prologue_start; | |
528 | CORE_ADDR prologue_end; | |
529 | CORE_ADDR current_pc; | |
94c30b78 | 530 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
531 | int saved_reg[16]; |
532 | /* findmask: | |
533 | bit 0 - push { rlist } | |
534 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
535 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
536 | */ | |
537 | int findmask = 0; | |
c5aa993b | 538 | int i; |
c906108c | 539 | |
848cfffb | 540 | /* Don't try to scan dummy frames. */ |
07555a72 | 541 | if (fi != NULL |
ae45cd16 | 542 | && DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
848cfffb AC |
543 | return; |
544 | ||
c5aa993b | 545 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
546 | { |
547 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
548 | ||
94c30b78 | 549 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
550 | prologue_end = fi->pc; |
551 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
94c30b78 | 552 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
553 | } |
554 | else | |
da3c6d4a MS |
555 | /* We're in the boondocks: allow for |
556 | 16 pushes, an add, and "mv fp,sp". */ | |
557 | prologue_end = prologue_start + 40; | |
c906108c SS |
558 | |
559 | prologue_end = min (prologue_end, fi->pc); | |
560 | ||
561 | /* Initialize the saved register map. When register H is copied to | |
562 | register L, we will put H in saved_reg[L]. */ | |
563 | for (i = 0; i < 16; i++) | |
564 | saved_reg[i] = i; | |
565 | ||
566 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
567 | frame pointer, adjust the stack pointer, and save registers. |
568 | Do this until all basic prolog instructions are found. */ | |
c906108c | 569 | |
c3b4394c | 570 | fi->extra_info->framesize = 0; |
da59e081 JM |
571 | for (current_pc = prologue_start; |
572 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
573 | current_pc += 2) | |
c906108c SS |
574 | { |
575 | unsigned short insn; | |
576 | int regno; | |
577 | int offset; | |
578 | ||
579 | insn = read_memory_unsigned_integer (current_pc, 2); | |
580 | ||
c5aa993b | 581 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 582 | { |
da59e081 | 583 | int mask; |
94c30b78 | 584 | findmask |= 1; /* push found */ |
c906108c SS |
585 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
586 | whether to save LR (R14). */ | |
da59e081 | 587 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 588 | |
b8d5e71d | 589 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 590 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 591 | if (mask & (1 << regno)) |
c5aa993b | 592 | { |
c3b4394c RE |
593 | fi->extra_info->framesize += 4; |
594 | fi->saved_regs[saved_reg[regno]] = | |
595 | -(fi->extra_info->framesize); | |
da3c6d4a MS |
596 | /* Reset saved register map. */ |
597 | saved_reg[regno] = regno; | |
c906108c SS |
598 | } |
599 | } | |
da3c6d4a MS |
600 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
601 | sub sp, #simm */ | |
c906108c | 602 | { |
b8d5e71d | 603 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
604 | continue; |
605 | else | |
94c30b78 | 606 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 607 | |
94c30b78 MS |
608 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
609 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 610 | { |
c3b4394c | 611 | fi->extra_info->frameoffset += offset; |
da59e081 JM |
612 | offset = -offset; |
613 | } | |
c3b4394c | 614 | fi->extra_info->framesize -= offset; |
c906108c SS |
615 | } |
616 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
617 | { | |
94c30b78 | 618 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
619 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
620 | /* get scaled offset */ | |
621 | fi->extra_info->frameoffset = (insn & 0xff) << 2; | |
c906108c | 622 | } |
da59e081 | 623 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 624 | { |
94c30b78 | 625 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
626 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
627 | fi->extra_info->frameoffset = 0; | |
34e8f22d | 628 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
629 | } |
630 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
631 | { | |
da3c6d4a | 632 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 633 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 634 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
635 | } |
636 | else | |
da3c6d4a MS |
637 | /* Something in the prolog that we don't care about or some |
638 | instruction from outside the prolog scheduled here for | |
639 | optimization. */ | |
640 | continue; | |
c906108c SS |
641 | } |
642 | } | |
643 | ||
ed9a39eb JM |
644 | /* Check if prologue for this frame's PC has already been scanned. If |
645 | it has, copy the relevant information about that prologue and | |
c906108c SS |
646 | return non-zero. Otherwise do not copy anything and return zero. |
647 | ||
648 | The information saved in the cache includes: | |
c5aa993b JM |
649 | * the frame register number; |
650 | * the size of the stack frame; | |
651 | * the offsets of saved regs (relative to the old SP); and | |
652 | * the offset from the stack pointer to the frame pointer | |
c906108c | 653 | |
ed9a39eb JM |
654 | The cache contains only one entry, since this is adequate for the |
655 | typical sequence of prologue scan requests we get. When performing | |
656 | a backtrace, GDB will usually ask to scan the same function twice | |
657 | in a row (once to get the frame chain, and once to fill in the | |
658 | extra frame information). */ | |
c906108c SS |
659 | |
660 | static struct frame_info prologue_cache; | |
661 | ||
662 | static int | |
ed9a39eb | 663 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
664 | { |
665 | int i; | |
666 | ||
667 | if (fi->pc == prologue_cache.pc) | |
668 | { | |
c3b4394c RE |
669 | fi->extra_info->framereg = prologue_cache.extra_info->framereg; |
670 | fi->extra_info->framesize = prologue_cache.extra_info->framesize; | |
671 | fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset; | |
672 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) | |
673 | fi->saved_regs[i] = prologue_cache.saved_regs[i]; | |
c906108c SS |
674 | return 1; |
675 | } | |
676 | else | |
677 | return 0; | |
678 | } | |
679 | ||
680 | ||
ed9a39eb | 681 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
682 | |
683 | static void | |
ed9a39eb | 684 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
685 | { |
686 | int i; | |
687 | ||
c5aa993b | 688 | prologue_cache.pc = fi->pc; |
c3b4394c RE |
689 | prologue_cache.extra_info->framereg = fi->extra_info->framereg; |
690 | prologue_cache.extra_info->framesize = fi->extra_info->framesize; | |
691 | prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset; | |
c5aa993b | 692 | |
c3b4394c RE |
693 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
694 | prologue_cache.saved_regs[i] = fi->saved_regs[i]; | |
c906108c SS |
695 | } |
696 | ||
697 | ||
ed9a39eb | 698 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
699 | 1) the size of the stack frame |
700 | 2) which registers are saved on it | |
701 | 3) the offsets of saved regs | |
702 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
703 | This information is stored in the "extra" fields of the frame_info. |
704 | ||
96baa820 JM |
705 | There are two basic forms for the ARM prologue. The fixed argument |
706 | function call will look like: | |
ed9a39eb JM |
707 | |
708 | mov ip, sp | |
709 | stmfd sp!, {fp, ip, lr, pc} | |
710 | sub fp, ip, #4 | |
711 | [sub sp, sp, #4] | |
96baa820 | 712 | |
c906108c | 713 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
714 | IP -> 4 (caller's stack) |
715 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
716 | -4 LR (return address in caller) | |
717 | -8 IP (copy of caller's SP) | |
718 | -12 FP (caller's FP) | |
719 | SP -> -28 Local variables | |
720 | ||
c906108c | 721 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
722 | 28 bytes. The stmfd call can also save any of the vN registers it |
723 | plans to use, which increases the frame size accordingly. | |
724 | ||
725 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
726 | because the ARM Store instructions always store PC + 8 when you read | |
727 | the PC register. | |
ed9a39eb | 728 | |
96baa820 JM |
729 | A variable argument function call will look like: |
730 | ||
ed9a39eb JM |
731 | mov ip, sp |
732 | stmfd sp!, {a1, a2, a3, a4} | |
733 | stmfd sp!, {fp, ip, lr, pc} | |
734 | sub fp, ip, #20 | |
735 | ||
96baa820 | 736 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
737 | IP -> 20 (caller's stack) |
738 | 16 A4 | |
739 | 12 A3 | |
740 | 8 A2 | |
741 | 4 A1 | |
742 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
743 | -4 LR (return address in caller) | |
744 | -8 IP (copy of caller's SP) | |
745 | -12 FP (caller's FP) | |
746 | SP -> -28 Local variables | |
96baa820 JM |
747 | |
748 | The frame size would thus be 48 bytes, and the frame offset would be | |
749 | 28 bytes. | |
750 | ||
751 | There is another potential complication, which is that the optimizer | |
752 | will try to separate the store of fp in the "stmfd" instruction from | |
753 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
754 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
755 | ||
756 | Also, note, the original version of the ARM toolchain claimed that there | |
757 | should be an | |
758 | ||
759 | instruction at the end of the prologue. I have never seen GCC produce | |
760 | this, and the ARM docs don't mention it. We still test for it below in | |
761 | case it happens... | |
ed9a39eb JM |
762 | |
763 | */ | |
c906108c SS |
764 | |
765 | static void | |
ed9a39eb | 766 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
767 | { |
768 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 769 | LONGEST return_value; |
c906108c SS |
770 | CORE_ADDR prologue_start, prologue_end, current_pc; |
771 | ||
94c30b78 | 772 | /* Check if this function is already in the cache of frame information. */ |
c906108c SS |
773 | if (check_prologue_cache (fi)) |
774 | return; | |
775 | ||
776 | /* Assume there is no frame until proven otherwise. */ | |
34e8f22d | 777 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
778 | fi->extra_info->framesize = 0; |
779 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
780 | |
781 | /* Check for Thumb prologue. */ | |
782 | if (arm_pc_is_thumb (fi->pc)) | |
783 | { | |
784 | thumb_scan_prologue (fi); | |
785 | save_prologue_cache (fi); | |
786 | return; | |
787 | } | |
788 | ||
789 | /* Find the function prologue. If we can't find the function in | |
790 | the symbol table, peek in the stack frame to find the PC. */ | |
791 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
792 | { | |
2a451106 KB |
793 | /* One way to find the end of the prologue (which works well |
794 | for unoptimized code) is to do the following: | |
795 | ||
796 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
797 | ||
798 | if (sal.line == 0) | |
799 | prologue_end = fi->pc; | |
800 | else if (sal.end < prologue_end) | |
801 | prologue_end = sal.end; | |
802 | ||
803 | This mechanism is very accurate so long as the optimizer | |
804 | doesn't move any instructions from the function body into the | |
805 | prologue. If this happens, sal.end will be the last | |
806 | instruction in the first hunk of prologue code just before | |
807 | the first instruction that the scheduler has moved from | |
808 | the body to the prologue. | |
809 | ||
810 | In order to make sure that we scan all of the prologue | |
811 | instructions, we use a slightly less accurate mechanism which | |
812 | may scan more than necessary. To help compensate for this | |
813 | lack of accuracy, the prologue scanning loop below contains | |
814 | several clauses which'll cause the loop to terminate early if | |
815 | an implausible prologue instruction is encountered. | |
816 | ||
817 | The expression | |
818 | ||
819 | prologue_start + 64 | |
820 | ||
821 | is a suitable endpoint since it accounts for the largest | |
822 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 823 | the scheduler. */ |
2a451106 KB |
824 | |
825 | if (prologue_end > prologue_start + 64) | |
826 | { | |
94c30b78 | 827 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 828 | } |
c906108c SS |
829 | } |
830 | else | |
831 | { | |
94c30b78 MS |
832 | /* Get address of the stmfd in the prologue of the callee; |
833 | the saved PC is the address of the stmfd + 8. */ | |
16a0f3e7 EZ |
834 | if (!safe_read_memory_integer (fi->frame, 4, &return_value)) |
835 | return; | |
836 | else | |
837 | { | |
838 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 839 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 840 | } |
c906108c SS |
841 | } |
842 | ||
843 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 844 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 845 | |
96baa820 JM |
846 | Be careful, however, and if it doesn't look like a prologue, |
847 | don't try to scan it. If, for instance, a frameless function | |
848 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 849 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
850 | and other operations that rely on a knowledge of the stack |
851 | traceback. | |
852 | ||
853 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 854 | if we don't see this as the first insn, we will stop. |
c906108c | 855 | |
f43845b3 MS |
856 | [Note: This doesn't seem to be true any longer, so it's now an |
857 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 858 | |
f43845b3 MS |
859 | [Note further: The "mov ip,sp" only seems to be missing in |
860 | frameless functions at optimization level "-O2" or above, | |
861 | in which case it is often (but not always) replaced by | |
b8d5e71d | 862 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 863 | |
f43845b3 MS |
864 | sp_offset = fp_offset = 0; |
865 | ||
94c30b78 MS |
866 | for (current_pc = prologue_start; |
867 | current_pc < prologue_end; | |
f43845b3 | 868 | current_pc += 4) |
96baa820 | 869 | { |
d4473757 KB |
870 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
871 | ||
94c30b78 | 872 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
873 | { |
874 | continue; | |
875 | } | |
94c30b78 | 876 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
877 | { |
878 | /* Function is frameless: extra_info defaults OK? */ | |
879 | continue; | |
880 | } | |
881 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
882 | /* stmfd sp!, {..., fp, ip, lr, pc} |
883 | or | |
884 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 885 | { |
d4473757 | 886 | int mask = insn & 0xffff; |
ed9a39eb | 887 | |
94c30b78 | 888 | /* Calculate offsets of saved registers. */ |
34e8f22d | 889 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
890 | if (mask & (1 << regno)) |
891 | { | |
892 | sp_offset -= 4; | |
c3b4394c | 893 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
894 | } |
895 | } | |
b8d5e71d MS |
896 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
897 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
898 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
899 | { | |
900 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
901 | continue; | |
902 | } | |
903 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
904 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
905 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
906 | { |
907 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
908 | continue; | |
909 | } | |
d4473757 KB |
910 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
911 | { | |
94c30b78 MS |
912 | unsigned imm = insn & 0xff; /* immediate value */ |
913 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
914 | imm = (imm >> rot) | (imm << (32 - rot)); |
915 | fp_offset = -imm; | |
34e8f22d | 916 | fi->extra_info->framereg = ARM_FP_REGNUM; |
d4473757 KB |
917 | } |
918 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
919 | { | |
94c30b78 MS |
920 | unsigned imm = insn & 0xff; /* immediate value */ |
921 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
922 | imm = (imm >> rot) | (imm << (32 - rot)); |
923 | sp_offset -= imm; | |
924 | } | |
925 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
926 | { | |
927 | sp_offset -= 12; | |
34e8f22d | 928 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
c3b4394c | 929 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
930 | } |
931 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
932 | { | |
933 | int n_saved_fp_regs; | |
934 | unsigned int fp_start_reg, fp_bound_reg; | |
935 | ||
94c30b78 | 936 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 937 | { |
d4473757 KB |
938 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
939 | n_saved_fp_regs = 3; | |
940 | else | |
941 | n_saved_fp_regs = 1; | |
96baa820 | 942 | } |
d4473757 | 943 | else |
96baa820 | 944 | { |
d4473757 KB |
945 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
946 | n_saved_fp_regs = 2; | |
947 | else | |
948 | n_saved_fp_regs = 4; | |
96baa820 | 949 | } |
d4473757 | 950 | |
34e8f22d | 951 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
952 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
953 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
954 | { |
955 | sp_offset -= 12; | |
c3b4394c | 956 | fi->saved_regs[fp_start_reg++] = sp_offset; |
96baa820 | 957 | } |
c906108c | 958 | } |
d4473757 | 959 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 960 | break; /* Condition not true, exit early */ |
b8d5e71d | 961 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 962 | break; /* Don't scan past a block load */ |
d4473757 KB |
963 | else |
964 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 965 | so we just skip what we don't recognize. */ |
d4473757 | 966 | continue; |
c906108c SS |
967 | } |
968 | ||
94c30b78 MS |
969 | /* The frame size is just the negative of the offset (from the |
970 | original SP) of the last thing thing we pushed on the stack. | |
971 | The frame offset is [new FP] - [new SP]. */ | |
c3b4394c | 972 | fi->extra_info->framesize = -sp_offset; |
34e8f22d | 973 | if (fi->extra_info->framereg == ARM_FP_REGNUM) |
c3b4394c | 974 | fi->extra_info->frameoffset = fp_offset - sp_offset; |
d4473757 | 975 | else |
c3b4394c | 976 | fi->extra_info->frameoffset = 0; |
ed9a39eb | 977 | |
c906108c SS |
978 | save_prologue_cache (fi); |
979 | } | |
980 | ||
ed9a39eb JM |
981 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
982 | One thing we might want to do here is to check REGNUM against the | |
983 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
984 | the stack somewhere. This would provide a graceful failure mode | |
985 | when trying to get the value of caller-saves registers for an inner | |
986 | frame. */ | |
c906108c SS |
987 | |
988 | static CORE_ADDR | |
ed9a39eb | 989 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 990 | { |
848cfffb AC |
991 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
992 | needed. Instead the (still being written) register unwind | |
993 | function could be called directly. */ | |
c906108c | 994 | for (; fi; fi = fi->next) |
848cfffb | 995 | { |
ae45cd16 | 996 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
848cfffb | 997 | { |
135c175f | 998 | return deprecated_read_register_dummy (fi->pc, fi->frame, regnum); |
848cfffb AC |
999 | } |
1000 | else if (fi->saved_regs[regnum] != 0) | |
1001 | { | |
1002 | /* NOTE: cagney/2002-05-03: This would normally need to | |
1003 | handle ARM_SP_REGNUM as a special case as, according to | |
1004 | the frame.h comments, saved_regs[SP_REGNUM] contains the | |
1005 | SP value not its address. It appears that the ARM isn't | |
1006 | doing this though. */ | |
1007 | return read_memory_integer (fi->saved_regs[regnum], | |
1008 | REGISTER_RAW_SIZE (regnum)); | |
1009 | } | |
1010 | } | |
c906108c SS |
1011 | return read_register (regnum); |
1012 | } | |
148754e5 RE |
1013 | /* Function: frame_chain Given a GDB frame, determine the address of |
1014 | the calling function's frame. This will be used to create a new | |
a5afb99f AC |
1015 | GDB frame struct, and then INIT_EXTRA_FRAME_INFO and |
1016 | DEPRECATED_INIT_FRAME_PC will be called for the new frame. For | |
1017 | ARM, we save the frame size when we initialize the frame_info. */ | |
c5aa993b | 1018 | |
148754e5 | 1019 | static CORE_ADDR |
ed9a39eb | 1020 | arm_frame_chain (struct frame_info *fi) |
c906108c | 1021 | { |
848cfffb | 1022 | CORE_ADDR caller_pc; |
c3b4394c | 1023 | int framereg = fi->extra_info->framereg; |
c906108c | 1024 | |
ae45cd16 | 1025 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
848cfffb AC |
1026 | /* A generic call dummy's frame is the same as caller's. */ |
1027 | return fi->frame; | |
1028 | ||
c906108c SS |
1029 | if (fi->pc < LOWEST_PC) |
1030 | return 0; | |
1031 | ||
1032 | /* If the caller is the startup code, we're at the end of the chain. */ | |
1033 | caller_pc = FRAME_SAVED_PC (fi); | |
c906108c SS |
1034 | |
1035 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
1036 | the frame register of the caller is different from ours. | |
1037 | So we must scan the prologue of the caller to determine its | |
94c30b78 | 1038 | frame register number. */ |
c3b4394c RE |
1039 | /* XXX Fixme, we should try to do this without creating a temporary |
1040 | caller_fi. */ | |
c906108c SS |
1041 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
1042 | { | |
c3b4394c RE |
1043 | struct frame_info caller_fi; |
1044 | struct cleanup *old_chain; | |
1045 | ||
1046 | /* Create a temporary frame suitable for scanning the caller's | |
1047 | prologue. (Ugh.) */ | |
c5aa993b | 1048 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c3b4394c RE |
1049 | caller_fi.extra_info = (struct frame_extra_info *) |
1050 | xcalloc (1, sizeof (struct frame_extra_info)); | |
1051 | old_chain = make_cleanup (xfree, caller_fi.extra_info); | |
1052 | caller_fi.saved_regs = (CORE_ADDR *) | |
1053 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
1054 | make_cleanup (xfree, caller_fi.saved_regs); | |
1055 | ||
1056 | /* Now, scan the prologue and obtain the frame register. */ | |
c906108c | 1057 | caller_fi.pc = caller_pc; |
c5aa993b | 1058 | arm_scan_prologue (&caller_fi); |
c3b4394c RE |
1059 | framereg = caller_fi.extra_info->framereg; |
1060 | ||
1061 | /* Deallocate the storage associated with the temporary frame | |
1062 | created above. */ | |
1063 | do_cleanups (old_chain); | |
c906108c SS |
1064 | } |
1065 | ||
1066 | /* If the caller used a frame register, return its value. | |
1067 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 1068 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
1069 | return arm_find_callers_reg (fi, framereg); |
1070 | else | |
c3b4394c | 1071 | return fi->frame + fi->extra_info->framesize; |
c906108c SS |
1072 | } |
1073 | ||
ed9a39eb JM |
1074 | /* This function actually figures out the frame address for a given pc |
1075 | and sp. This is tricky because we sometimes don't use an explicit | |
1076 | frame pointer, and the previous stack pointer isn't necessarily | |
1077 | recorded on the stack. The only reliable way to get this info is | |
1078 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1079 | this is the next frame up the chain AFTER a frameless function. If | |
1080 | this is true, then the frame value for this frame is still in the | |
1081 | fp register. */ | |
c906108c | 1082 | |
148754e5 | 1083 | static void |
ed9a39eb | 1084 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1085 | { |
1086 | int reg; | |
f079148d | 1087 | CORE_ADDR sp; |
c906108c | 1088 | |
c3b4394c RE |
1089 | if (fi->saved_regs == NULL) |
1090 | frame_saved_regs_zalloc (fi); | |
1091 | ||
1092 | fi->extra_info = (struct frame_extra_info *) | |
1093 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1094 | ||
1095 | fi->extra_info->framesize = 0; | |
1096 | fi->extra_info->frameoffset = 0; | |
1097 | fi->extra_info->framereg = 0; | |
1098 | ||
c906108c SS |
1099 | if (fi->next) |
1100 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1101 | ||
c3b4394c | 1102 | memset (fi->saved_regs, '\000', sizeof fi->saved_regs); |
c906108c | 1103 | |
da3c6d4a MS |
1104 | /* Compute stack pointer for this frame. We use this value for both |
1105 | the sigtramp and call dummy cases. */ | |
f079148d KB |
1106 | if (!fi->next) |
1107 | sp = read_sp(); | |
ae45cd16 | 1108 | else if (DEPRECATED_PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) |
848cfffb AC |
1109 | /* For generic dummy frames, pull the value direct from the frame. |
1110 | Having an unwind function to do this would be nice. */ | |
135c175f AC |
1111 | sp = deprecated_read_register_dummy (fi->next->pc, fi->next->frame, |
1112 | ARM_SP_REGNUM); | |
f079148d | 1113 | else |
c3b4394c RE |
1114 | sp = (fi->next->frame - fi->next->extra_info->frameoffset |
1115 | + fi->next->extra_info->framesize); | |
f079148d | 1116 | |
d7bd68ca | 1117 | /* Determine whether or not we're in a sigtramp frame. |
5a203e44 AC |
1118 | Unfortunately, it isn't sufficient to test (get_frame_type (fi) |
1119 | == SIGTRAMP_FRAME) because this value is sometimes set after | |
1120 | invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
1121 | (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to | |
1122 | determine if we need to use the sigcontext addresses for the | |
1123 | saved registers. | |
2a451106 | 1124 | |
d7bd68ca AC |
1125 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1126 | against the name of the function, the code below will have to be | |
1127 | changed to first fetch the name of the function and then pass | |
1128 | this name to PC_IN_SIGTRAMP. */ | |
2a451106 | 1129 | |
5a203e44 AC |
1130 | /* FIXME: cagney/2002-11-18: This problem will go away once |
1131 | frame.c:get_prev_frame() is modified to set the frame's type | |
1132 | before calling functions like this. */ | |
1133 | ||
3bb04bdd | 1134 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
5a203e44 | 1135 | && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (fi->pc, (char *)0))) |
2a451106 | 1136 | { |
2a451106 | 1137 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c | 1138 | fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
2a451106 | 1139 | |
94c30b78 | 1140 | /* FIXME: What about thumb mode? */ |
34e8f22d | 1141 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
1142 | fi->frame = |
1143 | read_memory_integer (fi->saved_regs[fi->extra_info->framereg], | |
1144 | REGISTER_RAW_SIZE (fi->extra_info->framereg)); | |
1145 | fi->extra_info->framesize = 0; | |
1146 | fi->extra_info->frameoffset = 0; | |
2a451106 KB |
1147 | |
1148 | } | |
1149 | else | |
c906108c SS |
1150 | { |
1151 | arm_scan_prologue (fi); | |
1152 | ||
104c1213 | 1153 | if (!fi->next) |
94c30b78 | 1154 | /* This is the innermost frame? */ |
c3b4394c | 1155 | fi->frame = read_register (fi->extra_info->framereg); |
ae45cd16 | 1156 | else if (DEPRECATED_PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) |
848cfffb AC |
1157 | /* Next inner most frame is a dummy, just grab its frame. |
1158 | Dummy frames always have the same FP as their caller. */ | |
1159 | fi->frame = fi->next->frame; | |
34e8f22d | 1160 | else if (fi->extra_info->framereg == ARM_FP_REGNUM |
c3b4394c | 1161 | || fi->extra_info->framereg == THUMB_FP_REGNUM) |
ed9a39eb JM |
1162 | { |
1163 | /* not the innermost frame */ | |
94c30b78 | 1164 | /* If we have an FP, the callee saved it. */ |
c3b4394c | 1165 | if (fi->next->saved_regs[fi->extra_info->framereg] != 0) |
ed9a39eb | 1166 | fi->frame = |
c3b4394c RE |
1167 | read_memory_integer (fi->next |
1168 | ->saved_regs[fi->extra_info->framereg], 4); | |
ed9a39eb JM |
1169 | else if (fromleaf) |
1170 | /* If we were called by a frameless fn. then our frame is | |
94c30b78 | 1171 | still in the frame pointer register on the board... */ |
ed9a39eb JM |
1172 | fi->frame = read_fp (); |
1173 | } | |
c906108c | 1174 | |
ed9a39eb JM |
1175 | /* Calculate actual addresses of saved registers using offsets |
1176 | determined by arm_scan_prologue. */ | |
c906108c | 1177 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c RE |
1178 | if (fi->saved_regs[reg] != 0) |
1179 | fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize | |
1180 | - fi->extra_info->frameoffset); | |
c906108c SS |
1181 | } |
1182 | } | |
1183 | ||
1184 | ||
34e8f22d | 1185 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1186 | is saved in the stack anywhere, otherwise we get it from the |
1187 | registers. | |
c906108c SS |
1188 | |
1189 | The old definition of this function was a macro: | |
c5aa993b | 1190 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1191 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1192 | |
148754e5 | 1193 | static CORE_ADDR |
ed9a39eb | 1194 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1195 | { |
848cfffb | 1196 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
ae45cd16 | 1197 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, 0, 0)) |
135c175f | 1198 | return deprecated_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM); |
848cfffb | 1199 | |
ae45cd16 | 1200 | if (DEPRECATED_PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset, |
c3b4394c | 1201 | fi->frame)) |
f079148d | 1202 | { |
34e8f22d RE |
1203 | return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM], |
1204 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); | |
f079148d KB |
1205 | } |
1206 | else | |
c906108c | 1207 | { |
34e8f22d | 1208 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1209 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1210 | } | |
1211 | } | |
1212 | ||
c906108c SS |
1213 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1214 | Examine the Program Status Register to decide which state we're in. */ | |
1215 | ||
148754e5 RE |
1216 | static CORE_ADDR |
1217 | arm_read_fp (void) | |
c906108c | 1218 | { |
34e8f22d | 1219 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1220 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1221 | else | |
34e8f22d | 1222 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1223 | } |
1224 | ||
148754e5 RE |
1225 | /* Store into a struct frame_saved_regs the addresses of the saved |
1226 | registers of frame described by FRAME_INFO. This includes special | |
1227 | registers such as PC and FP saved in special ways in the stack | |
1228 | frame. SP is even more special: the address we return for it IS | |
1229 | the sp for the next frame. */ | |
c906108c | 1230 | |
148754e5 | 1231 | static void |
c3b4394c | 1232 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1233 | { |
c3b4394c RE |
1234 | |
1235 | if (fip->saved_regs) | |
1236 | return; | |
1237 | ||
1238 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1239 | } |
1240 | ||
848cfffb AC |
1241 | /* Set the return address for a generic dummy frame. ARM uses the |
1242 | entry point. */ | |
1243 | ||
1244 | static CORE_ADDR | |
1245 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1246 | { | |
1247 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1248 | return sp; | |
1249 | } | |
1250 | ||
148754e5 RE |
1251 | /* Push an empty stack frame, to record the current PC, etc. */ |
1252 | ||
1253 | static void | |
ed9a39eb | 1254 | arm_push_dummy_frame (void) |
c906108c | 1255 | { |
34e8f22d | 1256 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1257 | CORE_ADDR sp = old_sp; |
1258 | CORE_ADDR fp, prologue_start; | |
1259 | int regnum; | |
1260 | ||
1261 | /* Push the two dummy prologue instructions in reverse order, | |
1262 | so that they'll be in the correct low-to-high order in memory. */ | |
1263 | /* sub fp, ip, #4 */ | |
1264 | sp = push_word (sp, 0xe24cb004); | |
1265 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1266 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1267 | ||
ed9a39eb JM |
1268 | /* Push a pointer to the dummy prologue + 12, because when stm |
1269 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1270 | instruction itself plus 12. */ |
1271 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1272 | |
f079148d | 1273 | /* Push the processor status. */ |
34e8f22d | 1274 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1275 | |
1276 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1277 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1278 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1279 | |
f079148d | 1280 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1281 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1282 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1283 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1284 | } |
1285 | ||
6eb69eab RE |
1286 | /* CALL_DUMMY_WORDS: |
1287 | This sequence of words is the instructions | |
1288 | ||
1289 | mov lr,pc | |
1290 | mov pc,r4 | |
1291 | illegal | |
1292 | ||
1293 | Note this is 12 bytes. */ | |
1294 | ||
34e8f22d | 1295 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1296 | { |
1297 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1298 | }; | |
1299 | ||
3fb4b924 RE |
1300 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1301 | breakpoint to the proper address in the call dummy, so that | |
1302 | `finish' after a stop in a call dummy works. | |
1303 | ||
d7b486e7 RE |
1304 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1305 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
1306 | followed by a call to run_stack_dummy, which is the only function | |
1307 | where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1308 | |
1309 | ||
1310 | static void | |
1311 | arm_set_call_dummy_breakpoint_offset (void) | |
1312 | { | |
1313 | if (caller_is_thumb) | |
1314 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); | |
1315 | else | |
1316 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); | |
1317 | } | |
1318 | ||
c906108c | 1319 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1320 | in Thumb or ARM mode, and whether the target function is Thumb or |
1321 | ARM. There are three different situations requiring three | |
c906108c SS |
1322 | different dummies: |
1323 | ||
1324 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1325 | been copied into the dummy parameter to this function. |
c906108c | 1326 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1327 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1328 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1329 | works for calling both ARM and Thumb functions. |
c906108c | 1330 | |
ed9a39eb JM |
1331 | All three call dummies expect to receive the target function |
1332 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1333 | |
34e8f22d | 1334 | static void |
ed9a39eb | 1335 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1336 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1337 | { |
1338 | static short thumb_dummy[4] = | |
1339 | { | |
c5aa993b JM |
1340 | 0xf000, 0xf801, /* bl label */ |
1341 | 0xdf18, /* swi 24 */ | |
1342 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1343 | }; |
1344 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1345 | ||
94c30b78 | 1346 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1347 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1348 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1349 | |
ed9a39eb JM |
1350 | /* If the target function is Thumb, set the low bit of the function |
1351 | address. And if the CPU is currently in ARM mode, patch the | |
1352 | second instruction of call dummy to use a BX instruction to | |
1353 | switch to Thumb mode. */ | |
c906108c SS |
1354 | target_is_thumb = arm_pc_is_thumb (fun); |
1355 | if (target_is_thumb) | |
1356 | { | |
1357 | fun |= 1; | |
1358 | if (!caller_is_thumb) | |
1359 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1360 | } | |
1361 | ||
1362 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1363 | instead of the ARM one that's already been copied. This will | |
1364 | work for both Thumb and ARM target functions. */ | |
1365 | if (caller_is_thumb) | |
1366 | { | |
1367 | int i; | |
1368 | char *p = dummy; | |
1369 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1370 | ||
1371 | for (i = 0; i < len; i++) | |
1372 | { | |
1373 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1374 | p += sizeof (thumb_dummy[0]); | |
1375 | } | |
1376 | } | |
1377 | ||
ed9a39eb | 1378 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1379 | the PC. */ |
c906108c SS |
1380 | write_register (4, fun); |
1381 | } | |
1382 | ||
ed9a39eb JM |
1383 | /* Note: ScottB |
1384 | ||
1385 | This function does not support passing parameters using the FPA | |
1386 | variant of the APCS. It passes any floating point arguments in the | |
1387 | general registers and/or on the stack. */ | |
c906108c | 1388 | |
39bbf761 | 1389 | static CORE_ADDR |
ea7c478f | 1390 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1391 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1392 | { |
6529d2dd AC |
1393 | CORE_ADDR fp; |
1394 | int argnum; | |
1395 | int argreg; | |
1396 | int nstack; | |
1397 | int simd_argreg; | |
1398 | int second_pass; | |
1399 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
ed9a39eb JM |
1400 | |
1401 | /* Walk through the list of args and determine how large a temporary | |
1402 | stack is required. Need to take care here as structs may be | |
6529d2dd AC |
1403 | passed on the stack, and we have to to push them. On the second |
1404 | pass, do the store. */ | |
1405 | nstack = 0; | |
1406 | fp = sp; | |
1407 | for (second_pass = 0; second_pass < 2; second_pass++) | |
c906108c | 1408 | { |
6529d2dd AC |
1409 | /* Compute the FP using the information computed during the |
1410 | first pass. */ | |
1411 | if (second_pass) | |
1412 | fp = sp - nstack; | |
1413 | ||
1414 | simd_argreg = 0; | |
1415 | argreg = ARM_A1_REGNUM; | |
1416 | nstack = 0; | |
1417 | ||
1418 | /* The struct_return pointer occupies the first parameter | |
1419 | passing register. */ | |
1420 | if (struct_return) | |
c906108c | 1421 | { |
6529d2dd AC |
1422 | if (second_pass) |
1423 | { | |
1424 | if (arm_debug) | |
1425 | fprintf_unfiltered (gdb_stdlog, | |
1426 | "struct return in %s = 0x%s\n", | |
1427 | REGISTER_NAME (argreg), | |
1428 | paddr (struct_addr)); | |
1429 | write_register (argreg, struct_addr); | |
1430 | } | |
1431 | argreg++; | |
c906108c | 1432 | } |
ed9a39eb | 1433 | |
6529d2dd AC |
1434 | for (argnum = 0; argnum < nargs; argnum++) |
1435 | { | |
1436 | int len; | |
1437 | struct type *arg_type; | |
1438 | struct type *target_type; | |
1439 | enum type_code typecode; | |
1440 | char *val; | |
1441 | ||
1442 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1443 | len = TYPE_LENGTH (arg_type); | |
1444 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1445 | typecode = TYPE_CODE (arg_type); | |
1446 | val = VALUE_CONTENTS (args[argnum]); | |
1447 | ||
1448 | /* If the argument is a pointer to a function, and it is a | |
1449 | Thumb function, create a LOCAL copy of the value and set | |
1450 | the THUMB bit in it. */ | |
1451 | if (second_pass | |
1452 | && TYPE_CODE_PTR == typecode | |
1453 | && target_type != NULL | |
1454 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1455 | { |
6529d2dd AC |
1456 | CORE_ADDR regval = extract_address (val, len); |
1457 | if (arm_pc_is_thumb (regval)) | |
1458 | { | |
1459 | val = alloca (len); | |
1460 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1461 | } | |
c906108c | 1462 | } |
6529d2dd AC |
1463 | |
1464 | /* Copy the argument to general registers or the stack in | |
1465 | register-sized pieces. Large arguments are split between | |
1466 | registers and stack. */ | |
1467 | while (len > 0) | |
ed9a39eb | 1468 | { |
6529d2dd AC |
1469 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1470 | ||
1471 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1472 | { | |
1473 | /* The argument is being passed in a general purpose | |
1474 | register. */ | |
1475 | if (second_pass) | |
1476 | { | |
1477 | CORE_ADDR regval = extract_address (val, | |
1478 | partial_len); | |
1479 | if (arm_debug) | |
1480 | fprintf_unfiltered (gdb_stdlog, | |
1481 | "arg %d in %s = 0x%s\n", | |
1482 | argnum, | |
1483 | REGISTER_NAME (argreg), | |
1484 | phex (regval, REGISTER_SIZE)); | |
1485 | write_register (argreg, regval); | |
1486 | } | |
1487 | argreg++; | |
1488 | } | |
1489 | else | |
1490 | { | |
1491 | if (second_pass) | |
1492 | { | |
1493 | /* Push the arguments onto the stack. */ | |
1494 | if (arm_debug) | |
1495 | fprintf_unfiltered (gdb_stdlog, | |
1496 | "arg %d @ 0x%s + %d\n", | |
1497 | argnum, paddr (fp), nstack); | |
1498 | write_memory (fp + nstack, val, REGISTER_SIZE); | |
1499 | } | |
1500 | nstack += REGISTER_SIZE; | |
1501 | } | |
1502 | ||
1503 | len -= partial_len; | |
1504 | val += partial_len; | |
ed9a39eb JM |
1505 | } |
1506 | ||
c906108c SS |
1507 | } |
1508 | } | |
c906108c | 1509 | |
6529d2dd AC |
1510 | /* Return the botom of the argument list (pointed to by fp). */ |
1511 | return fp; | |
c906108c SS |
1512 | } |
1513 | ||
da3c6d4a MS |
1514 | /* Pop the current frame. So long as the frame info has been |
1515 | initialized properly (see arm_init_extra_frame_info), this code | |
1516 | works for dummy frames as well as regular frames. I.e, there's no | |
1517 | need to have a special case for dummy frames. */ | |
148754e5 | 1518 | static void |
ed9a39eb | 1519 | arm_pop_frame (void) |
c906108c | 1520 | { |
c906108c | 1521 | int regnum; |
8b93c638 | 1522 | struct frame_info *frame = get_current_frame (); |
c3b4394c RE |
1523 | CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset |
1524 | + frame->extra_info->framesize); | |
c906108c | 1525 | |
ae45cd16 | 1526 | if (DEPRECATED_PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) |
848cfffb AC |
1527 | { |
1528 | generic_pop_dummy_frame (); | |
1529 | flush_cached_frames (); | |
1530 | return; | |
1531 | } | |
1532 | ||
f079148d | 1533 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c3b4394c | 1534 | if (frame->saved_regs[regnum] != 0) |
f079148d | 1535 | write_register (regnum, |
c3b4394c | 1536 | read_memory_integer (frame->saved_regs[regnum], |
f079148d | 1537 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1538 | |
34e8f22d RE |
1539 | write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame)); |
1540 | write_register (ARM_SP_REGNUM, old_SP); | |
c906108c SS |
1541 | |
1542 | flush_cached_frames (); | |
1543 | } | |
1544 | ||
1545 | static void | |
ed9a39eb | 1546 | print_fpu_flags (int flags) |
c906108c | 1547 | { |
c5aa993b JM |
1548 | if (flags & (1 << 0)) |
1549 | fputs ("IVO ", stdout); | |
1550 | if (flags & (1 << 1)) | |
1551 | fputs ("DVZ ", stdout); | |
1552 | if (flags & (1 << 2)) | |
1553 | fputs ("OFL ", stdout); | |
1554 | if (flags & (1 << 3)) | |
1555 | fputs ("UFL ", stdout); | |
1556 | if (flags & (1 << 4)) | |
1557 | fputs ("INX ", stdout); | |
1558 | putchar ('\n'); | |
c906108c SS |
1559 | } |
1560 | ||
5e74b15c RE |
1561 | /* Print interesting information about the floating point processor |
1562 | (if present) or emulator. */ | |
34e8f22d | 1563 | static void |
d855c300 | 1564 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1565 | struct frame_info *frame, const char *args) |
c906108c | 1566 | { |
34e8f22d | 1567 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1568 | int type; |
1569 | ||
1570 | type = (status >> 24) & 127; | |
1571 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1572 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1573 | type); |
1574 | fputs ("mask: ", stdout); | |
1575 | print_fpu_flags (status >> 16); | |
1576 | fputs ("flags: ", stdout); | |
1577 | print_fpu_flags (status); | |
c906108c SS |
1578 | } |
1579 | ||
34e8f22d RE |
1580 | /* Return the GDB type object for the "standard" data type of data in |
1581 | register N. */ | |
1582 | ||
1583 | static struct type * | |
032758dc AC |
1584 | arm_register_type (int regnum) |
1585 | { | |
34e8f22d | 1586 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1587 | { |
d7449b42 | 1588 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1589 | return builtin_type_arm_ext_big; |
1590 | else | |
1591 | return builtin_type_arm_ext_littlebyte_bigword; | |
1592 | } | |
1593 | else | |
1594 | return builtin_type_int32; | |
1595 | } | |
1596 | ||
34e8f22d RE |
1597 | /* Index within `registers' of the first byte of the space for |
1598 | register N. */ | |
1599 | ||
1600 | static int | |
1601 | arm_register_byte (int regnum) | |
1602 | { | |
1603 | if (regnum < ARM_F0_REGNUM) | |
1604 | return regnum * INT_REGISTER_RAW_SIZE; | |
1605 | else if (regnum < ARM_PS_REGNUM) | |
1606 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1607 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1608 | else | |
1609 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1610 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1611 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1612 | } | |
1613 | ||
1614 | /* Number of bytes of storage in the actual machine representation for | |
1615 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1616 | 12 bytes in length. */ | |
1617 | ||
1618 | static int | |
1619 | arm_register_raw_size (int regnum) | |
1620 | { | |
1621 | if (regnum < ARM_F0_REGNUM) | |
1622 | return INT_REGISTER_RAW_SIZE; | |
1623 | else if (regnum < ARM_FPS_REGNUM) | |
1624 | return FP_REGISTER_RAW_SIZE; | |
1625 | else | |
1626 | return STATUS_REGISTER_SIZE; | |
1627 | } | |
1628 | ||
1629 | /* Number of bytes of storage in a program's representation | |
1630 | for register N. */ | |
1631 | static int | |
1632 | arm_register_virtual_size (int regnum) | |
1633 | { | |
1634 | if (regnum < ARM_F0_REGNUM) | |
1635 | return INT_REGISTER_VIRTUAL_SIZE; | |
1636 | else if (regnum < ARM_FPS_REGNUM) | |
1637 | return FP_REGISTER_VIRTUAL_SIZE; | |
1638 | else | |
1639 | return STATUS_REGISTER_SIZE; | |
1640 | } | |
1641 | ||
26216b98 AC |
1642 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1643 | static int | |
1644 | arm_register_sim_regno (int regnum) | |
1645 | { | |
1646 | int reg = regnum; | |
1647 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1648 | ||
1649 | if (reg < NUM_GREGS) | |
1650 | return SIM_ARM_R0_REGNUM + reg; | |
1651 | reg -= NUM_GREGS; | |
1652 | ||
1653 | if (reg < NUM_FREGS) | |
1654 | return SIM_ARM_FP0_REGNUM + reg; | |
1655 | reg -= NUM_FREGS; | |
1656 | ||
1657 | if (reg < NUM_SREGS) | |
1658 | return SIM_ARM_FPS_REGNUM + reg; | |
1659 | reg -= NUM_SREGS; | |
1660 | ||
1661 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1662 | } | |
34e8f22d | 1663 | |
a37b3cc0 AC |
1664 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1665 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1666 | It is thought that this is is the floating-point register format on | |
1667 | little-endian systems. */ | |
c906108c | 1668 | |
ed9a39eb | 1669 | static void |
b508a996 RE |
1670 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1671 | void *dbl) | |
c906108c | 1672 | { |
a37b3cc0 | 1673 | DOUBLEST d; |
d7449b42 | 1674 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1675 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1676 | else | |
1677 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1678 | ptr, &d); | |
b508a996 | 1679 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1680 | } |
1681 | ||
34e8f22d | 1682 | static void |
b508a996 | 1683 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1684 | { |
a37b3cc0 | 1685 | DOUBLEST d; |
b508a996 | 1686 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1687 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1688 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1689 | else | |
1690 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1691 | &d, dbl); | |
c906108c | 1692 | } |
ed9a39eb | 1693 | |
c906108c | 1694 | static int |
ed9a39eb | 1695 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1696 | { |
1697 | if (cond == INST_AL || cond == INST_NV) | |
1698 | return 1; | |
1699 | ||
1700 | switch (cond) | |
1701 | { | |
1702 | case INST_EQ: | |
1703 | return ((status_reg & FLAG_Z) != 0); | |
1704 | case INST_NE: | |
1705 | return ((status_reg & FLAG_Z) == 0); | |
1706 | case INST_CS: | |
1707 | return ((status_reg & FLAG_C) != 0); | |
1708 | case INST_CC: | |
1709 | return ((status_reg & FLAG_C) == 0); | |
1710 | case INST_MI: | |
1711 | return ((status_reg & FLAG_N) != 0); | |
1712 | case INST_PL: | |
1713 | return ((status_reg & FLAG_N) == 0); | |
1714 | case INST_VS: | |
1715 | return ((status_reg & FLAG_V) != 0); | |
1716 | case INST_VC: | |
1717 | return ((status_reg & FLAG_V) == 0); | |
1718 | case INST_HI: | |
1719 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1720 | case INST_LS: | |
1721 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1722 | case INST_GE: | |
1723 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1724 | case INST_LT: | |
1725 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1726 | case INST_GT: | |
1727 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1728 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1729 | case INST_LE: |
1730 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1731 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1732 | } |
1733 | return 1; | |
1734 | } | |
1735 | ||
9512d7fd | 1736 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1737 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1738 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1739 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1740 | #define sbits(obj,st,fn) \ | |
1741 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1742 | #define BranchDest(addr,instr) \ | |
1743 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1744 | #define ARM_PC_32 1 | |
1745 | ||
1746 | static unsigned long | |
ed9a39eb JM |
1747 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1748 | unsigned long status_reg) | |
c906108c SS |
1749 | { |
1750 | unsigned long res, shift; | |
1751 | int rm = bits (inst, 0, 3); | |
1752 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1753 | |
1754 | if (bit (inst, 4)) | |
c906108c SS |
1755 | { |
1756 | int rs = bits (inst, 8, 11); | |
1757 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1758 | } | |
1759 | else | |
1760 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1761 | |
1762 | res = (rm == 15 | |
c906108c | 1763 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1764 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1765 | : read_register (rm)); |
1766 | ||
1767 | switch (shifttype) | |
1768 | { | |
c5aa993b | 1769 | case 0: /* LSL */ |
c906108c SS |
1770 | res = shift >= 32 ? 0 : res << shift; |
1771 | break; | |
c5aa993b JM |
1772 | |
1773 | case 1: /* LSR */ | |
c906108c SS |
1774 | res = shift >= 32 ? 0 : res >> shift; |
1775 | break; | |
1776 | ||
c5aa993b JM |
1777 | case 2: /* ASR */ |
1778 | if (shift >= 32) | |
1779 | shift = 31; | |
c906108c SS |
1780 | res = ((res & 0x80000000L) |
1781 | ? ~((~res) >> shift) : res >> shift); | |
1782 | break; | |
1783 | ||
c5aa993b | 1784 | case 3: /* ROR/RRX */ |
c906108c SS |
1785 | shift &= 31; |
1786 | if (shift == 0) | |
1787 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1788 | else | |
c5aa993b | 1789 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1790 | break; |
1791 | } | |
1792 | ||
1793 | return res & 0xffffffff; | |
1794 | } | |
1795 | ||
c906108c SS |
1796 | /* Return number of 1-bits in VAL. */ |
1797 | ||
1798 | static int | |
ed9a39eb | 1799 | bitcount (unsigned long val) |
c906108c SS |
1800 | { |
1801 | int nbits; | |
1802 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1803 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1804 | return nbits; |
1805 | } | |
1806 | ||
34e8f22d | 1807 | CORE_ADDR |
ed9a39eb | 1808 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1809 | { |
c5aa993b | 1810 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1811 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1812 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1813 | unsigned long offset; |
1814 | ||
1815 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1816 | { | |
1817 | CORE_ADDR sp; | |
1818 | ||
1819 | /* Fetch the saved PC from the stack. It's stored above | |
1820 | all of the other registers. */ | |
1821 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
34e8f22d | 1822 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1823 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1824 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1825 | if (nextpc == pc) | |
1826 | error ("Infinite loop detected"); | |
1827 | } | |
1828 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1829 | { | |
34e8f22d | 1830 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1831 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1832 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1833 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1834 | } | |
1835 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1836 | { | |
1837 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1838 | } | |
1839 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1840 | { | |
1841 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1842 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1843 | nextpc = pc_val + offset; |
1844 | } | |
1845 | ||
1846 | return nextpc; | |
1847 | } | |
1848 | ||
34e8f22d | 1849 | CORE_ADDR |
ed9a39eb | 1850 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1851 | { |
1852 | unsigned long pc_val; | |
1853 | unsigned long this_instr; | |
1854 | unsigned long status; | |
1855 | CORE_ADDR nextpc; | |
1856 | ||
1857 | if (arm_pc_is_thumb (pc)) | |
1858 | return thumb_get_next_pc (pc); | |
1859 | ||
1860 | pc_val = (unsigned long) pc; | |
1861 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1862 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1863 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1864 | |
1865 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1866 | { | |
1867 | switch (bits (this_instr, 24, 27)) | |
1868 | { | |
c5aa993b | 1869 | case 0x0: |
94c30b78 | 1870 | case 0x1: /* data processing */ |
c5aa993b JM |
1871 | case 0x2: |
1872 | case 0x3: | |
c906108c SS |
1873 | { |
1874 | unsigned long operand1, operand2, result = 0; | |
1875 | unsigned long rn; | |
1876 | int c; | |
c5aa993b | 1877 | |
c906108c SS |
1878 | if (bits (this_instr, 12, 15) != 15) |
1879 | break; | |
1880 | ||
1881 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1882 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1883 | error ("Illegal update to pc in instruction"); |
1884 | ||
1885 | /* Multiply into PC */ | |
1886 | c = (status & FLAG_C) ? 1 : 0; | |
1887 | rn = bits (this_instr, 16, 19); | |
1888 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1889 | |
c906108c SS |
1890 | if (bit (this_instr, 25)) |
1891 | { | |
1892 | unsigned long immval = bits (this_instr, 0, 7); | |
1893 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1894 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1895 | & 0xffffffff; | |
c906108c | 1896 | } |
c5aa993b | 1897 | else /* operand 2 is a shifted register */ |
c906108c | 1898 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1899 | |
c906108c SS |
1900 | switch (bits (this_instr, 21, 24)) |
1901 | { | |
c5aa993b | 1902 | case 0x0: /*and */ |
c906108c SS |
1903 | result = operand1 & operand2; |
1904 | break; | |
1905 | ||
c5aa993b | 1906 | case 0x1: /*eor */ |
c906108c SS |
1907 | result = operand1 ^ operand2; |
1908 | break; | |
1909 | ||
c5aa993b | 1910 | case 0x2: /*sub */ |
c906108c SS |
1911 | result = operand1 - operand2; |
1912 | break; | |
1913 | ||
c5aa993b | 1914 | case 0x3: /*rsb */ |
c906108c SS |
1915 | result = operand2 - operand1; |
1916 | break; | |
1917 | ||
c5aa993b | 1918 | case 0x4: /*add */ |
c906108c SS |
1919 | result = operand1 + operand2; |
1920 | break; | |
1921 | ||
c5aa993b | 1922 | case 0x5: /*adc */ |
c906108c SS |
1923 | result = operand1 + operand2 + c; |
1924 | break; | |
1925 | ||
c5aa993b | 1926 | case 0x6: /*sbc */ |
c906108c SS |
1927 | result = operand1 - operand2 + c; |
1928 | break; | |
1929 | ||
c5aa993b | 1930 | case 0x7: /*rsc */ |
c906108c SS |
1931 | result = operand2 - operand1 + c; |
1932 | break; | |
1933 | ||
c5aa993b JM |
1934 | case 0x8: |
1935 | case 0x9: | |
1936 | case 0xa: | |
1937 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1938 | result = (unsigned long) nextpc; |
1939 | break; | |
1940 | ||
c5aa993b | 1941 | case 0xc: /*orr */ |
c906108c SS |
1942 | result = operand1 | operand2; |
1943 | break; | |
1944 | ||
c5aa993b | 1945 | case 0xd: /*mov */ |
c906108c SS |
1946 | /* Always step into a function. */ |
1947 | result = operand2; | |
c5aa993b | 1948 | break; |
c906108c | 1949 | |
c5aa993b | 1950 | case 0xe: /*bic */ |
c906108c SS |
1951 | result = operand1 & ~operand2; |
1952 | break; | |
1953 | ||
c5aa993b | 1954 | case 0xf: /*mvn */ |
c906108c SS |
1955 | result = ~operand2; |
1956 | break; | |
1957 | } | |
1958 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1959 | ||
1960 | if (nextpc == pc) | |
1961 | error ("Infinite loop detected"); | |
1962 | break; | |
1963 | } | |
c5aa993b JM |
1964 | |
1965 | case 0x4: | |
1966 | case 0x5: /* data transfer */ | |
1967 | case 0x6: | |
1968 | case 0x7: | |
c906108c SS |
1969 | if (bit (this_instr, 20)) |
1970 | { | |
1971 | /* load */ | |
1972 | if (bits (this_instr, 12, 15) == 15) | |
1973 | { | |
1974 | /* rd == pc */ | |
c5aa993b | 1975 | unsigned long rn; |
c906108c | 1976 | unsigned long base; |
c5aa993b | 1977 | |
c906108c SS |
1978 | if (bit (this_instr, 22)) |
1979 | error ("Illegal update to pc in instruction"); | |
1980 | ||
1981 | /* byte write to PC */ | |
1982 | rn = bits (this_instr, 16, 19); | |
1983 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1984 | if (bit (this_instr, 24)) | |
1985 | { | |
1986 | /* pre-indexed */ | |
1987 | int c = (status & FLAG_C) ? 1 : 0; | |
1988 | unsigned long offset = | |
c5aa993b | 1989 | (bit (this_instr, 25) |
ed9a39eb | 1990 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1991 | : bits (this_instr, 0, 11)); |
c906108c SS |
1992 | |
1993 | if (bit (this_instr, 23)) | |
1994 | base += offset; | |
1995 | else | |
1996 | base -= offset; | |
1997 | } | |
c5aa993b | 1998 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1999 | 4); |
c5aa993b | 2000 | |
c906108c SS |
2001 | nextpc = ADDR_BITS_REMOVE (nextpc); |
2002 | ||
2003 | if (nextpc == pc) | |
2004 | error ("Infinite loop detected"); | |
2005 | } | |
2006 | } | |
2007 | break; | |
c5aa993b JM |
2008 | |
2009 | case 0x8: | |
2010 | case 0x9: /* block transfer */ | |
c906108c SS |
2011 | if (bit (this_instr, 20)) |
2012 | { | |
2013 | /* LDM */ | |
2014 | if (bit (this_instr, 15)) | |
2015 | { | |
2016 | /* loading pc */ | |
2017 | int offset = 0; | |
2018 | ||
2019 | if (bit (this_instr, 23)) | |
2020 | { | |
2021 | /* up */ | |
2022 | unsigned long reglist = bits (this_instr, 0, 14); | |
2023 | offset = bitcount (reglist) * 4; | |
c5aa993b | 2024 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
2025 | offset += 4; |
2026 | } | |
2027 | else if (bit (this_instr, 24)) | |
2028 | offset = -4; | |
c5aa993b | 2029 | |
c906108c | 2030 | { |
c5aa993b JM |
2031 | unsigned long rn_val = |
2032 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
2033 | nextpc = |
2034 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2035 | + offset), |
c906108c SS |
2036 | 4); |
2037 | } | |
2038 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2039 | if (nextpc == pc) | |
2040 | error ("Infinite loop detected"); | |
2041 | } | |
2042 | } | |
2043 | break; | |
c5aa993b JM |
2044 | |
2045 | case 0xb: /* branch & link */ | |
2046 | case 0xa: /* branch */ | |
c906108c SS |
2047 | { |
2048 | nextpc = BranchDest (pc, this_instr); | |
2049 | ||
2050 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2051 | if (nextpc == pc) | |
2052 | error ("Infinite loop detected"); | |
2053 | break; | |
2054 | } | |
c5aa993b JM |
2055 | |
2056 | case 0xc: | |
2057 | case 0xd: | |
2058 | case 0xe: /* coproc ops */ | |
2059 | case 0xf: /* SWI */ | |
c906108c SS |
2060 | break; |
2061 | ||
2062 | default: | |
97e03143 | 2063 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
2064 | return (pc); |
2065 | } | |
2066 | } | |
2067 | ||
2068 | return nextpc; | |
2069 | } | |
2070 | ||
9512d7fd FN |
2071 | /* single_step() is called just before we want to resume the inferior, |
2072 | if we want to single-step it but there is no hardware or kernel | |
2073 | single-step support. We find the target of the coming instruction | |
2074 | and breakpoint it. | |
2075 | ||
94c30b78 MS |
2076 | single_step() is also called just after the inferior stops. If we |
2077 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2078 | |
34e8f22d RE |
2079 | static void |
2080 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2081 | { |
b8d5e71d | 2082 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2083 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2084 | ||
2085 | if (insert_bpt) | |
2086 | { | |
34e8f22d | 2087 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2088 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2089 | } |
2090 | else | |
80fcf3f0 | 2091 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2092 | } |
9512d7fd | 2093 | |
c906108c SS |
2094 | #include "bfd-in2.h" |
2095 | #include "libcoff.h" | |
2096 | ||
2097 | static int | |
ed9a39eb | 2098 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2099 | { |
2100 | if (arm_pc_is_thumb (memaddr)) | |
2101 | { | |
c5aa993b JM |
2102 | static asymbol *asym; |
2103 | static combined_entry_type ce; | |
2104 | static struct coff_symbol_struct csym; | |
2105 | static struct _bfd fake_bfd; | |
2106 | static bfd_target fake_target; | |
c906108c SS |
2107 | |
2108 | if (csym.native == NULL) | |
2109 | { | |
da3c6d4a MS |
2110 | /* Create a fake symbol vector containing a Thumb symbol. |
2111 | This is solely so that the code in print_insn_little_arm() | |
2112 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2113 | the presence of a Thumb symbol and switch to decoding | |
2114 | Thumb instructions. */ | |
c5aa993b JM |
2115 | |
2116 | fake_target.flavour = bfd_target_coff_flavour; | |
2117 | fake_bfd.xvec = &fake_target; | |
c906108c | 2118 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2119 | csym.native = &ce; |
2120 | csym.symbol.the_bfd = &fake_bfd; | |
2121 | csym.symbol.name = "fake"; | |
2122 | asym = (asymbol *) & csym; | |
c906108c | 2123 | } |
c5aa993b | 2124 | |
c906108c | 2125 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2126 | info->symbols = &asym; |
c906108c SS |
2127 | } |
2128 | else | |
2129 | info->symbols = NULL; | |
c5aa993b | 2130 | |
d7449b42 | 2131 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2132 | return print_insn_big_arm (memaddr, info); |
2133 | else | |
2134 | return print_insn_little_arm (memaddr, info); | |
2135 | } | |
2136 | ||
66e810cd RE |
2137 | /* The following define instruction sequences that will cause ARM |
2138 | cpu's to take an undefined instruction trap. These are used to | |
2139 | signal a breakpoint to GDB. | |
2140 | ||
2141 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2142 | modes. A different instruction is required for each mode. The ARM | |
2143 | cpu's can also be big or little endian. Thus four different | |
2144 | instructions are needed to support all cases. | |
2145 | ||
2146 | Note: ARMv4 defines several new instructions that will take the | |
2147 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2148 | not in fact add the new instructions. The new undefined | |
2149 | instructions in ARMv4 are all instructions that had no defined | |
2150 | behaviour in earlier chips. There is no guarantee that they will | |
2151 | raise an exception, but may be treated as NOP's. In practice, it | |
2152 | may only safe to rely on instructions matching: | |
2153 | ||
2154 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2155 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2156 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2157 | ||
2158 | Even this may only true if the condition predicate is true. The | |
2159 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2160 | ||
2161 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2162 | and NetBSD all use a software interrupt rather than an undefined | |
2163 | instruction to force a trap. This can be handled by by the | |
2164 | abi-specific code during establishment of the gdbarch vector. */ | |
2165 | ||
2166 | ||
d7b486e7 RE |
2167 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2168 | override these definitions. */ | |
66e810cd RE |
2169 | #ifndef ARM_LE_BREAKPOINT |
2170 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2171 | #endif | |
2172 | #ifndef ARM_BE_BREAKPOINT | |
2173 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2174 | #endif | |
2175 | #ifndef THUMB_LE_BREAKPOINT | |
2176 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2177 | #endif | |
2178 | #ifndef THUMB_BE_BREAKPOINT | |
2179 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2180 | #endif | |
2181 | ||
2182 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2183 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2184 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2185 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2186 | ||
34e8f22d RE |
2187 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2188 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2189 | breakpoint should be used. It returns a pointer to a string of |
2190 | bytes that encode a breakpoint instruction, stores the length of | |
2191 | the string to *lenptr, and adjusts the program counter (if | |
2192 | necessary) to point to the actual memory location where the | |
c906108c SS |
2193 | breakpoint should be inserted. */ |
2194 | ||
34e8f22d RE |
2195 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2196 | breakpoints and storing their handles instread of what was in | |
2197 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2198 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2199 | |
ab89facf | 2200 | static const unsigned char * |
ed9a39eb | 2201 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2202 | { |
66e810cd RE |
2203 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2204 | ||
c906108c SS |
2205 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2206 | { | |
66e810cd RE |
2207 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2208 | *lenptr = tdep->thumb_breakpoint_size; | |
2209 | return tdep->thumb_breakpoint; | |
c906108c SS |
2210 | } |
2211 | else | |
2212 | { | |
66e810cd RE |
2213 | *lenptr = tdep->arm_breakpoint_size; |
2214 | return tdep->arm_breakpoint; | |
c906108c SS |
2215 | } |
2216 | } | |
ed9a39eb JM |
2217 | |
2218 | /* Extract from an array REGBUF containing the (raw) register state a | |
2219 | function return value of type TYPE, and copy that, in virtual | |
2220 | format, into VALBUF. */ | |
2221 | ||
34e8f22d | 2222 | static void |
ed9a39eb | 2223 | arm_extract_return_value (struct type *type, |
b508a996 RE |
2224 | struct regcache *regs, |
2225 | void *dst) | |
ed9a39eb | 2226 | { |
b508a996 RE |
2227 | bfd_byte *valbuf = dst; |
2228 | ||
ed9a39eb | 2229 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 RE |
2230 | { |
2231 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2232 | ||
2233 | switch (tdep->fp_model) | |
2234 | { | |
2235 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2236 | { |
2237 | /* The value is in register F0 in internal format. We need to | |
2238 | extract the raw value and then convert it to the desired | |
2239 | internal type. */ | |
2240 | bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE]; | |
2241 | ||
2242 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2243 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2244 | valbuf); | |
2245 | } | |
08216dd7 RE |
2246 | break; |
2247 | ||
2248 | case ARM_FLOAT_SOFT: | |
2249 | case ARM_FLOAT_SOFT_VFP: | |
b508a996 RE |
2250 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2251 | if (TYPE_LENGTH (type) > 4) | |
2252 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
2253 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2254 | break; |
2255 | ||
2256 | default: | |
2257 | internal_error | |
2258 | (__FILE__, __LINE__, | |
2259 | "arm_extract_return_value: Floating point model not supported"); | |
2260 | break; | |
2261 | } | |
2262 | } | |
b508a996 RE |
2263 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2264 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2265 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2266 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2267 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2268 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2269 | { | |
2270 | /* If the the type is a plain integer, then the access is | |
2271 | straight-forward. Otherwise we have to play around a bit more. */ | |
2272 | int len = TYPE_LENGTH (type); | |
2273 | int regno = ARM_A1_REGNUM; | |
2274 | ULONGEST tmp; | |
2275 | ||
2276 | while (len > 0) | |
2277 | { | |
2278 | /* By using store_unsigned_integer we avoid having to do | |
2279 | anything special for small big-endian values. */ | |
2280 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2281 | store_unsigned_integer (valbuf, | |
2282 | (len > INT_REGISTER_RAW_SIZE | |
2283 | ? INT_REGISTER_RAW_SIZE : len), | |
2284 | tmp); | |
2285 | len -= INT_REGISTER_RAW_SIZE; | |
2286 | valbuf += INT_REGISTER_RAW_SIZE; | |
2287 | } | |
2288 | } | |
ed9a39eb | 2289 | else |
b508a996 RE |
2290 | { |
2291 | /* For a structure or union the behaviour is as if the value had | |
2292 | been stored to word-aligned memory and then loaded into | |
2293 | registers with 32-bit load instruction(s). */ | |
2294 | int len = TYPE_LENGTH (type); | |
2295 | int regno = ARM_A1_REGNUM; | |
2296 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2297 | ||
2298 | while (len > 0) | |
2299 | { | |
2300 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2301 | memcpy (valbuf, tmpbuf, | |
2302 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2303 | len -= INT_REGISTER_RAW_SIZE; | |
2304 | valbuf += INT_REGISTER_RAW_SIZE; | |
2305 | } | |
2306 | } | |
34e8f22d RE |
2307 | } |
2308 | ||
67255d04 RE |
2309 | /* Extract from an array REGBUF containing the (raw) register state |
2310 | the address in which a function should return its structure value. */ | |
2311 | ||
2312 | static CORE_ADDR | |
95f95911 | 2313 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2314 | { |
95f95911 MS |
2315 | ULONGEST ret; |
2316 | ||
2317 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2318 | return ret; | |
67255d04 RE |
2319 | } |
2320 | ||
2321 | /* Will a function return an aggregate type in memory or in a | |
2322 | register? Return 0 if an aggregate type can be returned in a | |
2323 | register, 1 if it must be returned in memory. */ | |
2324 | ||
2325 | static int | |
2326 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2327 | { | |
2328 | int nRc; | |
2329 | register enum type_code code; | |
2330 | ||
2331 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2332 | registers. For an aggregate type to be integer like, its size | |
2333 | must be less than or equal to REGISTER_SIZE and the offset of | |
2334 | each addressable subfield must be zero. Note that bit fields are | |
2335 | not addressable, and all addressable subfields of unions always | |
2336 | start at offset zero. | |
2337 | ||
2338 | This function is based on the behaviour of GCC 2.95.1. | |
2339 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2340 | ||
2341 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2342 | parameters correctly for a function returning the following | |
2343 | structure: struct { float f;}; This should be returned in memory, | |
2344 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2345 | know of any way to detect if a function like the above has been | |
2346 | compiled with the correct calling convention. */ | |
2347 | ||
2348 | /* All aggregate types that won't fit in a register must be returned | |
2349 | in memory. */ | |
2350 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
2351 | { | |
2352 | return 1; | |
2353 | } | |
2354 | ||
2355 | /* The only aggregate types that can be returned in a register are | |
2356 | structs and unions. Arrays must be returned in memory. */ | |
2357 | code = TYPE_CODE (type); | |
2358 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2359 | { | |
2360 | return 1; | |
2361 | } | |
2362 | ||
2363 | /* Assume all other aggregate types can be returned in a register. | |
2364 | Run a check for structures, unions and arrays. */ | |
2365 | nRc = 0; | |
2366 | ||
2367 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2368 | { | |
2369 | int i; | |
2370 | /* Need to check if this struct/union is "integer" like. For | |
2371 | this to be true, its size must be less than or equal to | |
2372 | REGISTER_SIZE and the offset of each addressable subfield | |
2373 | must be zero. Note that bit fields are not addressable, and | |
2374 | unions always start at offset zero. If any of the subfields | |
2375 | is a floating point type, the struct/union cannot be an | |
2376 | integer type. */ | |
2377 | ||
2378 | /* For each field in the object, check: | |
2379 | 1) Is it FP? --> yes, nRc = 1; | |
2380 | 2) Is it addressable (bitpos != 0) and | |
2381 | not packed (bitsize == 0)? | |
2382 | --> yes, nRc = 1 | |
2383 | */ | |
2384 | ||
2385 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2386 | { | |
2387 | enum type_code field_type_code; | |
2388 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2389 | ||
2390 | /* Is it a floating point type field? */ | |
2391 | if (field_type_code == TYPE_CODE_FLT) | |
2392 | { | |
2393 | nRc = 1; | |
2394 | break; | |
2395 | } | |
2396 | ||
2397 | /* If bitpos != 0, then we have to care about it. */ | |
2398 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2399 | { | |
2400 | /* Bitfields are not addressable. If the field bitsize is | |
2401 | zero, then the field is not packed. Hence it cannot be | |
2402 | a bitfield or any other packed type. */ | |
2403 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2404 | { | |
2405 | nRc = 1; | |
2406 | break; | |
2407 | } | |
2408 | } | |
2409 | } | |
2410 | } | |
2411 | ||
2412 | return nRc; | |
2413 | } | |
2414 | ||
34e8f22d RE |
2415 | /* Write into appropriate registers a function return value of type |
2416 | TYPE, given in virtual format. */ | |
2417 | ||
2418 | static void | |
b508a996 RE |
2419 | arm_store_return_value (struct type *type, struct regcache *regs, |
2420 | const void *src) | |
34e8f22d | 2421 | { |
b508a996 RE |
2422 | const bfd_byte *valbuf = src; |
2423 | ||
34e8f22d RE |
2424 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2425 | { | |
08216dd7 | 2426 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7bbcf283 | 2427 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2428 | |
08216dd7 RE |
2429 | switch (tdep->fp_model) |
2430 | { | |
2431 | case ARM_FLOAT_FPA: | |
2432 | ||
b508a996 RE |
2433 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2434 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2435 | break; |
2436 | ||
2437 | case ARM_FLOAT_SOFT: | |
2438 | case ARM_FLOAT_SOFT_VFP: | |
b508a996 RE |
2439 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2440 | if (TYPE_LENGTH (type) > 4) | |
2441 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
2442 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2443 | break; |
2444 | ||
2445 | default: | |
2446 | internal_error | |
2447 | (__FILE__, __LINE__, | |
2448 | "arm_store_return_value: Floating point model not supported"); | |
2449 | break; | |
2450 | } | |
34e8f22d | 2451 | } |
b508a996 RE |
2452 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2453 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2454 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2455 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2456 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2457 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2458 | { | |
2459 | if (TYPE_LENGTH (type) <= 4) | |
2460 | { | |
2461 | /* Values of one word or less are zero/sign-extended and | |
2462 | returned in r0. */ | |
2463 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2464 | LONGEST val = unpack_long (type, valbuf); | |
2465 | ||
2466 | store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val); | |
2467 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); | |
2468 | } | |
2469 | else | |
2470 | { | |
2471 | /* Integral values greater than one word are stored in consecutive | |
2472 | registers starting with r0. This will always be a multiple of | |
2473 | the regiser size. */ | |
2474 | int len = TYPE_LENGTH (type); | |
2475 | int regno = ARM_A1_REGNUM; | |
2476 | ||
2477 | while (len > 0) | |
2478 | { | |
2479 | regcache_cooked_write (regs, regno++, valbuf); | |
2480 | len -= INT_REGISTER_RAW_SIZE; | |
2481 | valbuf += INT_REGISTER_RAW_SIZE; | |
2482 | } | |
2483 | } | |
2484 | } | |
34e8f22d | 2485 | else |
b508a996 RE |
2486 | { |
2487 | /* For a structure or union the behaviour is as if the value had | |
2488 | been stored to word-aligned memory and then loaded into | |
2489 | registers with 32-bit load instruction(s). */ | |
2490 | int len = TYPE_LENGTH (type); | |
2491 | int regno = ARM_A1_REGNUM; | |
2492 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2493 | ||
2494 | while (len > 0) | |
2495 | { | |
2496 | memcpy (tmpbuf, valbuf, | |
2497 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2498 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2499 | len -= INT_REGISTER_RAW_SIZE; | |
2500 | valbuf += INT_REGISTER_RAW_SIZE; | |
2501 | } | |
2502 | } | |
34e8f22d RE |
2503 | } |
2504 | ||
2505 | /* Store the address of the place in which to copy the structure the | |
94c30b78 | 2506 | subroutine will return. This is called from call_function. */ |
34e8f22d RE |
2507 | |
2508 | static void | |
2509 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2510 | { | |
2511 | write_register (ARM_A1_REGNUM, addr); | |
ed9a39eb JM |
2512 | } |
2513 | ||
9df628e0 RE |
2514 | static int |
2515 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2516 | { | |
2517 | CORE_ADDR jb_addr; | |
2518 | char buf[INT_REGISTER_RAW_SIZE]; | |
2519 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2520 | ||
2521 | jb_addr = read_register (ARM_A1_REGNUM); | |
2522 | ||
2523 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2524 | INT_REGISTER_RAW_SIZE)) | |
2525 | return 0; | |
2526 | ||
2527 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); | |
2528 | return 1; | |
2529 | } | |
2530 | ||
ed9a39eb | 2531 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2532 | |
2533 | int | |
ed9a39eb | 2534 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2535 | { |
2536 | CORE_ADDR start_addr; | |
2537 | ||
ed9a39eb JM |
2538 | /* Find the starting address of the function containing the PC. If |
2539 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2540 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2541 | &start_addr, NULL)) | |
c906108c SS |
2542 | return 0; |
2543 | ||
2544 | return strncmp (name, "_call_via_r", 11) == 0; | |
2545 | } | |
2546 | ||
ed9a39eb JM |
2547 | /* If PC is in a Thumb call or return stub, return the address of the |
2548 | target PC, which is in a register. The thunk functions are called | |
2549 | _called_via_xx, where x is the register name. The possible names | |
2550 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2551 | |
2552 | CORE_ADDR | |
ed9a39eb | 2553 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2554 | { |
c5aa993b | 2555 | char *name; |
c906108c SS |
2556 | CORE_ADDR start_addr; |
2557 | ||
2558 | /* Find the starting address and name of the function containing the PC. */ | |
2559 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2560 | return 0; | |
2561 | ||
2562 | /* Call thunks always start with "_call_via_". */ | |
2563 | if (strncmp (name, "_call_via_", 10) == 0) | |
2564 | { | |
ed9a39eb JM |
2565 | /* Use the name suffix to determine which register contains the |
2566 | target PC. */ | |
c5aa993b JM |
2567 | static char *table[15] = |
2568 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2569 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2570 | }; | |
c906108c SS |
2571 | int regno; |
2572 | ||
2573 | for (regno = 0; regno <= 14; regno++) | |
2574 | if (strcmp (&name[10], table[regno]) == 0) | |
2575 | return read_register (regno); | |
2576 | } | |
ed9a39eb | 2577 | |
c5aa993b | 2578 | return 0; /* not a stub */ |
c906108c SS |
2579 | } |
2580 | ||
da3c6d4a MS |
2581 | /* If the user changes the register disassembly flavor used for info |
2582 | register and other commands, we have to also switch the flavor used | |
2583 | in opcodes for disassembly output. This function is run in the set | |
94c30b78 | 2584 | disassembly_flavor command, and does that. */ |
bc90b915 FN |
2585 | |
2586 | static void | |
2587 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2588 | struct cmd_list_element *c) | |
2589 | { | |
2590 | set_disassembly_flavor (); | |
2591 | } | |
2592 | \f | |
966fbf70 | 2593 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2594 | static const char * |
34e8f22d | 2595 | arm_register_name (int i) |
966fbf70 RE |
2596 | { |
2597 | return arm_register_names[i]; | |
2598 | } | |
2599 | ||
bc90b915 FN |
2600 | static void |
2601 | set_disassembly_flavor (void) | |
2602 | { | |
2603 | const char *setname, *setdesc, **regnames; | |
2604 | int numregs, j; | |
2605 | ||
94c30b78 | 2606 | /* Find the flavor that the user wants in the opcodes table. */ |
bc90b915 FN |
2607 | int current = 0; |
2608 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2609 | while ((disassembly_flavor != setname) | |
2610 | && (current < num_flavor_options)) | |
2611 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2612 | current_option = current; | |
2613 | ||
94c30b78 | 2614 | /* Fill our copy. */ |
bc90b915 FN |
2615 | for (j = 0; j < numregs; j++) |
2616 | arm_register_names[j] = (char *) regnames[j]; | |
2617 | ||
94c30b78 | 2618 | /* Adjust case. */ |
34e8f22d | 2619 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2620 | { |
34e8f22d RE |
2621 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2622 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2623 | } |
2624 | else | |
2625 | { | |
34e8f22d RE |
2626 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2627 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2628 | } |
2629 | ||
94c30b78 | 2630 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2631 | set_arm_regname_option (current); |
2632 | } | |
2633 | ||
2634 | /* arm_othernames implements the "othernames" command. This is kind | |
2635 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2636 | also used for the x86 gdb. I will keep this around, however, in | |
94c30b78 | 2637 | case anyone is actually using it. */ |
bc90b915 FN |
2638 | |
2639 | static void | |
2640 | arm_othernames (char *names, int n) | |
2641 | { | |
94c30b78 | 2642 | /* Circle through the various flavors. */ |
bc90b915 FN |
2643 | current_option = (current_option + 1) % num_flavor_options; |
2644 | ||
2645 | disassembly_flavor = valid_flavors[current_option]; | |
94c30b78 | 2646 | set_disassembly_flavor (); |
bc90b915 FN |
2647 | } |
2648 | ||
a42dd537 KB |
2649 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2650 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2651 | Note, however, that link.h is not actually referred to in this file. | |
2652 | Instead, the relevant structs offsets were obtained from examining | |
2653 | link.h. (We can't refer to link.h from this file because the host | |
2654 | system won't necessarily have it, or if it does, the structs which | |
94c30b78 | 2655 | it defines will refer to the host system, not the target). */ |
a42dd537 KB |
2656 | |
2657 | struct link_map_offsets * | |
2658 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2659 | { | |
2660 | static struct link_map_offsets lmo; | |
2661 | static struct link_map_offsets *lmp = 0; | |
2662 | ||
2663 | if (lmp == 0) | |
2664 | { | |
2665 | lmp = &lmo; | |
2666 | ||
2667 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
94c30b78 | 2668 | need. */ |
a42dd537 KB |
2669 | |
2670 | lmo.r_map_offset = 4; | |
2671 | lmo.r_map_size = 4; | |
2672 | ||
2673 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
94c30b78 | 2674 | need. */ |
a42dd537 KB |
2675 | |
2676 | lmo.l_addr_offset = 0; | |
2677 | lmo.l_addr_size = 4; | |
2678 | ||
2679 | lmo.l_name_offset = 4; | |
2680 | lmo.l_name_size = 4; | |
2681 | ||
2682 | lmo.l_next_offset = 12; | |
2683 | lmo.l_next_size = 4; | |
2684 | ||
2685 | lmo.l_prev_offset = 16; | |
2686 | lmo.l_prev_size = 4; | |
2687 | } | |
2688 | ||
2689 | return lmp; | |
2690 | } | |
2691 | ||
082fc60d RE |
2692 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2693 | function. */ | |
2694 | ||
2695 | static int | |
2696 | coff_sym_is_thumb (int val) | |
2697 | { | |
2698 | return (val == C_THUMBEXT || | |
2699 | val == C_THUMBSTAT || | |
2700 | val == C_THUMBEXTFUNC || | |
2701 | val == C_THUMBSTATFUNC || | |
2702 | val == C_THUMBLABEL); | |
2703 | } | |
2704 | ||
2705 | /* arm_coff_make_msymbol_special() | |
2706 | arm_elf_make_msymbol_special() | |
2707 | ||
2708 | These functions test whether the COFF or ELF symbol corresponds to | |
2709 | an address in thumb code, and set a "special" bit in a minimal | |
2710 | symbol to indicate that it does. */ | |
2711 | ||
34e8f22d | 2712 | static void |
082fc60d RE |
2713 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2714 | { | |
2715 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2716 | STT_ARM_TFUNC). */ | |
2717 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2718 | == STT_LOPROC) | |
2719 | MSYMBOL_SET_SPECIAL (msym); | |
2720 | } | |
2721 | ||
34e8f22d | 2722 | static void |
082fc60d RE |
2723 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2724 | { | |
2725 | if (coff_sym_is_thumb (val)) | |
2726 | MSYMBOL_SET_SPECIAL (msym); | |
2727 | } | |
2728 | ||
97e03143 | 2729 | \f |
70f80edf JT |
2730 | static enum gdb_osabi |
2731 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2732 | { |
70f80edf JT |
2733 | unsigned int elfosabi, eflags; |
2734 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2735 | |
70f80edf | 2736 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2737 | |
70f80edf | 2738 | switch (elfosabi) |
97e03143 | 2739 | { |
70f80edf JT |
2740 | case ELFOSABI_NONE: |
2741 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2742 | file are conforming to the base specification for that machine | |
2743 | (there are no OS-specific extensions). In order to determine the | |
2744 | real OS in use we must look for OS notes that have been added. */ | |
2745 | bfd_map_over_sections (abfd, | |
2746 | generic_elf_osabi_sniff_abi_tag_sections, | |
2747 | &osabi); | |
2748 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2749 | { |
70f80edf JT |
2750 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2751 | field for more information. */ | |
2752 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2753 | switch (eflags) | |
97e03143 | 2754 | { |
70f80edf JT |
2755 | case EF_ARM_EABI_VER1: |
2756 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2757 | break; |
2758 | ||
70f80edf JT |
2759 | case EF_ARM_EABI_VER2: |
2760 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2761 | break; |
2762 | ||
70f80edf JT |
2763 | case EF_ARM_EABI_UNKNOWN: |
2764 | /* Assume GNU tools. */ | |
2765 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2766 | break; |
2767 | ||
70f80edf JT |
2768 | default: |
2769 | internal_error (__FILE__, __LINE__, | |
2770 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2771 | "version 0x%x", eflags); | |
97e03143 RE |
2772 | } |
2773 | } | |
70f80edf | 2774 | break; |
97e03143 | 2775 | |
70f80edf JT |
2776 | case ELFOSABI_ARM: |
2777 | /* GNU tools use this value. Check note sections in this case, | |
2778 | as well. */ | |
97e03143 | 2779 | bfd_map_over_sections (abfd, |
70f80edf JT |
2780 | generic_elf_osabi_sniff_abi_tag_sections, |
2781 | &osabi); | |
2782 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2783 | { |
70f80edf JT |
2784 | /* Assume APCS ABI. */ |
2785 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2786 | } |
2787 | break; | |
2788 | ||
97e03143 | 2789 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2790 | osabi = GDB_OSABI_FREEBSD_ELF; |
2791 | break; | |
97e03143 | 2792 | |
70f80edf JT |
2793 | case ELFOSABI_NETBSD: |
2794 | osabi = GDB_OSABI_NETBSD_ELF; | |
2795 | break; | |
97e03143 | 2796 | |
70f80edf JT |
2797 | case ELFOSABI_LINUX: |
2798 | osabi = GDB_OSABI_LINUX; | |
2799 | break; | |
97e03143 RE |
2800 | } |
2801 | ||
70f80edf | 2802 | return osabi; |
97e03143 RE |
2803 | } |
2804 | ||
70f80edf | 2805 | \f |
da3c6d4a MS |
2806 | /* Initialize the current architecture based on INFO. If possible, |
2807 | re-use an architecture from ARCHES, which is a list of | |
2808 | architectures already created during this debugging session. | |
97e03143 | 2809 | |
da3c6d4a MS |
2810 | Called e.g. at program startup, when reading a core file, and when |
2811 | reading a binary file. */ | |
97e03143 | 2812 | |
39bbf761 RE |
2813 | static struct gdbarch * |
2814 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2815 | { | |
97e03143 | 2816 | struct gdbarch_tdep *tdep; |
39bbf761 | 2817 | struct gdbarch *gdbarch; |
70f80edf | 2818 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
39bbf761 | 2819 | |
97e03143 | 2820 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2821 | |
97e03143 RE |
2822 | if (info.abfd != NULL) |
2823 | { | |
70f80edf JT |
2824 | osabi = gdbarch_lookup_osabi (info.abfd); |
2825 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2826 | { |
70f80edf JT |
2827 | switch (bfd_get_flavour (info.abfd)) |
2828 | { | |
2829 | case bfd_target_aout_flavour: | |
2830 | /* Assume it's an old APCS-style ABI. */ | |
2831 | osabi = GDB_OSABI_ARM_APCS; | |
2832 | break; | |
97e03143 | 2833 | |
70f80edf JT |
2834 | case bfd_target_coff_flavour: |
2835 | /* Assume it's an old APCS-style ABI. */ | |
2836 | /* XXX WinCE? */ | |
2837 | osabi = GDB_OSABI_ARM_APCS; | |
2838 | break; | |
97e03143 | 2839 | |
70f80edf JT |
2840 | default: |
2841 | /* Leave it as "unknown". */ | |
2842 | } | |
97e03143 RE |
2843 | } |
2844 | } | |
2845 | ||
d7afb4c9 | 2846 | /* Find a candidate among extant architectures. */ |
97e03143 RE |
2847 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2848 | arches != NULL; | |
2849 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2850 | { | |
2851 | /* Make sure the ABI selection matches. */ | |
2852 | tdep = gdbarch_tdep (arches->gdbarch); | |
70f80edf | 2853 | if (tdep && tdep->osabi == osabi) |
97e03143 RE |
2854 | return arches->gdbarch; |
2855 | } | |
2856 | ||
2857 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2858 | gdbarch = gdbarch_alloc (&info, tdep); | |
2859 | ||
a5afb99f AC |
2860 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
2861 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
2862 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
2863 | ||
70f80edf | 2864 | tdep->osabi = osabi; |
39bbf761 | 2865 | |
08216dd7 RE |
2866 | /* This is the way it has always defaulted. */ |
2867 | tdep->fp_model = ARM_FLOAT_FPA; | |
2868 | ||
2869 | /* Breakpoints. */ | |
67255d04 RE |
2870 | switch (info.byte_order) |
2871 | { | |
2872 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2873 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2874 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2875 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2876 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2877 | ||
67255d04 RE |
2878 | break; |
2879 | ||
2880 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2881 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2882 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2883 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2884 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2885 | ||
67255d04 RE |
2886 | break; |
2887 | ||
2888 | default: | |
2889 | internal_error (__FILE__, __LINE__, | |
2890 | "arm_gdbarch_init: bad byte order for float format"); | |
2891 | } | |
2892 | ||
d7b486e7 RE |
2893 | /* On ARM targets char defaults to unsigned. */ |
2894 | set_gdbarch_char_signed (gdbarch, 0); | |
2895 | ||
9df628e0 | 2896 | /* This should be low enough for everything. */ |
97e03143 | 2897 | tdep->lowest_pc = 0x20; |
94c30b78 | 2898 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2899 | |
848cfffb AC |
2900 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
2901 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2902 | ||
2903 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
2904 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2905 | ||
2906 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); | |
2907 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
2908 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
2909 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
2910 | ||
2911 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
848cfffb AC |
2912 | |
2913 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
2914 | set_gdbarch_push_return_address (gdbarch, arm_push_return_address); | |
39bbf761 | 2915 | |
39bbf761 | 2916 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); |
d7afb4c9 RE |
2917 | set_gdbarch_coerce_float_to_double (gdbarch, |
2918 | standard_coerce_float_to_double); | |
39bbf761 | 2919 | |
148754e5 | 2920 | /* Frame handling. */ |
39bbf761 | 2921 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
148754e5 RE |
2922 | set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
2923 | set_gdbarch_read_fp (gdbarch, arm_read_fp); | |
2924 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); | |
2925 | set_gdbarch_frameless_function_invocation | |
2926 | (gdbarch, arm_frameless_function_invocation); | |
2927 | set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc); | |
2928 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); | |
2929 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); | |
2930 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); | |
2931 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2932 | set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); | |
848cfffb | 2933 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); |
148754e5 RE |
2934 | set_gdbarch_pop_frame (gdbarch, arm_pop_frame); |
2935 | ||
34e8f22d RE |
2936 | /* Address manipulation. */ |
2937 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2938 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2939 | ||
2940 | /* Offset from address of function to start of its code. */ | |
2941 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2942 | ||
2943 | /* Advance PC across function entry code. */ | |
2944 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2945 | ||
2946 | /* Get the PC when a frame might not be available. */ | |
2947 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); | |
2948 | ||
2949 | /* The stack grows downward. */ | |
2950 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2951 | ||
2952 | /* Breakpoint manipulation. */ | |
2953 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2954 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2955 | ||
2956 | /* Information about registers, etc. */ | |
2957 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
94c30b78 | 2958 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2959 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2960 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
2961 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
2962 | set_gdbarch_register_bytes (gdbarch, | |
2963 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2964 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2965 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
2966 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); | |
2967 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
2968 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
2969 | set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); | |
2970 | set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
2971 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); | |
2972 | ||
26216b98 AC |
2973 | /* Internal <-> external register number maps. */ |
2974 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2975 | ||
34e8f22d RE |
2976 | /* Integer registers are 4 bytes. */ |
2977 | set_gdbarch_register_size (gdbarch, 4); | |
2978 | set_gdbarch_register_name (gdbarch, arm_register_name); | |
2979 | ||
2980 | /* Returning results. */ | |
b508a996 RE |
2981 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2982 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
34e8f22d | 2983 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); |
67255d04 | 2984 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
95f95911 | 2985 | set_gdbarch_extract_struct_value_address (gdbarch, |
67255d04 | 2986 | arm_extract_struct_value_address); |
34e8f22d RE |
2987 | |
2988 | /* Single stepping. */ | |
2989 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2990 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2991 | ||
2992 | /* Minsymbol frobbing. */ | |
2993 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2994 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2995 | arm_coff_make_msymbol_special); | |
2996 | ||
97e03143 | 2997 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
70f80edf | 2998 | gdbarch_init_osabi (info, gdbarch, osabi); |
97e03143 RE |
2999 | |
3000 | /* Now we have tuned the configuration, set a few final things, | |
3001 | based on what the OS ABI has told us. */ | |
3002 | ||
9df628e0 RE |
3003 | if (tdep->jb_pc >= 0) |
3004 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
3005 | ||
08216dd7 RE |
3006 | /* Floating point sizes and format. */ |
3007 | switch (info.byte_order) | |
3008 | { | |
3009 | case BFD_ENDIAN_BIG: | |
3010 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
3011 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
3012 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
3013 | ||
3014 | break; | |
3015 | ||
3016 | case BFD_ENDIAN_LITTLE: | |
3017 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
3018 | if (tdep->fp_model == ARM_FLOAT_VFP | |
3019 | || tdep->fp_model == ARM_FLOAT_SOFT_VFP) | |
3020 | { | |
3021 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
3022 | set_gdbarch_long_double_format (gdbarch, | |
3023 | &floatformat_ieee_double_little); | |
3024 | } | |
3025 | else | |
3026 | { | |
3027 | set_gdbarch_double_format | |
3028 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
3029 | set_gdbarch_long_double_format | |
3030 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
3031 | } | |
3032 | break; | |
3033 | ||
3034 | default: | |
3035 | internal_error (__FILE__, __LINE__, | |
3036 | "arm_gdbarch_init: bad byte order for float format"); | |
3037 | } | |
3038 | ||
97e03143 | 3039 | /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still |
34e8f22d RE |
3040 | references the old architecture vector, not the one we are |
3041 | building here. */ | |
3042 | if (prologue_cache.saved_regs != NULL) | |
3043 | xfree (prologue_cache.saved_regs); | |
3044 | ||
a0abec03 AC |
3045 | /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still |
3046 | references the old architecture vector, not the one we are | |
3047 | building here. */ | |
34e8f22d RE |
3048 | prologue_cache.saved_regs = (CORE_ADDR *) |
3049 | xcalloc (1, (sizeof (CORE_ADDR) | |
29673b29 AC |
3050 | * (gdbarch_num_regs (gdbarch) |
3051 | + gdbarch_num_pseudo_regs (gdbarch)))); | |
39bbf761 RE |
3052 | |
3053 | return gdbarch; | |
3054 | } | |
3055 | ||
97e03143 RE |
3056 | static void |
3057 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3058 | { | |
3059 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3060 | ||
3061 | if (tdep == NULL) | |
3062 | return; | |
3063 | ||
70f80edf JT |
3064 | fprintf_unfiltered (file, "arm_dump_tdep: OS ABI = %s\n", |
3065 | gdbarch_osabi_name (tdep->osabi)); | |
97e03143 RE |
3066 | |
3067 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", | |
3068 | (unsigned long) tdep->lowest_pc); | |
3069 | } | |
3070 | ||
3071 | static void | |
3072 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
3073 | struct gdbarch *gdbarch) | |
3074 | { | |
3075 | /* Place-holder. */ | |
3076 | } | |
3077 | ||
3078 | static void | |
3079 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
3080 | struct gdbarch *gdbarch) | |
3081 | { | |
3082 | /* Place-holder. */ | |
3083 | } | |
3084 | ||
3085 | static void | |
3086 | arm_init_abi_apcs (struct gdbarch_info info, | |
3087 | struct gdbarch *gdbarch) | |
3088 | { | |
3089 | /* Place-holder. */ | |
3090 | } | |
3091 | ||
c906108c | 3092 | void |
ed9a39eb | 3093 | _initialize_arm_tdep (void) |
c906108c | 3094 | { |
bc90b915 FN |
3095 | struct ui_file *stb; |
3096 | long length; | |
96baa820 | 3097 | struct cmd_list_element *new_cmd; |
53904c9e AC |
3098 | const char *setname; |
3099 | const char *setdesc; | |
3100 | const char **regnames; | |
bc90b915 FN |
3101 | int numregs, i, j; |
3102 | static char *helptext; | |
085dd6e6 | 3103 | |
39bbf761 | 3104 | if (GDB_MULTI_ARCH) |
97e03143 RE |
3105 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
3106 | ||
70f80edf JT |
3107 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3108 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3109 | bfd_target_elf_flavour, | |
3110 | arm_elf_osabi_sniffer); | |
3111 | ||
97e03143 | 3112 | /* Register some ABI variants for embedded systems. */ |
70f80edf JT |
3113 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V1, |
3114 | arm_init_abi_eabi_v1); | |
3115 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V2, | |
3116 | arm_init_abi_eabi_v2); | |
3117 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_APCS, | |
3118 | arm_init_abi_apcs); | |
39bbf761 | 3119 | |
c906108c | 3120 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 3121 | |
94c30b78 | 3122 | /* Get the number of possible sets of register names defined in opcodes. */ |
bc90b915 FN |
3123 | num_flavor_options = get_arm_regname_num_options (); |
3124 | ||
94c30b78 | 3125 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3126 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3127 | |
94c30b78 | 3128 | /* Begin creating the help text. */ |
bc90b915 FN |
3129 | stb = mem_fileopen (); |
3130 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
3131 | The valid values are:\n"); | |
ed9a39eb | 3132 | |
94c30b78 | 3133 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
bc90b915 FN |
3134 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); |
3135 | for (i = 0; i < num_flavor_options; i++) | |
3136 | { | |
3137 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 3138 | valid_flavors[i] = setname; |
bc90b915 FN |
3139 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3140 | setdesc); | |
94c30b78 | 3141 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3142 | if (!strcmp (setname, "std")) |
3143 | { | |
53904c9e | 3144 | disassembly_flavor = setname; |
bc90b915 FN |
3145 | current_option = i; |
3146 | for (j = 0; j < numregs; j++) | |
3147 | arm_register_names[j] = (char *) regnames[j]; | |
3148 | set_arm_regname_option (i); | |
3149 | } | |
3150 | } | |
94c30b78 | 3151 | /* Mark the end of valid options. */ |
bc90b915 | 3152 | valid_flavors[num_flavor_options] = NULL; |
c906108c | 3153 | |
94c30b78 | 3154 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3155 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3156 | helptext = ui_file_xstrdup (stb, &length); | |
3157 | ui_file_delete (stb); | |
ed9a39eb | 3158 | |
94c30b78 | 3159 | /* Add the disassembly-flavor command. */ |
96baa820 | 3160 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 3161 | valid_flavors, |
1ed2a135 | 3162 | &disassembly_flavor, |
bc90b915 | 3163 | helptext, |
ed9a39eb | 3164 | &setlist); |
9f60d481 | 3165 | set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc); |
ed9a39eb JM |
3166 | add_show_from_set (new_cmd, &showlist); |
3167 | ||
c906108c SS |
3168 | /* ??? Maybe this should be a boolean. */ |
3169 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 3170 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 3171 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 3172 | &showlist); |
c906108c | 3173 | |
94c30b78 | 3174 | /* Add the deprecated "othernames" command. */ |
bc90b915 FN |
3175 | |
3176 | add_com ("othernames", class_obscure, arm_othernames, | |
3177 | "Switch to the next set of register names."); | |
c3b4394c RE |
3178 | |
3179 | /* Fill in the prologue_cache fields. */ | |
34e8f22d | 3180 | prologue_cache.saved_regs = NULL; |
c3b4394c RE |
3181 | prologue_cache.extra_info = (struct frame_extra_info *) |
3182 | xcalloc (1, sizeof (struct frame_extra_info)); | |
6529d2dd AC |
3183 | |
3184 | /* Debugging flag. */ | |
3185 | add_show_from_set (add_set_cmd ("arm", class_maintenance, var_zinteger, | |
3186 | &arm_debug, "Set arm debugging.\n\ | |
3187 | When non-zero, arm specific debugging is enabled.", &setdebuglist), | |
3188 | &showdebuglist); | |
c906108c | 3189 | } |